From nobody Mon Feb 9 15:29:55 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1BED6326D51; Thu, 22 Jan 2026 17:16:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769102219; cv=none; b=OGtLZwbZx3UTsQPh0GusPzzwLpyLBVV7X4RZPdQsTU2yeDdg1gvXdmWgYYUeh9FM0I2DP53lXWPWOVd1DVax6q5EtIW3O+dKu7pq6V5FBSYmJTrcZD+hdt+3/bZc0HyDy/QBKyAcIxdi5fMc5OcjsFBetDLQtXjRR8P2JutlNIE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769102219; c=relaxed/simple; bh=gVmezFj2iQXhmhcILTgidtMn8b85ekdhlcEn4N9gnPw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WxdMLnphZFDbh6MAa5TseuCQwbfRRzKuvgtkitt8CBIHp5JSF2QSEKE4rknH6slDP8n0+5X+WZTsnpSlsiv5IPHAMcNKWqva6cRncDtZgtt5vnClJ07CEaLdBNShwOrRjEAOTEaibOgLt+wXVvevtWf5TuS+aj5KQZGDgH4cl7Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=QuCjt+0v; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QuCjt+0v" Received: by smtp.kernel.org (Postfix) with ESMTPS id 69354C19422; Thu, 22 Jan 2026 17:16:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769102217; bh=gVmezFj2iQXhmhcILTgidtMn8b85ekdhlcEn4N9gnPw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=QuCjt+0vmjhs4EqJEcrSyysYn0ZV0ujlWZqWsOW1oA3xAu7i7C1ZuvHLrn8FubMlI x4W6mc+ztGL7BLh/uYoP5Z5PJjZyO7iw5qGa083H9uA8ZrqoEqf8K+EXiTgWHSB8rf BrTtHgtrG9OoqBeHDqPhdC1gBW7k6O90fHqFfcwnBhqHNGyGfzYDxOTMnCj8Wr1Co8 gLjn6/M+28AftyAWBlnps2TQst+KuZ7SwLqULsKzeTcfC50Vx4tE+CrRR6Lie+O7hC ZI+xMuo8PL+qiWKanl3quvj/dhoXFszPX4IaqyG7ujDJikFdjxPPTHtPB+UWIQSp+4 EA3o9zBtLJzWA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5692DD3EE95; Thu, 22 Jan 2026 17:16:57 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Thu, 22 Jan 2026 22:46:51 +0530 Subject: [PATCH v6 1/4] dt-bindings: connector: Add PCIe M.2 Mechanical Key M connector Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260122-pci-m2-v6-1-575da9f97239@oss.qualcomm.com> References: <20260122-pci-m2-v6-0-575da9f97239@oss.qualcomm.com> In-Reply-To: <20260122-pci-m2-v6-0-575da9f97239@oss.qualcomm.com> To: Bjorn Helgaas , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Damien Le Moal , Niklas Cassel , Linus Walleij , Bartosz Golaszewski Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Stephan Gerhold , Dmitry Baryshkov , linux-pm@vger.kernel.org, linux-ide@vger.kernel.org, Manivannan Sadhasivam , Frank Li X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=5981; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=kpDdQgiW3zswqxs3HBiLd11K+duGGVHLZBnR2sgvg4I=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBpcluHFv81maaRQnWKN5jnqTM+aEhIRpasPzYoe N/8l6ySdaWJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaXJbhwAKCRBVnxHm/pHO 9QBaB/4vyYmLJLbY/toA0NYxwsJM6VJKfTC6Uxoz5gt4KRN2Ggi6jHKV+gPlLpYtfxdJD5z38fN e8/oL7ojgq/Wu2G9EBii9wCDAG4lImLajRsCIMzyz0cSfYy5+aLC9+15EB0ypx2l2XU+CanTptN iA0eNEfwQFEXQLs8Qfz5OKrWijLLc63mIpWPhMEoPMVF2Kpsjg2oxNJsWMiQDyo3QjVQAoHOPM/ m7Yldpa7KVRfJgcwfhQPHKJ4MlFypZP/Zq/PX9UlQkLijUmojenOWbBy4WZs08wfUXmSNezHQ5w p8mmCdpUazKBAEYo2yvOiG94qu5ALrpacM9sS8cj4slILCws X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam Add the devicetree binding for PCIe M.2 Mechanical Key M connector defined in the PCI Express M.2 Specification, r4.0, sec 5.3. This connector provides interfaces like PCIe and SATA to attach the Solid State Drives (SSDs) to the host machine along with additional interfaces like USB, and SMBus for debugging and supplementary features. The connector provides a primary power supply of 3.3v, along with an optional 1.8v VIO supply for the Adapter I/O buffer circuitry operating at 1.8v sideband signaling. The connector also supplies optional signals in the form of GPIOs for fine grained power management. Reviewed-by: Frank Li Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring (Arm) --- .../bindings/connector/pcie-m2-m-connector.yaml | 145 +++++++++++++++++= ++++ 1 file changed, 145 insertions(+) diff --git a/Documentation/devicetree/bindings/connector/pcie-m2-m-connecto= r.yaml b/Documentation/devicetree/bindings/connector/pcie-m2-m-connector.ya= ml new file mode 100644 index 000000000000..36a99a3b39d7 --- /dev/null +++ b/Documentation/devicetree/bindings/connector/pcie-m2-m-connector.yaml @@ -0,0 +1,145 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/connector/pcie-m2-m-connector.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCIe M.2 Mechanical Key M Connector + +maintainers: + - Manivannan Sadhasivam + +description: + A PCIe M.2 M connector node represents a physical PCIe M.2 Mechanical Ke= y M + connector. The Mechanical Key M connectors are used to connect SSDs to t= he + host system over PCIe/SATA interfaces. These connectors also offer optio= nal + interfaces like USB, SMBus. + +properties: + compatible: + const: pcie-m2-m-connector + + vpcie3v3-supply: + description: A phandle to the regulator for 3.3v supply. + + vpcie1v8-supply: + description: A phandle to the regulator for VIO 1.8v supply. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: OF graph bindings modeling the interfaces exposed on the + connector. Since a single connector can have multiple interfaces, ev= ery + interface has an assigned OF graph port number as described below. + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: PCIe interface + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: SATA interface + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: USB 2.0 interface + + anyOf: + - required: + - port@0 + - required: + - port@1 + + i2c-parent: + $ref: /schemas/types.yaml#/definitions/phandle + description: I2C interface + + clocks: + description: 32.768 KHz Suspend Clock (SUSCLK) input from the host sys= tem to + the M.2 card. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.= 1 for + more details. + maxItems: 1 + + pedet-gpios: + description: GPIO input to PEDET signal. This signal is used by the ho= st + systems to determine the communication protocol that the M.2 card us= es; + SATA signaling (low) or PCIe signaling (high). Refer, PCI Express M.2 + Specification r4.0, sec 3.3.4.2 for more details. + maxItems: 1 + + viocfg-gpios: + description: GPIO input to IO voltage configuration (VIO_CFG) signal. = This + signal is used by the host systems to determine whether the card sup= ports + an independent IO voltage domain for the sideband signals or not. Re= fer, + PCI Express M.2 Specification r4.0, sec 3.1.15.1 for more details. + maxItems: 1 + + pwrdis-gpios: + description: GPIO output to Power Disable (PWRDIS) signal. This signal= is + used by the host system to disable power on the M.2 card. Refer, PCI + Express M.2 Specification r4.0, sec 3.3.5.2 for more details. + maxItems: 1 + + pln-gpios: + description: GPIO output to Power Loss Notification (PLN#) signal. This + signal is used by the host system to notify the M.2 card that the po= wer + loss event is about to occur. Refer, PCI Express M.2 Specification r= 4.0, + sec 3.2.17.1 for more details. + maxItems: 1 + + plas3-gpios: + description: GPIO input to Power Loss Acknowledge (PLA_S3#) signal. Th= is + signal is used by the host system to receive the acknowledgment of t= he M.2 + card's preparation for power loss. + maxItems: 1 + +required: + - compatible + - vpcie3v3-supply + +additionalProperties: false + +examples: + # PCI M.2 Key M connector for SSDs with PCIe interface + - | + #include + + connector { + compatible =3D "pcie-m2-m-connector"; + vpcie3v3-supply =3D <&vreg_nvme>; + i2c-parent =3D <&i2c0>; + pedet-gpios =3D <&tlmm 95 GPIO_ACTIVE_HIGH>; + viocfg-gpios =3D <&tlmm 96 GPIO_ACTIVE_HIGH>; + pwrdis-gpios =3D <&tlmm 97 GPIO_ACTIVE_HIGH>; + pln-gpios =3D <&tlmm 98 GPIO_ACTIVE_LOW>; + plas3-gpios =3D <&tlmm 99 GPIO_ACTIVE_LOW>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + reg =3D <0>; + + endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&pcie6_port0_ep>; + }; + }; + + port@2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + reg =3D <2>; + + endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&usb_hs_ep>; + }; + }; + }; + }; --=20 2.51.0