From nobody Sun Feb 8 13:53:48 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1BED6326D51; Thu, 22 Jan 2026 17:16:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769102219; cv=none; b=OGtLZwbZx3UTsQPh0GusPzzwLpyLBVV7X4RZPdQsTU2yeDdg1gvXdmWgYYUeh9FM0I2DP53lXWPWOVd1DVax6q5EtIW3O+dKu7pq6V5FBSYmJTrcZD+hdt+3/bZc0HyDy/QBKyAcIxdi5fMc5OcjsFBetDLQtXjRR8P2JutlNIE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769102219; c=relaxed/simple; bh=gVmezFj2iQXhmhcILTgidtMn8b85ekdhlcEn4N9gnPw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WxdMLnphZFDbh6MAa5TseuCQwbfRRzKuvgtkitt8CBIHp5JSF2QSEKE4rknH6slDP8n0+5X+WZTsnpSlsiv5IPHAMcNKWqva6cRncDtZgtt5vnClJ07CEaLdBNShwOrRjEAOTEaibOgLt+wXVvevtWf5TuS+aj5KQZGDgH4cl7Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=QuCjt+0v; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QuCjt+0v" Received: by smtp.kernel.org (Postfix) with ESMTPS id 69354C19422; Thu, 22 Jan 2026 17:16:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769102217; bh=gVmezFj2iQXhmhcILTgidtMn8b85ekdhlcEn4N9gnPw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=QuCjt+0vmjhs4EqJEcrSyysYn0ZV0ujlWZqWsOW1oA3xAu7i7C1ZuvHLrn8FubMlI x4W6mc+ztGL7BLh/uYoP5Z5PJjZyO7iw5qGa083H9uA8ZrqoEqf8K+EXiTgWHSB8rf BrTtHgtrG9OoqBeHDqPhdC1gBW7k6O90fHqFfcwnBhqHNGyGfzYDxOTMnCj8Wr1Co8 gLjn6/M+28AftyAWBlnps2TQst+KuZ7SwLqULsKzeTcfC50Vx4tE+CrRR6Lie+O7hC ZI+xMuo8PL+qiWKanl3quvj/dhoXFszPX4IaqyG7ujDJikFdjxPPTHtPB+UWIQSp+4 EA3o9zBtLJzWA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5692DD3EE95; Thu, 22 Jan 2026 17:16:57 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Thu, 22 Jan 2026 22:46:51 +0530 Subject: [PATCH v6 1/4] dt-bindings: connector: Add PCIe M.2 Mechanical Key M connector Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260122-pci-m2-v6-1-575da9f97239@oss.qualcomm.com> References: <20260122-pci-m2-v6-0-575da9f97239@oss.qualcomm.com> In-Reply-To: <20260122-pci-m2-v6-0-575da9f97239@oss.qualcomm.com> To: Bjorn Helgaas , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Damien Le Moal , Niklas Cassel , Linus Walleij , Bartosz Golaszewski Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Stephan Gerhold , Dmitry Baryshkov , linux-pm@vger.kernel.org, linux-ide@vger.kernel.org, Manivannan Sadhasivam , Frank Li X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=5981; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=kpDdQgiW3zswqxs3HBiLd11K+duGGVHLZBnR2sgvg4I=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBpcluHFv81maaRQnWKN5jnqTM+aEhIRpasPzYoe N/8l6ySdaWJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaXJbhwAKCRBVnxHm/pHO 9QBaB/4vyYmLJLbY/toA0NYxwsJM6VJKfTC6Uxoz5gt4KRN2Ggi6jHKV+gPlLpYtfxdJD5z38fN e8/oL7ojgq/Wu2G9EBii9wCDAG4lImLajRsCIMzyz0cSfYy5+aLC9+15EB0ypx2l2XU+CanTptN iA0eNEfwQFEXQLs8Qfz5OKrWijLLc63mIpWPhMEoPMVF2Kpsjg2oxNJsWMiQDyo3QjVQAoHOPM/ m7Yldpa7KVRfJgcwfhQPHKJ4MlFypZP/Zq/PX9UlQkLijUmojenOWbBy4WZs08wfUXmSNezHQ5w p8mmCdpUazKBAEYo2yvOiG94qu5ALrpacM9sS8cj4slILCws X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam Add the devicetree binding for PCIe M.2 Mechanical Key M connector defined in the PCI Express M.2 Specification, r4.0, sec 5.3. This connector provides interfaces like PCIe and SATA to attach the Solid State Drives (SSDs) to the host machine along with additional interfaces like USB, and SMBus for debugging and supplementary features. The connector provides a primary power supply of 3.3v, along with an optional 1.8v VIO supply for the Adapter I/O buffer circuitry operating at 1.8v sideband signaling. The connector also supplies optional signals in the form of GPIOs for fine grained power management. Reviewed-by: Frank Li Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring (Arm) --- .../bindings/connector/pcie-m2-m-connector.yaml | 145 +++++++++++++++++= ++++ 1 file changed, 145 insertions(+) diff --git a/Documentation/devicetree/bindings/connector/pcie-m2-m-connecto= r.yaml b/Documentation/devicetree/bindings/connector/pcie-m2-m-connector.ya= ml new file mode 100644 index 000000000000..36a99a3b39d7 --- /dev/null +++ b/Documentation/devicetree/bindings/connector/pcie-m2-m-connector.yaml @@ -0,0 +1,145 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/connector/pcie-m2-m-connector.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCIe M.2 Mechanical Key M Connector + +maintainers: + - Manivannan Sadhasivam + +description: + A PCIe M.2 M connector node represents a physical PCIe M.2 Mechanical Ke= y M + connector. The Mechanical Key M connectors are used to connect SSDs to t= he + host system over PCIe/SATA interfaces. These connectors also offer optio= nal + interfaces like USB, SMBus. + +properties: + compatible: + const: pcie-m2-m-connector + + vpcie3v3-supply: + description: A phandle to the regulator for 3.3v supply. + + vpcie1v8-supply: + description: A phandle to the regulator for VIO 1.8v supply. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: OF graph bindings modeling the interfaces exposed on the + connector. Since a single connector can have multiple interfaces, ev= ery + interface has an assigned OF graph port number as described below. + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: PCIe interface + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: SATA interface + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: USB 2.0 interface + + anyOf: + - required: + - port@0 + - required: + - port@1 + + i2c-parent: + $ref: /schemas/types.yaml#/definitions/phandle + description: I2C interface + + clocks: + description: 32.768 KHz Suspend Clock (SUSCLK) input from the host sys= tem to + the M.2 card. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.= 1 for + more details. + maxItems: 1 + + pedet-gpios: + description: GPIO input to PEDET signal. This signal is used by the ho= st + systems to determine the communication protocol that the M.2 card us= es; + SATA signaling (low) or PCIe signaling (high). Refer, PCI Express M.2 + Specification r4.0, sec 3.3.4.2 for more details. + maxItems: 1 + + viocfg-gpios: + description: GPIO input to IO voltage configuration (VIO_CFG) signal. = This + signal is used by the host systems to determine whether the card sup= ports + an independent IO voltage domain for the sideband signals or not. Re= fer, + PCI Express M.2 Specification r4.0, sec 3.1.15.1 for more details. + maxItems: 1 + + pwrdis-gpios: + description: GPIO output to Power Disable (PWRDIS) signal. This signal= is + used by the host system to disable power on the M.2 card. Refer, PCI + Express M.2 Specification r4.0, sec 3.3.5.2 for more details. + maxItems: 1 + + pln-gpios: + description: GPIO output to Power Loss Notification (PLN#) signal. This + signal is used by the host system to notify the M.2 card that the po= wer + loss event is about to occur. Refer, PCI Express M.2 Specification r= 4.0, + sec 3.2.17.1 for more details. + maxItems: 1 + + plas3-gpios: + description: GPIO input to Power Loss Acknowledge (PLA_S3#) signal. Th= is + signal is used by the host system to receive the acknowledgment of t= he M.2 + card's preparation for power loss. + maxItems: 1 + +required: + - compatible + - vpcie3v3-supply + +additionalProperties: false + +examples: + # PCI M.2 Key M connector for SSDs with PCIe interface + - | + #include + + connector { + compatible =3D "pcie-m2-m-connector"; + vpcie3v3-supply =3D <&vreg_nvme>; + i2c-parent =3D <&i2c0>; + pedet-gpios =3D <&tlmm 95 GPIO_ACTIVE_HIGH>; + viocfg-gpios =3D <&tlmm 96 GPIO_ACTIVE_HIGH>; + pwrdis-gpios =3D <&tlmm 97 GPIO_ACTIVE_HIGH>; + pln-gpios =3D <&tlmm 98 GPIO_ACTIVE_LOW>; + plas3-gpios =3D <&tlmm 99 GPIO_ACTIVE_LOW>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + reg =3D <0>; + + endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&pcie6_port0_ep>; + }; + }; + + port@2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + reg =3D <2>; + + endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&usb_hs_ep>; + }; + }; + }; + }; --=20 2.51.0 From nobody Sun Feb 8 13:53:48 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1BDFC30EF67; Thu, 22 Jan 2026 17:16:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769102219; cv=none; b=DaBUs0OBuuGjduksLuBXbGwjXZCUxzk6iPgTNOI0AZJY++BkADqvzt3aSkGXewZl6JhwDUshVFfCNUmHYkIFa+Pu7R6WaYtJrqjOl9E3yxWaoa3WCPTEvXuEMWlFlcJKHa67+SDimwtF9HjBxq1+Uh3hhVAou9RQfkX6YieY2jg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769102219; c=relaxed/simple; bh=RebAKdOcdLux7Bzs3USnBVZCC294iJ88uiAmw8sBU+c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CarL06w/4BfoMmz6PyVUvb+ft9u7c9hk1kUv7GL9cYTNvqL3K4nDjm+cpypTQOuScrM72SXFwB/+nHSu7KQ2ahlBmKZGrPC6Z7jMs0B7wVBE8iUXPGmO00flP0QCPmF1fJJhVY32Jak6DA3mGE7d5rD9M48QFCnDEQx04Q77CnQ= ARC-Authentication-Results: i=1; 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Thu, 22 Jan 2026 17:16:57 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Thu, 22 Jan 2026 22:46:52 +0530 Subject: [PATCH v6 2/4] PCI/pwrctrl: Add support for handling PCIe M.2 connectors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260122-pci-m2-v6-2-575da9f97239@oss.qualcomm.com> References: <20260122-pci-m2-v6-0-575da9f97239@oss.qualcomm.com> In-Reply-To: <20260122-pci-m2-v6-0-575da9f97239@oss.qualcomm.com> To: Bjorn Helgaas , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Damien Le Moal , Niklas Cassel , Linus Walleij , Bartosz Golaszewski Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Stephan Gerhold , Dmitry Baryshkov , linux-pm@vger.kernel.org, linux-ide@vger.kernel.org, Manivannan Sadhasivam , Bartosz Golaszewski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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These connectors are exposed as the Power Sequencing devices as they often support multiple interfaces like PCIe/SATA, USB/UART to the host machine and each interfaces could be driven by different client drivers at the same time. This driver handles the PCIe interface of these connectors. It first checks for the presence of the graph port in the Root Port node with the help of of_graph_is_present() API, if present, it acquires/poweres ON the corresponding pwrseq device. Once the pwrseq device is powered ON, the driver will skip parsing the Root Port/Slot resources and registers with the pwrctrl framework. Reviewed-by: Bartosz Golaszewski Signed-off-by: Manivannan Sadhasivam --- drivers/pci/pwrctrl/Kconfig | 1 + drivers/pci/pwrctrl/slot.c | 35 ++++++++++++++++++++++++++++++----- 2 files changed, 31 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pwrctrl/Kconfig b/drivers/pci/pwrctrl/Kconfig index e0f999f299bb..cd3aa15bad00 100644 --- a/drivers/pci/pwrctrl/Kconfig +++ b/drivers/pci/pwrctrl/Kconfig @@ -13,6 +13,7 @@ config PCI_PWRCTRL_PWRSEQ =20 config PCI_PWRCTRL_SLOT tristate "PCI Power Control driver for PCI slots" + select POWER_SEQUENCING select PCI_PWRCTRL help Say Y here to enable the PCI Power Control driver to control the power diff --git a/drivers/pci/pwrctrl/slot.c b/drivers/pci/pwrctrl/slot.c index 3320494b62d8..d46c2365208a 100644 --- a/drivers/pci/pwrctrl/slot.c +++ b/drivers/pci/pwrctrl/slot.c @@ -8,8 +8,10 @@ #include #include #include +#include #include #include +#include #include #include =20 @@ -17,12 +19,18 @@ struct pci_pwrctrl_slot_data { struct pci_pwrctrl ctx; struct regulator_bulk_data *supplies; int num_supplies; + struct pwrseq_desc *pwrseq; }; =20 static void devm_pci_pwrctrl_slot_power_off(void *data) { struct pci_pwrctrl_slot_data *slot =3D data; =20 + if (slot->pwrseq) { + pwrseq_power_off(slot->pwrseq); + return; + } + regulator_bulk_disable(slot->num_supplies, slot->supplies); regulator_bulk_free(slot->num_supplies, slot->supplies); } @@ -38,6 +46,20 @@ static int pci_pwrctrl_slot_probe(struct platform_device= *pdev) if (!slot) return -ENOMEM; =20 + if (of_graph_is_present(dev_of_node(dev))) { + slot->pwrseq =3D devm_pwrseq_get(dev, "pcie"); + if (IS_ERR(slot->pwrseq)) + return dev_err_probe(dev, PTR_ERR(slot->pwrseq), + "Failed to get the power sequencer\n"); + + ret =3D pwrseq_power_on(slot->pwrseq); + if (ret) + return dev_err_probe(dev, ret, + "Failed to power-on the device\n"); + + goto skip_resources; + } + ret =3D of_regulator_bulk_get_all(dev, dev_of_node(dev), &slot->supplies); if (ret < 0) { @@ -53,17 +75,20 @@ static int pci_pwrctrl_slot_probe(struct platform_devic= e *pdev) return ret; } =20 - ret =3D devm_add_action_or_reset(dev, devm_pci_pwrctrl_slot_power_off, - slot); - if (ret) - return ret; - clk =3D devm_clk_get_optional_enabled(dev, NULL); if (IS_ERR(clk)) { + regulator_bulk_disable(slot->num_supplies, slot->supplies); + regulator_bulk_free(slot->num_supplies, slot->supplies); return dev_err_probe(dev, PTR_ERR(clk), "Failed to enable slot clock\n"); } =20 +skip_resources: + ret =3D devm_add_action_or_reset(dev, devm_pci_pwrctrl_slot_power_off, + slot); + if (ret) + return ret; + pci_pwrctrl_init(&slot->ctx, dev); =20 ret =3D devm_pci_pwrctrl_device_set_ready(dev, &slot->ctx); --=20 2.51.0 From nobody Sun Feb 8 13:53:48 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C2B237107F; Thu, 22 Jan 2026 17:16:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260122-pci-m2-v6-3-575da9f97239@oss.qualcomm.com> References: <20260122-pci-m2-v6-0-575da9f97239@oss.qualcomm.com> In-Reply-To: <20260122-pci-m2-v6-0-575da9f97239@oss.qualcomm.com> To: Bjorn Helgaas , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Damien Le Moal , Niklas Cassel , Linus Walleij , Bartosz Golaszewski Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Stephan Gerhold , Dmitry Baryshkov , linux-pm@vger.kernel.org, linux-ide@vger.kernel.org, Manivannan Sadhasivam , Bartosz Golaszewski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1400; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=smE99RkHH/faoB1zmIkyAwcapkpSsjVsJxAileZoxaE=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBpcluHA0O3bTT6GBQKs4Bu0/0Naq3FTjxCqXovG NOe4mh+GOeJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaXJbhwAKCRBVnxHm/pHO 9cfIB/sGcr8YJfw/XQuIliox5JDL3oiCWObJ6JZ386V5PCHHcvxQir+n8t/gVfSS/0ZNuBqebWO cv7QP/+WPeUslJZxTf+50wzKOt7Wt/Kj0O3/IrdoeFTt9LqhZ9fq3xvgJTQsz3Y/LX+SY2tB5hJ IhitRK4DPRiG0eLAcx5uVw4PTQSeZ4Vqb+KYynrCuuglmkDbzG5wAepctYwn1OZ6zpZkDbZC4vr 3Q1aRCFoMN5qH8ablj7WFUEtMWTbdOA2MlFyKrFvbRvX8Bv6dBY459F5YGi8ov0Xh5H+IT2bA/V HLdEZrYEws3DXkh4i/MTtXpXLba50XJIzDt2ZN0HBvCTQ7k0 X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam The devicetree node of the PCIe Root Port/Slot could have the graph port to link the PCIe M.2 connector node. Since the M.2 connectors are modelled as Power Sequencing devices, they need to be controlled by the pwrctrl driver as like the Root Port/Slot supplies. Hence, create the pwrctrl device if the graph port is found in the node. Reviewed-by: Bartosz Golaszewski Signed-off-by: Manivannan Sadhasivam --- drivers/pci/probe.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 41183aed8f5d..cd7efd20a74a 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -2585,7 +2586,7 @@ static struct platform_device *pci_pwrctrl_create_dev= ice(struct pci_bus *bus, in * not. This is decided based on at least one of the power supplies * being defined in the devicetree node of the device. */ - if (!of_pci_supply_present(np)) { + if (!of_pci_supply_present(np) && !of_graph_is_present(np)) { pr_debug("PCI/pwrctrl: Skipping OF node: %s\n", np->name); goto err_put_of_node; } --=20 2.51.0 From nobody Sun Feb 8 13:53:48 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CF21372B28; Thu, 22 Jan 2026 17:16:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769102219; cv=none; b=jGUPg4KQ+uuEJ8T3pdY7hALHkTRoEf5cBabZLgW6aiAWt8G6LrqxVtWcAfIZwdR3vtb2nARNpLYyfY5ENI70E64lGAT/sF+kOj406n7C+WQ+5skxe3cJ2w1jr6bJwrh9GIewVxv+0AKh4k8nDi5DqAADXIh2o/OUlESntkSFHNs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769102219; c=relaxed/simple; bh=czhrt6qU9W53d83wWXZNXSUrEG4WPODCrM75X7CHTjM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=L0fdesjo6o1W38FzD6EJWGDuY74qz55CmOFJuHdxCjacJdpP1VqA2yu2Rv6OxmLtdot0xZf8l0fH4IdFLb3gRS7GUNFPi3Zo0Ukc1weaGXBH+zM7ttVL1qBMZr3e8EzxPN4MnMsITPiKJ5HetEGjeqs+onQGR9FrXVlQgr9Hn6k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=h1WWek2/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="h1WWek2/" Received: by smtp.kernel.org (Postfix) with ESMTPS id 9378FC2BCB2; Thu, 22 Jan 2026 17:16:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769102217; bh=czhrt6qU9W53d83wWXZNXSUrEG4WPODCrM75X7CHTjM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=h1WWek2/5jcqZdn4fVlQo+m553ZImFYTaqn5kLRgxSQX6oo++iB4VyfP6Y8qpOkYP Y6fwm/MRHOrWfJfP1ZSqXGmkSH5ejzDH92uvu4KKKDNMww27LnmBuzU8jRzkENek+M Stskzhu3YcfqOc8Se6ClFNe43jpfu4XTJb7EYYuEb9A4oearHzXQBJ0lj/LLgBzXGu YjzbXx68tMCm2n0/NvZ6sAPGt5cN0SZ0LuaDZe4tzQ1H68bpc4bJWWfbeKBKSMTv4S vlUTk7Yo2s4NnODexudSr4YRL3TAF9Ti4jiZruQhQDEwaG2k/63SYi3dUHAji+5F99 LzsAt5TFhwVEw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86BA9D3EE9E; Thu, 22 Jan 2026 17:16:57 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Thu, 22 Jan 2026 22:46:54 +0530 Subject: [PATCH v6 4/4] power: sequencing: Add the Power Sequencing driver for the PCIe M.2 connectors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260122-pci-m2-v6-4-575da9f97239@oss.qualcomm.com> References: <20260122-pci-m2-v6-0-575da9f97239@oss.qualcomm.com> In-Reply-To: <20260122-pci-m2-v6-0-575da9f97239@oss.qualcomm.com> To: Bjorn Helgaas , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Damien Le Moal , Niklas Cassel , Linus Walleij , Bartosz Golaszewski Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Stephan Gerhold , Dmitry Baryshkov , linux-pm@vger.kernel.org, linux-ide@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=7812; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=MrmblrG2JUxLhRhHQkVgoN7g+pVLmcvg9aZ9Ii+xtN8=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBpcluHN3RueTwQ/o3zdxZcr6aj+Ny3g+qnSPyCX RI/5CTvL0mJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaXJbhwAKCRBVnxHm/pHO 9WbiB/98lvib3si3lbW+GSz8HT/YeqkOOxmZfVBQZ2VIxZe5fqwxu7ryxWOngkDxAMsySUSb6Jd umwrPa3RVCWhilEs3rP1K6OFK5Opiwu9746mIHpYXYC3rMgqZ6J8mhJji9Ml4nLF64/AKwc9Sos g4agtEoXH1O0CisnLMg8QhxWOo5G7oq46Dz9RieyxkZ1cLaG2jJrSZHH+PRaVJ91YKXHPBylRKk jjOsZzrm66NzL6aNZ+WixH0KlDgcHROC7HRW5V7pDjg1C7S/mQBKMKnRLqaRajlwp3oeY86pVyC ROOl7IUCPjuafsjqJfZIcBPYmDKZ3xpu14AHmvZPiYKx1LOZ X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam This driver is used to control the PCIe M.2 connectors of different Mechanical Keys attached to the host machines and supporting different interfaces like PCIe/SATA, USB/UART etc... Currently, this driver supports only the Mechanical Key M connectors with PCIe interface. The driver also only supports driving the mandatory 3.3v and optional 1.8v power supplies. The optional signals of the Key M connectors are not currently supported. Signed-off-by: Manivannan Sadhasivam --- MAINTAINERS | 7 ++ drivers/power/sequencing/Kconfig | 8 ++ drivers/power/sequencing/Makefile | 1 + drivers/power/sequencing/pwrseq-pcie-m2.c | 168 ++++++++++++++++++++++++++= ++++ 4 files changed, 184 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5b11839cba9d..2eb7b6d26573 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20791,6 +20791,13 @@ F: Documentation/driver-api/pwrseq.rst F: drivers/power/sequencing/ F: include/linux/pwrseq/ =20 +PCIE M.2 POWER SEQUENCING +M: Manivannan Sadhasivam +L: linux-pci@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/connector/pcie-m2-m-connector.yaml +F: drivers/power/sequencing/pwrseq-pcie-m2.c + POWER STATE COORDINATION INTERFACE (PSCI) M: Mark Rutland M: Lorenzo Pieralisi diff --git a/drivers/power/sequencing/Kconfig b/drivers/power/sequencing/Kc= onfig index 280f92beb5d0..f5fff84566ba 100644 --- a/drivers/power/sequencing/Kconfig +++ b/drivers/power/sequencing/Kconfig @@ -35,4 +35,12 @@ config POWER_SEQUENCING_TH1520_GPU GPU. This driver handles the complex clock and reset sequence required to power on the Imagination BXM GPU on this platform. =20 +config POWER_SEQUENCING_PCIE_M2 + tristate "PCIe M.2 connector power sequencing driver" + depends on OF || COMPILE_TEST + help + Say Y here to enable the power sequencing driver for PCIe M.2 + connectors. This driver handles the power sequencing for the M.2 + connectors exposing multiple interfaces like PCIe, SATA, UART, etc... + endif diff --git a/drivers/power/sequencing/Makefile b/drivers/power/sequencing/M= akefile index 96c1cf0a98ac..0911d4618298 100644 --- a/drivers/power/sequencing/Makefile +++ b/drivers/power/sequencing/Makefile @@ -5,3 +5,4 @@ pwrseq-core-y :=3D core.o =20 obj-$(CONFIG_POWER_SEQUENCING_QCOM_WCN) +=3D pwrseq-qcom-wcn.o obj-$(CONFIG_POWER_SEQUENCING_TH1520_GPU) +=3D pwrseq-thead-gpu.o +obj-$(CONFIG_POWER_SEQUENCING_PCIE_M2) +=3D pwrseq-pcie-m2.o diff --git a/drivers/power/sequencing/pwrseq-pcie-m2.c b/drivers/power/sequ= encing/pwrseq-pcie-m2.c new file mode 100644 index 000000000000..96ea4adc9d22 --- /dev/null +++ b/drivers/power/sequencing/pwrseq-pcie-m2.c @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Author: Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct pwrseq_pcie_m2_pdata { + const struct pwrseq_target_data **targets; +}; + +struct pwrseq_pcie_m2_ctx { + struct pwrseq_device *pwrseq; + struct device_node *of_node; + const struct pwrseq_pcie_m2_pdata *pdata; + struct regulator_bulk_data *regs; + size_t num_vregs; + struct notifier_block nb; +}; + +static int pwrseq_pcie_m2_m_vregs_enable(struct pwrseq_device *pwrseq) +{ + struct pwrseq_pcie_m2_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + + return regulator_bulk_enable(ctx->num_vregs, ctx->regs); +} + +static int pwrseq_pcie_m2_m_vregs_disable(struct pwrseq_device *pwrseq) +{ + struct pwrseq_pcie_m2_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + + return regulator_bulk_disable(ctx->num_vregs, ctx->regs); +} + +static const struct pwrseq_unit_data pwrseq_pcie_m2_vregs_unit_data =3D { + .name =3D "regulators-enable", + .enable =3D pwrseq_pcie_m2_m_vregs_enable, + .disable =3D pwrseq_pcie_m2_m_vregs_disable, +}; + +static const struct pwrseq_unit_data *pwrseq_pcie_m2_m_unit_deps[] =3D { + &pwrseq_pcie_m2_vregs_unit_data, + NULL +}; + +static const struct pwrseq_unit_data pwrseq_pcie_m2_m_pcie_unit_data =3D { + .name =3D "pcie-enable", + .deps =3D pwrseq_pcie_m2_m_unit_deps, +}; + +static const struct pwrseq_target_data pwrseq_pcie_m2_m_pcie_target_data = =3D { + .name =3D "pcie", + .unit =3D &pwrseq_pcie_m2_m_pcie_unit_data, +}; + +static const struct pwrseq_target_data *pwrseq_pcie_m2_m_targets[] =3D { + &pwrseq_pcie_m2_m_pcie_target_data, + NULL +}; + +static const struct pwrseq_pcie_m2_pdata pwrseq_pcie_m2_m_of_data =3D { + .targets =3D pwrseq_pcie_m2_m_targets, +}; + +static int pwrseq_pcie_m2_match(struct pwrseq_device *pwrseq, + struct device *dev) +{ + struct pwrseq_pcie_m2_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + struct device_node *endpoint __free(device_node) =3D NULL; + + /* + * Traverse the 'remote-endpoint' nodes and check if the remote node's + * parent matches the OF node of 'dev'. + */ + for_each_endpoint_of_node(ctx->of_node, endpoint) { + struct device_node *remote __free(device_node) =3D + of_graph_get_remote_port_parent(endpoint); + if (remote && (remote =3D=3D dev_of_node(dev))) + return PWRSEQ_MATCH_OK; + } + + return PWRSEQ_NO_MATCH; +} + +static void pwrseq_pcie_m2_free_resources(void *data) +{ + struct pwrseq_pcie_m2_ctx *ctx =3D data; + + regulator_bulk_free(ctx->num_vregs, ctx->regs); +} + +static int pwrseq_pcie_m2_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct pwrseq_pcie_m2_ctx *ctx; + struct pwrseq_config config =3D {}; + int ret; + + ctx =3D devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->of_node =3D of_node_get(dev->of_node); + ctx->pdata =3D device_get_match_data(dev); + if (!ctx->pdata) + return dev_err_probe(dev, -ENODEV, + "Failed to obtain platform data\n"); + + /* + * Currently, of_regulator_bulk_get_all() is the only regulator API that + * allows to get all supplies in the devicetree node without manually + * specifying them. + */ + ret =3D of_regulator_bulk_get_all(dev, dev_of_node(dev), &ctx->regs); + if (ret < 0) + return dev_err_probe(dev, ret, + "Failed to get all regulators\n"); + + ctx->num_vregs =3D ret; + + ret =3D devm_add_action_or_reset(dev, pwrseq_pcie_m2_free_resources, ctx); + if (ret) + return ret; + + config.parent =3D dev; + config.owner =3D THIS_MODULE; + config.drvdata =3D ctx; + config.match =3D pwrseq_pcie_m2_match; + config.targets =3D ctx->pdata->targets; + + ctx->pwrseq =3D devm_pwrseq_device_register(dev, &config); + if (IS_ERR(ctx->pwrseq)) + return dev_err_probe(dev, PTR_ERR(ctx->pwrseq), + "Failed to register the power sequencer\n"); + + return 0; +} + +static const struct of_device_id pwrseq_pcie_m2_of_match[] =3D { + { + .compatible =3D "pcie-m2-m-connector", + .data =3D &pwrseq_pcie_m2_m_of_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, pwrseq_pcie_m2_of_match); + +static struct platform_driver pwrseq_pcie_m2_driver =3D { + .driver =3D { + .name =3D "pwrseq-pcie-m2", + .of_match_table =3D pwrseq_pcie_m2_of_match, + }, + .probe =3D pwrseq_pcie_m2_probe, +}; +module_platform_driver(pwrseq_pcie_m2_driver); + +MODULE_AUTHOR("Manivannan Sadhasivam "); +MODULE_DESCRIPTION("Power Sequencing driver for PCIe M.2 connector"); +MODULE_LICENSE("GPL"); --=20 2.51.0