From nobody Mon Feb 9 06:24:54 2026 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E85C34575D for ; Wed, 21 Jan 2026 22:55:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.74 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769036113; cv=none; b=D5aRh9cyfA3ZvSwiUOLV+yf/xBGm7aA3HcajNEtnH+Kmc1FFC3F77E3Ov27zgCxRyfY6yORtp6SDMyjdeZ/mTL0WlVBECkJtWHCKwS/Tsk6SjOqQMBFoHYNYAQT+vdrKAGHONQaRv2WFvcfTNb39aomP/hTlopzMtUKB0CkIkbc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769036113; c=relaxed/simple; bh=Pk/3QwlgAbVKnYQPlfuyPgZDvQuA1ZpRf9r+jYY8pfQ=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=OZ6JAaJnTrmdeD5Qyrp5AwnLkeRd37742u5XI/xEGsuBvc3vbnOs06rW1IqO4aiMt2blSbZk/ukMEpiX/L/mcL5UHcHEV6D2umzIYmtDCZBx0r3Sn8vw3ikOIfos0m972rn7itK5bVqHFMB7gFqTrtcxbwKjiqMuuEZhXNY7SrE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--jmattson.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=blT4m+/B; arc=none smtp.client-ip=209.85.216.74 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--jmattson.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="blT4m+/B" Received: by mail-pj1-f74.google.com with SMTP id 98e67ed59e1d1-34c314af2d4so256677a91.3 for ; Wed, 21 Jan 2026 14:55:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1769036106; x=1769640906; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=HMs2hdc0hNqNKtUHLf8UfyYdyy8QH+t4ULVxDyYCi60=; b=blT4m+/BSEqVX3S/YUpCMTs4CbXTOZtziwFx6dwktDIMfbU/4HF/6yxvArLL+E7QYS w/UXg6qsGfeg/MST3MpH2PGCcFMch2FzDyFTNfPZsK0ob/H2BPHn6OXa6vt9eCYEBZ75 1ba1mwlYf+6nnQmAzzaOWjjQVqTO3YrKatyUCD+eDNk1idPNV57HqOAZVlhFwR7HZfDm sUfAxOXWaAEOtthBlNMwhVcpL6/LfiYgt50dpssSXHRMKKwY8ERR/lN8gK6BpFRLpire HxqrRwrdxA46oChrKwpTSDDGY0GJx+islo3OkWoQ6CfPGkuM5zR0yjyajuVX7ftvsghE zcRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769036106; x=1769640906; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=HMs2hdc0hNqNKtUHLf8UfyYdyy8QH+t4ULVxDyYCi60=; b=fvWGGKy1XYkLMxmjZsuaRymffqqQt5EYn0khSm3L+FnY6J7eFPe3zYrJnRjpCUja9U m6NtPQZVT6U8KYfltuQ99MZBLOFv5o2i2x59KQzoIrJX5IR4L7La+jQYwWfadsLia/XB chAvsVQzCyjdkKlKs66s/r8MJ52frm4ckUGQdFeXBZZMkDPiLwlqjb3BN1oqr43uL9Wg 8Qp40yUQgJfJHnqbPGH726VWDJ3l2F/j1L+TN5IRB6gmf6RO8HTRZlfyEnZ+5ttjiiyF iBxtZvO8JH7+SYdAC6E0LxV9L2Sdpe4uwmRxWpdsUtHWh0EYwMK8Ec3MJtiRpqBdsH6F /GMg== X-Forwarded-Encrypted: i=1; AJvYcCU0eJck3YbdET4C9WiGL6oMw3mWi5cthMzfDsH8KbMFi9+HIb0VPLiSNdyjzy4Qj8Ix46fxfGHQ4caR52A=@vger.kernel.org X-Gm-Message-State: AOJu0YwHjVnfEuxAYQW3Eyu8rSHKvUKERY0cL/YpFYx7rXA/b6SLZgJe zwNktmm7t7kiGmzSEvr33/P0P8hJGNDCl5BYnrpXjrZPKK5Xl3OzCv2aUos3N6uQBkJquSpUh6N wIl5yZR4fdJ00Hg== X-Received: from pjbge20.prod.google.com ([2002:a17:90b:e14:b0:352:c381:4153]) (user=jmattson job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:570f:b0:330:bca5:13d9 with SMTP id 98e67ed59e1d1-352732775a8mr13429526a91.32.1769036106410; Wed, 21 Jan 2026 14:55:06 -0800 (PST) Date: Wed, 21 Jan 2026 14:54:00 -0800 In-Reply-To: <20260121225438.3908422-1-jmattson@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260121225438.3908422-1-jmattson@google.com> X-Mailer: git-send-email 2.52.0.457.g6b5491de43-goog Message-ID: <20260121225438.3908422-3-jmattson@google.com> Subject: [PATCH 2/6] KVM: x86/pmu: Disable HG_ONLY events as appropriate for current vCPU state From: Jim Mattson To: Sean Christopherson , Paolo Bonzini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Peter Zijlstra , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Shuah Khan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org Cc: Jim Mattson Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce amd_pmu_dormant_hg_event(), which determines whether an AMD PMC should be dormant (i.e. not count) based on the guest's Host-Only and Guest-Only event selector bits and the current vCPU state. Update amd_pmu_set_eventsel_hw() to clear the event selector's enable bit when the event is dormant. Signed-off-by: Jim Mattson --- arch/x86/include/asm/perf_event.h | 2 ++ arch/x86/kvm/svm/pmu.c | 23 +++++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index 0d9af4135e0a..7649d79d91a6 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -58,6 +58,8 @@ #define AMD64_EVENTSEL_INT_CORE_ENABLE (1ULL << 36) #define AMD64_EVENTSEL_GUESTONLY (1ULL << 40) #define AMD64_EVENTSEL_HOSTONLY (1ULL << 41) +#define AMD64_EVENTSEL_HG_ONLY \ + (AMD64_EVENTSEL_HOSTONLY | AMD64_EVENTSEL_GUESTONLY) =20 #define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT 37 #define AMD64_EVENTSEL_INT_CORE_SEL_MASK \ diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index 33c139b23a9e..f619417557f9 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -147,10 +147,33 @@ static int amd_pmu_get_msr(struct kvm_vcpu *vcpu, str= uct msr_data *msr_info) return 1; } =20 +static bool amd_pmu_dormant_hg_event(struct kvm_pmc *pmc) +{ + u64 hg_only =3D pmc->eventsel & AMD64_EVENTSEL_HG_ONLY; + struct kvm_vcpu *vcpu =3D pmc->vcpu; + + if (hg_only =3D=3D 0) + /* Not an HG_ONLY event */ + return false; + + if (!(vcpu->arch.efer & EFER_SVME)) + /* HG_ONLY bits are ignored when SVME is clear */ + return false; + + /* Always active if both HG_ONLY bits are set */ + if (hg_only =3D=3D AMD64_EVENTSEL_HG_ONLY) + return false; + + return !!(hg_only & AMD64_EVENTSEL_HOSTONLY) =3D=3D is_guest_mode(vcpu); +} + static void amd_pmu_set_eventsel_hw(struct kvm_pmc *pmc) { pmc->eventsel_hw =3D (pmc->eventsel & ~AMD64_EVENTSEL_HOSTONLY) | AMD64_EVENTSEL_GUESTONLY; + + if (amd_pmu_dormant_hg_event(pmc)) + pmc->eventsel_hw &=3D ~ARCH_PERFMON_EVENTSEL_ENABLE; } =20 static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_inf= o) --=20 2.52.0.457.g6b5491de43-goog