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Peter Anvin" , Peter Zijlstra , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Shuah Khan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org Cc: Jim Mattson Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extract the computation of eventsel_hw from amd_pmu_set_msr() into a separate helper function, amd_pmu_set_eventsel_hw(). No functional change intended. Signed-off-by: Jim Mattson --- arch/x86/kvm/svm/pmu.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index 7aa298eeb072..33c139b23a9e 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -147,6 +147,12 @@ static int amd_pmu_get_msr(struct kvm_vcpu *vcpu, stru= ct msr_data *msr_info) return 1; } =20 +static void amd_pmu_set_eventsel_hw(struct kvm_pmc *pmc) +{ + pmc->eventsel_hw =3D (pmc->eventsel & ~AMD64_EVENTSEL_HOSTONLY) | + AMD64_EVENTSEL_GUESTONLY; +} + static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_inf= o) { struct kvm_pmu *pmu =3D vcpu_to_pmu(vcpu); @@ -166,8 +172,7 @@ static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, struc= t msr_data *msr_info) data &=3D ~pmu->reserved_bits; if (data !=3D pmc->eventsel) { pmc->eventsel =3D data; - pmc->eventsel_hw =3D (data & ~AMD64_EVENTSEL_HOSTONLY) | - AMD64_EVENTSEL_GUESTONLY; + amd_pmu_set_eventsel_hw(pmc); kvm_pmu_request_counter_reprogram(pmc); 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AJvYcCU0eJck3YbdET4C9WiGL6oMw3mWi5cthMzfDsH8KbMFi9+HIb0VPLiSNdyjzy4Qj8Ix46fxfGHQ4caR52A=@vger.kernel.org X-Gm-Message-State: AOJu0YwHjVnfEuxAYQW3Eyu8rSHKvUKERY0cL/YpFYx7rXA/b6SLZgJe zwNktmm7t7kiGmzSEvr33/P0P8hJGNDCl5BYnrpXjrZPKK5Xl3OzCv2aUos3N6uQBkJquSpUh6N wIl5yZR4fdJ00Hg== X-Received: from pjbge20.prod.google.com ([2002:a17:90b:e14:b0:352:c381:4153]) (user=jmattson job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:570f:b0:330:bca5:13d9 with SMTP id 98e67ed59e1d1-352732775a8mr13429526a91.32.1769036106410; Wed, 21 Jan 2026 14:55:06 -0800 (PST) Date: Wed, 21 Jan 2026 14:54:00 -0800 In-Reply-To: <20260121225438.3908422-1-jmattson@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260121225438.3908422-1-jmattson@google.com> X-Mailer: git-send-email 2.52.0.457.g6b5491de43-goog Message-ID: <20260121225438.3908422-3-jmattson@google.com> Subject: [PATCH 2/6] KVM: x86/pmu: Disable HG_ONLY events as appropriate for current vCPU state From: Jim Mattson To: Sean Christopherson , Paolo Bonzini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Peter Zijlstra , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Shuah Khan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org Cc: Jim Mattson Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce amd_pmu_dormant_hg_event(), which determines whether an AMD PMC should be dormant (i.e. not count) based on the guest's Host-Only and Guest-Only event selector bits and the current vCPU state. Update amd_pmu_set_eventsel_hw() to clear the event selector's enable bit when the event is dormant. Signed-off-by: Jim Mattson --- arch/x86/include/asm/perf_event.h | 2 ++ arch/x86/kvm/svm/pmu.c | 23 +++++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index 0d9af4135e0a..7649d79d91a6 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -58,6 +58,8 @@ #define AMD64_EVENTSEL_INT_CORE_ENABLE (1ULL << 36) #define AMD64_EVENTSEL_GUESTONLY (1ULL << 40) #define AMD64_EVENTSEL_HOSTONLY (1ULL << 41) +#define AMD64_EVENTSEL_HG_ONLY \ + (AMD64_EVENTSEL_HOSTONLY | AMD64_EVENTSEL_GUESTONLY) =20 #define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT 37 #define AMD64_EVENTSEL_INT_CORE_SEL_MASK \ diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index 33c139b23a9e..f619417557f9 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -147,10 +147,33 @@ static int amd_pmu_get_msr(struct kvm_vcpu *vcpu, str= uct msr_data *msr_info) return 1; } =20 +static bool amd_pmu_dormant_hg_event(struct kvm_pmc *pmc) +{ + u64 hg_only =3D pmc->eventsel & AMD64_EVENTSEL_HG_ONLY; + struct kvm_vcpu *vcpu =3D pmc->vcpu; + + if (hg_only =3D=3D 0) + /* Not an HG_ONLY event */ + return false; + + if (!(vcpu->arch.efer & EFER_SVME)) + /* HG_ONLY bits are ignored when SVME is clear */ + return false; + + /* Always active if both HG_ONLY bits are set */ + if (hg_only =3D=3D AMD64_EVENTSEL_HG_ONLY) + return false; + + return !!(hg_only & AMD64_EVENTSEL_HOSTONLY) =3D=3D is_guest_mode(vcpu); +} + static void amd_pmu_set_eventsel_hw(struct kvm_pmc *pmc) { pmc->eventsel_hw =3D (pmc->eventsel & ~AMD64_EVENTSEL_HOSTONLY) | AMD64_EVENTSEL_GUESTONLY; + + if (amd_pmu_dormant_hg_event(pmc)) + pmc->eventsel_hw &=3D ~ARCH_PERFMON_EVENTSEL_ENABLE; } =20 static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_inf= o) --=20 2.52.0.457.g6b5491de43-goog From nobody Sat Feb 7 17:48:40 2026 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07A944418C7 for ; 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Wed, 21 Jan 2026 14:55:08 -0800 (PST) Date: Wed, 21 Jan 2026 14:54:01 -0800 In-Reply-To: <20260121225438.3908422-1-jmattson@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260121225438.3908422-1-jmattson@google.com> X-Mailer: git-send-email 2.52.0.457.g6b5491de43-goog Message-ID: <20260121225438.3908422-4-jmattson@google.com> Subject: [PATCH 3/6] KVM: x86/pmu: Track enabled AMD PMCs with Host-Only xor Guest-Only bits set From: Jim Mattson To: Sean Christopherson , Paolo Bonzini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Peter Zijlstra , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Shuah Khan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org Cc: Jim Mattson Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add pmc_hostonly and pmc_guestonly bitmaps to struct kvm_pmu to track which guest-enabled performance counters have just one of the Host-Only and Guest-Only event selector bits set. PMCs that are disabled, have neither HG_ONLY bit set, or have both HG_ONLY bits set are not tracked, because they don't require special handling at vCPU state transitions. Update the bitmaps when the guest writes to an event selector MSR. Signed-off-by: Jim Mattson --- arch/x86/include/asm/kvm_host.h | 4 ++++ arch/x86/kvm/pmu.c | 2 ++ arch/x86/kvm/svm/pmu.c | 28 ++++++++++++++++++++++++++++ 3 files changed, 34 insertions(+) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index ecd4019b84b7..92050f76f84b 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -593,6 +593,10 @@ struct kvm_pmu { DECLARE_BITMAP(pmc_counting_instructions, X86_PMC_IDX_MAX); DECLARE_BITMAP(pmc_counting_branches, X86_PMC_IDX_MAX); =20 + /* AMD only: track PMCs with Host-Only or Guest-Only bits set */ + DECLARE_BITMAP(pmc_hostonly, X86_PMC_IDX_MAX); + DECLARE_BITMAP(pmc_guestonly, X86_PMC_IDX_MAX); + u64 ds_area; u64 pebs_enable; u64 pebs_enable_rsvd; diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index bd6b785cf261..833ee2ecd43f 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -921,6 +921,8 @@ static void kvm_pmu_reset(struct kvm_vcpu *vcpu) pmu->need_cleanup =3D false; =20 bitmap_zero(pmu->reprogram_pmi, X86_PMC_IDX_MAX); + bitmap_zero(pmu->pmc_hostonly, X86_PMC_IDX_MAX); + bitmap_zero(pmu->pmc_guestonly, X86_PMC_IDX_MAX); =20 kvm_for_each_pmc(pmu, pmc, i, pmu->all_valid_pmc_idx) { pmc_stop_counter(pmc); diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index f619417557f9..c06013e2b4b1 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -147,6 +147,33 @@ static int amd_pmu_get_msr(struct kvm_vcpu *vcpu, stru= ct msr_data *msr_info) return 1; } =20 +static void amd_pmu_update_hg_bitmaps(struct kvm_pmc *pmc) +{ + struct kvm_pmu *pmu =3D pmc_to_pmu(pmc); + u64 eventsel =3D pmc->eventsel; + + if (!(eventsel & ARCH_PERFMON_EVENTSEL_ENABLE)) { + bitmap_clear(pmu->pmc_hostonly, pmc->idx, 1); + bitmap_clear(pmu->pmc_guestonly, pmc->idx, 1); + return; + } + + switch (eventsel & AMD64_EVENTSEL_HG_ONLY) { + case AMD64_EVENTSEL_HOSTONLY: + bitmap_set(pmu->pmc_hostonly, pmc->idx, 1); + bitmap_clear(pmu->pmc_guestonly, pmc->idx, 1); + break; + case AMD64_EVENTSEL_GUESTONLY: + bitmap_clear(pmu->pmc_hostonly, pmc->idx, 1); + bitmap_set(pmu->pmc_guestonly, pmc->idx, 1); + break; + default: + bitmap_clear(pmu->pmc_hostonly, pmc->idx, 1); + bitmap_clear(pmu->pmc_guestonly, pmc->idx, 1); + break; + } +} + static bool amd_pmu_dormant_hg_event(struct kvm_pmc *pmc) { u64 hg_only =3D pmc->eventsel & AMD64_EVENTSEL_HG_ONLY; @@ -196,6 +223,7 @@ static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, struc= t msr_data *msr_info) if (data !=3D pmc->eventsel) { pmc->eventsel =3D data; amd_pmu_set_eventsel_hw(pmc); + amd_pmu_update_hg_bitmaps(pmc); kvm_pmu_request_counter_reprogram(pmc); } return 0; --=20 2.52.0.457.g6b5491de43-goog From nobody Sat Feb 7 17:48:40 2026 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E898544A707 for ; Wed, 21 Jan 2026 22:55:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 21 Jan 2026 14:55:09 -0800 (PST) Date: Wed, 21 Jan 2026 14:54:02 -0800 In-Reply-To: <20260121225438.3908422-1-jmattson@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260121225438.3908422-1-jmattson@google.com> X-Mailer: git-send-email 2.52.0.457.g6b5491de43-goog Message-ID: <20260121225438.3908422-5-jmattson@google.com> Subject: [PATCH 4/6] KVM: x86/pmu: [De]activate HG_ONLY PMCs at SVME changes and nested transitions From: Jim Mattson To: Sean Christopherson , Paolo Bonzini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Peter Zijlstra , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Shuah Khan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org Cc: Jim Mattson Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a new function, kvm_pmu_set_pmc_eventsel_hw_enable(), to set or clear the enable bit in eventsel_hw for PMCs identified by a bitmap. Use this function to update Host-Only and Guest-Only counters at the following transitions: - svm_set_efer(): When SVME changes, enable Guest-Only counters if SVME is being cleared (HG_ONLY bits become ignored), or disable them if SVME is being set (L1 is active). - nested_svm_vmrun(): Disable Host-Only counters and enable Guest-Only counters. - nested_svm_vmexit(): Disable Guest-Only counters and enable Host-Only counters. Signed-off-by: Jim Mattson --- arch/x86/include/asm/kvm-x86-pmu-ops.h | 1 + arch/x86/kvm/pmu.c | 7 +++++++ arch/x86/kvm/pmu.h | 4 ++++ arch/x86/kvm/svm/nested.c | 10 ++++++++++ arch/x86/kvm/svm/pmu.c | 17 +++++++++++++++++ arch/x86/kvm/svm/svm.c | 3 +++ 6 files changed, 42 insertions(+) diff --git a/arch/x86/include/asm/kvm-x86-pmu-ops.h b/arch/x86/include/asm/= kvm-x86-pmu-ops.h index f0aa6996811f..7b32796213a0 100644 --- a/arch/x86/include/asm/kvm-x86-pmu-ops.h +++ b/arch/x86/include/asm/kvm-x86-pmu-ops.h @@ -26,6 +26,7 @@ KVM_X86_PMU_OP_OPTIONAL(cleanup) KVM_X86_PMU_OP_OPTIONAL(write_global_ctrl) KVM_X86_PMU_OP(mediated_load) KVM_X86_PMU_OP(mediated_put) +KVM_X86_PMU_OP_OPTIONAL(set_pmc_eventsel_hw_enable) =20 #undef KVM_X86_PMU_OP #undef KVM_X86_PMU_OP_OPTIONAL diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 833ee2ecd43f..1541c201285b 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -1142,6 +1142,13 @@ void kvm_pmu_branch_retired(struct kvm_vcpu *vcpu) } EXPORT_SYMBOL_FOR_KVM_INTERNAL(kvm_pmu_branch_retired); =20 +void kvm_pmu_set_pmc_eventsel_hw_enable(struct kvm_vcpu *vcpu, + unsigned long *bitmap, bool enable) +{ + kvm_pmu_call(set_pmc_eventsel_hw_enable)(vcpu, bitmap, enable); +} +EXPORT_SYMBOL_FOR_KVM_INTERNAL(kvm_pmu_set_pmc_eventsel_hw_enable); + static bool is_masked_filter_valid(const struct kvm_x86_pmu_event_filter *= filter) { u64 mask =3D kvm_pmu_ops.EVENTSEL_EVENT | diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index 0925246731cb..b8be8b6e40d8 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -41,6 +41,8 @@ struct kvm_pmu_ops { void (*mediated_load)(struct kvm_vcpu *vcpu); void (*mediated_put)(struct kvm_vcpu *vcpu); void (*write_global_ctrl)(u64 global_ctrl); + void (*set_pmc_eventsel_hw_enable)(struct kvm_vcpu *vcpu, + unsigned long *bitmap, bool enable); =20 const u64 EVENTSEL_EVENT; const int MAX_NR_GP_COUNTERS; @@ -258,6 +260,8 @@ void kvm_pmu_destroy(struct kvm_vcpu *vcpu); int kvm_vm_ioctl_set_pmu_event_filter(struct kvm *kvm, void __user *argp); void kvm_pmu_instruction_retired(struct kvm_vcpu *vcpu); void kvm_pmu_branch_retired(struct kvm_vcpu *vcpu); +void kvm_pmu_set_pmc_eventsel_hw_enable(struct kvm_vcpu *vcpu, + unsigned long *bitmap, bool enable); void kvm_mediated_pmu_load(struct kvm_vcpu *vcpu); void kvm_mediated_pmu_put(struct kvm_vcpu *vcpu); =20 diff --git a/arch/x86/kvm/svm/nested.c b/arch/x86/kvm/svm/nested.c index de90b104a0dd..edaa76e38417 100644 --- a/arch/x86/kvm/svm/nested.c +++ b/arch/x86/kvm/svm/nested.c @@ -28,6 +28,7 @@ #include "smm.h" #include "cpuid.h" #include "lapic.h" +#include "pmu.h" #include "svm.h" #include "hyperv.h" =20 @@ -1054,6 +1055,11 @@ int nested_svm_vmrun(struct kvm_vcpu *vcpu) if (enter_svm_guest_mode(vcpu, vmcb12_gpa, vmcb12, true)) goto out_exit_err; =20 + kvm_pmu_set_pmc_eventsel_hw_enable(vcpu, + vcpu_to_pmu(vcpu)->pmc_hostonly, false); + kvm_pmu_set_pmc_eventsel_hw_enable(vcpu, + vcpu_to_pmu(vcpu)->pmc_guestonly, true); + if (nested_svm_merge_msrpm(vcpu)) goto out; =20 @@ -1137,6 +1143,10 @@ int nested_svm_vmexit(struct vcpu_svm *svm) =20 /* Exit Guest-Mode */ leave_guest_mode(vcpu); + kvm_pmu_set_pmc_eventsel_hw_enable(vcpu, + vcpu_to_pmu(vcpu)->pmc_hostonly, true); + kvm_pmu_set_pmc_eventsel_hw_enable(vcpu, + vcpu_to_pmu(vcpu)->pmc_guestonly, false); svm->nested.vmcb12_gpa =3D 0; WARN_ON_ONCE(svm->nested.nested_run_pending); =20 diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index c06013e2b4b1..85155d65fa38 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -316,6 +316,22 @@ static void amd_mediated_pmu_put(struct kvm_vcpu *vcpu) wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, pmu->global_status); } =20 +static void amd_pmu_set_pmc_eventsel_hw_enable(struct kvm_vcpu *vcpu, + unsigned long *bitmap, + bool enable) +{ + struct kvm_pmu *pmu =3D vcpu_to_pmu(vcpu); + struct kvm_pmc *pmc; + int i; + + kvm_for_each_pmc(pmu, pmc, i, bitmap) { + if (enable) + pmc->eventsel_hw |=3D ARCH_PERFMON_EVENTSEL_ENABLE; + else + pmc->eventsel_hw &=3D ~ARCH_PERFMON_EVENTSEL_ENABLE; + } +} + struct kvm_pmu_ops amd_pmu_ops __initdata =3D { .rdpmc_ecx_to_pmc =3D amd_rdpmc_ecx_to_pmc, .msr_idx_to_pmc =3D amd_msr_idx_to_pmc, @@ -329,6 +345,7 @@ struct kvm_pmu_ops amd_pmu_ops __initdata =3D { .is_mediated_pmu_supported =3D amd_pmu_is_mediated_pmu_supported, .mediated_load =3D amd_mediated_pmu_load, .mediated_put =3D amd_mediated_pmu_put, + .set_pmc_eventsel_hw_enable =3D amd_pmu_set_pmc_eventsel_hw_enable, =20 .EVENTSEL_EVENT =3D AMD64_EVENTSEL_EVENT, .MAX_NR_GP_COUNTERS =3D KVM_MAX_NR_AMD_GP_COUNTERS, diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 7803d2781144..953089b38921 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -244,6 +244,9 @@ int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) if (svm_gp_erratum_intercept && !sev_guest(vcpu->kvm)) set_exception_intercept(svm, GP_VECTOR); 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Peter Anvin" , Peter Zijlstra , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Shuah Khan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org Cc: Jim Mattson Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If the vCPU advertises SVM and uses the mediated PMU, allow the guest to set the Host-Only and Guest-Only bits in the event selector MSRs. Signed-off-by: Jim Mattson --- arch/x86/kvm/svm/pmu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index 85155d65fa38..a1eeb7b38219 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -262,8 +262,13 @@ static void amd_pmu_refresh(struct kvm_vcpu *vcpu) pmu->global_status_rsvd =3D pmu->global_ctrl_rsvd; } =20 - pmu->counter_bitmask[KVM_PMC_GP] =3D BIT_ULL(48) - 1; pmu->reserved_bits =3D 0xfffffff000280000ull; + if (guest_cpu_cap_has(vcpu, X86_FEATURE_SVM) && + kvm_vcpu_has_mediated_pmu(vcpu)) + /* Allow Host-Only and Guest-Only bits */ + pmu->reserved_bits &=3D ~AMD64_EVENTSEL_HG_ONLY; + + pmu->counter_bitmask[KVM_PMC_GP] =3D BIT_ULL(48) - 1; pmu->raw_event_mask =3D AMD64_RAW_EVENT_MASK; /* not applicable to AMD; but clean them to prevent any fall out */ pmu->counter_bitmask[KVM_PMC_FIXED] =3D 0; --=20 2.52.0.457.g6b5491de43-goog From nobody Sat Feb 7 17:48:40 2026 Received: from mail-pl1-f201.google.com (mail-pl1-f201.google.com [209.85.214.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41A5B44D682 for ; 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Wed, 21 Jan 2026 14:55:12 -0800 (PST) Date: Wed, 21 Jan 2026 14:54:04 -0800 In-Reply-To: <20260121225438.3908422-1-jmattson@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260121225438.3908422-1-jmattson@google.com> X-Mailer: git-send-email 2.52.0.457.g6b5491de43-goog Message-ID: <20260121225438.3908422-7-jmattson@google.com> Subject: [PATCH 6/6] KVM: selftests: x86: Add svm_pmu_hg_test for HG_ONLY bits From: Jim Mattson To: Sean Christopherson , Paolo Bonzini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Peter Zijlstra , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Shuah Khan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org Cc: Jim Mattson Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a selftest to verify KVM correctly virtualizes the AMD PMU Host-Only (bit 41) and Guest-Only (bit 40) event selector bits across all relevant SVM state transitions. For both Guest-Only and Host-Only counters, verify that: 1. SVME=3D0: counter counts (HG_ONLY bits ignored) 2. Set SVME=3D1: counter behavior changes based on HG_ONLY bit 3. VMRUN to L2: counter behavior switches (guest vs host mode) 4. VMEXIT to L1: counter behavior switches back 5. Clear SVME=3D0: counter counts (HG_ONLY bits ignored again) Also confirm that setting both bits is the same as setting neither bit. Signed-off-by: Jim Mattson --- tools/testing/selftests/kvm/Makefile.kvm | 1 + .../selftests/kvm/x86/svm_pmu_hg_test.c | 297 ++++++++++++++++++ 2 files changed, 298 insertions(+) create mode 100644 tools/testing/selftests/kvm/x86/svm_pmu_hg_test.c diff --git a/tools/testing/selftests/kvm/Makefile.kvm b/tools/testing/selft= ests/kvm/Makefile.kvm index e88699e227dd..06ba85d97618 100644 --- a/tools/testing/selftests/kvm/Makefile.kvm +++ b/tools/testing/selftests/kvm/Makefile.kvm @@ -112,6 +112,7 @@ TEST_GEN_PROGS_x86 +=3D x86/svm_vmcall_test TEST_GEN_PROGS_x86 +=3D x86/svm_int_ctl_test TEST_GEN_PROGS_x86 +=3D x86/svm_nested_shutdown_test TEST_GEN_PROGS_x86 +=3D x86/svm_nested_soft_inject_test +TEST_GEN_PROGS_x86 +=3D x86/svm_pmu_hg_test TEST_GEN_PROGS_x86 +=3D x86/tsc_scaling_sync TEST_GEN_PROGS_x86 +=3D x86/sync_regs_test TEST_GEN_PROGS_x86 +=3D x86/ucna_injection_test diff --git a/tools/testing/selftests/kvm/x86/svm_pmu_hg_test.c b/tools/test= ing/selftests/kvm/x86/svm_pmu_hg_test.c new file mode 100644 index 000000000000..e811b4c1a818 --- /dev/null +++ b/tools/testing/selftests/kvm/x86/svm_pmu_hg_test.c @@ -0,0 +1,297 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * KVM nested SVM PMU Host-Only/Guest-Only test + * + * Copyright (C) 2026, Google LLC. + * + * Test that KVM correctly virtualizes the AMD PMU Host-Only (bit 41) and + * Guest-Only (bit 40) event selector bits across all SVM state transition= s. + * + * For Guest-Only counters: + * 1. SVME=3D0: counter counts (HG_ONLY bits ignored) + * 2. Set SVME=3D1: counter stops (in host mode) + * 3. VMRUN to L2: counter counts (in guest mode) + * 4. VMEXIT to L1: counter stops (back to host mode) + * 5. Clear SVME=3D0: counter counts (HG_ONLY bits ignored) + * + * For Host-Only counters: + * 1. SVME=3D0: counter counts (HG_ONLY bits ignored) + * 2. Set SVME=3D1: counter counts (in host mode) + * 3. VMRUN to L2: counter stops (in guest mode) + * 4. VMEXIT to L1: counter counts (back to host mode) + * 5. Clear SVME=3D0: counter counts (HG_ONLY bits ignored) + */ +#include +#include +#include +#include + +#include "test_util.h" +#include "kvm_util.h" +#include "processor.h" +#include "svm_util.h" +#include "pmu.h" + +#define L2_GUEST_STACK_SIZE 256 + +#define MSR_F15H_PERF_CTL0 0xc0010200 +#define MSR_F15H_PERF_CTR0 0xc0010201 + +#define AMD64_EVENTSEL_GUESTONLY BIT_ULL(40) +#define AMD64_EVENTSEL_HOSTONLY BIT_ULL(41) + +#define EVENTSEL_RETIRED_INSNS (ARCH_PERFMON_EVENTSEL_OS | \ + ARCH_PERFMON_EVENTSEL_USR | \ + ARCH_PERFMON_EVENTSEL_ENABLE | \ + AMD_ZEN_INSTRUCTIONS_RETIRED) + +#define LOOP_INSNS 1000 + +static __always_inline void run_instruction_loop(void) +{ + unsigned int i; + + for (i =3D 0; i < LOOP_INSNS; i++) + __asm__ __volatile__("nop"); +} + +static __always_inline uint64_t run_and_measure(void) +{ + uint64_t count_before, count_after; + + count_before =3D rdmsr(MSR_F15H_PERF_CTR0); + run_instruction_loop(); + count_after =3D rdmsr(MSR_F15H_PERF_CTR0); + + return count_after - count_before; +} + +struct hg_test_data { + uint64_t l2_delta; + bool l2_done; +}; + +static struct hg_test_data *hg_data; + +static void l2_guest_code(void) +{ + hg_data->l2_delta =3D run_and_measure(); + hg_data->l2_done =3D true; + vmmcall(); +} + +/* + * Test Guest-Only counter across all relevant state transitions. + */ +static void l1_guest_code_guestonly(struct svm_test_data *svm, + struct hg_test_data *data) +{ + unsigned long l2_guest_stack[L2_GUEST_STACK_SIZE]; + struct vmcb *vmcb =3D svm->vmcb; + uint64_t eventsel, delta; + + hg_data =3D data; + + eventsel =3D EVENTSEL_RETIRED_INSNS | AMD64_EVENTSEL_GUESTONLY; + wrmsr(MSR_F15H_PERF_CTL0, eventsel); + wrmsr(MSR_F15H_PERF_CTR0, 0); + + /* Step 1: SVME=3D0; HG_ONLY ignored */ + wrmsr(MSR_EFER, rdmsr(MSR_EFER) & ~EFER_SVME); + delta =3D run_and_measure(); + GUEST_ASSERT_NE(delta, 0); + + /* Step 2: Set SVME=3D1; Guest-Only counter stops */ + wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_SVME); + delta =3D run_and_measure(); + GUEST_ASSERT_EQ(delta, 0); + + /* Step 3: VMRUN to L2; Guest-Only counter counts */ + generic_svm_setup(svm, l2_guest_code, + &l2_guest_stack[L2_GUEST_STACK_SIZE]); + vmcb->control.intercept &=3D ~(1ULL << INTERCEPT_MSR_PROT); + + run_guest(vmcb, svm->vmcb_gpa); + + GUEST_ASSERT_EQ(vmcb->control.exit_code, SVM_EXIT_VMMCALL); + GUEST_ASSERT(data->l2_done); + GUEST_ASSERT_NE(data->l2_delta, 0); + + /* Step 4: After VMEXIT to L1; Guest-Only counter stops */ + delta =3D run_and_measure(); + GUEST_ASSERT_EQ(delta, 0); + + /* Step 5: Clear SVME; HG_ONLY ignored */ + wrmsr(MSR_EFER, rdmsr(MSR_EFER) & ~EFER_SVME); + delta =3D run_and_measure(); + GUEST_ASSERT_NE(delta, 0); + + GUEST_DONE(); +} + +/* + * Test Host-Only counter across all relevant state transitions. + */ +static void l1_guest_code_hostonly(struct svm_test_data *svm, + struct hg_test_data *data) +{ + unsigned long l2_guest_stack[L2_GUEST_STACK_SIZE]; + struct vmcb *vmcb =3D svm->vmcb; + uint64_t eventsel, delta; + + hg_data =3D data; + + eventsel =3D EVENTSEL_RETIRED_INSNS | AMD64_EVENTSEL_HOSTONLY; + wrmsr(MSR_F15H_PERF_CTL0, eventsel); + wrmsr(MSR_F15H_PERF_CTR0, 0); + + + /* Step 1: SVME=3D0; HG_ONLY ignored */ + wrmsr(MSR_EFER, rdmsr(MSR_EFER) & ~EFER_SVME); + delta =3D run_and_measure(); + GUEST_ASSERT_NE(delta, 0); + + /* Step 2: Set SVME=3D1; Host-Only counter still counts */ + wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_SVME); + delta =3D run_and_measure(); + GUEST_ASSERT_NE(delta, 0); + + /* Step 3: VMRUN to L2; Host-Only counter stops */ + generic_svm_setup(svm, l2_guest_code, + &l2_guest_stack[L2_GUEST_STACK_SIZE]); + vmcb->control.intercept &=3D ~(1ULL << INTERCEPT_MSR_PROT); + + run_guest(vmcb, svm->vmcb_gpa); + + GUEST_ASSERT_EQ(vmcb->control.exit_code, SVM_EXIT_VMMCALL); + GUEST_ASSERT(data->l2_done); + GUEST_ASSERT_EQ(data->l2_delta, 0); + + /* Step 4: After VMEXIT to L1; Host-Only counter counts */ + delta =3D run_and_measure(); + GUEST_ASSERT_NE(delta, 0); + + /* Step 5: Clear SVME; HG_ONLY ignored */ + wrmsr(MSR_EFER, rdmsr(MSR_EFER) & ~EFER_SVME); + delta =3D run_and_measure(); + GUEST_ASSERT_NE(delta, 0); + + GUEST_DONE(); +} + +/* + * Test that both bits set is the same as neither bit set (always counts). + */ +static void l1_guest_code_both_bits(struct svm_test_data *svm, + struct hg_test_data *data) +{ + unsigned long l2_guest_stack[L2_GUEST_STACK_SIZE]; + struct vmcb *vmcb =3D svm->vmcb; + uint64_t eventsel, delta; + + hg_data =3D data; + + eventsel =3D EVENTSEL_RETIRED_INSNS | + AMD64_EVENTSEL_HOSTONLY | AMD64_EVENTSEL_GUESTONLY; + wrmsr(MSR_F15H_PERF_CTL0, eventsel); + wrmsr(MSR_F15H_PERF_CTR0, 0); + + /* Step 1: SVME=3D0 */ + wrmsr(MSR_EFER, rdmsr(MSR_EFER) & ~EFER_SVME); + delta =3D run_and_measure(); + GUEST_ASSERT_NE(delta, 0); + + /* Step 2: Set SVME=3D1 */ + wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_SVME); + delta =3D run_and_measure(); + GUEST_ASSERT_NE(delta, 0); + + /* Step 3: VMRUN to L2 */ + generic_svm_setup(svm, l2_guest_code, + &l2_guest_stack[L2_GUEST_STACK_SIZE]); + vmcb->control.intercept &=3D ~(1ULL << INTERCEPT_MSR_PROT); + + run_guest(vmcb, svm->vmcb_gpa); + + GUEST_ASSERT_EQ(vmcb->control.exit_code, SVM_EXIT_VMMCALL); + GUEST_ASSERT(data->l2_done); + GUEST_ASSERT_NE(data->l2_delta, 0); + + /* Step 4: After VMEXIT to L1 */ + delta =3D run_and_measure(); + GUEST_ASSERT_NE(delta, 0); + + /* Step 5: Clear SVME */ + wrmsr(MSR_EFER, rdmsr(MSR_EFER) & ~EFER_SVME); + delta =3D run_and_measure(); + GUEST_ASSERT_NE(delta, 0); + + GUEST_DONE(); +} + +static void l1_guest_code(struct svm_test_data *svm, struct hg_test_data *= data, + int test_num) +{ + switch (test_num) { + case 0: + l1_guest_code_guestonly(svm, data); + break; + case 1: + l1_guest_code_hostonly(svm, data); + break; + case 2: + l1_guest_code_both_bits(svm, data); + break; + } +} + +static void run_test(int test_number, const char *test_name) +{ + struct hg_test_data *data_hva; + vm_vaddr_t svm_gva, data_gva; + struct kvm_vcpu *vcpu; + struct kvm_vm *vm; + struct ucall uc; + + pr_info("Testing: %s\n", test_name); + + vm =3D vm_create_with_one_vcpu(&vcpu, l1_guest_code); + + vcpu_alloc_svm(vm, &svm_gva); + + data_gva =3D vm_vaddr_alloc_page(vm); + data_hva =3D addr_gva2hva(vm, data_gva); + memset(data_hva, 0, sizeof(*data_hva)); + + vcpu_args_set(vcpu, 3, svm_gva, data_gva, test_number); + + for (;;) { + vcpu_run(vcpu); + TEST_ASSERT_KVM_EXIT_REASON(vcpu, KVM_EXIT_IO); + + switch (get_ucall(vcpu, &uc)) { + case UCALL_ABORT: + REPORT_GUEST_ASSERT(uc); + /* NOT REACHED */ + case UCALL_DONE: + pr_info(" PASSED\n"); + kvm_vm_free(vm); + return; + default: + TEST_FAIL("Unknown ucall %lu", uc.cmd); + } + } +} + +int main(int argc, char *argv[]) +{ + TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_SVM)); + TEST_REQUIRE(kvm_is_pmu_enabled()); + TEST_REQUIRE(get_kvm_amd_param_bool("enable_mediated_pmu")); + + run_test(0, "Guest-Only counter across all transitions"); + run_test(1, "Host-Only counter across all transitions"); + run_test(2, "Both HG_ONLY bits set (always count)"); + + return 0; +} --=20 2.52.0.457.g6b5491de43-goog