From nobody Sat Feb 7 06:39:33 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E05053C199E; Wed, 21 Jan 2026 19:06:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769022397; cv=none; b=MfxH0KqlSIrZMefLOXkRr18O4thC9z6QujDUEpr737fdUMN058fy6Y3wTTJwGnO4dXM/IsCppCqA/5DOY+nzJlfuuxLKgQk1iNnyw3ANhe7QRzuFlKZnngi1/LVYDffL7rhTjwWc9EM/pYuIyghoe5o1hJh95LI07u5wU7vMO80= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769022397; c=relaxed/simple; bh=6TOl+ancS3QXn338RWCqLR4HIk4+OJ77QHGJPreqdi0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=o/UtJR5xyPexswhCUoawIFbo7jKTVeNb52AQkxA0yBuCqloX1APVE02cMdqfbuzKFbzKE+y7MkePx6AZFHzcGqEc6DR5NbZQtLz4fi7gynVCgRYySykgPnkQWt8IQktGXzV4Jt44YhopowvdRhNbts4WPy42HAr2hm61Bd71yXY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 77C641516; Wed, 21 Jan 2026 11:06:27 -0800 (PST) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 055F13F632; Wed, 21 Jan 2026 11:06:30 -0800 (PST) From: Yeoreum Yun To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org Cc: catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, broonie@kernel.org, oliver.upton@linux.dev, miko.lenczewski@arm.com, kevin.brodsky@arm.com, ardb@kernel.org, suzuki.poulose@arm.com, lpieralisi@kernel.org, scott@os.amperecomputing.com, joey.gouly@arm.com, yuzenghui@huawei.com, pbonzini@redhat.com, shuah@kernel.org, mark.rutland@arm.com, arnd@arndb.de, Yeoreum Yun Subject: [PATCH v12 2/7] arm64: cpufeature: add FEAT_LSUI Date: Wed, 21 Jan 2026 19:06:17 +0000 Message-Id: <20260121190622.2218669-3-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260121190622.2218669-1-yeoreum.yun@arm.com> References: <20260121190622.2218669-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since Armv9.6, FEAT_LSUI introduces load/store instructions that allow privileged code to access user memory without clearing the PSTATE.PAN bit. Add CPU feature detection for FEAT_LSUI and enable its use when FEAT_PAN is present so that removes the need for SW_PAN handling when using LSUI instructions. Signed-off-by: Yeoreum Yun --- arch/arm64/kernel/cpufeature.c | 27 +++++++++++++++++++++++++++ arch/arm64/tools/cpucaps | 1 + 2 files changed, 28 insertions(+) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index c840a93b9ef9..b41ea479c868 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -280,6 +280,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar2[] = =3D { =20 static const struct arm64_ftr_bits ftr_id_aa64isar3[] =3D { ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_E= L1_FPRCVT_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL= 1_LSUI_SHIFT, 4, ID_AA64ISAR3_EL1_LSUI_NI), ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_E= L1_LSFE_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_E= L1_FAMINMAX_SHIFT, 4, 0), ARM64_FTR_END, @@ -2509,6 +2510,23 @@ test_has_gicv5_legacy(const struct arm64_cpu_capabil= ities *entry, int scope) return !!(read_sysreg_s(SYS_ICC_IDR0_EL1) & ICC_IDR0_EL1_GCIE_LEGACY); } =20 +#ifdef CONFIG_ARM64_LSUI +static bool has_lsui(const struct arm64_cpu_capabilities *entry, int scope) +{ + if (!has_cpuid_feature(entry, scope)) + return false; + + /* + * A CPU that supports LSUI should also support FEAT_PAN, + * so that SW_PAN handling is not required. + */ + if (WARN_ON(!__system_matches_cap(ARM64_HAS_PAN))) + return false; + + return true; +} +#endif + static const struct arm64_cpu_capabilities arm64_features[] =3D { { .capability =3D ARM64_ALWAYS_BOOT, @@ -3148,6 +3166,15 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .matches =3D has_cpuid_feature, ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, XNX, IMP) }, +#ifdef CONFIG_ARM64_LSUI + { + .desc =3D "Unprivileged Load Store Instructions (LSUI)", + .capability =3D ARM64_HAS_LSUI, + .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, + .matches =3D has_lsui, + ARM64_CPUID_FIELDS(ID_AA64ISAR3_EL1, LSUI, IMP) + }, +#endif {}, }; =20 diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 0fac75f01534..4b2f7f3f2b80 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -46,6 +46,7 @@ HAS_HCX HAS_LDAPR HAS_LPA2 HAS_LSE_ATOMICS +HAS_LSUI HAS_MOPS HAS_NESTED_VIRT HAS_BBML2_NOABORT --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}