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charset="utf-8" The three instances of CCI found on the QCS8300 are functionally the same as on a number of existing Qualcomm SoCs. Introduce a new SoC-specific compatible string "qcom,qcs8300-cci" with a common fallback. Signed-off-by: Nihal Kumar Gupta Signed-off-by: Vikram Sharma Reviewed-by: Bryan O'Donoghue Acked-by: Rob Herring (Arm) Reviewed-by: Vladimir Zapolskiy --- Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Docu= mentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml index a3fe1eea6aec..399a09409e07 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml @@ -28,6 +28,7 @@ properties: - enum: - qcom,kaanapali-cci - qcom,qcm2290-cci + - qcom,qcs8300-cci - qcom,sa8775p-cci - qcom,sc7280-cci - qcom,sc8280xp-cci @@ -133,6 +134,7 @@ allOf: enum: - qcom,kaanapali-cci - qcom,qcm2290-cci + - qcom,qcs8300-cci - qcom,sm8750-cci then: properties: --=20 2.34.1 From nobody Mon Feb 9 04:04:33 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 57571345CC0; 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charset="utf-8" Qualcomm QCS8300 SoC contains three Camera Control Interface (CCI). Compared to Lemans, the key difference is in SDA/SCL GPIO assignments and number of CCIs. Signed-off-by: Nihal Kumar Gupta Co-developed-by: Ravi Shankar Signed-off-by: Ravi Shankar Co-developed-by: Vishal Verma Signed-off-by: Vishal Verma Co-developed-by: Suresh Vankadara Signed-off-by: Suresh Vankadara Signed-off-by: Vikram Sharma Reviewed-by: Vladimir Zapolskiy Reviewed-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/monaco.dtsi | 303 +++++++++++++++++++++++++++ 1 file changed, 303 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qco= m/monaco.dtsi index 5d2df4305d1c..634337611012 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -5319,6 +5319,117 @@ videocc: clock-controller@abf0000 { #power-domain-cells =3D <1>; }; =20 + cci0: cci@ac13000 { + compatible =3D "qcom,qcs8300-cci", "qcom,msm8996-cci"; + reg =3D <0x0 0x0ac13000 0x0 0x1000>; + + interrupts =3D ; + + clocks =3D <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names =3D "cpas_ahb", + "cci"; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 =3D <&cci0_0_default &cci0_1_default>; + pinctrl-1 =3D <&cci0_0_sleep &cci0_1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci1: cci@ac14000 { + compatible =3D "qcom,qcs8300-cci", "qcom,msm8996-cci"; + reg =3D <0x0 0x0ac14000 0x0 0x1000>; + + interrupts =3D ; + + clocks =3D <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names =3D "cpas_ahb", + "cci"; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 =3D <&cci1_0_default &cci1_1_default>; + pinctrl-1 =3D <&cci1_0_sleep &cci1_1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci2: cci@ac15000 { + compatible =3D "qcom,qcs8300-cci", "qcom,msm8996-cci"; + reg =3D <0x0 0x0ac15000 0x0 0x1000>; + + interrupts =3D ; + + clocks =3D <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_2_CLK>; + clock-names =3D "cpas_ahb", + "cci"; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 =3D <&cci2_0_default &cci2_1_default>; + pinctrl-1 =3D <&cci2_0_sleep &cci2_1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci2_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci2_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + camss: isp@ac78000 { compatible =3D "qcom,qcs8300-camss"; =20 @@ -5876,6 +5987,198 @@ tlmm: pinctrl@f100000 { #interrupt-cells =3D <2>; wakeup-parent =3D <&pdc>; =20 + cci0_0_default: cci0-0-default-state { + sda-pins { + pins =3D "gpio57"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + scl-pins { + pins =3D "gpio58"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + }; + + cci0_0_sleep: cci0-0-sleep-state { + sda-pins { + pins =3D "gpio57"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio58"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci0_1_default: cci0-1-default-state { + sda-pins { + pins =3D "gpio29"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + scl-pins { + pins =3D "gpio30"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + }; + + cci0_1_sleep: cci0-1-sleep-state { + sda-pins { + pins =3D "gpio29"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio30"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci1_0_default: cci1-0-default-state { + sda-pins { + pins =3D "gpio59"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + scl-pins { + pins =3D "gpio60"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + }; + + cci1_0_sleep: cci1-0-sleep-state { + sda-pins { + pins =3D "gpio59"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio60"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci1_1_default: cci1-1-default-state { + sda-pins { + pins =3D "gpio31"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + scl-pins { + pins =3D "gpio32"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + }; + + cci1_1_sleep: cci1-1-sleep-state { + sda-pins { + pins =3D "gpio31"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio32"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci2_0_default: cci2-0-default-state { + sda-pins { + pins =3D "gpio61"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + scl-pins { + pins =3D "gpio62"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + }; + + cci2_0_sleep: cci2-0-sleep-state { + sda-pins { + pins =3D "gpio61"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio62"; + function =3D "cci_i2c_scl"; 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charset="utf-8" Define pinctrl definitions to enable camera master clocks on Monaco. Signed-off-by: Nihal Kumar Gupta Signed-off-by: Vikram Sharma Reviewed-by: Konrad Dybcio Reviewed-by: Vladimir Zapolskiy --- arch/arm64/boot/dts/qcom/monaco.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qco= m/monaco.dtsi index 634337611012..0c0d7fa09cfb 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -5987,6 +5987,27 @@ tlmm: pinctrl@f100000 { #interrupt-cells =3D <2>; wakeup-parent =3D <&pdc>; =20 + cam0_default: cam0-default-state { + pins =3D "gpio67"; + function =3D "cam_mclk"; + drive-strength =3D <2>; + bias-disable; + }; + + cam1_default: cam1-default-state { + pins =3D "gpio68"; + function =3D "cam_mclk"; + drive-strength =3D <2>; + bias-disable; + }; + + cam2_default: cam2-default-state { + pins =3D "gpio69"; + function =3D "cam_mclk"; + drive-strength =3D <2>; + bias-disable; + }; + cci0_0_default: cci0-0-default-state { sda-pins { pins =3D "gpio57"; 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charset="utf-8" Define three fixed regulators for camera AVDD rails, each gpio-controlled with corresponding pinctrl definitions. Signed-off-by: Nihal Kumar Gupta Signed-off-by: Vikram Sharma Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/monaco-evk.dts | 51 +++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/= qcom/monaco-evk.dts index 565418b86b2a..65c1b49c6dfb 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -77,6 +77,36 @@ platform { }; }; }; + + vreg_cam0_2p8: vreg-cam0-2p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_cam0_2p8"; + startup-delay-us =3D <10000>; + enable-active-high; + gpio =3D <&tlmm 73 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&cam0_avdd_2v8_en_default>; + pinctrl-names =3D "default"; + }; + + vreg_cam1_2p8: vreg-cam1-2p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_cam1_2p8"; + startup-delay-us =3D <10000>; + enable-active-high; + gpio =3D <&tlmm 74 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&cam1_avdd_2v8_en_default>; + pinctrl-names =3D "default"; + }; + + vreg_cam2_2p8: vreg-cam2-2p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_cam2_2p8"; + startup-delay-us =3D <10000>; + enable-active-high; + gpio =3D <&tlmm 75 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&cam2_avdd_2v8_en_default>; + pinctrl-names =3D "default"; + }; }; =20 &apps_rsc { @@ -564,6 +594,27 @@ perst-pins { }; }; =20 + cam0_avdd_2v8_en_default: cam0-avdd-2v8-en-state { + pins =3D "gpio73"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + cam1_avdd_2v8_en_default: cam1-avdd-2v8-en-state { + pins =3D "gpio74"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + cam2_avdd_2v8_en_default: cam2-avdd-2v8-en-state { + pins =3D "gpio75"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + qup_i2c15_default: qup-i2c15-state { pins =3D "gpio91", "gpio92"; function =3D "qup1_se7"; --=20 2.34.1 From nobody Mon Feb 9 04:04:33 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 337FF3D3CFC; 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charset="utf-8" Monaco EVK board does not include a camera sensor in its default hardware configuration. Introducing a device tree overlay to support optional integration of the IMX577 sensor via CSIPHY1. Camera reset is handled through an I2C expander, and power is enabled via TLMM GPIO74. An example media-ctl pipeline for the imx577 is: media-ctl --reset media-ctl -V '"imx577 3-001a":0[fmt:SRGGB10/4056x3040 field:none]' media-ctl -V '"msm_csiphy1":0[fmt:SRGGB10/4056x3040]' media-ctl -V '"msm_csid0":0[fmt:SRGGB10/4056x3040]' media-ctl -V '"msm_vfe0_rdi0":0[fmt:SRGGB10/4056x3040]' media-ctl -l '"msm_csiphy1":1->"msm_csid0":0[1]' media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]' yavta -B capture-mplane -c -I -n 5 -f SRGGB10P -s 4056x3040 -F /dev/video1 Signed-off-by: Nihal Kumar Gupta Co-developed-by: Ravi Shankar Signed-off-by: Ravi Shankar Co-developed-by: Vishal Verma Signed-off-by: Vishal Verma Signed-off-by: Vikram Sharma Reviewed-by: Vladimir Zapolskiy Reviewed-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/Makefile | 4 ++ .../dts/qcom/monaco-evk-camera-imx577.dtso | 66 +++++++++++++++++++ 2 files changed, 70 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/monaco-evk-camera-imx577.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index f80b5d9cf1e8..4c348cf62d59 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -45,6 +45,10 @@ lemans-evk-el2-dtbs :=3D lemans-evk.dtb lemans-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk-el2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D milos-fairphone-fp6.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D monaco-evk.dtb + +monaco-evk-camera-imx577-dtbs :=3D monaco-evk.dtb monaco-evk-camera-imx577= .dtbo +dtb-$(CONFIG_ARCH_QCOM) +=3D monaco-evk-camera-imx577.dtb + dtb-$(CONFIG_ARCH_QCOM) +=3D msm8216-samsung-fortuna3g.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-alcatel-idol347.dtb diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-camera-imx577.dtso b/arch/= arm64/boot/dts/qcom/monaco-evk-camera-imx577.dtso new file mode 100644 index 000000000000..0d5ccd020e6e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-evk-camera-imx577.dtso @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&camss { + vdda-phy-supply =3D <&vreg_l4a>; + vdda-pll-supply =3D <&vreg_l5a>; + + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@1 { + reg =3D <1>; + + csiphy1_ep: endpoint { + data-lanes =3D <0 1 2 3>; + remote-endpoint =3D <&imx577_ep1>; + }; + }; + }; +}; + +&cci1 { + pinctrl-0 =3D <&cci1_0_default>; + pinctrl-1 =3D <&cci1_0_sleep>; + + status =3D "okay"; +}; + +&cci1_i2c0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + camera@1a { + compatible =3D "sony,imx577"; + reg =3D <0x1a>; + + reset-gpios =3D <&expander2 1 GPIO_ACTIVE_LOW>; + pinctrl-0 =3D <&cam1_default>; + pinctrl-names =3D "default"; + + clocks =3D <&camcc CAM_CC_MCLK1_CLK>; + assigned-clocks =3D <&camcc CAM_CC_MCLK1_CLK>; + assigned-clock-rates =3D <24000000>; + + avdd-supply =3D <&vreg_cam1_2p8>; + + port { + imx577_ep1: endpoint { + link-frequencies =3D /bits/ 64 <600000000>; + data-lanes =3D <1 2 3 4>; + remote-endpoint =3D <&csiphy1_ep>; + }; + }; + }; +}; --=20 2.34.1