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Wed, 21 Jan 2026 07:30:30 -0800 From: Kartik Rajput To: , , , , , , , , , CC: Kartik Rajput Subject: [PATCH v9 4/4] i2c: tegra: Add support for Tegra410 Date: Wed, 21 Jan 2026 21:00:11 +0530 Message-ID: <20260121153012.92243-5-kkartik@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260121153012.92243-1-kkartik@nvidia.com> References: <20260121153012.92243-1-kkartik@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000A6732:EE_|IA1PR12MB6162:EE_ X-MS-Office365-Filtering-Correlation-Id: 1f82bc9f-b0f0-4e23-ee65-08de59021999 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?gS4/JYX2LgBXYNevRlRKYbZsDsRD1x+PcV9mnhLFBI2IjXTsw6oYYB6W7pPT?= =?us-ascii?Q?jvu4KlTQpUJ/GXTnChFfiLoXbdPqwxcMhHtAyRfFhzvbImQJPakkV3DsrzWo?= =?us-ascii?Q?JI+j/x7POih8IFrw1SqJR8nAJ34DJ52MMYVgNNkT01xIyihBZ2Sr2mXLqG58?= =?us-ascii?Q?yAmz4/zKWxwsshLtbiXiOEzOWnsaiJM26AFfwgHZYvYYj38iX8S85d561br8?= =?us-ascii?Q?Z+0N4u4Vl5VcufqOoaGc2OnuqjNSEXJ1/CaBnyjLAdqddtUfimn71K06gb4I?= =?us-ascii?Q?+fQfcCclkALJC9I9ZViAZV2tWyTFRqajq7gzJ0NMB+afzseaicXYm96BXG66?= =?us-ascii?Q?pSsdb9fKtoXkK78kwnp4Vpa4XmI7iYhoLQ0Z8M6nMlje2eAXTQNGYNsqNkS9?= =?us-ascii?Q?kCO5+iQDRxjK4eL4Z1krszjEJvGKN71EVrqR+n3uqHDT+Y2VyrA2tTxzEqKp?= =?us-ascii?Q?DmKE5WR97j4+pp1ocRgcIn0HODIxs2oFOvy7px/o80vkE+zN3k0C5DZ8T1da?= =?us-ascii?Q?VtMcJxYNn0XNjyGxQiF9V8VfWNfJzQzfDYFEBpie7wqcGbmDzQIPTJ1L+fAz?= =?us-ascii?Q?05uzRIKPief5F8XS7juMloWjh52PJ7vhdbITTiYbRlOtgF98Y5A8TeTcL8/3?= =?us-ascii?Q?mBKmDV+Li1//kkuMRZcQV65V+dNh/C63xrYfDLS944UAEuD7oRMnv6RRPO1o?= =?us-ascii?Q?M05VHDOvkvokj9nqliLyMkoOdBCoQZ8GWspqwoCYKFb6nSwSjaEjAr02tq2h?= =?us-ascii?Q?Q2OPSnaGFW2JoByYawjZEvyJrZcEUEt1r3jo40LiIKshdrtFO9YiB7QdXL+/?= =?us-ascii?Q?nbSTgjZgO7FpQ93nBzIdaiFQWy6ogrd9+u3o8XDM+RDJ6s5kjUtu3ihtzHs6?= =?us-ascii?Q?/ZWHmy+FuyIXGkcBuss2aZJawOKI+DxfmnHrn7SlvNRbYqn2GH2juB2AnuI6?= =?us-ascii?Q?v14SCir44L2Ug5/KAH/cqIq3xxOIMhxAm1ZNuFgby/+VeJNOSHfGAoslVIBs?= =?us-ascii?Q?Y+NA+8Gt9CkLjPlio8rJ0x7XbNtuyET876LhQGQh9rLLQAvVF8/Xnj7CRQoD?= =?us-ascii?Q?VbbN+Na/UupwEiT/f+IF2kuyCLMQ2BcToJXE6NFUTYTe7i6yrq7AzaQG/xlr?= =?us-ascii?Q?w2BIHVppo6jqev6jEAby/QY/7CancsdZ2YSgYAXr7c3KAnt5Eu4mF7fJpyMf?= =?us-ascii?Q?z4eo+TldMH5zn8ofmpomeyKhM8siKc1Tx+OgwqPmikkszRuQhhyXhNAdSs4A?= =?us-ascii?Q?PhYMIcK8wnhNiDYkS5Zdo10GnQ5g26hsLu7NCYH0/gOA0499Hq4L1cD8lwOM?= =?us-ascii?Q?IEAnkH4DqL9omBx/oyOx6dSbbkiNKuTwdJSQOelqpVN8K241IVmmlMlXSHOP?= =?us-ascii?Q?pqY8dDOP9KsmvXXA0JLf+V93+PfRthUn68RB+A9MtsPIIriEGQyb1JwA3SOh?= =?us-ascii?Q?S6lZh/Va7Rv4sQKBazqFqrl6rP79B/91TKxg1LcFFwn5wIl8j2m/TEMc2Ntz?= =?us-ascii?Q?TVgUYIWjUUQX1PE8KA37Qcj642e2eZ9b3wVsrlC6pmQCFgr83V1B+7acengA?= =?us-ascii?Q?D4NCR0OccaU8SI7RJCHmfy/L3ycmjO988B+dIT43Ps1FYs+KA2zjqcuWPuWr?= =?us-ascii?Q?0zHy3ReER7g8exQQ77JDYMfcVohZdmzK2bSdWUqXXEdfPqZwn3HniRkGH+lO?= =?us-ascii?Q?QUywmVbbaOmFMDCpzwVGOApqcmE=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jan 2026 15:31:08.5940 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1f82bc9f-b0f0-4e23-ee65-08de59021999 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A6732.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6162 Content-Type: text/plain; charset="utf-8" Add support for the Tegra410 SoC, which has 4 I2C controllers. The controllers are feature-equivalent to Tegra264; only the register offsets differ. Signed-off-by: Kartik Rajput --- Changes in v3: * Updated timing parameters for Tegra410. --- drivers/i2c/busses/i2c-tegra.c | 63 ++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index d845b8782f4f..3c672f05373c 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -275,6 +275,34 @@ static const struct tegra_i2c_regs tegra264_i2c_regs = =3D { .sw_mutex =3D 0x0ec, }; =20 +static const struct tegra_i2c_regs tegra410_i2c_regs =3D { + .cnfg =3D 0x000, + .status =3D 0x01c, + .sl_cnfg =3D 0x020, + .sl_addr1 =3D 0x02c, + .sl_addr2 =3D 0x030, + .tx_fifo =3D 0x054, + .rx_fifo =3D 0x058, + .packet_transfer_status =3D 0x05c, + .fifo_control =3D 0x060, + .fifo_status =3D 0x064, + .int_mask =3D 0x068, + .int_status =3D 0x06c, + .clk_divisor =3D 0x070, + .bus_clear_cnfg =3D 0x088, + .bus_clear_status =3D 0x08c, + .config_load =3D 0x090, + .clken_override =3D 0x094, + .interface_timing_0 =3D 0x098, + .interface_timing_1 =3D 0x09c, + .hs_interface_timing_0 =3D 0x0a0, + .hs_interface_timing_1 =3D 0x0a4, + .master_reset_cntrl =3D 0x0ac, + .mst_fifo_control =3D 0x0b8, + .mst_fifo_status =3D 0x0bc, + .sw_mutex =3D 0x0f0, +}; + /* * msg_end_type: The bus control which needs to be sent at end of transfer. * @MSG_END_STOP: Send stop pulse. @@ -2085,6 +2113,40 @@ static const struct tegra_i2c_hw_feature tegra264_i2= c_hw =3D { .regs =3D &tegra264_i2c_regs, }; =20 +static const struct tegra_i2c_hw_feature tegra410_i2c_hw =3D { + .has_continue_xfer_support =3D true, + .has_per_pkt_xfer_complete_irq =3D true, + .clk_divisor_hs_mode =3D 1, + .clk_divisor_std_mode =3D 0x3f, + .clk_divisor_fast_mode =3D 0x2c, + .clk_divisor_fast_plus_mode =3D 0x11, + .has_config_load_reg =3D true, + .has_multi_master_mode =3D true, + .has_slcg_override_reg =3D true, + .has_mst_fifo =3D true, + .has_mst_reset =3D true, + .quirks =3D &tegra194_i2c_quirks, + .supports_bus_clear =3D true, + .has_apb_dma =3D false, + .tlow_std_mode =3D 0x8, + .thigh_std_mode =3D 0x7, + .tlow_fast_mode =3D 0x2, + .thigh_fast_mode =3D 0x2, + .tlow_fastplus_mode =3D 0x2, + .thigh_fastplus_mode =3D 0x2, + .tlow_hs_mode =3D 0x8, + .thigh_hs_mode =3D 0x6, + .setup_hold_time_std_mode =3D 0x08080808, + .setup_hold_time_fast_mode =3D 0x02020202, + .setup_hold_time_fastplus_mode =3D 0x02020202, + .setup_hold_time_hs_mode =3D 0x0b0b0b, + .has_interface_timing_reg =3D true, + .enable_hs_mode_support =3D true, + .has_mutex =3D true, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, + .regs =3D &tegra410_i2c_regs, +}; + static const struct of_device_id tegra_i2c_of_match[] =3D { { .compatible =3D "nvidia,tegra264-i2c", .data =3D &tegra264_i2c_hw, }, { .compatible =3D "nvidia,tegra256-i2c", .data =3D &tegra256_i2c_hw, }, @@ -2395,6 +2457,7 @@ static const struct acpi_device_id tegra_i2c_acpi_mat= ch[] =3D { {.id =3D "NVDA0101", .driver_data =3D (kernel_ulong_t)&tegra210_i2c_hw}, {.id =3D "NVDA0201", .driver_data =3D (kernel_ulong_t)&tegra186_i2c_hw}, {.id =3D "NVDA0301", .driver_data =3D (kernel_ulong_t)&tegra194_i2c_hw}, + {.id =3D "NVDA2017", .driver_data =3D (kernel_ulong_t)&tegra410_i2c_hw}, { } }; MODULE_DEVICE_TABLE(acpi, tegra_i2c_acpi_match); --=20 2.43.0