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Peter Anvin" Subject: [PATCH 4/4] x86/mtrr: Drop cache_disable_lock Date: Wed, 21 Jan 2026 15:11:06 +0100 Message-ID: <20260121141106.755458-5-jgross@suse.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260121141106.755458-1-jgross@suse.com> References: <20260121141106.755458-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spamd-Result: default: False [-3.01 / 50.00]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; R_DKIM_ALLOW(-0.20)[suse.com:s=susede1]; MIME_GOOD(-0.10)[text/plain]; MX_GOOD(-0.01)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,imap1.dmz-prg2.suse.org:rdns,suse.com:mid,suse.com:dkim,suse.com:email]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[2a07:de40:b281:104:10:150:64:97:from]; FUZZY_RATELIMITED(0.00)[rspamd.com]; MIME_TRACE(0.00)[0:+]; FROM_HAS_DN(0.00)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCPT_COUNT_SEVEN(0.00)[8]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[2a07:de40:b281:106:10:150:64:167:received]; RCVD_COUNT_TWO(0.00)[2]; RCVD_TLS_ALL(0.00)[]; TO_DN_SOME(0.00)[]; DKIM_TRACE(0.00)[suse.com:+] X-Spam-Flag: NO X-Spam-Score: -3.01 X-Rspamd-Queue-Id: 74DBE3368F X-Rspamd-Action: no action X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Spam-Level: Content-Type: text/plain; charset="utf-8" Now that no global state is modified under cache_disable_lock, it can be dropped. All required serialization is done via mtrr_mutex and cpus_read_lock(), ensuring that only one set_mtrr() can be active at any time and that this call can't run concurrently with CPU bringup. The main advantages are a faster boot of machines with lots of CPUs, and avoiding hard lockups on those machines in case mtrr_generic_set_state() takes too long in uncached mode, resulting in other CPUs waiting for seconds to get the cache_disable_lock. This has been seen happening in more than 1% of all boots on an Intel machine with 960 CPUs. With this patch applied boot was always successful. Signed-off-by: Juergen Gross --- I was considering applying a "Fixes:" tag, but this could only reference the initial kernel git commit, as MTRR support predates git, and the problem existed since MTRRs became a thing. arch/x86/kernel/cpu/mtrr/generic.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/= generic.c index bfd5a7ba17cb..280f9491ec2e 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -970,7 +970,6 @@ static void mtrr_enable(struct mtrr_work_state *state) * The caller must ensure that local interrupts are disabled and * are reenabled after cache_enable() has been called. */ -static DEFINE_RAW_SPINLOCK(cache_disable_lock); =20 /* * Cache flushing is the most time-consuming step when programming the @@ -984,17 +983,9 @@ static void maybe_flush_caches(void) } =20 static void cache_disable(struct mtrr_work_state *state) - __acquires(cache_disable_lock) { unsigned long cr0; =20 - /* - * This is not ideal since the cache is only flushed/disabled - * for this CPU while the MTRRs are changed, but changing this - * requires more invasive changes to the way the kernel boots. - */ - raw_spin_lock(&cache_disable_lock); - /* Enter the no-fill (CD=3D1, NW=3D0) cache mode and flush caches. */ cr0 =3D read_cr0() | X86_CR0_CD; write_cr0(cr0); @@ -1018,7 +1009,6 @@ static void cache_disable(struct mtrr_work_state *sta= te) } =20 static void cache_enable(struct mtrr_work_state *state) - __releases(cache_disable_lock) { /* Flush TLBs (no need to flush caches - they are disabled) */ count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); @@ -1033,8 +1023,6 @@ static void cache_enable(struct mtrr_work_state *stat= e) /* Restore value of CR4 */ if (cpu_feature_enabled(X86_FEATURE_PGE)) __write_cr4(state->cr4); - - raw_spin_unlock(&cache_disable_lock); } =20 void mtrr_generic_set_state(void) --=20 2.52.0