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Peter Anvin" Subject: [PATCH 3/4] x86/mtrr: Add a prepare_set hook to mtrr_ops Date: Wed, 21 Jan 2026 15:11:05 +0100 Message-ID: <20260121141106.755458-4-jgross@suse.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260121141106.755458-1-jgross@suse.com> References: <20260121141106.755458-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spamd-Result: default: False [-3.01 / 50.00]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; R_DKIM_ALLOW(-0.20)[suse.com:s=susede1]; MIME_GOOD(-0.10)[text/plain]; MX_GOOD(-0.01)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,imap1.dmz-prg2.suse.org:rdns,suse.com:mid,suse.com:dkim,suse.com:email]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; FUZZY_RATELIMITED(0.00)[rspamd.com]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[2a07:de40:b281:104:10:150:64:97:from]; MIME_TRACE(0.00)[0:+]; FROM_HAS_DN(0.00)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCPT_COUNT_SEVEN(0.00)[8]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[2a07:de40:b281:106:10:150:64:167:received]; RCVD_COUNT_TWO(0.00)[2]; RCVD_TLS_ALL(0.00)[]; TO_DN_SOME(0.00)[]; DKIM_TRACE(0.00)[suse.com:+] X-Spam-Flag: NO X-Spam-Score: -3.01 X-Rspamd-Queue-Id: B8D015BD14 X-Rspamd-Action: no action X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Spam-Level: Content-Type: text/plain; charset="utf-8" In order to prepare dropping the cache_disable_lock add a new hook to struct mtrr_ops, allowing to set some global state before calling the .set hook on all active CPUs. Move setting of mtrr_state.var_ranges[] from generic_set_mtrr() to the new prepare hook. Note that doing that only once outside the cache_disable_lock is fine, as generic_set_mtrr() is called via set_mtrr() only and this call is protected by mtrr_mutex. Signed-off-by: Juergen Gross --- arch/x86/kernel/cpu/mtrr/generic.c | 32 ++++++++++++++++++++++++------ arch/x86/kernel/cpu/mtrr/mtrr.c | 3 +++ arch/x86/kernel/cpu/mtrr/mtrr.h | 2 ++ 3 files changed, 31 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/= generic.c index ac95b19b01d0..bfd5a7ba17cb 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -1057,6 +1057,31 @@ void mtrr_generic_set_state(void) cache_enable(&state); } =20 +/** + * generic_prepare_set_mtrr - set variable MTRR register data in mtrr_state + * + * @reg: The register to set. + * @base: The base address of the region. + * @size: The size of the region. If this is 0 the region is disabled. + * @type: The type of the region. + * + * Returns nothing. + */ +static void generic_prepare_set_mtrr(unsigned int reg, unsigned long base, + unsigned long size, mtrr_type type) +{ + struct mtrr_var_range *vr =3D &mtrr_state.var_ranges[reg]; + + if (size =3D=3D 0) { + memset(vr, 0, sizeof(struct mtrr_var_range)); + } else { + vr->base_lo =3D base << PAGE_SHIFT | type; + vr->base_hi =3D (base >> (32 - PAGE_SHIFT)) & ~phys_hi_rsvd; + vr->mask_lo =3D -size << PAGE_SHIFT | MTRR_PHYSMASK_V; + vr->mask_hi =3D (-size >> (32 - PAGE_SHIFT)) & ~phys_hi_rsvd; + } +} + /** * generic_set_mtrr - set variable MTRR register on the local CPU. * @@ -1085,13 +1110,7 @@ static void generic_set_mtrr(unsigned int reg, unsig= ned long base, * clear the relevant mask register to disable a range. */ mtrr_wrmsr(MTRRphysMask_MSR(reg), 0, 0); - memset(vr, 0, sizeof(struct mtrr_var_range)); } else { - vr->base_lo =3D base << PAGE_SHIFT | type; - vr->base_hi =3D (base >> (32 - PAGE_SHIFT)) & ~phys_hi_rsvd; - vr->mask_lo =3D -size << PAGE_SHIFT | MTRR_PHYSMASK_V; - vr->mask_hi =3D (-size >> (32 - PAGE_SHIFT)) & ~phys_hi_rsvd; - mtrr_wrmsr(MTRRphysBase_MSR(reg), vr->base_lo, vr->base_hi); mtrr_wrmsr(MTRRphysMask_MSR(reg), vr->mask_lo, vr->mask_hi); } @@ -1156,6 +1175,7 @@ int positive_have_wrcomb(void) const struct mtrr_ops generic_mtrr_ops =3D { .get =3D generic_get_mtrr, .get_free_region =3D generic_get_free_region, + .prepare_set =3D generic_prepare_set_mtrr, .set =3D generic_set_mtrr, .validate_add_page =3D generic_validate_add_page, .have_wrcomb =3D generic_have_wrcomb, diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtr= r.c index 4b3d492afe17..32948fb4e742 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -175,6 +175,9 @@ static void set_mtrr(unsigned int reg, unsigned long ba= se, unsigned long size, .smp_type =3D type }; =20 + if (mtrr_if->prepare_set) + mtrr_if->prepare_set(reg, base, size, type); + stop_machine_cpuslocked(mtrr_rendezvous_handler, &data, cpu_online_mask); =20 generic_rebuild_map(); diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.h b/arch/x86/kernel/cpu/mtrr/mtr= r.h index 2de3bd2f95d1..4d32c095cfc5 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.h +++ b/arch/x86/kernel/cpu/mtrr/mtrr.h @@ -17,6 +17,8 @@ extern unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES]; =20 struct mtrr_ops { u32 var_regs; + void (*prepare_set)(unsigned int reg, unsigned long base, + unsigned long size, mtrr_type type); void (*set)(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type); void (*get)(unsigned int reg, unsigned long *base, --=20 2.52.0