From nobody Sat Feb 7 08:45:35 2026 Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazon11013020.outbound.protection.outlook.com [40.107.201.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D9E97481648; Wed, 21 Jan 2026 13:25:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.201.20 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769001943; cv=fail; b=tiXsul8YvaeOYNIWSkXHY8M7BnjYLx8d0qE6SJe+FbSuwqh9YvWhCEI1A9WmQz5eoDvZABh6Vwm05LgUMsz9gdQ6EzMDZc6vjeyrRFTNOJJuxRUn9CdKyfYabqJfPPpN85irUdqqUqMyxAxO8k6zEdJxXZyviQ2MpZRB5aUn2lM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769001943; c=relaxed/simple; bh=7lg0ZUpVBBUwu45A2ozNf7UAFS0n6CVxZHs03yH8XEs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ovzTNrJRDI/sxCstNmyzbi5w6/0QZ7+1DqBRRwdGgCaieOTVQTCgEftqaidWnsEPEzt3abqle8EKW/trryDC/VzEEUD7Toc5T4zkdBhPkBgifWkRR2riYKAh/sc1x/BW3UcW4go4/KhpPdFvvYNqpvJ6DHcWu8WEEszH8oc+eBY= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=b8cM0Nxp; arc=fail smtp.client-ip=40.107.201.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="b8cM0Nxp" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=KUA69IfgyuGtOUEbpemfEAQPRvUJ6XT2uZPAQOzHDaJX4wipLMI2cDg+Kxg3tUNGy6ahrQiRSeL4k/0klQcxg/RfB/o5itcNLeK3g3kAuL2p6H05ZljhFyrdfmx9D9qOZjwd16aaJoejs8eBLTC2CmCVFkFalIRdlOJrbZH38Ix39sMdhJVrnd60ePNog/ROoUrUNl++UT812T05RpZBfpaWbBLkqKFiHI7vGrr4lGodT0kKhRfsfrXrKi64r9mrL1Hn6KhL22ewQd+P5Hih10jbFH30uEBD7ZoNpp9BtAXtYVvD2bL40eK6mi3kOqlbfEv4R/HT4vM1y0qdy6IdoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=dRYbl2kJUG1ynG6HXSDab2+jpirleYMcRPmzGUFEex0=; b=pl2xitVzYqw1K08FBebjhfoYL3CZ/KFWbY2Xfuql7KCBPtzS7FdBaKriCQYi7ll44FYG4MKOmNeIBXy9aeBQEjAhOIReXM2JrYYWLQVo+I7ROTZpUp5M89GLfCLizhTM0ye6NdV5YXZaAQBZZtgLVqbZGwo52HGcHPwK+UP9H+N3+u0U1eLj8Md+zZENkvmMclKapGsVSORpw4L5er16UqVnmPzyYkioRFaeQxOATUvVs41gUFayICtRUBn4nZQel62vq3knnovPiBr+lHQH34EaLrcbW3WWIq+HSyx+38c1qZ9jnlP1sNRyJ75l5L4+lRtby4rolDf1C32gFik9MA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 198.47.21.195) smtp.rcpttodomain=gondor.apana.org.au smtp.mailfrom=ti.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=ti.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=dRYbl2kJUG1ynG6HXSDab2+jpirleYMcRPmzGUFEex0=; b=b8cM0NxpQarDbJm5jclYO2YHtYPdjNXYMpPe4yveiwJJYt6htk2/My+nAKCz3xOA6LLha2aQKLKkiJBhWzkVN4EpPx3k01mKeHCpLVbeuYpNlUjRgoiS37TfdCRoihRRDpSOep1BVg5WHZWH7zam0uI4g4c0EeKgMk1mXacu/OA= Received: from SN7P220CA0005.NAMP220.PROD.OUTLOOK.COM (2603:10b6:806:123::10) by SA1PR10MB5685.namprd10.prod.outlook.com (2603:10b6:806:23d::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9542.9; Wed, 21 Jan 2026 13:25:36 +0000 Received: from SN1PEPF0002636A.namprd02.prod.outlook.com (2603:10b6:806:123:cafe::98) by SN7P220CA0005.outlook.office365.com (2603:10b6:806:123::10) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9542.10 via Frontend Transport; Wed, 21 Jan 2026 13:25:36 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 198.47.21.195) smtp.mailfrom=ti.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ti.com; Received-SPF: Pass (protection.outlook.com: domain of ti.com designates 198.47.21.195 as permitted sender) receiver=protection.outlook.com; client-ip=198.47.21.195; helo=flwvzet201.ext.ti.com; pr=C Received: from flwvzet201.ext.ti.com (198.47.21.195) by SN1PEPF0002636A.mail.protection.outlook.com (10.167.241.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9542.4 via Frontend Transport; Wed, 21 Jan 2026 13:25:34 +0000 Received: from DFLE210.ent.ti.com (10.64.6.68) by flwvzet201.ext.ti.com (10.248.192.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 21 Jan 2026 07:24:42 -0600 Received: from DFLE203.ent.ti.com (10.64.6.61) by DFLE210.ent.ti.com (10.64.6.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 21 Jan 2026 07:24:42 -0600 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE203.ent.ti.com (10.64.6.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Wed, 21 Jan 2026 07:24:42 -0600 Received: from pratham-Workstation-PC (pratham-workstation-pc.dhcp.ti.com [10.24.69.191]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 60LDOeiA2926860; Wed, 21 Jan 2026 07:24:41 -0600 From: T Pratham To: T Pratham , Herbert Xu , "David S. Miller" CC: Manorit Chawdhry , Kamlesh Gurudasani , Shiva Tripathi , Kavitha Malarvizhi , Vishal Mahaveer , Praneeth Bajjuri , , Subject: [PATCH v2 1/3] crypto: ti - Add support for SHA224/256/384/512 in DTHEv2 driver Date: Wed, 21 Jan 2026 18:54:05 +0530 Message-ID: <20260121132408.743777-2-t-pratham@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260121132408.743777-1-t-pratham@ti.com> References: <20260121132408.743777-1-t-pratham@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636A:EE_|SA1PR10MB5685:EE_ X-MS-Office365-Filtering-Correlation-Id: 08b96c39-9da5-494c-5e09-08de58f08f24 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026|7142099003; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?788gnEVxcn9Qo3noseBSlMo0UJnIMbH0Wuby7rwMyeMzeax6FOifNj9gqWKD?= =?us-ascii?Q?TWTy8wn4AhIPJkS4LHcNUPv7Ami04P7J5ErOE9p7ypFdhhqBqCxvzemfjQU3?= =?us-ascii?Q?3H9Lg5vlg4YnxqPAzgDNJiNaYukZvwZrmaH/F+2ueBEilH34W0Q8Q5jMGy9Z?= =?us-ascii?Q?MqjTLQrjgX8yspYl97CxbY3Y1cFLExNGrwOU/T2H327ekYbblNNOQni4CSyB?= =?us-ascii?Q?a70tOQLGuCqHUj5mJzCkWAkOXmutCcZQsnzyYc95qAlJZ5J/bcvRTwfFQ9RR?= =?us-ascii?Q?4mzJSG/UT9sX+1lg7kwSQe9l9C3mmBnPOFHVsnx5Bbp+c6XDqsO9QQCOmSwp?= =?us-ascii?Q?muexsDPyKhhPbc/ijagQ35EQzTn2nnkmEKWic5PMKzk+/oLJsimFYGysWj/J?= =?us-ascii?Q?cGwpxn2JTXlfPH9xK8xO6O/XebkxcKzMnwsMTNcOmyD5rCwNDIBWumZ6wHAA?= =?us-ascii?Q?PlfN0DAjy3C6w3J+sm8VI4XBV8lGssd+DVrD2VMhx8tIsV981cJHWCbdxoI6?= =?us-ascii?Q?diw63bxfAZf8XQ9adypSsawm2TUsWDOWErgXdotGHxCPAkZAEbCgzRfqysW2?= =?us-ascii?Q?8a8taGu5hloNPvaflqfjiCrK8qjcdFpYNlYbgc8G/zN0LxM9c6zIoC2fnC51?= =?us-ascii?Q?S59D4qY9SkzHdGvtEBSJcOj0tF8UrhBnAMWvbRZ6AqScSPFT3VyCh6M5pMNy?= =?us-ascii?Q?9cm6aEuv/+lngxDbN2dA3T4Fi2CU7OoyOaITHlYkqvN6f8qdCXvdpf4sCmHl?= =?us-ascii?Q?3d3VX0OsX2WGo3GnEQiOcwY/c+G59TT2pJmU7AmCXriwX2qv6xWArCE4GDDs?= =?us-ascii?Q?X2u2ifSISCQZhQ3p8BeCPgHtbQJH29vZ/VUFna0YpuwnII10cv4KBO2XWVag?= =?us-ascii?Q?mdZ/oNP+76TUeT5iCkUUrYV/DFXUDZvKqjAAV6DYtL2WQnYPlek0JqITI5nb?= =?us-ascii?Q?6bxeQXKzgDaK0XfFLp1ddr7nZ5YSuQsgKfcVeJa6UUB4kCHyL9oT8GDJTa5V?= =?us-ascii?Q?mArPNo+BuFLTb+GfWEnVSCr25rM5yz5xyzfE6VzN9K00GdgX5xi5AGELI9U+?= =?us-ascii?Q?wk+F8UaBYlfl5AqSplFgf6yz3TN18bOtESi5O7cf5x+DeFGdsyBDnKh3+cqN?= =?us-ascii?Q?QseEqVGitKduhfeRzcx+nB4jcVz0hbTapaxW/Pe/KXpyhytPA44gq5n1CJMB?= =?us-ascii?Q?r402QxkgDRyBPCn0mgegGOcaFWuEu6hD/ejPDIOIirxVuIxZtazmqs/W6dhI?= =?us-ascii?Q?B00I42zP/aBVZa7kQQtsV8mGBk7BV3zmGgclqYsBrJQLw6uI4ucZ5uE1SQsd?= =?us-ascii?Q?1I2lUrUTf5qHpFhz+JugImtxSitTURT7VDdujtusY3HX2eNg7VSWINgcyq7m?= =?us-ascii?Q?XE6I+HxtLZJ6Zv3rHn0hEjmC5CU+acJHs0CypEsAv4TRTgVXEH74We3XEXA0?= =?us-ascii?Q?ujh0ZikfDnzvZaIvbVOqW6scMXSj1lQx3Ozk1Sa95HPM/ZSaDaawPQc3IcDk?= =?us-ascii?Q?8vy4zw92T/Xa5dJwlEmwDqQlL95M9G665at14SIKPRBdEMeBdgPvt1Id22i4?= =?us-ascii?Q?YnzCt5baT/fpkpaVZa4+0mo/4mRMds0wctobYPnJzh1NIPEZ7GnGm7KX78VU?= =?us-ascii?Q?QA=3D=3D?= X-Forefront-Antispam-Report: CIP:198.47.21.195;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:flwvzet201.ext.ti.com;PTR:ErrorRetry;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026)(7142099003);DIR:OUT;SFP:1101; X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jan 2026 13:25:34.9368 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 08b96c39-9da5-494c-5e09-08de58f08f24 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.195];Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR10MB5685 Content-Type: text/plain; charset="utf-8" Add support for SHA224, SHA256, SHA384, SHA512 algorithms in the Hashing Engine of the DTHEv2 hardware cryptographic engine. Signed-off-by: T Pratham --- drivers/crypto/ti/Kconfig | 2 + drivers/crypto/ti/Makefile | 2 +- drivers/crypto/ti/dthev2-aes.c | 6 +- drivers/crypto/ti/dthev2-common.c | 37 +- drivers/crypto/ti/dthev2-common.h | 47 ++- drivers/crypto/ti/dthev2-hash.c | 591 ++++++++++++++++++++++++++++++ 6 files changed, 671 insertions(+), 14 deletions(-) create mode 100644 drivers/crypto/ti/dthev2-hash.c diff --git a/drivers/crypto/ti/Kconfig b/drivers/crypto/ti/Kconfig index 1a3a571ac8cef..90af2c7cb1c55 100644 --- a/drivers/crypto/ti/Kconfig +++ b/drivers/crypto/ti/Kconfig @@ -10,6 +10,8 @@ config CRYPTO_DEV_TI_DTHEV2 select CRYPTO_XTS select CRYPTO_GCM select CRYPTO_CCM + select CRYPTO_SHA256 + select CRYPTO_SHA512 select SG_SPLIT help This enables support for the TI DTHE V2 hw cryptography engine diff --git a/drivers/crypto/ti/Makefile b/drivers/crypto/ti/Makefile index b883078f203d7..a90bc97a52321 100644 --- a/drivers/crypto/ti/Makefile +++ b/drivers/crypto/ti/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_CRYPTO_DEV_TI_DTHEV2) +=3D dthev2.o -dthev2-objs :=3D dthev2-common.o dthev2-aes.o +dthev2-objs :=3D dthev2-common.o dthev2-aes.o dthev2-hash.o diff --git a/drivers/crypto/ti/dthev2-aes.c b/drivers/crypto/ti/dthev2-aes.c index c1f4170cbb558..22f4bbc9cc987 100644 --- a/drivers/crypto/ti/dthev2-aes.c +++ b/drivers/crypto/ti/dthev2-aes.c @@ -520,7 +520,7 @@ static int dthe_aes_run(struct crypto_engine *engine, v= oid *areq) } =20 local_bh_disable(); - crypto_finalize_skcipher_request(dev_data->engine, req, ret); + crypto_finalize_skcipher_request(engine, req, ret); local_bh_enable(); return 0; } @@ -564,7 +564,7 @@ static int dthe_aes_crypt(struct skcipher_request *req) return 0; } =20 - engine =3D dev_data->engine; + engine =3D dev_data->aes_engine; return crypto_transfer_skcipher_request_to_engine(engine, req); } =20 @@ -1170,7 +1170,7 @@ static int dthe_aead_crypt(struct aead_request *req) (ctx->aes_mode =3D=3D DTHE_AES_CCM && !is_zero_ctr)) return dthe_aead_do_fallback(req); =20 - engine =3D dev_data->engine; + engine =3D dev_data->aes_engine; return crypto_transfer_aead_request_to_engine(engine, req); } =20 diff --git a/drivers/crypto/ti/dthev2-common.c b/drivers/crypto/ti/dthev2-c= ommon.c index a2ad79bec105a..af9b68ebdd023 100644 --- a/drivers/crypto/ti/dthev2-common.c +++ b/drivers/crypto/ti/dthev2-common.c @@ -96,6 +96,9 @@ static int dthe_dma_init(struct dthe_data *dev_data) goto err_dma_sha_tx; } =20 + // Do AES Rx and Tx channel config here because it is invariant of AES mo= de + // SHA Tx channel config is done before DMA transfer depending on hashing= algorithm + memzero_explicit(&cfg, sizeof(cfg)); =20 cfg.src_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; @@ -130,11 +133,17 @@ static int dthe_dma_init(struct dthe_data *dev_data) =20 static int dthe_register_algs(void) { - return dthe_register_aes_algs(); + int ret =3D 0; + + ret |=3D dthe_register_hash_algs(); + ret |=3D dthe_register_aes_algs(); + + return ret; } =20 static void dthe_unregister_algs(void) { + dthe_unregister_hash_algs(); dthe_unregister_aes_algs(); } =20 @@ -163,15 +172,26 @@ static int dthe_probe(struct platform_device *pdev) if (ret) goto probe_dma_err; =20 - dev_data->engine =3D crypto_engine_alloc_init(dev, 1); - if (!dev_data->engine) { + dev_data->aes_engine =3D crypto_engine_alloc_init(dev, 1); + if (!dev_data->aes_engine) { ret =3D -ENOMEM; goto probe_engine_err; } + dev_data->hash_engine =3D crypto_engine_alloc_init(dev, 1); + if (!dev_data->hash_engine) { + ret =3D -ENOMEM; + goto probe_hash_engine_err; + } + + ret =3D crypto_engine_start(dev_data->aes_engine); + if (ret) { + dev_err(dev, "Failed to start crypto engine for AES\n"); + goto probe_engine_start_err; + } =20 - ret =3D crypto_engine_start(dev_data->engine); + ret =3D crypto_engine_start(dev_data->hash_engine); if (ret) { - dev_err(dev, "Failed to start crypto engine\n"); + dev_err(dev, "Failed to start crypto engine for hash\n"); goto probe_engine_start_err; } =20 @@ -184,7 +204,9 @@ static int dthe_probe(struct platform_device *pdev) return 0; =20 probe_engine_start_err: - crypto_engine_exit(dev_data->engine); + crypto_engine_exit(dev_data->hash_engine); +probe_hash_engine_err: + crypto_engine_exit(dev_data->aes_engine); probe_engine_err: dma_release_channel(dev_data->dma_aes_rx); dma_release_channel(dev_data->dma_aes_tx); @@ -207,7 +229,8 @@ static void dthe_remove(struct platform_device *pdev) =20 dthe_unregister_algs(); =20 - crypto_engine_exit(dev_data->engine); + crypto_engine_exit(dev_data->aes_engine); + crypto_engine_exit(dev_data->hash_engine); =20 dma_release_channel(dev_data->dma_aes_rx); dma_release_channel(dev_data->dma_aes_tx); diff --git a/drivers/crypto/ti/dthev2-common.h b/drivers/crypto/ti/dthev2-c= ommon.h index 3b6f97356e1b3..c2e8fbb566cc4 100644 --- a/drivers/crypto/ti/dthev2-common.h +++ b/drivers/crypto/ti/dthev2-common.h @@ -17,6 +17,7 @@ #include #include #include +#include =20 #include #include @@ -33,6 +34,16 @@ */ #define DTHE_MAX_KEYSIZE (AES_MAX_KEY_SIZE * 2) =20 +enum dthe_hash_alg_sel { + DTHE_HASH_MD5 =3D 0, + DTHE_HASH_SHA1 =3D BIT(1), + DTHE_HASH_SHA224 =3D BIT(2), + DTHE_HASH_SHA256 =3D BIT(1) | BIT(2), + DTHE_HASH_SHA384 =3D BIT(0), + DTHE_HASH_SHA512 =3D BIT(0) | BIT(1), + DTHE_HASH_ERR =3D BIT(0) | BIT(1) | BIT(2), +}; + enum dthe_aes_mode { DTHE_AES_ECB =3D 0, DTHE_AES_CBC, @@ -49,7 +60,8 @@ enum dthe_aes_mode { * @dev: Device pointer * @regs: Base address of the register space * @list: list node for dev - * @engine: Crypto engine instance + * @aes_engine: Crypto engine instance for AES Engine + * @hash_engine: Crypto engine instance for Hashing Engine * @dma_aes_rx: AES Rx DMA Channel * @dma_aes_tx: AES Tx DMA Channel * @dma_sha_tx: SHA Tx DMA Channel @@ -58,7 +70,8 @@ struct dthe_data { struct device *dev; void __iomem *regs; struct list_head list; - struct crypto_engine *engine; + struct crypto_engine *aes_engine; + struct crypto_engine *hash_engine; =20 struct dma_chan *dma_aes_rx; struct dma_chan *dma_aes_tx; @@ -83,6 +96,8 @@ struct dthe_list { * @authsize: Authentication size for modes with authentication * @key: AES key * @aes_mode: AES mode + * @hash_mode: Hashing Engine mode + * @phash_size: partial hash size of the hash algorithm selected * @aead_fb: Fallback crypto aead handle * @skcipher_fb: Fallback crypto skcipher handle for AES-XTS mode */ @@ -91,7 +106,11 @@ struct dthe_tfm_ctx { unsigned int keylen; unsigned int authsize; u32 key[DTHE_MAX_KEYSIZE / sizeof(u32)]; - enum dthe_aes_mode aes_mode; + union { + enum dthe_aes_mode aes_mode; + enum dthe_hash_alg_sel hash_mode; + }; + unsigned int phash_size; union { struct crypto_sync_aead *aead_fb; struct crypto_sync_skcipher *skcipher_fb; @@ -110,6 +129,25 @@ struct dthe_aes_req_ctx { struct completion aes_compl; }; =20 +/** + * struct dthe_hash_req_ctx - Hashing engine ctx struct + * @phash: buffer to store a partial hash from a previous operation + * @digestcnt: stores the digest count from a previous operation; currentl= y hardware only provides + * a single 32-bit value even for SHA384/512 + * @phash_available: flag indicating if a partial hash from a previous ope= ration is available + * @flags: flags for internal use + * @padding: padding buffer for handling unaligned data + * @hash_compl: Completion variable for use in manual completion in case o= f DMA callback failure + */ +struct dthe_hash_req_ctx { + u32 phash[SHA512_DIGEST_SIZE / sizeof(u32)]; + u64 digestcnt[2]; + u8 phash_available; + u8 flags; + u8 padding[SHA512_BLOCK_SIZE]; + struct completion hash_compl; +}; + /* Struct definitions end */ =20 struct dthe_data *dthe_get_dev(struct dthe_tfm_ctx *ctx); @@ -131,4 +169,7 @@ struct scatterlist *dthe_copy_sg(struct scatterlist *ds= t, int dthe_register_aes_algs(void); void dthe_unregister_aes_algs(void); =20 +int dthe_register_hash_algs(void); +void dthe_unregister_hash_algs(void); + #endif diff --git a/drivers/crypto/ti/dthev2-hash.c b/drivers/crypto/ti/dthev2-has= h.c new file mode 100644 index 0000000000000..b1394262bf630 --- /dev/null +++ b/drivers/crypto/ti/dthev2-hash.c @@ -0,0 +1,591 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * K3 DTHE V2 crypto accelerator driver + * + * Copyright (C) Texas Instruments 2025 - https://www.ti.com + * Author: T Pratham + */ + +#include +#include +#include +#include + +#include "dthev2-common.h" + +#include +#include +#include +#include +#include + +/* Registers */ + +#define DTHE_P_HASH_BASE 0x5000 +#define DTHE_P_HASH512_IDIGEST_A 0x0240 +#define DTHE_P_HASH512_DIGEST_COUNT 0x0280 +#define DTHE_P_HASH512_MODE 0x0284 +#define DTHE_P_HASH512_LENGTH 0x0288 +#define DTHE_P_HASH512_DATA_IN_START 0x0080 +#define DTHE_P_HASH512_DATA_IN_END 0x00FC + +#define DTHE_P_HASH_SYSCONFIG 0x0110 +#define DTHE_P_HASH_IRQSTATUS 0x0118 +#define DTHE_P_HASH_IRQENABLE 0x011C + +/* Register write values and macros */ +#define DTHE_HASH_SYSCONFIG_INT_EN BIT(2) +#define DTHE_HASH_SYSCONFIG_DMA_EN BIT(3) +#define DTHE_HASH_IRQENABLE_EN_ALL GENMASK(3, 0) +#define DTHE_HASH_IRQSTATUS_OP_READY BIT(0) +#define DTHE_HASH_IRQSTATUS_IP_READY BIT(1) +#define DTHE_HASH_IRQSTATUS_PH_READY BIT(2) +#define DTHE_HASH_IRQSTATUS_CTX_READY BIT(3) + +#define DTHE_HASH_MODE_USE_ALG_CONST BIT(3) +#define DTHE_HASH_MODE_CLOSE_HASH BIT(4) + +enum dthe_hash_op { + DTHE_HASH_OP_UPDATE =3D 0, + DTHE_HASH_OP_FINUP, +}; + +static void dthe_hash_write_zero_message(enum dthe_hash_alg_sel mode, void= *dst) +{ + switch (mode) { + case DTHE_HASH_SHA512: + memcpy(dst, sha512_zero_message_hash, SHA512_DIGEST_SIZE); + break; + case DTHE_HASH_SHA384: + memcpy(dst, sha384_zero_message_hash, SHA384_DIGEST_SIZE); + break; + case DTHE_HASH_SHA256: + memcpy(dst, sha256_zero_message_hash, SHA256_DIGEST_SIZE); + break; + case DTHE_HASH_SHA224: + memcpy(dst, sha224_zero_message_hash, SHA224_DIGEST_SIZE); + break; + default: + break; + } +} + +static enum dthe_hash_alg_sel dthe_hash_get_hash_mode(struct crypto_ahash = *tfm) +{ + unsigned int ds =3D crypto_ahash_digestsize(tfm); + enum dthe_hash_alg_sel hash_mode; + + /* + * Currently, all hash algorithms supported by DTHEv2 have unique digest = sizes. + * So we can do this. Otherwise, we would have to get the algorithm from = the + * alg_name and do a strcmp. + */ + switch (ds) { + case SHA512_DIGEST_SIZE: + hash_mode =3D DTHE_HASH_SHA512; + break; + case SHA384_DIGEST_SIZE: + hash_mode =3D DTHE_HASH_SHA384; + break; + case SHA256_DIGEST_SIZE: + hash_mode =3D DTHE_HASH_SHA256; + break; + case SHA224_DIGEST_SIZE: + hash_mode =3D DTHE_HASH_SHA224; + break; + default: + hash_mode =3D DTHE_HASH_ERR; + break; + } + + return hash_mode; +} + +static unsigned int dthe_hash_get_phash_size(struct dthe_tfm_ctx *ctx) +{ + unsigned int phash_size =3D 0; + + switch (ctx->hash_mode) { + case DTHE_HASH_SHA512: + case DTHE_HASH_SHA384: + phash_size =3D SHA512_DIGEST_SIZE; + break; + case DTHE_HASH_SHA256: + case DTHE_HASH_SHA224: + phash_size =3D SHA256_DIGEST_SIZE; + break; + default: + break; + } + + return phash_size; +} + +static int dthe_hash_init_tfm(struct crypto_ahash *tfm) +{ + struct dthe_tfm_ctx *ctx =3D crypto_ahash_ctx(tfm); + struct dthe_data *dev_data =3D dthe_get_dev(ctx); + + if (!dev_data) + return -ENODEV; + + ctx->dev_data =3D dev_data; + + ctx->hash_mode =3D dthe_hash_get_hash_mode(tfm); + if (ctx->hash_mode =3D=3D DTHE_HASH_ERR) + return -EINVAL; + + ctx->phash_size =3D dthe_hash_get_phash_size(ctx); + + return 0; +} + +static int dthe_hash_config_dma_chan(struct dma_chan *chan, struct crypto_= ahash *tfm) +{ + struct dma_slave_config cfg; + int bs =3D crypto_ahash_blocksize(tfm); + + memzero_explicit(&cfg, sizeof(cfg)); + + cfg.dst_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; + cfg.dst_maxburst =3D bs / 4; + + return dmaengine_slave_config(chan, &cfg); +} + +static void dthe_hash_dma_in_callback(void *data) +{ + struct ahash_request *req =3D (struct ahash_request *)data; + struct dthe_hash_req_ctx *rctx =3D ahash_request_ctx(req); + + complete(&rctx->hash_compl); +} + +static int dthe_hash_dma_start(struct ahash_request *req, struct scatterli= st *src, + int src_nents, size_t len) +{ + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct dthe_tfm_ctx *ctx =3D crypto_ahash_ctx(tfm); + struct dthe_hash_req_ctx *rctx =3D ahash_request_ctx(req); + struct dthe_data *dev_data =3D dthe_get_dev(ctx); + struct device *tx_dev; + struct dma_async_tx_descriptor *desc_out; + int mapped_nents; + enum dma_data_direction src_dir =3D DMA_TO_DEVICE; + u32 hash_mode; + int ds =3D crypto_ahash_digestsize(tfm); + int ret =3D 0; + u32 *dst; + u32 dst_len; + void __iomem *sha_base_reg =3D dev_data->regs + DTHE_P_HASH_BASE; + + u32 hash_sysconfig_val =3D DTHE_HASH_SYSCONFIG_INT_EN | DTHE_HASH_SYSCONF= IG_DMA_EN; + u32 hash_irqenable_val =3D DTHE_HASH_IRQENABLE_EN_ALL; + + writel_relaxed(hash_sysconfig_val, sha_base_reg + DTHE_P_HASH_SYSCONFIG); + writel_relaxed(hash_irqenable_val, sha_base_reg + DTHE_P_HASH_IRQENABLE); + + /* Config SHA DMA channel as per SHA mode */ + ret =3D dthe_hash_config_dma_chan(dev_data->dma_sha_tx, tfm); + if (ret) { + dev_err(dev_data->dev, "Can't configure sha_tx dmaengine slave: %d\n", r= et); + goto hash_err; + } + + tx_dev =3D dmaengine_get_dma_device(dev_data->dma_sha_tx); + if (!tx_dev) { + ret =3D -ENODEV; + goto hash_err; + } + + mapped_nents =3D dma_map_sg(tx_dev, src, src_nents, src_dir); + if (mapped_nents =3D=3D 0) { + ret =3D -EINVAL; + goto hash_err; + } + + desc_out =3D dmaengine_prep_slave_sg(dev_data->dma_sha_tx, src, mapped_ne= nts, + DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); + if (!desc_out) { + dev_err(dev_data->dev, "OUT prep_slave_sg() failed\n"); + ret =3D -EINVAL; + goto hash_prep_err; + } + + desc_out->callback =3D dthe_hash_dma_in_callback; + desc_out->callback_param =3D req; + + init_completion(&rctx->hash_compl); + + hash_mode =3D ctx->hash_mode; + + if (rctx->flags =3D=3D DTHE_HASH_OP_FINUP) + hash_mode |=3D DTHE_HASH_MODE_CLOSE_HASH; + + if (rctx->phash_available) { + for (int i =3D 0; i < ctx->phash_size / sizeof(u32); ++i) + writel_relaxed(rctx->phash[i], + sha_base_reg + + DTHE_P_HASH512_IDIGEST_A + + (DTHE_REG_SIZE * i)); + + writel_relaxed(rctx->digestcnt[0], + sha_base_reg + DTHE_P_HASH512_DIGEST_COUNT); + } else { + hash_mode |=3D DTHE_HASH_MODE_USE_ALG_CONST; + } + + writel_relaxed(hash_mode, sha_base_reg + DTHE_P_HASH512_MODE); + writel_relaxed(len, sha_base_reg + DTHE_P_HASH512_LENGTH); + + dmaengine_submit(desc_out); + + dma_async_issue_pending(dev_data->dma_sha_tx); + + ret =3D wait_for_completion_timeout(&rctx->hash_compl, + msecs_to_jiffies(DTHE_DMA_TIMEOUT_MS)); + if (!ret) { + dmaengine_terminate_sync(dev_data->dma_sha_tx); + ret =3D -ETIMEDOUT; + } else { + ret =3D 0; + } + + if (rctx->flags =3D=3D DTHE_HASH_OP_UPDATE) { + /* If coming from update, we need to read the phash and store it for fut= ure */ + dst =3D rctx->phash; + dst_len =3D ctx->phash_size / sizeof(u32); + } else { + /* If coming from finup or final, we need to read the final digest */ + dst =3D (u32 *)req->result; + dst_len =3D ds / sizeof(u32); + } + + for (int i =3D 0; i < dst_len; ++i) + dst[i] =3D readl_relaxed(sha_base_reg + + DTHE_P_HASH512_IDIGEST_A + + (DTHE_REG_SIZE * i)); + + rctx->digestcnt[0] =3D readl_relaxed(sha_base_reg + DTHE_P_HASH512_DIGEST= _COUNT); + rctx->phash_available =3D 1; + +hash_prep_err: + dma_unmap_sg(tx_dev, src, src_nents, src_dir); +hash_err: + return ret; +} + +static int dthe_hash_run(struct crypto_engine *engine, void *areq) +{ + struct ahash_request *req =3D container_of(areq, struct ahash_request, ba= se); + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct dthe_hash_req_ctx *rctx =3D ahash_request_ctx(req); + + struct scatterlist *src, *sg; + int src_nents =3D 0; + unsigned int bs =3D crypto_ahash_blocksize(tfm); + unsigned int tot_len =3D req->nbytes; + unsigned int len_to_process; + unsigned int len_to_buffer; + unsigned int pad_len =3D 0; + u8 *pad_buf =3D rctx->padding; + int ret =3D 0; + + if (rctx->flags =3D=3D DTHE_HASH_OP_UPDATE) { + len_to_process =3D tot_len - (tot_len % bs); + len_to_buffer =3D tot_len % bs; + + if (len_to_process =3D=3D 0) { + ret =3D len_to_buffer; + goto hash_buf_all; + } + } else { + len_to_process =3D tot_len; + len_to_buffer =3D 0; + } + + src_nents =3D sg_nents_for_len(req->src, len_to_process); + + /* + * Certain DMA restrictions forced us to send data in multiples of BLOCK_= SIZE + * bytes. So, add a padding 0s at the end of src scatterlist if data is n= ot a + * multiple of block_size bytes (Can only happen in final or finup). The = extra + * data is ignored by the DTHE hardware. + */ + if (len_to_process % bs) { + pad_len =3D bs - (len_to_process % bs); + src_nents++; + } + + src =3D kcalloc(src_nents, sizeof(*src), GFP_KERNEL); + if (!src) { + ret =3D -ENOMEM; + goto hash_buf_all; + } + + sg_init_table(src, src_nents); + sg =3D dthe_copy_sg(src, req->src, len_to_process); + if (pad_len > 0) { + memset(pad_buf, 0, pad_len); + sg_set_buf(sg, pad_buf, pad_len); + } + + ret =3D dthe_hash_dma_start(req, src, src_nents, len_to_process); + if (!ret) + ret =3D len_to_buffer; + + kfree(src); + +hash_buf_all: + local_bh_disable(); + crypto_finalize_hash_request(engine, req, ret); + local_bh_enable(); + return 0; +} + +static int dthe_hash_init(struct ahash_request *req) +{ + struct dthe_hash_req_ctx *rctx =3D ahash_request_ctx(req); + + rctx->phash_available =3D 0; + rctx->digestcnt[0] =3D 0; + rctx->digestcnt[1] =3D 0; + + return 0; +} + +static int dthe_hash_update(struct ahash_request *req) +{ + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct dthe_tfm_ctx *ctx =3D crypto_ahash_ctx(tfm); + struct dthe_hash_req_ctx *rctx =3D ahash_request_ctx(req); + struct dthe_data *dev_data =3D dthe_get_dev(ctx); + struct crypto_engine *engine =3D dev_data->hash_engine; + + if (req->nbytes =3D=3D 0) + return 0; + + rctx->flags =3D DTHE_HASH_OP_UPDATE; + + return crypto_transfer_hash_request_to_engine(engine, req); +} + +static int dthe_hash_final(struct ahash_request *req) +{ + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct dthe_tfm_ctx *ctx =3D crypto_ahash_ctx(tfm); + struct dthe_hash_req_ctx *rctx =3D ahash_request_ctx(req); + struct dthe_data *dev_data =3D dthe_get_dev(ctx); + struct crypto_engine *engine =3D dev_data->hash_engine; + + /** + * We are always buffering data in update, except when nbytes =3D 0. + * So, either we get the buffered data here (nbytes > 0) or + * it is the case that we got zero message to begin with + */ + if (req->nbytes > 0) { + rctx->flags =3D DTHE_HASH_OP_FINUP; + + return crypto_transfer_hash_request_to_engine(engine, req); + } + + dthe_hash_write_zero_message(ctx->hash_mode, req->result); + + return 0; +} + +static int dthe_hash_finup(struct ahash_request *req) +{ + /* With AHASH_ALG_BLOCK_ONLY, final becomes same as finup. */ + return dthe_hash_final(req); +} + +static int dthe_hash_digest(struct ahash_request *req) +{ + dthe_hash_init(req); + return dthe_hash_finup(req); +} + +static int dthe_hash_export(struct ahash_request *req, void *out) +{ + struct dthe_hash_req_ctx *rctx =3D ahash_request_ctx(req); + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct dthe_tfm_ctx *ctx =3D crypto_ahash_ctx(tfm); + union { + u8 *u8; + u64 *u64; + } p =3D { .u8 =3D out }; + + memcpy(out, rctx->phash, ctx->phash_size); + p.u8 +=3D ctx->phash_size; + put_unaligned(rctx->digestcnt[0], p.u64++); + if (ctx->phash_size >=3D SHA512_DIGEST_SIZE) + put_unaligned(rctx->digestcnt[1], p.u64++); + + return 0; +} + +static int dthe_hash_import(struct ahash_request *req, const void *in) +{ + struct dthe_hash_req_ctx *rctx =3D ahash_request_ctx(req); + struct crypto_ahash *tfm =3D crypto_ahash_reqtfm(req); + struct dthe_tfm_ctx *ctx =3D crypto_ahash_ctx(tfm); + union { + const u8 *u8; + const u64 *u64; + } p =3D { .u8 =3D in }; + + memcpy(rctx->phash, in, ctx->phash_size); + p.u8 +=3D ctx->phash_size; + rctx->digestcnt[0] =3D get_unaligned(p.u64++); + if (ctx->phash_size >=3D SHA512_DIGEST_SIZE) + rctx->digestcnt[1] =3D get_unaligned(p.u64++); + rctx->phash_available =3D ((rctx->digestcnt[0]) ? 1 : 0); + + return 0; +} + +static struct ahash_engine_alg hash_algs[] =3D { + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.halg =3D { + .digestsize =3D SHA512_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "sha512", + .cra_driver_name =3D "sha512-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_OPTIONAL_KEY | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_FINAL_NONZERO | + CRYPTO_AHASH_ALG_FINUP_MAX | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D SHA512_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.halg =3D { + .digestsize =3D SHA384_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "sha384", + .cra_driver_name =3D "sha384-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_OPTIONAL_KEY | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_FINAL_NONZERO | + CRYPTO_AHASH_ALG_FINUP_MAX | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D SHA384_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.halg =3D { + .digestsize =3D SHA256_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "sha256", + .cra_driver_name =3D "sha256-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_OPTIONAL_KEY | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_FINAL_NONZERO | + CRYPTO_AHASH_ALG_FINUP_MAX | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D SHA256_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.halg =3D { + .digestsize =3D SHA224_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "sha224", + .cra_driver_name =3D "sha224-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_OPTIONAL_KEY | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_FINAL_NONZERO | + CRYPTO_AHASH_ALG_FINUP_MAX | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D SHA224_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, +}; + +int dthe_register_hash_algs(void) +{ + return crypto_engine_register_ahashes(hash_algs, ARRAY_SIZE(hash_algs)); +} + +void dthe_unregister_hash_algs(void) +{ + crypto_engine_unregister_ahashes(hash_algs, ARRAY_SIZE(hash_algs)); +} --=20 2.34.1 From nobody Sat Feb 7 08:45:35 2026 Received: from PH7PR06CU001.outbound.protection.outlook.com (mail-westus3azon11010034.outbound.protection.outlook.com [52.101.201.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEE9736213F; Wed, 21 Jan 2026 13:24:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.201.34 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769001894; cv=fail; b=AmliORR2DocpiSPp8ERglUW7xOTDU3ADCGQLsKf2KhFdyrn4aeksv5hhGJM4PVetjaONoj87plPf5TyCFjFNdsR4z4+Jv+znogjCVFpO6JaSx+/ca8toH5f1pQ8mdwA2nw7UDsJWlvDvHsvDCbBcz11VhCItfvC/ncJ7mskagS8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769001894; c=relaxed/simple; bh=zkXqwsYr/RAgr8rc1RzcuQwxL7SE3BEXtpfFhmKm490=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fUpWFvyrqwwd0ZgkpoFOTgdOPhljB/bPWkWOisvJX/id/zLxb2t3rmIkQyrmsWbeDR8iApyo2lVSCoAsxjbffjTdmhYCzGEyyLsoJYRg7pUdiFCoPCj7roEVADvPTmjZYm/JKTcgfUAvbIR68a+/gGJtwpS5cb3snWK+IUkL0kY= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=slxwrU+2; arc=fail smtp.client-ip=52.101.201.34 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="slxwrU+2" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=RSmF9CNLbRSfhIYbeVgeY9EHn7ytAW58tRGYoAZO0Kw47p/Op0OjbzqF12L1JBHyo7iemcaLtJlRAXz3zNwdY/rZYKAZfAVVKhBMubNIXGXwmwRJKNdUUmaktfVwWq6T/2tJjsvdcoDfx8BMlRAhQaKQXxDfBtQ6itXmy29cE9nEYJB0PxbwoiqqRUMeqRdRfzqMX+3G8b4hpoRXuvbZ/XfVuHQPMRxm6RGOmOy7/KkilY8DMxEjpgFYlOsKQuv1Yl9U2o7QmMcSl3ojvbYs1Iy9sn7swSHePxrOc41T5eO4A34ituVNFrL4/+1OfE9iLR1X1XVA92TlRsnRcGkKjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=KKdZIcbWXqez8ELpEg/yZ27Vlzzg+jaCG+ZTdGCSk9Q=; b=oTFvbAPPm0LCDq16yZYI30ojX/BtSdzfZtyHyHW5KiSiCZxmwe7heBNWnNA7ZmgkpG4B+h8+/Rf7klaSIF3KQS32CT7AAg3RaVtCPcJjIHEX5cFWAqcDCIb9pT0QlxAYyASD5zRgeOiMKbvLtxAsAIh23k6dxPizJtLdiSWKlLT5VY2P70fr87x9dOoWiT5jE380B9B7mEYUnYAjjUYXMTgEf1tJ7h+PFfgiKL3YKXzyUQwbzSHWWTS/9qOaJ//EHxErfZFoQJWKMqdPuPmKDuAwwqH0HTXcV33iwIYhuqLP5J26WKEb+x5oFzWXE7yWYug02PZur9Qo6xGO8kbx4A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 198.47.23.195) smtp.rcpttodomain=gondor.apana.org.au smtp.mailfrom=ti.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=ti.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=KKdZIcbWXqez8ELpEg/yZ27Vlzzg+jaCG+ZTdGCSk9Q=; b=slxwrU+2k7tSmdbG9+4aVJjOYZl3FIb6e/Oryp/eFIep070b4lp/fhThopdHyGy4dYmqPbwgt6+zuSLwrsKqkvvWf42hhLv6Hg7IvilNNS5i4kUbc5rY9NQ21pxFZFuL/vUSy1HYUAgemsZ4/M3daUS9/snyMZCNSUrzaOR6IUQ= Received: from SJ0PR03CA0352.namprd03.prod.outlook.com (2603:10b6:a03:39c::27) by PH0PR10MB7026.namprd10.prod.outlook.com (2603:10b6:510:289::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9542.9; Wed, 21 Jan 2026 13:24:47 +0000 Received: from SJ5PEPF000001D6.namprd05.prod.outlook.com (2603:10b6:a03:39c:cafe::79) by SJ0PR03CA0352.outlook.office365.com (2603:10b6:a03:39c::27) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9542.10 via Frontend Transport; Wed, 21 Jan 2026 13:24:47 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 198.47.23.195) smtp.mailfrom=ti.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ti.com; Received-SPF: Pass (protection.outlook.com: domain of ti.com designates 198.47.23.195 as permitted sender) receiver=protection.outlook.com; client-ip=198.47.23.195; helo=lewvzet201.ext.ti.com; pr=C Received: from lewvzet201.ext.ti.com (198.47.23.195) by SJ5PEPF000001D6.mail.protection.outlook.com (10.167.242.58) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9542.4 via Frontend Transport; Wed, 21 Jan 2026 13:24:46 +0000 Received: from DLEE214.ent.ti.com (157.170.170.117) by lewvzet201.ext.ti.com (10.4.14.104) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 21 Jan 2026 07:24:46 -0600 Received: from DLEE210.ent.ti.com (157.170.170.112) by DLEE214.ent.ti.com (157.170.170.117) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 21 Jan 2026 07:24:45 -0600 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE210.ent.ti.com (157.170.170.112) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Wed, 21 Jan 2026 07:24:45 -0600 Received: from pratham-Workstation-PC (pratham-workstation-pc.dhcp.ti.com [10.24.69.191]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 60LDOi9P3065849; Wed, 21 Jan 2026 07:24:45 -0600 From: T Pratham To: T Pratham , Herbert Xu , "David S. Miller" CC: Manorit Chawdhry , Kamlesh Gurudasani , Shiva Tripathi , Kavitha Malarvizhi , Vishal Mahaveer , Praneeth Bajjuri , , Subject: [PATCH v2 2/3] crypto: ti - Add support for MD5 in DTHEv2 Hashing Engine driver Date: Wed, 21 Jan 2026 18:54:06 +0530 Message-ID: <20260121132408.743777-3-t-pratham@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260121132408.743777-1-t-pratham@ti.com> References: <20260121132408.743777-1-t-pratham@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D6:EE_|PH0PR10MB7026:EE_ X-MS-Office365-Filtering-Correlation-Id: 833dd6a8-4463-43b9-daf8-08de58f0727b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024|7142099003; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?jZMN5KiEXo68rJy1899xVZi6c55WNfp8wCC89HAkrrNJ5d/9IHmeTH2wBXCD?= =?us-ascii?Q?pTzRWJMZBOlrCZPe+b28KfnkIlfaAp86ZmnC2eCHJhqvS7PfkoYS8rCjyE0d?= =?us-ascii?Q?hrLakyqwT4+EtwiRtT+W5OEOH3UMRYAgVDXQezxlrKdnNF3vtCabaYf1MTS4?= =?us-ascii?Q?1r/GtECver2xJqZROhERoe9SI4QtpmkMov6K6CWth5nIQEf5Iah4ixzIUhth?= =?us-ascii?Q?L+QvC5fG8AwcblWITtQqv2ayLCe6G+DjvoRbp1EXiBdCo2/8jfR9X6uaQd5e?= =?us-ascii?Q?y5dv1sLxp7pghauDCX6bYmlReGQdlqmiSPfw9+xPqGTfSdZBa4/U18xsCMhn?= =?us-ascii?Q?ER0RWhjGT7K3G1Huqj+P9MGNQFKuiyl+6h1DxNYyVTXSSF8SmaWbunxQJSMy?= =?us-ascii?Q?JUvcJ5iJAI+5B4eTzyaD6VYLJwy4p/ePnT61r1YL9L+PZJkPvIhCrFI8zL9F?= =?us-ascii?Q?BuVCIZJM7u60xrP7UZPBsOIEoXfuo7v+IBIPjNIJr4bYzhRxdO6XFn37GPp6?= =?us-ascii?Q?hfnbT7y90FfJDNHKsjS38CGu+irruokjRB9c2ABSilA0SOiujZsGwCMd0iog?= =?us-ascii?Q?A4BQgtonrSJykdykzMpeH8OFMP5fKEPIXfw0najRcL0oj37Yx2EC0LuPkyyz?= =?us-ascii?Q?JLG+R+coLt+3oM66YkJByE4/ZDBAkdkyJbEDkcKjem2JLUctt/q/JKoekxn0?= =?us-ascii?Q?tnEb2MzugbnuMKYLmzYEoKdzqKicfBPpyHPdiIoZQoTdxt/VTrQdssbWY4QE?= =?us-ascii?Q?6pF1JUMssXkzogHd4wzaieRkx4xRc0K0yTXrSfUkykHw135UK+dmVgST+lq3?= =?us-ascii?Q?JUQEpljqOyKGh9lgyOydhWBFboY+kvd4XE+tHX+gBhsrh6WSgQ5uJNG78QIx?= =?us-ascii?Q?0sF51PxTl5Hg+nroKdkd/4mbyO1YD1bL5/ODfG14F93ESeQyM+0hGa1Dkht7?= =?us-ascii?Q?slhgOKCyBhFRzI7AH9w7DAfSjCUhv8pEqWaIyWkKIBrNMmtJzgCpakeKlxOQ?= =?us-ascii?Q?PP4GfeBoi8Qm3bakX821rvoPanjB7WgGVldEGA52E8amuMVpgL7vyTVt6XlC?= =?us-ascii?Q?vwxj8v2giUWS0OBSwT0O05mYm7yjNMge4S7IF7ZMOPs36UW5HXhOHKDKNRjs?= =?us-ascii?Q?e9xzR0eKmm3HTy6qsQHNMN3aN4oXeaiGcu2MFhqivtbA+Z4kr+k0ZuWLhm3f?= =?us-ascii?Q?+HlBZtY9GOl+McGsxK9QsnRA+7evD6mg+/qNRIxKgn2FPcHqKfZeLYlB0ZnZ?= =?us-ascii?Q?p22ywjrGFfEumdl/bw0yAdfCPw+k0huYb2v4070KSvPCXYqFFoEhhDTdcn4F?= =?us-ascii?Q?LG8nFusbZgCV+qu572oTIQp+dq/M1xpSlVUnhpfE+4MBUotcmfRajk7oPIGI?= =?us-ascii?Q?cEMPUaJJoVCetDYI7z5Z+w31dzwZ9N5JO9OPghuXoxSVcm1DNgIY43SNMDPk?= =?us-ascii?Q?eO7CEs5DWRIoh6eEhbRp91aueWSX3V7vyBRp+vles7K+AoijiQfUZQN7OlIE?= =?us-ascii?Q?wfoxOfOf65XduKuDQdOAAzyvN7/UGfe9yVQqxDrJgNsqCsEqLc7ZLUPRIjlG?= =?us-ascii?Q?OELOsr6JoEkctCBkHV7kSxmGub1P/XwVofRBKWAMTxkVHeOnrapXVUwIGw0U?= =?us-ascii?Q?ezCuiVbcz6UAyT0C2v0a8sD0gk41Q/Y3OGFu98AnoeMeyCU/IZuYf+x8LxcJ?= =?us-ascii?Q?jFdxXQ=3D=3D?= X-Forefront-Antispam-Report: CIP:198.47.23.195;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:lewvzet201.ext.ti.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024)(7142099003);DIR:OUT;SFP:1101; X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jan 2026 13:24:46.8052 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 833dd6a8-4463-43b9-daf8-08de58f0727b X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.195];Helo=[lewvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR10MB7026 Content-Type: text/plain; charset="utf-8" Add support for MD5 algorithm in the hashing engine of DTHEv2 hardware cryptographic engine. Signed-off-by: T Pratham --- drivers/crypto/ti/Kconfig | 1 + drivers/crypto/ti/dthev2-common.h | 1 + drivers/crypto/ti/dthev2-hash.c | 43 +++++++++++++++++++++++++++++++ 3 files changed, 45 insertions(+) diff --git a/drivers/crypto/ti/Kconfig b/drivers/crypto/ti/Kconfig index 90af2c7cb1c55..9c2aa50cfbfbe 100644 --- a/drivers/crypto/ti/Kconfig +++ b/drivers/crypto/ti/Kconfig @@ -12,6 +12,7 @@ config CRYPTO_DEV_TI_DTHEV2 select CRYPTO_CCM select CRYPTO_SHA256 select CRYPTO_SHA512 + select CRYPTO_MD5 select SG_SPLIT help This enables support for the TI DTHE V2 hw cryptography engine diff --git a/drivers/crypto/ti/dthev2-common.h b/drivers/crypto/ti/dthev2-c= ommon.h index c2e8fbb566cc4..c305eca26ce82 100644 --- a/drivers/crypto/ti/dthev2-common.h +++ b/drivers/crypto/ti/dthev2-common.h @@ -17,6 +17,7 @@ #include #include #include +#include #include =20 #include diff --git a/drivers/crypto/ti/dthev2-hash.c b/drivers/crypto/ti/dthev2-has= h.c index b1394262bf630..e4efcad375bf9 100644 --- a/drivers/crypto/ti/dthev2-hash.c +++ b/drivers/crypto/ti/dthev2-hash.c @@ -9,6 +9,7 @@ #include #include #include +#include #include =20 #include "dthev2-common.h" @@ -65,6 +66,9 @@ static void dthe_hash_write_zero_message(enum dthe_hash_a= lg_sel mode, void *dst) case DTHE_HASH_SHA224: memcpy(dst, sha224_zero_message_hash, SHA224_DIGEST_SIZE); break; + case DTHE_HASH_MD5: + memcpy(dst, md5_zero_message_hash, MD5_DIGEST_SIZE); + break; default: break; } @@ -93,6 +97,9 @@ static enum dthe_hash_alg_sel dthe_hash_get_hash_mode(str= uct crypto_ahash *tfm) case SHA224_DIGEST_SIZE: hash_mode =3D DTHE_HASH_SHA224; break; + case MD5_DIGEST_SIZE: + hash_mode =3D DTHE_HASH_MD5; + break; default: hash_mode =3D DTHE_HASH_ERR; break; @@ -114,6 +121,9 @@ static unsigned int dthe_hash_get_phash_size(struct dth= e_tfm_ctx *ctx) case DTHE_HASH_SHA224: phash_size =3D SHA256_DIGEST_SIZE; break; + case DTHE_HASH_MD5: + phash_size =3D MD5_DIGEST_SIZE; + break; default: break; } @@ -578,6 +588,39 @@ static struct ahash_engine_alg hash_algs[] =3D { }, .op.do_one_request =3D dthe_hash_run, }, + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.halg =3D { + .digestsize =3D MD5_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "md5", + .cra_driver_name =3D "md5-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_OPTIONAL_KEY | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_FINAL_NONZERO | + CRYPTO_AHASH_ALG_FINUP_MAX | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D MD5_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, }; =20 int dthe_register_hash_algs(void) --=20 2.34.1 From nobody Sat Feb 7 08:45:35 2026 Received: from CH5PR02CU005.outbound.protection.outlook.com (mail-northcentralusazon11012010.outbound.protection.outlook.com [40.107.200.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA35948BD4F; Wed, 21 Jan 2026 13:25:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.200.10 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769001952; cv=fail; b=oyheLg73+u6HuMetIvd1xd+/3Z1l/SA5GUhZOwSekEf9D/PJir/jveKevzt5zcWkDfhdSApzY0fSPcL+DMG9QybaYHYdS5hsS8eRHFFrU4urxX8suXfLSscLYFqi62z0as7J1BxuF/zwUGnS8UtTkVG7+ykU3nJCQi9JjaOIVzk= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769001952; c=relaxed/simple; bh=Bm57+KwBD3d/OVz7/PnZnp2Gz4hZx0G3sbWQBoUL45c=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=SV8f16VL/31Ne5tQsHC+PMonb5bFkGybfoNjwgVpnhVOwebdziQApORu605rONFn72Wk8NmTxKSBqzU3c16V6k7dts7dzCvhjIl1+W+nMGe4UzFf1hGklbtSRo4RY07SkKUzaj8YqvjVzJbiToYCkEk8JnxaJtvInieV0uPN33g= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=v8lqnbIb; arc=fail smtp.client-ip=40.107.200.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="v8lqnbIb" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=fb/qUkhpFNpaqeHMZ+ddGjj68rb86IEb0Hfp8Z+3DXPvzGEOEcJrjr11kKHn6IWNd9wm611S5FyhAf2Qzl6hHSJzXGDlPouwasDZ8sfa29gF6dhSdncXTyPBtrSIkxW/ENzkcx3NY9bhiwJiCHo5aJnQ2VBa0ynYOvwr5NsqrcOXdIHx7gMxFvcZFPSrTKCZcjULDu8p8n0ki5J7u1uWw/e3XpqZvd455krysbxPHAcDYzWHWWRffupxWHNukMijuZtfBMlI/5f6/rVOuvK6MGVcRQoE1yjBs9l1/tkgGiyf2XNCLMoYkeaPXjMT2Npz1CaBWeSBh31GXn1rIjmwLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=2jw/d6xsHzx0Ru4x0UZjBfnn33pPvTqwqVxbtKBuE+k=; b=Ga/7BFF8PLc1RsWF4Zj0cX8RcYENWw24RLTf4cqw4pGjh54w5z9bC5p7M9dV5DUPuwjPQKPSsLF5lJKf+kwgesBGZBlSEDwKD8Cz3SNL3IoDnTawJRCeTcv838HJ9GQ+9sqN5tNID6KVeG/cnLGJ7G7cUzFE0yNR0zMvbTPjvhcrct7uatletceyCVWd/A6oYCjoNMxFYBRReRRZyzPLatXXA1X+joUzX5DkkRG3oKI0H3NhoGvB0Tq+93TRuhlA2QqNWVldF6jNpE1nQREBkKg+/c4g7mzlcBlAKD+Y0bxEaa3TkfD8Dnk+KZaff0Iibk6Z/ioBR0a/N5b8U0RZhA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 198.47.21.195) smtp.rcpttodomain=gondor.apana.org.au smtp.mailfrom=ti.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=ti.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=2jw/d6xsHzx0Ru4x0UZjBfnn33pPvTqwqVxbtKBuE+k=; b=v8lqnbIbMV2bBCbzb3HbvoZGI+uYNTVAJxszRfYJjiP9ERljUaIIkM0n75wa8osZji/NaH+8YXVKYXMFpcfwBXu9h+H/sB64P+j8RY/OIvaraw4hzAEeBg1plKHGmIM5o12KhR2Vb2ruCGeiF4pi7M1aRL21qiJyaezfZbQsfv0= Received: from SN7P220CA0025.NAMP220.PROD.OUTLOOK.COM (2603:10b6:806:123::30) by IA1PR10MB6832.namprd10.prod.outlook.com (2603:10b6:208:424::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9542.9; Wed, 21 Jan 2026 13:25:44 +0000 Received: from SN1PEPF0002636A.namprd02.prod.outlook.com (2603:10b6:806:123:cafe::51) by SN7P220CA0025.outlook.office365.com (2603:10b6:806:123::30) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9542.9 via Frontend Transport; Wed, 21 Jan 2026 13:25:43 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 198.47.21.195) smtp.mailfrom=ti.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ti.com; Received-SPF: Pass (protection.outlook.com: domain of ti.com designates 198.47.21.195 as permitted sender) receiver=protection.outlook.com; client-ip=198.47.21.195; helo=flwvzet201.ext.ti.com; pr=C Received: from flwvzet201.ext.ti.com (198.47.21.195) by SN1PEPF0002636A.mail.protection.outlook.com (10.167.241.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9542.4 via Frontend Transport; Wed, 21 Jan 2026 13:25:42 +0000 Received: from DFLE213.ent.ti.com (10.64.6.71) by flwvzet201.ext.ti.com (10.248.192.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 21 Jan 2026 07:24:49 -0600 Received: from DFLE200.ent.ti.com (10.64.6.58) by DFLE213.ent.ti.com (10.64.6.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 21 Jan 2026 07:24:49 -0600 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE200.ent.ti.com (10.64.6.58) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Wed, 21 Jan 2026 07:24:49 -0600 Received: from pratham-Workstation-PC (pratham-workstation-pc.dhcp.ti.com [10.24.69.191]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 60LDOmoo3065906; Wed, 21 Jan 2026 07:24:48 -0600 From: T Pratham To: T Pratham , Herbert Xu , "David S. Miller" CC: Manorit Chawdhry , Kamlesh Gurudasani , Shiva Tripathi , Kavitha Malarvizhi , Vishal Mahaveer , Praneeth Bajjuri , , Subject: [PATCH v2 3/3] crypto: ti - Add support for HMAC in DTHEv2 Hashing Engine driver Date: Wed, 21 Jan 2026 18:54:07 +0530 Message-ID: <20260121132408.743777-4-t-pratham@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260121132408.743777-1-t-pratham@ti.com> References: <20260121132408.743777-1-t-pratham@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636A:EE_|IA1PR10MB6832:EE_ X-MS-Office365-Filtering-Correlation-Id: 4a82ecb3-e3ec-45cd-3f1e-08de58f093e0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024|7142099003; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Xat2VAcHklFBdMvnh7LnmcU2JPVMs/YNBblVe7iZLeVG+vfXpYsv5Zm5DcBf?= =?us-ascii?Q?rJ5IDT//cQqlsTtfM8DBV3pVQ5MzwBfyx8bHWU+YIir16OpTRuIc+oTYyXS+?= =?us-ascii?Q?uEGgeQBANrjNSI4ilYHy3GWYF3dZlPBAS4iEQbKqz5hFWfC7VO4KOkR+Rdtp?= =?us-ascii?Q?FFm+stBh2SE8HYUtejEtN8+bsrQ4f9dMqPshjShF93AEO4az9iUpG0fubCa3?= =?us-ascii?Q?xZl1YDazMIa1cL5bfiyLa3SoB/g1VKEztiuzQ5/FnNgWnglkpMuaya2aWY4V?= =?us-ascii?Q?hERvLyQdX0SE+EW4D9YVTmhbMTggGYQW3tvX10Ka5X92Yg4p/MBAUm+F8u2A?= =?us-ascii?Q?9jfn3nREiI0twEfa1g7GFSzowZmG7UjRaRwM1WGlRxFugfc6szKwXBuMaFVe?= =?us-ascii?Q?6Y4Ng+e11L11Cg7c+shdIju+eY/RCjBYSy/tFA2MgBrL2w9xpCHihP+z4oaR?= =?us-ascii?Q?FbjtChypXaIBFe4aL5+zeDRkfwNCtdGCh2vFlw2RKp1IzzJ0cwM/tHGsYy62?= =?us-ascii?Q?iHUWYJokM8YtQEh70qIdxYbvuL3HpBcIOJ4XCsGZkrfILKWvc7OcA/5aJG4m?= =?us-ascii?Q?fpZKfVuczUbFX8DzoSLhe/IMQSOUZBBkvYhCwNP/nOQUaQO0HOLvPJVI0w58?= =?us-ascii?Q?o8t8Idv5+IHeeddiZ8sXwbM2LUwpxwQcxNkNdCBPgZCMs0g/lD9ghszLtTCI?= =?us-ascii?Q?xOeutwWGxC7y/PUuokLWm6UpHPqXgrQDIqFsVE/R1uop5xwUxVEEeHn0lMHj?= =?us-ascii?Q?7XGeW1tkWIY3gHUvqiCbJnZcjR8umGx3HZiqDBoP15G5Vmr95kUA+uox4jKJ?= =?us-ascii?Q?xQzNrakwKzq+746LzoYvvcvaert5sV/T+d5Z/QgIdhbrRiuvf8H9PRf8iEge?= =?us-ascii?Q?JuPbQCbRkLIHsSmmprHPKFuRK5a95xs03Q4HDtRaf38lFy8YCSY9q0+D6dFy?= =?us-ascii?Q?3zVfenzeIUIQUh8rLmu8Lr+ZMup6w827SixrDBNVzcUSo4RuztJCE5MwtpN1?= =?us-ascii?Q?jtNgrO1RKRnSdb2vjq/0INrUUXX2f1PN/iJszrkLZiy6hbMR8jOmD6PwpmQV?= =?us-ascii?Q?ccSwAb8kyoqBX6bRzU9DxFy0O8rC2DNfsdd0A0wj/kZdh2LVG3U3zJpusUkM?= =?us-ascii?Q?to1yMKsr6LetgQFYNImbiT/hFB/kKm37/LAor2W/fBaq0jwEmpsMcWNSbflA?= =?us-ascii?Q?FQRdgo+O8GCuRHjYEHTtukfw0twfaUp5LRAk8cPWwBuwJKoFhsODS5iEYqIM?= =?us-ascii?Q?VDLUyEraqFZow3OIXUn7nIfszJ+9txW7rsaqjlALkYTEEanscqMjOaXLBCUx?= =?us-ascii?Q?GZHwK2q6W/HferWkE1hUzBt3WwoC290GDo7n7DLE2eJDNOmyRA7i2nQuAH4t?= =?us-ascii?Q?kL+BJCuQMl021Xy75fihBu+NJd+obmWL4ne1JF8AqWqF4f7oy/Ld70/kjG+V?= =?us-ascii?Q?BMVVxb8HpHkNz6raYqGY0yGgdMs5ueVlVfVLOMM+F0GY9+uteEmPB5EUfrK+?= =?us-ascii?Q?QjdYQjKSLnmrZRphIk7qvkcpKT1fR7jl2JgV5eb34FkUwNH8QtV+uPpC7bGl?= =?us-ascii?Q?gx5RrL7dJBlqtAAR0nMsL+KS3kPvj9mFnuoHuc5BXsKUCuGROWlL12ymtC18?= =?us-ascii?Q?RITVkzSvrjkT9bVMOPL0kFZxHyk8V9VMjLct63m38DGF8VJfiW7QCJnSYHaN?= =?us-ascii?Q?EoW/Sg=3D=3D?= X-Forefront-Antispam-Report: CIP:198.47.21.195;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:flwvzet201.ext.ti.com;PTR:ErrorRetry;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024)(7142099003);DIR:OUT;SFP:1101; X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jan 2026 13:25:42.8762 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4a82ecb3-e3ec-45cd-3f1e-08de58f093e0 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.195];Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR10MB6832 Content-Type: text/plain; charset="utf-8" Add support for HMAC-SHA512/384/256/224 and HMAC-MD5 algorithms in the hashing engine of the DTHEv2 hardware cryptographic engine. Signed-off-by: T Pratham --- drivers/crypto/ti/Kconfig | 1 + drivers/crypto/ti/dthev2-common.h | 10 +- drivers/crypto/ti/dthev2-hash.c | 290 +++++++++++++++++++++++++++++- 3 files changed, 296 insertions(+), 5 deletions(-) diff --git a/drivers/crypto/ti/Kconfig b/drivers/crypto/ti/Kconfig index 9c2aa50cfbfbe..68dccf92f5382 100644 --- a/drivers/crypto/ti/Kconfig +++ b/drivers/crypto/ti/Kconfig @@ -13,6 +13,7 @@ config CRYPTO_DEV_TI_DTHEV2 select CRYPTO_SHA256 select CRYPTO_SHA512 select CRYPTO_MD5 + select CRYPTO_HMAC select SG_SPLIT help This enables support for the TI DTHE V2 hw cryptography engine diff --git a/drivers/crypto/ti/dthev2-common.h b/drivers/crypto/ti/dthev2-c= ommon.h index c305eca26ce82..2027dda0b5bdb 100644 --- a/drivers/crypto/ti/dthev2-common.h +++ b/drivers/crypto/ti/dthev2-common.h @@ -31,9 +31,9 @@ #define DTHE_DMA_TIMEOUT_MS 2000 /* * Size of largest possible key (of all algorithms) to be stored in dthe_t= fm_ctx - * This is currently the keysize of XTS-AES-256 which is 512 bits (64 byte= s) + * This is currently the keysize of HMAC-SHA512 which is 1024 bits (128 by= tes) */ -#define DTHE_MAX_KEYSIZE (AES_MAX_KEY_SIZE * 2) +#define DTHE_MAX_KEYSIZE (SHA512_BLOCK_SIZE) =20 enum dthe_hash_alg_sel { DTHE_HASH_MD5 =3D 0, @@ -93,9 +93,9 @@ struct dthe_list { /** * struct dthe_tfm_ctx - Transform ctx struct containing ctx for all sub-c= omponents of DTHE V2 * @dev_data: Device data struct pointer - * @keylen: AES key length + * @keylen: Key length for algorithms that use a key * @authsize: Authentication size for modes with authentication - * @key: AES key + * @key: Buffer storing the key * @aes_mode: AES mode * @hash_mode: Hashing Engine mode * @phash_size: partial hash size of the hash algorithm selected @@ -135,6 +135,7 @@ struct dthe_aes_req_ctx { * @phash: buffer to store a partial hash from a previous operation * @digestcnt: stores the digest count from a previous operation; currentl= y hardware only provides * a single 32-bit value even for SHA384/512 + * @odigest: buffer to store the outer digest from a previous operation * @phash_available: flag indicating if a partial hash from a previous ope= ration is available * @flags: flags for internal use * @padding: padding buffer for handling unaligned data @@ -143,6 +144,7 @@ struct dthe_aes_req_ctx { struct dthe_hash_req_ctx { u32 phash[SHA512_DIGEST_SIZE / sizeof(u32)]; u64 digestcnt[2]; + u32 odigest[SHA512_DIGEST_SIZE / sizeof(u32)]; u8 phash_available; u8 flags; u8 padding[SHA512_BLOCK_SIZE]; diff --git a/drivers/crypto/ti/dthev2-hash.c b/drivers/crypto/ti/dthev2-has= h.c index e4efcad375bf9..ca4a0a724b4d9 100644 --- a/drivers/crypto/ti/dthev2-hash.c +++ b/drivers/crypto/ti/dthev2-hash.c @@ -23,6 +23,7 @@ /* Registers */ =20 #define DTHE_P_HASH_BASE 0x5000 +#define DTHE_P_HASH512_ODIGEST_A 0x0200 #define DTHE_P_HASH512_IDIGEST_A 0x0240 #define DTHE_P_HASH512_DIGEST_COUNT 0x0280 #define DTHE_P_HASH512_MODE 0x0284 @@ -45,6 +46,13 @@ =20 #define DTHE_HASH_MODE_USE_ALG_CONST BIT(3) #define DTHE_HASH_MODE_CLOSE_HASH BIT(4) +#define DTHE_HASH_MODE_HMAC_KEY_PROCESSING BIT(5) +#define DTHE_HASH_MODE_HMAC_OUTER_HASH BIT(7) + +/* Misc */ +#define DTHE_HMAC_SHA512_MAX_KEYSIZE (SHA512_BLOCK_SIZE) +#define DTHE_HMAC_SHA256_MAX_KEYSIZE (SHA256_BLOCK_SIZE) +#define DTHE_HMAC_MD5_MAX_KEYSIZE (MD5_BLOCK_SIZE) =20 enum dthe_hash_op { DTHE_HASH_OP_UPDATE =3D 0, @@ -74,6 +82,19 @@ static void dthe_hash_write_zero_message(enum dthe_hash_= alg_sel mode, void *dst) } } =20 +static int dthe_hmac_write_zero_message(struct ahash_request *req) +{ + HASH_FBREQ_ON_STACK(fbreq, req); + int ret; + + ahash_request_set_crypt(fbreq, req->src, req->result, + req->nbytes); + + ret =3D crypto_ahash_digest(fbreq); + HASH_REQUEST_ZERO(fbreq); + return ret; +} + static enum dthe_hash_alg_sel dthe_hash_get_hash_mode(struct crypto_ahash = *tfm) { unsigned int ds =3D crypto_ahash_digestsize(tfm); @@ -184,6 +205,7 @@ static int dthe_hash_dma_start(struct ahash_request *re= q, struct scatterlist *sr enum dma_data_direction src_dir =3D DMA_TO_DEVICE; u32 hash_mode; int ds =3D crypto_ahash_digestsize(tfm); + bool is_hmac =3D (ctx->keylen > 0); int ret =3D 0; u32 *dst; u32 dst_len; @@ -229,8 +251,11 @@ static int dthe_hash_dma_start(struct ahash_request *r= eq, struct scatterlist *sr =20 hash_mode =3D ctx->hash_mode; =20 - if (rctx->flags =3D=3D DTHE_HASH_OP_FINUP) + if (rctx->flags =3D=3D DTHE_HASH_OP_FINUP) { hash_mode |=3D DTHE_HASH_MODE_CLOSE_HASH; + if (is_hmac) + hash_mode |=3D DTHE_HASH_MODE_HMAC_OUTER_HASH; + } =20 if (rctx->phash_available) { for (int i =3D 0; i < ctx->phash_size / sizeof(u32); ++i) @@ -238,9 +263,28 @@ static int dthe_hash_dma_start(struct ahash_request *r= eq, struct scatterlist *sr sha_base_reg + DTHE_P_HASH512_IDIGEST_A + (DTHE_REG_SIZE * i)); + if (is_hmac) { + for (int i =3D 0; i < ctx->phash_size / sizeof(u32); ++i) + writel_relaxed(rctx->odigest[i], + sha_base_reg + + DTHE_P_HASH512_ODIGEST_A + + (DTHE_REG_SIZE * i)); + } =20 writel_relaxed(rctx->digestcnt[0], sha_base_reg + DTHE_P_HASH512_DIGEST_COUNT); + } else if (is_hmac) { + hash_mode |=3D DTHE_HASH_MODE_HMAC_KEY_PROCESSING; + + for (int i =3D 0; i < (ctx->keylen / 2) / sizeof(u32); ++i) + writel_relaxed(ctx->key[i], sha_base_reg + + DTHE_P_HASH512_ODIGEST_A + + (DTHE_REG_SIZE * i)); + for (int i =3D 0; i < (ctx->keylen / 2) / sizeof(u32); ++i) + writel_relaxed(ctx->key[i + (ctx->keylen / 2) / sizeof(u32)], + sha_base_reg + + DTHE_P_HASH512_IDIGEST_A + + (DTHE_REG_SIZE * i)); } else { hash_mode |=3D DTHE_HASH_MODE_USE_ALG_CONST; } @@ -275,6 +319,12 @@ static int dthe_hash_dma_start(struct ahash_request *r= eq, struct scatterlist *sr dst[i] =3D readl_relaxed(sha_base_reg + DTHE_P_HASH512_IDIGEST_A + (DTHE_REG_SIZE * i)); + if (is_hmac) { + for (int i =3D 0; i < dst_len; ++i) + rctx->odigest[i] =3D readl_relaxed(sha_base_reg + + DTHE_P_HASH512_ODIGEST_A + + (DTHE_REG_SIZE * i)); + } =20 rctx->digestcnt[0] =3D readl_relaxed(sha_base_reg + DTHE_P_HASH512_DIGEST= _COUNT); rctx->phash_available =3D 1; @@ -399,6 +449,10 @@ static int dthe_hash_final(struct ahash_request *req) return crypto_transfer_hash_request_to_engine(engine, req); } =20 + if (ctx->keylen > 0) + /* HMAC with zero-length message */ + return dthe_hmac_write_zero_message(req); + dthe_hash_write_zero_message(ctx->hash_mode, req->result); =20 return 0; @@ -432,6 +486,11 @@ static int dthe_hash_export(struct ahash_request *req,= void *out) if (ctx->phash_size >=3D SHA512_DIGEST_SIZE) put_unaligned(rctx->digestcnt[1], p.u64++); =20 + if (ctx->keylen > 0) { + memcpy(p.u8, rctx->odigest, ctx->phash_size); + p.u8 +=3D ctx->phash_size; + } + return 0; } =20 @@ -452,9 +511,68 @@ static int dthe_hash_import(struct ahash_request *req,= const void *in) rctx->digestcnt[1] =3D get_unaligned(p.u64++); rctx->phash_available =3D ((rctx->digestcnt[0]) ? 1 : 0); =20 + if (ctx->keylen > 0) { + memcpy(rctx->odigest, p.u8, ctx->phash_size); + p.u8 +=3D ctx->phash_size; + } + return 0; } =20 +static int dthe_hmac_setkey(struct crypto_ahash *tfm, const u8 *key, + unsigned int keylen) +{ + struct dthe_tfm_ctx *ctx =3D crypto_ahash_ctx(tfm); + struct crypto_ahash *fb =3D crypto_ahash_fb(tfm); + unsigned int max_keysize; + const char *hash_alg_name; + + memzero_explicit(ctx->key, sizeof(ctx->key)); + + switch (ctx->hash_mode) { + case DTHE_HASH_SHA512: + hash_alg_name =3D "sha512"; + max_keysize =3D DTHE_HMAC_SHA512_MAX_KEYSIZE; + break; + case DTHE_HASH_SHA384: + hash_alg_name =3D "sha384"; + max_keysize =3D DTHE_HMAC_SHA512_MAX_KEYSIZE; + break; + case DTHE_HASH_SHA256: + hash_alg_name =3D "sha256"; + max_keysize =3D DTHE_HMAC_SHA256_MAX_KEYSIZE; + break; + case DTHE_HASH_SHA224: + hash_alg_name =3D "sha224"; + max_keysize =3D DTHE_HMAC_SHA256_MAX_KEYSIZE; + break; + case DTHE_HASH_MD5: + hash_alg_name =3D "md5"; + max_keysize =3D DTHE_HMAC_MD5_MAX_KEYSIZE; + break; + default: + return -EINVAL; + } + + if (keylen > max_keysize) { + struct crypto_shash *ktfm =3D crypto_alloc_shash(hash_alg_name, 0, 0); + SHASH_DESC_ON_STACK(desc, ktfm); + int err; + + desc->tfm =3D ktfm; + err =3D crypto_shash_digest(desc, key, keylen, (u8 *)ctx->key); + crypto_free_shash(ktfm); + if (err) + return err; + } else { + memcpy(ctx->key, key, keylen); + } + + ctx->keylen =3D max_keysize; + + return crypto_ahash_setkey(fb, key, keylen); +} + static struct ahash_engine_alg hash_algs[] =3D { { .base.init_tfm =3D dthe_hash_init_tfm, @@ -621,6 +739,176 @@ static struct ahash_engine_alg hash_algs[] =3D { }, .op.do_one_request =3D dthe_hash_run, }, + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.setkey =3D dthe_hmac_setkey, + .base.halg =3D { + .digestsize =3D SHA512_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "hmac(sha512)", + .cra_driver_name =3D "hmac-sha512-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_FINAL_NONZERO | + CRYPTO_AHASH_ALG_FINUP_MAX | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D SHA512_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.setkey =3D dthe_hmac_setkey, + .base.halg =3D { + .digestsize =3D SHA384_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "hmac(sha384)", + .cra_driver_name =3D "hmac-sha384-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_FINAL_NONZERO | + CRYPTO_AHASH_ALG_FINUP_MAX | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D SHA384_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.setkey =3D dthe_hmac_setkey, + .base.halg =3D { + .digestsize =3D SHA256_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "hmac(sha256)", + .cra_driver_name =3D "hmac-sha256-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_FINAL_NONZERO | + CRYPTO_AHASH_ALG_FINUP_MAX | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D SHA256_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.setkey =3D dthe_hmac_setkey, + .base.halg =3D { + .digestsize =3D SHA224_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "hmac(sha224)", + .cra_driver_name =3D "hmac-sha224-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_FINAL_NONZERO | + CRYPTO_AHASH_ALG_FINUP_MAX | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D SHA224_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, + { + .base.init_tfm =3D dthe_hash_init_tfm, + .base.init =3D dthe_hash_init, + .base.update =3D dthe_hash_update, + .base.final =3D dthe_hash_final, + .base.finup =3D dthe_hash_finup, + .base.digest =3D dthe_hash_digest, + .base.export =3D dthe_hash_export, + .base.import =3D dthe_hash_import, + .base.setkey =3D dthe_hmac_setkey, + .base.halg =3D { + .digestsize =3D MD5_DIGEST_SIZE, + .statesize =3D sizeof(struct dthe_hash_req_ctx), + .base =3D { + .cra_name =3D "hmac(md5)", + .cra_driver_name =3D "hmac-md5-dthev2", + .cra_priority =3D 299, + .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_FINAL_NONZERO | + CRYPTO_AHASH_ALG_FINUP_MAX | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize =3D MD5_BLOCK_SIZE, + .cra_ctxsize =3D sizeof(struct dthe_tfm_ctx), + .cra_reqsize =3D sizeof(struct dthe_hash_req_ctx), + .cra_module =3D THIS_MODULE, + } + }, + .op.do_one_request =3D dthe_hash_run, + }, }; =20 int dthe_register_hash_algs(void) --=20 2.34.1