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Wed, 21 Jan 2026 02:45:44 -0800 From: Sumit Gupta To: , , , , , , , CC: , Subject: [PATCH 1/3] arm64: dts: tegra234: Fix CPU compatible string to cortex-a78ae Date: Wed, 21 Jan 2026 16:15:34 +0530 Message-ID: <20260121104536.3214101-2-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260121104536.3214101-1-sumitg@nvidia.com> References: <20260121104536.3214101-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA4F:EE_|PH0PR12MB8151:EE_ X-MS-Office365-Filtering-Correlation-Id: 883c72dc-601f-4463-7fe8-08de58da42f8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?4pRFBF8Fq+KNBGmTVeCjak70RzO+DJw785Zc9izeK1lQIrAKVHfkxPjt3BTj?= =?us-ascii?Q?1HZICGujI1/LoIAB7SSuw9CF4buLnua1FfA+WPR19xI8phgKLH8vdWf1O0EH?= =?us-ascii?Q?zwQGrhDOvTM+0vgZ8ZfWE7DpQb/ID4i5ykigbyT5tymTp/H04Pj842huFdq8?= =?us-ascii?Q?TK9QzAP4BjI2wFdwvLumgAAyAr6RGT1/sF+1Ygo76xW2uopTXiU7AfZyMGNs?= =?us-ascii?Q?gZFe0+nA+v+4yDuL/E03EiqxCdOuhL44NkOxtBaqMEqB81I9itYNU4dtF6H9?= =?us-ascii?Q?9BGoN1yg65YeC5lrUCzXQY262EPM3MIb9IqHRoqPJZFS+BWBkzqmp/YqBIpv?= =?us-ascii?Q?mBZ7d3ZmX+B8LZ2Vgzd4P4ArCSqzVYovqhhbhuk+fOGr+IM+EuiqS2lHOhpk?= =?us-ascii?Q?SXA8+VWEJNBK+7ZZYN7RpNJU5q5Aj9fc6sJGcDMYNFxQ6Jbi8el3RD7eZo/m?= =?us-ascii?Q?IGM7lgNk3fpnlFtP0deYHkV6T3EUHbmxmFbyj6O3MKO8g736YZ3TBd0TiFNF?= =?us-ascii?Q?RWSb69ryRGwws/oU5dZNfxw6tnZfnko+3OHv8RPp4KO5m16ydem4xfxqsSk1?= =?us-ascii?Q?+Thnnz+QQGgF8ggMdSkgi7W/7FvA3NAwEXe4W5T4vWy/rQFHjEsYJsBuUDWk?= =?us-ascii?Q?EdgQVS1DzpZwF1BYYDoDZpT4lbhvTFsULoq/JC3ETtjAt7vivWYDRUdLhx42?= =?us-ascii?Q?HW0SlKO2/H92Q6gUJpO3OYIVj5K0J8aQglZ5SmxLCOCDEa9iK24YbCudN2QR?= =?us-ascii?Q?38ULnSDDqtNWeoAa8lUchQYDGOmxSbbp0QPxlQ6WDD++L8U0jqAGdwirSqHP?= =?us-ascii?Q?uyXkhXpXMyV/Yze0TYPi9z3HI0WrzDdks7OOlRWhQB8Yb1dbGah8FlOx2a8x?= =?us-ascii?Q?JFrwhwGW90dcxyKFFlCh82AOyG2SUdvvqPYiPgvIHLRNePYhWVpRLZlXbN5F?= =?us-ascii?Q?mMLFwrBAsrnv8wKV8vW2VO49b23tTM0+90hVqXs757dmR4D+mE21GgocUnV4?= =?us-ascii?Q?gI9bk8B4cZa1OtwFvmxCi3MvSq+G30hXBkUUDNXSnEGEERAIB3K96RqGVBJ6?= =?us-ascii?Q?JqIRvsxII7HB1oXVcl6wSwC6gHRkJTi/nMjjcpaJNbtlCHRtM20u75JEir94?= =?us-ascii?Q?Zyi6IYCeqFd4Ql/X78XKtNImR+yF9lrOgast7Gsj9+ux9wtayCBlxVlzFxOq?= =?us-ascii?Q?bmvWzQUa2U0IGmgmAcs+c+na0GSx8NgBv0iBS5YXYhczu/qamhrH951NE4Aw?= =?us-ascii?Q?f1jhiJR0qIpK7NpRoZA4Z0W4IqU5AnQu8R/yv68GRlNiS9ghSxSgnbTIkHYz?= =?us-ascii?Q?h/SMXPiCeK3i1qIv1Y23MgKBq6cOQir1ZHcMcyNsziHrdhzT2CQpcG0xvHqc?= =?us-ascii?Q?Mny0V93TBjhWBqthfGWVLVNkufKaUwdqARlWMUisazgHAW/ADkXrToyJB5y3?= =?us-ascii?Q?5eCc7zrPNr9Igg8uNNsXfiMMyTVAoFt6Cn7an8pEXsWiV4qWTe4rIbrbIFbi?= =?us-ascii?Q?5tdSErtqAJNhCAlS5eeKJu1MW7NhG70XGEF6vumkS6/FLR4UcYQJ1lNYq9lE?= =?us-ascii?Q?ck44bt+6i5J0xXAAz7H0N9KWRhzpohrIF6GePB9BycKeFm+iTRSer0uxmKiJ?= =?us-ascii?Q?DLKWdsY8MdWcYyQPCzjfI+odtnNFhGMpkLudqJh0sM1mXCu+e9w4kpHt2IxI?= =?us-ascii?Q?OgzMPg=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jan 2026 10:45:58.1421 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 883c72dc-601f-4463-7fe8-08de58da42f8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8151 Content-Type: text/plain; charset="utf-8" The Tegra234 SoC uses Cortex-A78AE cores, not Cortex-A78. Update the compatible string for all CPU nodes to match the actual hardware. Tegra234 hardware reports: # head /proc/cpuinfo | egrep 'implementer|part' CPU implementer : 0x41 CPU part : 0xd42 Which maps to (from arch/arm64/include/asm/cputype.h): #define ARM_CPU_IMP_ARM 0x41 #define ARM_CPU_PART_CORTEX_A78AE 0xD42 Fixes: a12cf5c339b08 ("arm64: tegra: Describe Tegra234 CPU hierarchy") Signed-off-by: Sumit Gupta --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts= /nvidia/tegra234.dtsi index 850c473235e3..13ec999e52ef 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -5339,7 +5339,7 @@ cpus { #size-cells =3D <0>; =20 cpu0_0: cpu@0 { - compatible =3D "arm,cortex-a78"; + compatible =3D "arm,cortex-a78ae"; device_type =3D "cpu"; reg =3D <0x00000>; =20 @@ -5358,7 +5358,7 @@ cpu0_0: cpu@0 { }; =20 cpu0_1: cpu@100 { - compatible =3D "arm,cortex-a78"; + compatible =3D "arm,cortex-a78ae"; device_type =3D "cpu"; reg =3D <0x00100>; =20 @@ -5377,7 +5377,7 @@ cpu0_1: cpu@100 { }; =20 cpu0_2: cpu@200 { - compatible =3D "arm,cortex-a78"; + compatible =3D "arm,cortex-a78ae"; device_type =3D "cpu"; reg =3D <0x00200>; =20 @@ -5396,7 +5396,7 @@ cpu0_2: cpu@200 { }; =20 cpu0_3: cpu@300 { - compatible =3D "arm,cortex-a78"; + compatible =3D "arm,cortex-a78ae"; device_type =3D "cpu"; reg =3D <0x00300>; =20 @@ -5415,7 +5415,7 @@ cpu0_3: cpu@300 { }; =20 cpu1_0: cpu@10000 { - compatible =3D "arm,cortex-a78"; + compatible =3D "arm,cortex-a78ae"; device_type =3D "cpu"; reg =3D <0x10000>; =20 @@ -5434,7 +5434,7 @@ cpu1_0: cpu@10000 { }; =20 cpu1_1: cpu@10100 { - compatible =3D "arm,cortex-a78"; + compatible =3D "arm,cortex-a78ae"; device_type =3D "cpu"; reg =3D <0x10100>; =20 @@ -5453,7 +5453,7 @@ cpu1_1: cpu@10100 { }; =20 cpu1_2: cpu@10200 { - compatible =3D "arm,cortex-a78"; + compatible =3D "arm,cortex-a78ae"; device_type =3D "cpu"; reg =3D <0x10200>; =20 @@ -5472,7 +5472,7 @@ cpu1_2: cpu@10200 { }; =20 cpu1_3: cpu@10300 { - compatible =3D "arm,cortex-a78"; + compatible =3D "arm,cortex-a78ae"; device_type =3D "cpu"; reg =3D <0x10300>; =20 @@ -5491,7 +5491,7 @@ cpu1_3: cpu@10300 { }; =20 cpu2_0: cpu@20000 { - compatible =3D "arm,cortex-a78"; + compatible =3D "arm,cortex-a78ae"; device_type =3D "cpu"; reg =3D <0x20000>; =20 @@ -5510,7 +5510,7 @@ cpu2_0: cpu@20000 { }; =20 cpu2_1: cpu@20100 { - compatible =3D "arm,cortex-a78"; + compatible =3D "arm,cortex-a78ae"; device_type =3D "cpu"; reg =3D <0x20100>; =20 @@ -5529,7 +5529,7 @@ cpu2_1: cpu@20100 { }; =20 cpu2_2: cpu@20200 { - compatible =3D "arm,cortex-a78"; + compatible =3D "arm,cortex-a78ae"; device_type =3D "cpu"; reg =3D <0x20200>; =20 @@ -5548,7 +5548,7 @@ cpu2_2: cpu@20200 { }; =20 cpu2_3: cpu@20300 { - compatible =3D "arm,cortex-a78"; + compatible =3D "arm,cortex-a78ae"; device_type =3D "cpu"; reg =3D <0x20300>; =20 --=20 2.34.1