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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , "Russell King (Oracle)" , Yao Zi , Yanteng Si , Vladimir Oltean , Inochi Amaoto , Lad Prabhakar , Chen-Yu Tsai , Choong Yong Liang , Shangjuan Wei , Jernej Skrabec , Boon Khai Ng , Maxime Chevallier , Quentin Schulz , Giuseppe Cavallaro , Jose Abreu Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Longbin Li Subject: [PATCH net-next v2 3/3] net: stmmac: Add glue layer for Spacemit K3 SoC Date: Wed, 21 Jan 2026 15:13:11 +0800 Message-ID: <20260121071315.940130-4-inochiama@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260121071315.940130-1-inochiama@gmail.com> References: <20260121071315.940130-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The etherenet controller on Spacemit K3 SoC is Synopsys DesignWare MAC (version 5.40a), with the following special point: 1. The rate of the tx clock line is auto changed when the mac speed rate is changed, and no need for changing the input tx clock. 2. This controller require a extra syscon device to configure the interface type, enable wake up interrupt and delay configuration if needed. Add Spacemit dwmac driver support on the Spacemit K3 SoC. Signed-off-by: Inochi Amaoto --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + .../ethernet/stmicro/stmmac/dwmac-spacemit.c | 221 ++++++++++++++++++ 3 files changed, 234 insertions(+) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethe= rnet/stmicro/stmmac/Kconfig index 907fe2e927f0..583a4692f5da 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -216,6 +216,18 @@ config DWMAC_SOPHGO for the stmmac device driver. This driver is used for the ethernet controllers on various Sophgo SoCs. =20 +config DWMAC_SPACEMIT + tristate "Spacemit dwmac support" + depends on OF && (ARCH_SPACEMIT || COMPILE_TEST) + select MFD_SYSCON + default m if ARCH_SPACEMIT + help + Support for ethernet controllers on Spacemit RISC-V SoCs + + This selects the Spacemit platform specific glue layer support + for the stmmac device driver. This driver is used for the + Spacemit K3 ethernet controllers. + config DWMAC_STARFIVE tristate "StarFive dwmac support" depends on OF && (ARCH_STARFIVE || COMPILE_TEST) diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/eth= ernet/stmicro/stmmac/Makefile index 7bf528731034..9e32045631d8 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_DWMAC_RZN1) +=3D dwmac-rzn1.o obj-$(CONFIG_DWMAC_S32) +=3D dwmac-s32.o obj-$(CONFIG_DWMAC_SOCFPGA) +=3D dwmac-altr-socfpga.o obj-$(CONFIG_DWMAC_SOPHGO) +=3D dwmac-sophgo.o +obj-$(CONFIG_DWMAC_SPACEMIT) +=3D dwmac-spacemit.o obj-$(CONFIG_DWMAC_STARFIVE) +=3D dwmac-starfive.o obj-$(CONFIG_DWMAC_STI) +=3D dwmac-sti.o obj-$(CONFIG_DWMAC_STM32) +=3D dwmac-stm32.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c b/drivers= /net/ethernet/stmicro/stmmac/dwmac-spacemit.c new file mode 100644 index 000000000000..ca600c068aaa --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c @@ -0,0 +1,221 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Spacemit DWMAC platform driver + * + * Copyright (C) 2026 Inochi Amaoto + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stmmac_platform.h" + +/* ctrl register bits */ +#define PHY_INTF_RGMII BIT(3) +#define PHY_INTF_MII BIT(4) + +#define WAKE_IRQ_EN BIT(9) +#define PHY_IRQ_EN BIT(12) + +/* dline register bits */ +#define RGMII_RX_DLINE_EN BIT(0) +#define RGMII_RX_DLINE_STEP GENMASK(5, 4) +#define RGMII_RX_DLINE_CODE GENMASK(15, 8) +#define RGMII_TX_DLINE_EN BIT(16) +#define RGMII_TX_DLINE_STEP GENMASK(21, 20) +#define RGMII_TX_DLINE_CODE GENMASK(31, 24) + +#define MAX_DLINE_DELAY_CODE 0xff +#define MAX_WORKED_DELAY 2800 + +/* Note: the delay step value is at 0.1ps */ +static const unsigned int k3_delay_step_10x[4] =3D { + 367, 493, 559, 685 +}; + +static int spacemit_dwmac_set_delay(struct regmap *apmu, + unsigned int dline_offset, + unsigned int tx_code, unsigned int tx_config, + unsigned int rx_code, unsigned int rx_config) +{ + unsigned int mask, val; + + mask =3D RGMII_RX_DLINE_STEP | RGMII_TX_DLINE_CODE | RGMII_TX_DLINE_EN | + RGMII_TX_DLINE_STEP | RGMII_RX_DLINE_CODE | RGMII_RX_DLINE_EN; + val =3D FIELD_PREP(RGMII_TX_DLINE_STEP, tx_config) | + FIELD_PREP(RGMII_TX_DLINE_CODE, tx_code) | RGMII_TX_DLINE_EN | + FIELD_PREP(RGMII_RX_DLINE_STEP, rx_config) | + FIELD_PREP(RGMII_RX_DLINE_CODE, rx_code) | RGMII_RX_DLINE_EN; + + return regmap_update_bits(apmu, dline_offset, mask, val); +} + +static int spacemit_dwmac_detected_delay_value(unsigned int delay, + unsigned int *config) +{ + unsigned int best_delay =3D 0; + unsigned int best_config =3D 0; + int best_code =3D 0; + int i; + + if (delay =3D=3D 0) + return 0; + + if (delay > MAX_WORKED_DELAY) + return -EINVAL; + + for (i =3D 0; i < ARRAY_SIZE(k3_delay_step_10x); i++) { + unsigned int step =3D k3_delay_step_10x[i]; + int code =3D DIV_ROUND_CLOSEST(delay * 10 * 10, step * 9); + unsigned int tmp =3D code * step * 9 / 10 / 10; + + if (abs(tmp - delay) < abs(best_delay - delay)) { + best_code =3D code; + best_delay =3D tmp; + best_config =3D i; + } + } + + *config =3D best_config; + + return best_code; +} + +static int spacemit_dwmac_fix_delay(struct plat_stmmacenet_data *plat_dat, + struct regmap *apmu, + unsigned int dline_offset, + unsigned int tx_delay, unsigned int rx_delay) +{ + bool mac_rxid =3D rx_delay !=3D 0; + bool mac_txid =3D tx_delay !=3D 0; + unsigned int rx_config =3D 0; + unsigned int tx_config =3D 0; + int rx_code; + int tx_code; + + plat_dat->phy_interface =3D phy_fix_phy_mode_for_mac_delays(plat_dat->phy= _interface, + mac_txid, + mac_rxid); + + if (plat_dat->phy_interface =3D=3D PHY_INTERFACE_MODE_NA) + return -EINVAL; + + rx_code =3D spacemit_dwmac_detected_delay_value(rx_delay, &rx_config); + if (rx_code < 0) + return rx_code; + + tx_code =3D spacemit_dwmac_detected_delay_value(tx_delay, &tx_config); + if (tx_code < 0) + return tx_code; + + return spacemit_dwmac_set_delay(apmu, dline_offset, + tx_code, tx_config, + rx_code, rx_config); +} + +static int spacemit_dwmac_update_ifconfig(struct plat_stmmacenet_data *pla= t_dat, + struct stmmac_resources *stmmac_res, + struct regmap *apmu, + unsigned int ctrl_offset) +{ + unsigned int mask =3D PHY_INTF_MII | PHY_INTF_RGMII | WAKE_IRQ_EN; + unsigned int val =3D 0; + + switch (plat_dat->phy_interface) { + case PHY_INTERFACE_MODE_MII: + val =3D PHY_INTF_MII; + break; + + case PHY_INTERFACE_MODE_RMII: + break; + + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + val =3D PHY_INTF_RGMII; + break; + + default: + return -EOPNOTSUPP; + } + + if (stmmac_res->wol_irq >=3D 0) + val |=3D WAKE_IRQ_EN; + + return regmap_update_bits(apmu, ctrl_offset, mask, val); +} + +static int spacemit_dwmac_probe(struct platform_device *pdev) +{ + struct plat_stmmacenet_data *plat_dat; + struct stmmac_resources stmmac_res; + struct device *dev =3D &pdev->dev; + unsigned int offset[2]; + struct regmap *apmu; + u32 rx_delay =3D 0; + u32 tx_delay =3D 0; + int ret; + + ret =3D stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return dev_err_probe(dev, ret, + "failed to get platform resources\n"); + + plat_dat =3D devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); + if (IS_ERR(plat_dat)) + return dev_err_probe(dev, PTR_ERR(plat_dat), + "failed to parse DT parameters\n"); + + plat_dat->clk_tx_i =3D devm_clk_get_enabled(&pdev->dev, "tx"); + if (IS_ERR(plat_dat->clk_tx_i)) + return dev_err_probe(&pdev->dev, PTR_ERR(plat_dat->clk_tx_i), + "failed to get tx clock\n"); + + apmu =3D syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node, "spacemi= t,apmu", 2, offset); + if (IS_ERR(apmu)) + return dev_err_probe(dev, PTR_ERR(apmu), + "Failed to get apmu regmap\n"); + + ret =3D spacemit_dwmac_update_ifconfig(plat_dat, &stmmac_res, + apmu, offset[0]); + if (ret) + return dev_err_probe(dev, ret, "Failed to configure ifconfig\n"); + + of_property_read_u32(pdev->dev.of_node, "tx-internal-delay-ps", &tx_delay= ); + of_property_read_u32(pdev->dev.of_node, "rx-internal-delay-ps", &rx_delay= ); + + ret =3D spacemit_dwmac_fix_delay(plat_dat, apmu, offset[1], tx_delay, rx_= delay); + if (ret) + return dev_err_probe(dev, ret, "Failed to configure delay\n"); + + return stmmac_dvr_probe(dev, plat_dat, &stmmac_res); +} + +static const struct of_device_id spacemit_dwmac_match[] =3D { + { .compatible =3D "spacemit,k3-dwmac" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, spacemit_dwmac_match); + +static struct platform_driver spacemit_dwmac_driver =3D { + .probe =3D spacemit_dwmac_probe, + .remove =3D stmmac_pltfr_remove, + .driver =3D { + .name =3D "spacemit-dwmac", + .pm =3D &stmmac_pltfr_pm_ops, + .of_match_table =3D spacemit_dwmac_match, + }, +}; +module_platform_driver(spacemit_dwmac_driver); + +MODULE_AUTHOR("Inochi Amaoto "); +MODULE_DESCRIPTION("Spacemit DWMAC platform driver"); +MODULE_LICENSE("GPL"); --=20 2.52.0