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Wed, 21 Jan 2026 08:40:31 -0800 (PST) From: Neil Armstrong Date: Wed, 21 Jan 2026 17:40:26 +0100 Subject: [PATCH 1/3] dt-binding: vendor-prefixes: document the Ayeneo brand Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-topic-sm8650-ayaneo-pocket-s2-base-v1-1-bb3f95f1c085@linaro.org> References: <20260121-topic-sm8650-ayaneo-pocket-s2-base-v1-0-bb3f95f1c085@linaro.org> In-Reply-To: <20260121-topic-sm8650-ayaneo-pocket-s2-base-v1-0-bb3f95f1c085@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Neil Armstrong X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Document the Ayaneo from the Anyun Intelligent Technology (Hong Kong) Co., Ltd company. Website: https://www.ayaneo.com/product/ayaneobrand.html Signed-off-by: Neil Armstrong Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index c7591b2aec2a..1f83979e0d09 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -216,6 +216,8 @@ patternProperties: "^axiado,.*": description: Axiado Corporation "^axis,.*": + description: Anyun Intelligent Technology (Hong Kong) Co., Ltd + "^ayaneo,.*": description: Axis Communications AB "^azoteq,.*": description: Azoteq (Pty) Ltd --=20 2.34.1 From nobody Mon Feb 9 13:10:35 2026 Received: from mail-wm1-f66.google.com (mail-wm1-f66.google.com [209.85.128.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADF9248B374 for ; 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Wed, 21 Jan 2026 08:40:33 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:3d9:2080:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-480470287c3sm1000255e9.3.2026.01.21.08.40.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jan 2026 08:40:32 -0800 (PST) From: Neil Armstrong Date: Wed, 21 Jan 2026 17:40:27 +0100 Subject: [PATCH 2/3] dt-bindings: arm: qcom: document the Ayaneo Pocket S2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-topic-sm8650-ayaneo-pocket-s2-base-v1-2-bb3f95f1c085@linaro.org> References: <20260121-topic-sm8650-ayaneo-pocket-s2-base-v1-0-bb3f95f1c085@linaro.org> In-Reply-To: <20260121-topic-sm8650-ayaneo-pocket-s2-base-v1-0-bb3f95f1c085@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Neil Armstrong X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Document the Qualcomm SM8650 based Ayaneo Pocket S2 gaming console. Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index d84bd3bca201..c6786dac5b59 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1045,6 +1045,7 @@ properties: - qcom,sm8650-hdk - qcom,sm8650-mtp - qcom,sm8650-qrd + - ayaneo,pocket-s2 - const: qcom,sm8650 =20 - items: --=20 2.34.1 From nobody Mon Feb 9 13:10:35 2026 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6034A3BC4C8 for ; Wed, 21 Jan 2026 16:40:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Wed, 21 Jan 2026 08:40:35 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:3d9:2080:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-480470287c3sm1000255e9.3.2026.01.21.08.40.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jan 2026 08:40:34 -0800 (PST) From: Neil Armstrong Date: Wed, 21 Jan 2026 17:40:28 +0100 Subject: [PATCH 3/3] arm64: dts: qcom: add basic devicetree for Ayaneo Pocket S2 gaming console Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-topic-sm8650-ayaneo-pocket-s2-base-v1-3-bb3f95f1c085@linaro.org> References: <20260121-topic-sm8650-ayaneo-pocket-s2-base-v1-0-bb3f95f1c085@linaro.org> In-Reply-To: <20260121-topic-sm8650-ayaneo-pocket-s2-base-v1-0-bb3f95f1c085@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Neil Armstrong , KancyJoe X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE From: KancyJoe Add initial Device Tree for the Ayaneo Pocket S2 gaming console based on the Qualcomm Snapdragon 8 Gen 3 platform. The design is similar to a phone wihout the modem, the game control is handled via a standalone controller connected to a PCIe USB controller. Display support will be added in a second time. Signed-off-by: KancyJoe Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts | 1445 ++++++++++++++++= ++++ arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +- drivers/gpu/drm/msm/dsi/dsi.c | 4 +- 4 files changed, 1449 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 6f34d5ed331c..1ba29755e5ba 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -313,6 +313,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sm8550-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8550-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8550-samsung-q5q.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8550-sony-xperia-yodo-pdx234.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sm8650-ayaneo-pocket-s2.dtb =20 sm8650-hdk-display-card-dtbs :=3D sm8650-hdk.dtb sm8650-hdk-display-card.d= tbo =20 diff --git a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts b/arch/ar= m64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts new file mode 100644 index 000000000000..141d92933957 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts @@ -0,0 +1,1445 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + * Copyright (c) 2025, Kancy Joe + */ + +/dts-v1/; + +#include +#include +#include "sm8650.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#define PMK8550VE_SID 8 +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" + +/delete-node/ &rmtfs_mem; +/delete-node/ &hwfence_shbuf; + +/ { + model =3D "AYANEO Pocket S2 (Pro)"; + compatible =3D "ayaneo,pocket-s2", "qcom,sm8650"; + + aliases { + serial0 =3D &uart15; + serial1 =3D &uart14; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + fan: pwm-fan { + status =3D "okay"; + compatible =3D "pwm-fan"; + + interrupt-parent =3D <&tlmm>; + interrupts =3D <14 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 =3D <&fan_pwr_active>, + <&pwm_fan_ctrl_default>, + <&fan_int_active>; + pinctrl-1 =3D <&fan_pwr_sleep>; + pinctrl-names =3D "default", + "sleep"; + + pwms =3D <&pm8550_pwm 3 50000>; + + #cooling-cells =3D <2>; + cooling-levels =3D <0 16 32 45 60 80 105 130 155 180 205 230 255>; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + pinctrl-0 =3D <&volume_up_n>; + pinctrl-names =3D "default"; + + key-volume-up { + label =3D "Volume Up"; + linux,code =3D ; + gpios =3D <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval =3D <15>; + linux,can-disable; + wakeup-source; + }; + }; + + pmic-glink { + compatible =3D "qcom,sm8650-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + orientation-gpios =3D <&tlmm 29 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible =3D "usb-c-connector"; + reg =3D <0>; + + power-role =3D "dual"; + data-role =3D "dual"; + self-powered; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint =3D <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg =3D <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint =3D <&redriver_ss_out>; + }; + }; + + port@2 { + reg =3D <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint =3D <&wcd_usbss_sbu_mux>; + }; + }; + }; + }; + }; + + sound { + compatible =3D "qcom,sm8650-sndcard", "qcom,sm8450-sndcard"; + model =3D "SM8650-APS2"; + audio-routing =3D "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "DMIC1", "MIC BIAS1", + "DMIC2", "MIC BIAS2", + "AMIC2", "MIC BIAS2", + "TX SWR_INPUT1", "ADC2_OUTPUT", + "TX SWR_INPUT7", "DMIC1_OUTPUT", + "TX SWR_INPUT8", "DMIC2_OUTPUT"; + + wcd-playback-dai-link { + link-name =3D "WCD Playback"; + + cpu { + sound-dai =3D <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai =3D <&wcd939x 0>, + <&swr1 0>, + <&lpass_rxmacro 0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name =3D "WCD Capture"; + + cpu { + sound-dai =3D <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai =3D <&wcd939x 1>, + <&swr2 0>, + <&lpass_txmacro 0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + wsa-dai-link { + link-name =3D "WSA Playback"; + + cpu { + sound-dai =3D <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai =3D <&right_spkr>, + <&left_spkr>, + <&swr3 0>, + <&lpass_wsa2macro 0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + }; + + wcd939x: audio-codec { + compatible =3D "qcom,wcd9395-codec", "qcom,wcd9390-codec"; + + pinctrl-0 =3D <&wcd_default>; + pinctrl-names =3D "default"; + + qcom,micbias1-microvolt =3D <1800000>; + qcom,micbias2-microvolt =3D <1800000>; + qcom,micbias3-microvolt =3D <1800000>; + qcom,micbias4-microvolt =3D <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt =3D <75000 150000 237000 500000 5= 00000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt =3D <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt =3D <50000>; + qcom,rx-device =3D <&wcd_rx>; + qcom,tx-device =3D <&wcd_tx>; + + reset-gpios =3D <&tlmm 107 GPIO_ACTIVE_LOW>; + + vdd-buck-supply =3D <&vreg_l15b_1p8>; + vdd-rxtx-supply =3D <&vreg_l15b_1p8>; + vdd-io-supply =3D <&vreg_l15b_1p8>; + vdd-mic-bias-supply =3D <&vreg_bob1>; + + #sound-dai-cells =3D <1>; + + mode-switch; + orientation-switch; + + port { + wcd_codec_headset_in: endpoint { + remote-endpoint =3D <&wcd_usbss_headset_out>; + }; + }; + }; + + thermal-zones { + cpu2-top-thermal { + trips { + cpu2_active: cpu2-active { + temperature =3D <38000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + }; + + cooling-maps { + map { + trip =3D <&cpu2_active>; + cooling-device =3D <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu3-top-thermal { + trips { + cpu3_active: cpu3-active { + temperature =3D <38000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + }; + + cooling-maps { + map { + trip =3D <&cpu3_active>; + cooling-device =3D <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + + cpu4-top-thermal { + trips { + cpu4_active: cpu4-top-active { + temperature =3D <38000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + }; + + cooling-maps { + map { + trip =3D <&cpu4_active>; + cooling-device =3D <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu5-top-thermal { + trips { + cpu5_active: cpu5-active { + temperature =3D <38000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + }; + + cooling-maps { + map { + trip =3D <&cpu5_active>; + cooling-device =3D <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu6-top-thermal { + trips { + cpu6_active: cpu6-active { + temperature =3D <38000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + }; + + cooling-maps { + map { + trip =3D <&cpu6_active>; + cooling-device =3D <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu7-top-thermal { + trips { + cpu7_active: cpu7-active { + temperature =3D <38000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + }; + + cooling-maps { + map { + trip =3D <&cpu7_active>; + cooling-device =3D <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpuss0-thermal { + trips { + gpuss0_active: gpuss0-active { + temperature =3D <38000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + }; + + cooling-maps { + map { + trip =3D <&gpuss0_active>; + cooling-device =3D <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpuss1-thermal { + trips { + gpuss1_active: gpuss1-active { + temperature =3D <38000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + }; + + cooling-maps { + map { + trip =3D <&gpuss1_active>; + cooling-device =3D <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpuss2-thermal { + trips { + gpuss2_active: gpuss2-active { + temperature =3D <38000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + }; + + cooling-maps { + map { + trip =3D <&gpuss2_active>; + cooling-device =3D <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpuss3-thermal { + trips { + gpuss3_active: gpuss3-active { + temperature =3D <38000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + }; + + cooling-maps { + map { + trip =3D <&gpuss3_active>; + cooling-device =3D <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpuss4-thermal { + trips { + gpuss4_active: gpuss4-active { + temperature =3D <38000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + }; + + cooling-maps { + map { + trip =3D <&gpuss4_active>; + cooling-device =3D <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpuss5-thermal { + trips { + gpuss5_active: gpuss5-active { + temperature =3D <38000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + }; + + cooling-maps { + map { + trip =3D <&gpuss5_active>; + cooling-device =3D <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpuss6-thermal { + trips { + gpuss6_active: gpuss6-active { + temperature =3D <38000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + }; + + cooling-maps { + map { + trip =3D <&gpuss6_active>; + cooling-device =3D <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible =3D "regulator-fixed"; + + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + wcn7850-pmu { + compatible =3D "qcom,wcn7850-pmu"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wlan_en>, <&bt_default>; + + wlan-enable-gpios =3D <&tlmm 16 GPIO_ACTIVE_HIGH>; + bt-enable-gpios =3D <&tlmm 17 GPIO_ACTIVE_HIGH>; + + vdd-supply =3D <&vreg_s4i_0p85>; + vddio-supply =3D <&vreg_l15b_1p8>; + vddio1p2-supply =3D <&vreg_l3c_1p2>; + vddaon-supply =3D <&vreg_s2c_0p8>; + vdddig-supply =3D <&vreg_s3c_0p9>; + vddrfa1p2-supply =3D <&vreg_s1c_1p2>; + vddrfa1p8-supply =3D <&vreg_s6c_1p8>; + + clocks =3D <&rpmhcc RPMH_RF_CLK1>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name =3D "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name =3D "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name =3D "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name =3D "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name =3D "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name =3D "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name =3D "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name =3D "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name =3D "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name =3D "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm8550-rpmh-regulators"; + + vdd-bob1-supply =3D <&vph_pwr>; + vdd-bob2-supply =3D <&vph_pwr>; + vdd-l2-l13-l14-supply =3D <&vreg_bob1>; + vdd-l3-supply =3D <&vreg_s1c_1p2>; + vdd-l5-l16-supply =3D <&vreg_bob1>; + vdd-l6-l7-supply =3D <&vreg_bob1>; + vdd-l8-l9-supply =3D <&vreg_bob1>; + vdd-l11-supply =3D <&vreg_s1c_1p2>; + vdd-l12-supply =3D <&vreg_s6c_1p8>; + vdd-l15-supply =3D <&vreg_s6c_1p8>; + vdd-l17-supply =3D <&vreg_bob2>; + + qcom,pmic-id =3D "b"; + + vreg_bob1: bob1 { + regulator-name =3D "vreg_bob1"; + regulator-min-microvolt =3D <3296000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + }; + + vreg_bob2: bob2 { + regulator-name =3D "vreg_bob2"; + regulator-min-microvolt =3D <2720000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name =3D "vreg_l2b_3p0"; + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name =3D "vreg_l5b_3p1"; + regulator-min-microvolt =3D <3104000>; + regulator-max-microvolt =3D <3104000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name =3D "vreg_l6b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name =3D "vreg_l7b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name =3D "vreg_l8b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name =3D "vreg_l9b_2p9"; + regulator-min-microvolt =3D <2960000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l11b_1p2: ldo11 { + regulator-name =3D "vreg_l11b_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1504000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name =3D "vreg_l12b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name =3D "vreg_l13b_3p0"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name =3D "vreg_l14b_3p2"; + regulator-min-microvolt =3D <3200000>; + regulator-max-microvolt =3D <3200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name =3D "vreg_l15b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l16b_2p8: ldo16 { + regulator-name =3D "vreg_l16b_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + regulator-always-on; + regulator-boot-on; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name =3D "vreg_l17b_2p5"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <2504000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply =3D <&vreg_s1c_1p2>; + vdd-l2-supply =3D <&vreg_s1c_1p2>; + vdd-l3-supply =3D <&vreg_s1c_1p2>; + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-s6-supply =3D <&vph_pwr>; + + qcom,pmic-id =3D "c"; + + vreg_s1c_1p2: smps1 { + regulator-name =3D "vreg_s1c_1p2"; + regulator-min-microvolt =3D <1256000>; + regulator-max-microvolt =3D <1348000>; + regulator-initial-mode =3D ; + }; + + vreg_s2c_0p8: smps2 { + regulator-name =3D "vreg_s2c_0p8"; + regulator-min-microvolt =3D <852000>; + regulator-max-microvolt =3D <1036000>; + regulator-initial-mode =3D ; + }; + + vreg_s3c_0p9: smps3 { + regulator-name =3D "vreg_s3c_0p9"; + regulator-min-microvolt =3D <976000>; + regulator-max-microvolt =3D <1064000>; + regulator-initial-mode =3D ; + }; + + vreg_s4c_1p2: smps4 { + regulator-name =3D "vreg_s4c_1p2"; + regulator-min-microvolt =3D <1224000>; + regulator-max-microvolt =3D <1280000>; + regulator-initial-mode =3D ; + }; + + vreg_s5c_0p7: smps5 { + regulator-name =3D "vreg_s5c_0p7"; + regulator-min-microvolt =3D <752000>; + regulator-max-microvolt =3D <900000>; + regulator-initial-mode =3D ; + }; + + vreg_s6c_1p8: smps6 { + regulator-name =3D "vreg_s6c_1p8"; + regulator-min-microvolt =3D <1856000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name =3D "vreg_l1c_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3c_1p2: ldo3 { + regulator-name =3D "vreg_l3c_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + regulator-always-on; + regulator-boot-on; + }; + }; + + regulators-2 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply =3D <&vreg_s3c_0p9>; + + qcom,pmic-id =3D "d"; + + vreg_l1d_0p88: ldo1 { + regulator-name =3D "vreg_l1d_0p88"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-3 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + + vdd-l3-supply =3D <&vreg_s3c_0p9>; + + qcom,pmic-id =3D "e"; + + vreg_l3e_0p9: ldo3 { + regulator-name =3D "vreg_l3e_0p9"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-4 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply =3D <&vreg_s3c_0p9>; + vdd-l3-supply =3D <&vreg_s3c_0p9>; + + qcom,pmic-id =3D "g"; + + vreg_l1g_0p91: ldo1 { + regulator-name =3D "vreg_l1g_0p91"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3g_0p91: ldo3 { + regulator-name =3D "vreg_l3g_0p91"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-5 { + compatible =3D "qcom,pm8550ve-rpmh-regulators"; + + vdd-l1-supply =3D <&vreg_s3c_0p9>; + vdd-l2-supply =3D <&vreg_s3c_0p9>; + vdd-l3-supply =3D <&vreg_s1c_1p2>; + vdd-s4-supply =3D <&vph_pwr>; + + qcom,pmic-id =3D "i"; + + vreg_s4i_0p85: smps4 { + regulator-name =3D "vreg_s4i_0p85"; + regulator-min-microvolt =3D <852000>; + regulator-max-microvolt =3D <1004000>; + regulator-initial-mode =3D ; + }; + + vreg_l1i_0p88: ldo1 { + regulator-name =3D "vreg_l1i_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2i_0p88: ldo2 { + regulator-name =3D "vreg_l2i_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3i_1p2: ldo3 { + regulator-name =3D "vreg_l3i_0p91"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; +}; + +&gpi_dma1 { + status =3D "okay"; +}; + +&gpi_dma2 { + status =3D "okay"; +}; + +&i2c3 { + status =3D "okay"; + + wcd_usbss: typec-mux@e { + compatible =3D "qcom,wcd9395-usbss", "qcom,wcd9390-usbss"; + reg =3D <0xe>; + + vdd-supply =3D <&vreg_l15b_1p8>; + reset-gpios =3D <&tlmm 152 GPIO_ACTIVE_HIGH>; + + mode-switch; + orientation-switch; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + wcd_usbss_sbu_mux: endpoint { + remote-endpoint =3D <&pmic_glink_sbu>; + }; + }; + + port@1 { + reg =3D <1>; + + wcd_usbss_headset_out: endpoint { + remote-endpoint =3D <&wcd_codec_headset_in>; + }; + }; + }; + }; +}; + +&i2c6 { + status =3D "okay"; + + typec-mux@1c { + compatible =3D "onnn,nb7vpq904m"; + reg =3D <0x1c>; + + vcc-supply =3D <&vreg_l15b_1p8>; + + retimer-switch; + orientation-switch; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + redriver_ss_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss_in>; + }; + }; + + port@1 { + reg =3D <1>; + + redriver_ss_in: endpoint { + remote-endpoint =3D <&usb_dp_qmpphy_out>; + }; + }; + }; + }; +}; + +&iris { + status =3D "okay"; +}; + +&lpass_wsa2macro { + status =3D "okay"; +}; + +&mdss { + status =3D "okay"; +}; + +&mdss_dp0 { + status =3D "okay"; +}; + +&mdss_dp0_out { + data-lanes =3D <0 1>; + + status =3D "okay"; +}; + +&pcie0 { + wake-gpios =3D <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios =3D <&tlmm 94 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&pcie0_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcieport0 { + wifi@0 { + compatible =3D "pci17cb,1107"; + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + + vddrfacmn-supply =3D <&vreg_pmu_rfa_cmn>; + vddaon-supply =3D <&vreg_pmu_aon_0p59>; + vddwlcx-supply =3D <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply =3D <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply =3D <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply =3D <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply =3D <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply =3D <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply =3D <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie0_phy { + vdda-phy-supply =3D <&vreg_l1i_0p88>; + vdda-pll-supply =3D <&vreg_l3i_1p2>; + + status =3D "okay"; +}; + +&pcie1 { + wake-gpios =3D <&tlmm 99 GPIO_ACTIVE_HIGH>; + perst-gpios =3D <&tlmm 97 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&pcie1_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcieport1 { + pinctrl-0 =3D <&upd720201_active>; + pinctrl-names =3D "default"; + + /* Renesas =CE=BCPD720201 PCIe USB3.0 HOST CONTROLLER */ + usb-controller@0 { + compatible =3D "pci1912,0014"; + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + + pinctrl-0 =3D <&gamepad_pwr_en>; + pinctrl-names =3D "default"; + }; +}; + +&pcie1_phy { + vdda-phy-supply =3D <&vreg_l3e_0p9>; + vdda-pll-supply =3D <&vreg_l3i_1p2>; + vdda-qref-supply =3D <&vreg_l1i_0p88>; + + status =3D "okay"; +}; + +&pon_pwrkey { + status =3D "okay"; +}; + +&pon_resin { + linux,code =3D ; + + status =3D "okay"; +}; + +&pm8550_gpios { + volume_up_n: volume-up-n-state { + pins =3D "gpio6"; + function =3D "normal"; + bias-pull-up; + input-enable; + power-source =3D <1>; + }; + + pwm_fan_ctrl_default: pwm-fan-ctrl-default-state { + pins =3D "gpio9"; + function =3D "normal"; + output-low; + bias-disable; + power-source =3D <0>; + qcom,drive-strength =3D <3>; /* PMIC_GPIO_STRENGTH_LOW */ + }; + + pwm_fan_ctrl_sleep: pwm-fan-ctrl-sleep-state { + pins =3D "gpio9"; + function =3D "normal"; + output-high; + bias-disable; + power-source =3D <0>; + qcom,drive-strength =3D <3>; /* PMIC_GPIO_STRENGTH_LOW */ + }; + + sdc2_card_det_n: sdc2-card-det-state { + pins =3D "gpio12"; + function =3D "normal"; + bias-pull-up; + input-enable; + output-disable; + power-source =3D <1>; /* 1.8 V */ + }; +}; + +&pm8550_pwm { + status =3D "okay"; + + multi-led { + color =3D ; + function =3D LED_FUNCTION_STATUS; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@1 { + reg =3D <1>; + color =3D ; + }; + + led@2 { + reg =3D <2>; + color =3D ; + }; + + led@3 { + reg =3D <3>; + color =3D ; + }; + }; +}; + +&pm8550b_eusb2_repeater { + vdd18-supply =3D <&vreg_l15b_1p8>; + vdd3-supply =3D <&vreg_l5b_3p1>; +}; + +&qup_i2c3_data_clk { + /* Use internal I2C pull-up */ + bias-pull-up =3D <2200>; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/sm8650/ayaneo/ps2/adsp.mbn", + "qcom/sm8650/ayaneo/ps2/adsp_dtb.mbn"; + + status =3D "okay"; +}; + +&remoteproc_cdsp { + firmware-name =3D "qcom/sm8650/ayaneo/ps2/cdsp.mbn", + "qcom/sm8650/ayaneo/ps2/cdsp_dtb.mbn"; + + status =3D "okay"; +}; + +&reserved_memory { + lost_reg_mem: lost-reg-mem { + reg =3D <0 0x9b09c000 0 0x4000>; + no-map; + }; + + hwfence_shbuf: hwfence-shbuf@d4e23000 { + reg =3D <0 0xd4e23000 0 0x2dd000>; + no-map; + }; + + splash_region: splash-region { + label =3D "cont_splash_region"; + reg =3D <0 0xd5100000 0 0x2b00000>; + no-map; + }; +}; + +&sdhc_2 { + cd-gpios =3D <&pm8550_gpios 12 GPIO_ACTIVE_LOW>; + + vmmc-supply =3D <&vreg_l9b_2p9>; + vqmmc-supply =3D <&vreg_l8b_1p8>; + bus-width =3D <4>; + no-sdio; + no-mmc; + + pinctrl-0 =3D <&sdc2_default>, <&sdc2_card_det_n>; + pinctrl-1 =3D <&sdc2_sleep>, <&sdc2_card_det_n>; + pinctrl-names =3D "default", "sleep"; + + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32764>; +}; + +&swr1 { + status =3D "okay"; + + /* WCD9395 RX */ + wcd_rx: codec@0,4 { + compatible =3D "sdw20217010e00"; + reg =3D <0 4>; + + /* + * WCD9395 RX Port 1 (HPH_L/R) <=3D> SWR1 Port 1 (HPH_L/R) + * WCD9395 RX Port 2 (CLSH) <=3D> SWR1 Port 2 (CLSH) + * WCD9395 RX Port 3 (COMP_L/R) <=3D> SWR1 Port 3 (COMP_L/R) + * WCD9395 RX Port 4 (LO) <=3D> SWR1 Port 4 (LO) + * WCD9395 RX Port 5 (DSD_L/R) <=3D> SWR1 Port 5 (DSD_L/R) + * WCD9395 RX Port 6 (HIFI_PCM_L/R) <=3D> SWR1 Port 9 (HIFI_PCM_L/R) + */ + qcom,rx-port-mapping =3D <1 2 3 4 5 9>; + }; +}; + +&swr2 { + status =3D "okay"; + + /* WCD9395 TX */ + wcd_tx: codec@0,3 { + compatible =3D "sdw20217010e00"; + reg =3D <0 3>; + + /* + * WCD9395 TX Port 1 (ADC1,2,3,4) <=3D> SWR2 Port 2 (TX SWR_INPU= T 0,1,2,3) + * WCD9395 TX Port 2 (ADC3,4 & DMIC0,1) <=3D> SWR2 Port 2 (TX SWR_INPU= T 0,1,2,3) + * WCD9395 TX Port 3 (DMIC0,1,2,3 & MBHC) <=3D> SWR2 Port 3 (TX SWR_INPU= T 4,5,6,7) + * WCD9395 TX Port 4 (DMIC4,5,6,7) <=3D> SWR2 Port 4 (TX SWR_INPU= T 8,9,10,11) + */ + qcom,tx-port-mapping =3D <2 2 3 4>; + }; +}; + +&swr3 { + status =3D "okay"; + + pinctrl-0 =3D <&wsa2_swr_active>, <&spkr_23_sd_n_active>; + pinctrl-names =3D "default"; + + /* WSA8845, Speaker Left */ + left_spkr: speaker@0,0 { + compatible =3D "sdw20217020400"; + reg =3D <0 0>; + #sound-dai-cells =3D <0>; + reset-gpios =3D <&tlmm 77 GPIO_ACTIVE_LOW>; + sound-name-prefix =3D "SpkrLeft"; + vdd-1p8-supply =3D <&vreg_l15b_1p8>; + vdd-io-supply =3D <&vreg_l3c_1p2>; + + /* + * WSA8845 Port 1 (DAC) <=3D> SWR3 Port 1 (SPKR_L) + * WSA8845 Port 2 (COMP) <=3D> SWR3 Port 2 (SPKR_L_COMP) + * WSA8845 Port 3 (BOOST) <=3D> SWR3 Port 3 (SPKR_L_BOOST) + * WSA8845 Port 4 (PBR) <=3D> SWR3 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=3D> SWR3 Port 10 (SPKR_L_VI) + * WSA8845 Port 6 (CPS) <=3D> SWR3 Port 13 (CPS) + */ + qcom,port-mapping =3D <1 2 3 7 10 13>; + }; + + /* WSA8845, Speaker Right */ + right_spkr: speaker@0,1 { + compatible =3D "sdw20217020400"; + reg =3D <0 1>; + #sound-dai-cells =3D <0>; + reset-gpios =3D <&tlmm 77 GPIO_ACTIVE_LOW>; + sound-name-prefix =3D "SpkrRight"; + vdd-1p8-supply =3D <&vreg_l15b_1p8>; + vdd-io-supply =3D <&vreg_l3c_1p2>; + + /* + * WSA8845 Port 1 (DAC) <=3D> SWR3 Port 4 (SPKR_R) + * WSA8845 Port 2 (COMP) <=3D> SWR3 Port 5 (SPKR_R_COMP) + * WSA8845 Port 3 (BOOST) <=3D> SWR3 Port 6 (SPKR_R_BOOST) + * WSA8845 Port 4 (PBR) <=3D> SWR3 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=3D> SWR3 Port 11 (SPKR_R_VI) + * WSA8845 Port 6 (CPS) <=3D> SWR3 Port 13 (CPS) + */ + qcom,port-mapping =3D <4 5 6 7 11 13>; + }; +}; + +&tlmm { + /* Reserved I/Os for NFC */ + gpio-reserved-ranges =3D <32 4>, <36 1>, <38 6>, <74 1>; + + bt_default: bt-default-state { + bt-en-pins { + pins =3D "gpio17"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + }; + + sw-ctrl-pins { + pins =3D "gpio18"; + function =3D "gpio"; + bias-pull-down; + }; + }; + + fan_pwr_active: fan-pwr-active-state { + pins =3D "gpio124", "gpio125"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + output-high; + }; + + fan_pwr_sleep: fan-pwr-sleep-state { + pins =3D "gpio124", "gpio125"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + output-low; + }; + + fan_int_active: fan-int-active-state { + pins =3D "gpio14"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + upd720201_active: upd720201-active-state { + pins =3D "gpio121", "gpio122", "gpio123"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + output-high; + }; + + gamepad_pwr_en: gamepad-pwr-en-active-state { + pins =3D "gpio28"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + output-high; + }; + + spkr_23_sd_n_active: spkr-23-sd-n-active-state { + pins =3D "gpio77"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + output-low; + }; + + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins =3D "gpio21"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + output-high; + }; + + wcd_default: wcd-reset-n-active-state { + pins =3D "gpio107"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + output-low; + }; + + wlan_en: wlan-en-state { + pins =3D "gpio16"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-down; + }; +}; + +&uart14 { + status =3D "okay"; + + bluetooth { + compatible =3D "qcom,wcn7850-bt"; + + vddrfacmn-supply =3D <&vreg_pmu_rfa_cmn>; + vddaon-supply =3D <&vreg_pmu_aon_0p59>; + vddwlcx-supply =3D <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply =3D <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply =3D <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply =3D <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply =3D <&vreg_pmu_rfa_1p8>; + + max-speed =3D <3200000>; + }; +}; + +&uart15 { + status =3D "okay"; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 210 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l17b_2p5>; + vcc-max-microamp =3D <1300000>; + vccq-supply =3D <&vreg_l1c_1p2>; + vccq-max-microamp =3D <1200000>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l1d_0p88>; + vdda-pll-supply =3D <&vreg_l3i_1p2>; + + status =3D "okay"; +}; + +/* + * DPAUX -> WCD9395 -> USB_SBU -> USB-C + * eUSB2 DP/DM -> PM85550HS -> eUSB2 DP/DM -> WCD9395 -> USB-C + * USB SS -> NB7VPQ904MMUTWG -> USB-C + */ + +&usb_1 { + dr_mode =3D "otg"; + usb-role-switch; + + status =3D "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint =3D <&pmic_glink_hs_in>; +}; + +&usb_1_hsphy { + vdd-supply =3D <&vreg_l1i_0p88>; + vdda12-supply =3D <&vreg_l3i_1p2>; + + phys =3D <&pm8550b_eusb2_repeater>; + + status =3D "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply =3D <&vreg_l3i_1p2>; + vdda-pll-supply =3D <&vreg_l3g_0p91>; + + status =3D "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint =3D <&redriver_ss_in>; +}; + +&xo_board { + clock-frequency =3D <76800000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index 07ae74851621..fcd5a1a45803 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3917,7 +3917,7 @@ opp-32000000-4 { }; }; =20 - pcie@0 { + pcieport1: pcie@0 { device_type =3D "pci"; reg =3D <0x0 0x0 0x0 0x0 0x0>; bus-range =3D <0x01 0xff>; diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c index d8bb40ef820e..0781dce7cda2 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.c +++ b/drivers/gpu/drm/msm/dsi/dsi.c @@ -43,12 +43,12 @@ static int dsi_get_phy(struct msm_dsi *msm_dsi) of_node_put(phy_node); =20 if (!phy_pdev) { - DRM_DEV_ERROR(&pdev->dev, "%s: phy driver is not ready\n", __func__); + DRM_DEV_ERROR(&pdev->dev, "%s: 0 phy driver is not ready\n", __func__); return -EPROBE_DEFER; } if (!msm_dsi->phy) { put_device(&phy_pdev->dev); - DRM_DEV_ERROR(&pdev->dev, "%s: phy driver is not ready\n", __func__); + DRM_DEV_ERROR(&pdev->dev, "%s: 1 phy driver is not ready\n", __func__); return -EPROBE_DEFER; } =20 --=20 2.34.1