From nobody Tue Feb 10 10:20:38 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7AD24DBD68 for ; Wed, 21 Jan 2026 17:05:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769015147; cv=none; b=uKbQS2sZj7oj0HUq9PJ+6tZdELUbU6/zLXgEF3RFNvFKZkgXZ5I+z0DeWHqE/8qkj+PPdUUcLMjCr53USHSHSnZXnQJb7Haq8WQsythOp+0DA/fYwrrTetAZY0Wya8CLUaotrd1xPPcal4qAgsn4Q6fUHGUnoiTnIeAYitF7dk8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769015147; c=relaxed/simple; bh=hyTwwJ/Ya5DWTrZNo9T/nYR5MC5dujwB/8NLyLhDkhA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dOBCBpwQHZ2tmQhcl1QpkHy2Ahq9VeJ8XJWBLumcYqm0bD9wo65gRBiokSo4JkMQ8gZ54BLdUUoS9x6xPTg5ZeqVbntPyKgc3KGJw3LHYFmSkcJcWIvfvjrC/0+QH+5gYSqgJasJ5iuqLuoW3MCucQnmAARbbWrsEKtAj+R0fF0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=mwpKwRId; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="mwpKwRId" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 33EB7C21A90; Wed, 21 Jan 2026 17:05:16 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 68A936070A; Wed, 21 Jan 2026 17:05:43 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id D2B0F119B17F5; Wed, 21 Jan 2026 18:05:40 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1769015142; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=VVRqIRwbr5v98YAdUusQ7vUrAWpnmI4l7K7vSQXWOkg=; b=mwpKwRIdOIo1uBv5nU/pBm6o0qqPb5Rxe5HHwpcQXJx0/ub+1CK+V9GvRNXbiCdDxte6MT kt+3FdiAg0m0Da1j+1tmcVyet0JE6GZwW1JbnHiqVwQ+oD/9yS6sEnarM6+u++nJFWgwEI ly1B7FMLKa22EDctH3OMaQ5xo8XSJvs/9nEHK2YXIR7J9gj6iSp8A95XrOv+TZPEWshdYu 7CpVe31aHW0Y534SiIC6UTygBm2o1RcNZSj0Y5+3PPfGCP2VbGBH1JCJS+NlL0DbSr+Jvm AgC0yWmA3UesYAUYFg6gXlKxXkBCxT4NIZbKVopLpkzNRe93fBhdFhexzJamSw== From: "Miquel Raynal (Schneider Electric)" Date: Wed, 21 Jan 2026 18:05:13 +0100 Subject: [PATCH v3 17/17] ARM: dts: r9a06g032: Describe the QSPI controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-schneider-6-19-rc1-qspi-v3-17-43e70fab4444@bootlin.com> References: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> In-Reply-To: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Add a node describing the QSPI controller. There are 2 clocks feeding this controller: - one for the reference clock - one that feeds both the ahb and the apb interfaces As the binding expect either the ref clock, or all three (ref, ahb and apb) clocks, it makes sense to provide the same clock twice. Reviewed-by: Geert Uytterhoeven Tested-by: Wolfram Sang Signed-off-by: Miquel Raynal (Schneider Electric) --- arch/arm/boot/dts/renesas/r9a06g032.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/r= enesas/r9a06g032.dtsi index 8debb77803bb..d20f397dcd96 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -66,6 +66,20 @@ soc { #size-cells =3D <1>; ranges; =20 + qspi0: spi@40005000 { + compatible =3D "renesas,r9a06g032-qspi", "renesas,rzn1-qspi"; + reg =3D <0x40005000 0x1000>, <0x10000000 0x10000000>; + interrupts =3D ; + clocks =3D <&sysctrl R9A06G032_CLK_QSPI0>, <&sysctrl R9A06G032_HCLK_QSP= I0>, + <&sysctrl R9A06G032_HCLK_QSPI0>; + clock-names =3D "ref", "ahb", "apb"; + #address-cells =3D <1>; + #size-cells =3D <0>; + cdns,fifo-width =3D <4>; + cdns,fifo-depth =3D <4>; + status =3D "disabled"; + }; + rtc0: rtc@40006000 { compatible =3D "renesas,r9a06g032-rtc", "renesas,rzn1-rtc"; reg =3D <0x40006000 0x1000>; --=20 2.51.1