From nobody Tue Feb 10 10:20:29 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70A734D9912; Wed, 21 Jan 2026 17:05:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769015141; cv=none; b=NH7DHdY64fA5X2DnwSo5MELtRoXPx7mS6SpYJxheNEc42OoUirzZOjYrwodJt1JH3i50raQNL934EcOms1hkt4N9S59MRktfMJuf4PUSlZhZcyOhX7PhfJfviORUUJeWFoCuQwMZhhu2NV8xAcpKgiBnvnxs8NpOysF49+IqyuM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769015141; c=relaxed/simple; bh=s5qeqBhzqXvBR0yVd6ehmw1JmdAeCogqylKOKRTU5a0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qw/zq6MrnbrYcIHEf2opEn65RBbQff1VGK5Jeh6TCOQ0ADU/TrIsW/fAlg4cpuRC0LURWkxLcrnQVwPeCznWVfMoraxU0ToQlO2uNga3mCexQWWa5LZyW0VYhykA6/dj+zTKmcAqPEtBc+Ci4cjdtKkZVM5KHVFYg0l+vV8BTDo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=L5om0/kD; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="L5om0/kD" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 11C504E421CC; Wed, 21 Jan 2026 17:05:38 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id D61C36070A; Wed, 21 Jan 2026 17:05:37 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 5ABF7119B18DD; Wed, 21 Jan 2026 18:05:35 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1769015136; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=QegLxnXsPbyMpFnnOsyJbRiNNWksSHe1X3JonRazV2o=; b=L5om0/kDVbhd1Yu4xbOO0TP9ULP8vxO2C7fdJX48QBoU8YOdmxkBsy71mWfMJsEcn6GsqL 1JafuysnawmyHfVsYjsETPnCxcuYp5j0zZjxJSk+awzMrtWstLCxnQDbr67wMsmltAdOsF bO/rKJe97Z6vgGoP0DOZxb9aipfg+LqWdS5IMckJV+nBlr4x73oq5NP1zMkjLWyGSeqCn3 bDy3Q2M+yAXrDFI8KciJ0IFefv9+eij3WoPYW8M5kChR/34vk+DCk1PPm9Ej0W2usEm2+I W51qtCmQhcNCOThat3ltU5sQzPG2PF30M8A7XHhqIFwdyMnJ9UuHLx+RaAmrig== From: "Miquel Raynal (Schneider Electric)" Date: Wed, 21 Jan 2026 18:05:10 +0100 Subject: [PATCH v3 14/17] spi: cadence-qspi: Make sure write protection is disabled Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-schneider-6-19-rc1-qspi-v3-14-43e70fab4444@bootlin.com> References: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> In-Reply-To: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Renesas RZ/N1 QSPI controllers embed the Cadence IP with some modifications. For instance, they feature a write protection of the direct mapping at the controller level, with this feature all data writes to the AHB region are aborted. Despite the fact that the flag setting write protection is disabled by default, Bootloaders may (and actually do) set it, so mark this feature as being available with a specific flag to, if applicable, make sure it is disabled. Tested-by: Wolfram Sang Signed-off-by: Miquel Raynal (Schneider Electric) --- drivers/spi/spi-cadence-quadspi.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index e1ec20684b0a..e0e4423baed9 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -48,6 +48,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <=3D SPI_DEVICE_CS_CNT= _MAX); #define CQSPI_DISABLE_STIG_MODE BIT(9) #define CQSPI_DISABLE_RUNTIME_PM BIT(10) #define CQSPI_NO_INDIRECT_MODE BIT(11) +#define CQSPI_HAS_WR_PROTECT BIT(12) =20 /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -218,6 +219,8 @@ struct cqspi_driver_platdata { #define CQSPI_REG_IRQSTATUS 0x40 #define CQSPI_REG_IRQMASK 0x44 =20 +#define CQSPI_REG_WR_PROT_CTRL 0x58 + #define CQSPI_REG_INDIRECTRD 0x60 #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1) @@ -1641,6 +1644,10 @@ static void cqspi_controller_init(struct cqspi_st *c= qspi) cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); } =20 + /* Disable write protection at controller level */ + if (cqspi->ddata && cqspi->ddata->quirks & CQSPI_HAS_WR_PROTECT) + writel(0, cqspi->iobase + CQSPI_REG_WR_PROT_CTRL); + /* Disable direct access controller */ if (!cqspi->use_direct_mode) { reg =3D readl(cqspi->iobase + CQSPI_REG_CONFIG); --=20 2.51.1