From nobody Mon Feb 9 15:04:41 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72D41421F18; Wed, 21 Jan 2026 17:05:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769015118; cv=none; b=goyOX1/zFgkcIHGKOXx/bZjT5kXAFivnGzUtjmm89c45kNIYbBUAW01bDnKLYYqzh4hc/DrPlBMMLMtx9oPzJDMm1J8Qe0sWEKI+/lPxn4u3bDFs4zZlVUbxZ6v8UxcOiwKb1ebxgbu6L3Gzwqx9b9N1VGifBfxngCW00w2ivxg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769015118; c=relaxed/simple; bh=aTWmaBXa7MhE/ICorPqq2ogaGH1Gh12fy/ipBZoQKGE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=N29pPlHxglls/EobAOXcM4uHZcEbyGhJuid8wMNJEL5M8b6G+mo2GdfL2OLxCIb8B0BNFjVTjL3O7DAzt5ziyQ7dygGMIClDWBMfA0c7LFpltJRaaGZoJEEiE7SIxl28LoYTyiEvB/sKssrcnkcPCw0QTT6H1f1kG1uhrlATwjo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=1qkkQkfK; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="1qkkQkfK" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 8D1871A2965; Wed, 21 Jan 2026 17:05:14 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 62D916070A; Wed, 21 Jan 2026 17:05:14 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 0F64E119B1874; Wed, 21 Jan 2026 18:05:11 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1769015113; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=KYcVrYYRRRVGg2zik0u1NSU2KMI85alPMqm6GdgYfj4=; b=1qkkQkfK3IrLlptljZnTiDT4YeZ91bRDVYmOk8+55RG/kmeZDg603ruOLVRi97MRbj69DN w4rvb6YafKhu9hJWChJQqkvgNdqT2lLokAyaCN2EUNfirJ+m4ElEVFGdXrSRu8VXcHE9DC qzYT1JdY+7cUg9XLrpk6WfC1Vtk2Z8uQqELxkv/2ApJax1ECBV1E4T0IoQUkyyKM8dmXR3 BMr7ahmMWo0iBxwcnQLobJ1pzZYgWrwVJXHj9jFy0kkuehOXzNhxlmIduloFJaPZcllXWW sfUbAbgK7sMZ1T+trg/R41S9Y6LKYdb4uGD6/x3sd58qXO+gP7Uj0ecbyf/XNg== From: "Miquel Raynal (Schneider Electric)" Date: Wed, 21 Jan 2026 18:04:57 +0100 Subject: [PATCH v3 01/17] spi: dt-bindings: cdns,qspi-nor: Remove duplicated constraints Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-schneider-6-19-rc1-qspi-v3-1-43e70fab4444@bootlin.com> References: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> In-Reply-To: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The if/then/else block sets the restrictions in all cases for resets/reset-names, very much like it does for other properties as well such as cdns,fifo-depth. Drop the constraints from the place where these constraints are simply ignored. Signed-off-by: Miquel Raynal (Schneider Electric) --- Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Doc= umentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index 53a52fb8b819..b85dba351822 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -136,15 +136,8 @@ properties: power-domains: maxItems: 1 =20 - resets: - minItems: 2 - maxItems: 3 - - reset-names: - minItems: 2 - maxItems: 3 - items: - enum: [ qspi, qspi-ocp, rstc_ref ] + resets: true + reset-names: true =20 patternProperties: "^flash@[0-9a-f]+$": --=20 2.51.1 From nobody Mon Feb 9 15:04:41 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F24748BD4B; Wed, 21 Jan 2026 17:05:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769015120; cv=none; b=nV7CURW6YREe09sKraoR4M/T3Gvsqb/nhJmDltCKRDBqwhvy2paHASOKTwf0AcYG837S3NnkWZBsdCdc2giHu7ZsCmCAh+NYu0R33dQZph0K1G6k5RtoeXCu22mC/kLwtvojYCXeushMeYsUyhOftnDqVju7Fu5KVmMdRCkWwTY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769015120; c=relaxed/simple; bh=bWZrmSiM6YWTx+i5vVQsu6mdes0U+efV52esmGFE7UA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DOiT7ot3PxmmKs3SkWDCULGMoU0zTJq6HPDmJ7EYeD1jpn9KLbOKoq4ZXGwTgw1YzhHAG1J6qJKPc2MGzxfhzyXOGq3JpMoxMGvktp7vz4aaTw5IPSsX43TFGZ6FoblopHVBb8nBvdBCTKPk8zKqWRhAr5Kn40vfmpBtbQClJL0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=mjSpX5z/; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="mjSpX5z/" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 054D0C21A91; Wed, 21 Jan 2026 17:04:49 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 39FF16070A; Wed, 21 Jan 2026 17:05:16 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id D1389119B1881; Wed, 21 Jan 2026 18:05:13 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1769015115; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=EGJbdGn0SD0aoabG2saaXwDhMHD4aEi0DEPAXPkHNUE=; b=mjSpX5z/wEIGdhf70w6GO7ghYg1Rd7bJ+R/Ngq/OBCQxSSuuNibsdryr2sWg4463F6ZQy7 rdAkjKKvS2LZ1U7d0TUhfZcyBME8w5yQYCLY8AU4kB4E7PU5mtXTkVwAC62J1aB4BG4/6V MZ8FdOH+uNTpOF3NoYNILsKSBeKTc4ubc1UMuvbkQmprA5NwXNe+Lxx6QjrVZ9dOnSn5ym oRrWP8CY3pwEbyQSqYmSlj4j4DgW2Pbg2Ems/RDAziI1raCFo997VQLcDO1v0FPWkzWeNl xoEe4k2AvD9+vml5GEz4gJ4TUpFaL+hiNzCtpvDXvfmi3y8TEqoCe5syfitv7A== From: "Miquel Raynal (Schneider Electric)" Date: Wed, 21 Jan 2026 18:04:58 +0100 Subject: [PATCH v3 02/17] spi: dt-bindings: cdns,qspi-nor: Drop label in example Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-schneider-6-19-rc1-qspi-v3-2-43e70fab4444@bootlin.com> References: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> In-Reply-To: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The label is useless here. Plus, if there are several examples with the same label, we'll get very useless yet annoying warnings. Signed-off-by: Miquel Raynal (Schneider Electric) Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Doc= umentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index b85dba351822..123caef8f61e 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -165,7 +165,7 @@ unevaluatedProperties: false =20 examples: - | - qspi: spi@ff705000 { + spi@ff705000 { compatible =3D "intel,socfpga-qspi", "cdns,qspi-nor"; #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.51.1 From nobody Mon Feb 9 15:04:41 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1460D48C8A6; Wed, 21 Jan 2026 17:05:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769015122; cv=none; b=BAZp04avYJOZDTtzlo401uSak3eKjBbREn7iyLogJaOoYvycH/91WcDVkUhuNghk7zeLj3kdqxFkgWXh4VrKOb8QfvxxBgF77xIUtJ6AMVZxL+6HFE7M4Lb1fPiyaO2GItn2kan6M3L0m5r2KyfK6FprwvCF3HhC5ifzdPDJ3U0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769015122; c=relaxed/simple; bh=JWhcKkvU8yD+gzDYy910G6kF2d2VDDoSVPZaBn7jQ+k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mX6KvvciDXOVroNfJ0Yu9zZYKH0xurIav5xwithAOQ/DxSu8MQ712kZKchcJa98mjr21is0QNZ6xHPqOi7QD5tGXXJsKga+ZiisLhHVeNPlS6GBDYZVBOO/J4BrIUAgZ3mtJpTnhtnyM8P28mg9LcPNaz+sBkU3Mqz2c1IDjhiY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=DjKrTtP5; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="DjKrTtP5" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id A7E57C21A8F; Wed, 21 Jan 2026 17:04:50 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id DCE0C6070A; Wed, 21 Jan 2026 17:05:17 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 95EDF119B1746; Wed, 21 Jan 2026 18:05:15 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1769015116; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=x2AlFWyc4Ip33zPaUlGPLmdBouK0MOvwiZBD25BSZIg=; b=DjKrTtP5crl1p8AAZ0noKrnf+YJi0CG+AoB1aY7R21kMddxR3QD9V5bIiK8Oz7pRoUNsoY 3crNIkY/7UTrrEbsaaQ2FX7llN0dDAr88q9qBCPQzgxzcTEDylurK8mFd/JB68EC2NISQ7 bDOo+tbpM1FfAGFSLQw8gv/QSOQjTuByaxh5ljr8I6oW6HDqQ6pnEHSh0Qu9WoN7OSFCVR KT4P3IJdPd3RqzH6iN6vIBP9RskKrlCZik8xG/Hwv94JsP7GJoYm2NhT+YZ6iVWjfJfmC2 qY7Mefi+yJj8BXNwl8HLNK9cl3WMmmzR7Tna//O1zYSsoHgjIe+QGvXJ+amOIQ== From: "Miquel Raynal (Schneider Electric)" Date: Wed, 21 Jan 2026 18:04:59 +0100 Subject: [PATCH v3 03/17] spi: dt-bindings: cdns,qspi-nor: Add examples for testing the specific cases Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-schneider-6-19-rc1-qspi-v3-3-43e70fab4444@bootlin.com> References: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> In-Reply-To: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 It is very painful to modify this file because the core IP described is so common, it has been implemented in many SoCs from different architectures. Both `dtbs_check` and `dt_binding_check` are rather long commands, even when restricted to a single schema files, and letting this file evolve without risking to break other DTSs is painful, because there are arm, arm64 and riscv platforms impacted and no way to check all of them at the same time. Instead, we can identify the few specific cases which may need extra testing, and fill the examples section to cover them all. Add examples to cover the Starfive (resets) and Pensando (fifo-depth) cases. Signed-off-by: Miquel Raynal (Schneider Electric) --- .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 35 ++++++++++++++++++= ++++ 1 file changed, 35 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Doc= umentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index 123caef8f61e..62b97ab607f3 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -189,3 +189,38 @@ examples: cdns,tslch-ns =3D <60>; }; }; + + - | + #include + #include + #include + spi@13010000 { + compatible =3D "starfive,jh7110-qspi", "cdns,qspi-nor"; + reg =3D <0x13010000 0x10000>, <0x21000000 0x400000>; + interrupts =3D <25>; + clocks =3D <&syscrg JH7110_SYSCLK_QSPI_REF>, <&syscrg JH7110_SYSCL= K_QSPI_AHB>, + <&syscrg JH7110_SYSCLK_QSPI_APB>; + clock-names =3D "ref", "ahb", "apb"; + resets =3D <&syscrg JH7110_SYSRST_QSPI_APB>, <&syscrg JH7110_SYSRS= T_QSPI_AHB>, + <&syscrg JH7110_SYSRST_QSPI_REF>; + reset-names =3D "qspi", "qspi-ocp", "rstc_ref"; + #address-cells =3D <1>; + #size-cells =3D <0>; + cdns,fifo-depth =3D <256>; + cdns,fifo-width =3D <4>; + cdns,trigger-address =3D <0x0>; + }; + + - | + #include + spi@2400 { + compatible =3D "amd,pensando-elba-qspi", "cdns,qspi-nor"; + reg =3D <0x2400 0x400>, <0x7fff0000 0x1000>; + interrupts =3D ; + clocks =3D <&flash_clk>; + #address-cells =3D <1>; + #size-cells =3D <0>; + cdns,fifo-depth =3D <1024>; + cdns,fifo-width =3D <4>; + cdns,trigger-address =3D <0x7fff0000>; + }; --=20 2.51.1 From nobody Mon Feb 9 15:04:41 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3AA21492536 for ; Wed, 21 Jan 2026 17:05:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769015123; cv=none; b=Sen5c4xYsbig7kZUYhdBPMG1N6pz6VHROkH7eNPhl6Uy12Hmp2Kv6F3eATys2NVpYZpIEDbfLSF4fax4f+Bpqn5FzO2LfQ1ShwTYc5W5KYZseTyMdQLNTIi6BP1KUEQ6qZ3lSczScG+UnGI/FqmR+uDwvVuCFVyt4AIKm8XawBk= ARC-Message-Signature: i=1; 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Wed, 21 Jan 2026 17:05:19 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 9B8F06070A; Wed, 21 Jan 2026 17:05:19 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 51A35119B1874; Wed, 21 Jan 2026 18:05:17 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1769015118; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=5Kj6ETSNf5AkrmQzs+0Qf4EJ+9HnqSnNyo5Un85LJLs=; b=yuERPHQp/NwQV2R5l2fwJUWIelMhbBo2r+psMK2XjPFCtl7km9JdQkqMlMx79hL+sw+Q6q UbvhHPqP5do8Gw90im/dpoebjPllnMl0ApR+1w5/qX14IxadErbWqTw0619VVOy5N9j2nD SpKUqUnwK7cgwZS30bTFOrHBLyH/HM9UFtRPoJo46tZfB81cOawTJ59+7qwKgrPAM8nmDP i0PqbIYqJ9nZnKD10YIB+svJ5UTc5fN+ecSr6/NxqBkN3nYvmx7H67dTQZKbZDbDxhiEva BR7lyUo9OqrGXmYnSzc64ho8l4VaelTeHyvlL2HAymxDAKFyKru5JOAAfYYoqQ== From: "Miquel Raynal (Schneider Electric)" Date: Wed, 21 Jan 2026 18:05:00 +0100 Subject: [PATCH v3 04/17] spi: dt-bindings: cdns,qspi-nor: Add Renesas RZ/N1D400 to the list Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-schneider-6-19-rc1-qspi-v3-4-43e70fab4444@bootlin.com> References: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> In-Reply-To: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Add support for the Renesas RZ/N1D400 QSPI controller. This SoC is identified in the bindings with its other name: r9a06g032. It is part of the RZ/N1 family, which contains a "D" and a "S" variant. IPs in this SoC are typically described using 2 compatibles: the SoC specific compatible and the family compatible. The original Cadence IP compatible is dropped because it is unusable on its own. Indirect accesses are not supported by this flavour of the Cadence IP, which means several properties have no meaning in the scope of the Renesas compatible. Let's make sure they are no longer expected nor mandatory. Tested-by: Wolfram Sang Signed-off-by: Miquel Raynal (Schneider Electric) Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 33 ++++++++++++++++++= ++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Doc= umentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index 62b97ab607f3..fdb25d16a8fb 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -61,6 +61,20 @@ allOf: cdns,fifo-depth: enum: [ 128, 256 ] default: 128 + - if: + properties: + compatible: + contains: + const: renesas,rzn1-qspi + then: + properties: + cdns,trigger-address: false + cdns,fifo-depth: false + cdns,fifo-width: false + else: + required: + - cdns,trigger-address + - cdns,fifo-depth =20 properties: compatible: @@ -80,6 +94,9 @@ properties: # controllers are meant to be used with flashes of all kinds, # ie. also NAND flashes, not only NOR flashes. - const: cdns,qspi-nor + - items: + - const: renesas,r9a06g032-qspi + - const: renesas,rzn1-qspi - const: cdns,qspi-nor deprecated: true =20 @@ -156,8 +173,6 @@ required: - reg - interrupts - clocks - - cdns,fifo-width - - cdns,trigger-address - '#address-cells' - '#size-cells' =20 @@ -224,3 +239,17 @@ examples: cdns,fifo-width =3D <4>; cdns,trigger-address =3D <0x7fff0000>; }; + + - | + #include + #include + spi@40005000 { + compatible =3D "renesas,r9a06g032-qspi", "renesas,rzn1-qspi"; + reg =3D <0x40005000 0x1000>, <0x10000000 0x10000000>; + interrupts =3D ; + clocks =3D <&sysctrl R9A06G032_CLK_QSPI0>, <&sysctrl R9A06G032_HCL= K_QSPI0>, + <&sysctrl R9A06G032_HCLK_QSPI0>; + clock-names =3D "ref", "ahb", "apb"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; --=20 2.51.1 From nobody Mon Feb 9 15:04:41 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74366495532; Wed, 21 Jan 2026 17:05:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769015124; cv=none; b=Ao2TGOJNlWuFg0luSUChFj996lzkbZACV4DZnCwkesJtnmL5JKeLvp8bHHbhsT0eYn7UQTpVUyB2JtpPcYWknK9Uh8eUJRU3jxXxaqqh1jVUtJTHX9eDaydFbH7mbRio4imnXcHOodYvCUpteLAhqnRnuIk4sHw6EPsDWgJAKKA= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-schneider-6-19-rc1-qspi-v3-5-43e70fab4444@bootlin.com> References: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> In-Reply-To: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Fix alignment on the #defines. Reviewed-by: Pratyush Yadav Tested-by: Wolfram Sang Signed-off-by: Miquel Raynal (Schneider Electric) --- drivers/spi/spi-cadence-quadspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index b1cf182d6566..cc28da7fc686 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -40,7 +40,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <=3D SPI_DEVICE_CS_CNT= _MAX); #define CQSPI_DISABLE_DAC_MODE BIT(1) #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) -#define CQSPI_SLOW_SRAM BIT(4) +#define CQSPI_SLOW_SRAM BIT(4) #define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) #define CQSPI_RD_NO_IRQ BIT(6) #define CQSPI_DMA_SET_MASK BIT(7) --=20 2.51.1 From nobody Mon Feb 9 15:04:41 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2DC64D2ED9 for ; Wed, 21 Jan 2026 17:05:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769015126; cv=none; b=Pf+W6zn/WKDidPPYmPrO1tb6U/2AWxxX1ivV1yfhEk9ZWzZ5zaXw4Dgnamicy51QKV2kfa/J+khrvyDFWffmcnRIOzqhmGA/oRYvu8cJrzXjfHfPvvQWnKgJ5bcOkXzjrwqd7oVLSu95MUUnSUuV9NRCUEIcD7o+Mw0HQ0zoq64= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769015126; c=relaxed/simple; bh=JD9J15FD3+7Fo755XEIaI+M7RJcrkXyMm5ZCiSP5OnY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SxQEWoJMa/l4NfrD41G+oil7gCwqOw4HCGGAMRuHZTPm142f8E8c1scFieKJU/dlaq14950X+gNF21MuqkA2wTagrgP4GnDWiR/oggJjLjp6mPHA1rps+K8bB87yuHY3Tdu1Ymt0VHjX7aLT/sxxwhrXqlesCVTYGp2/EeYVHxc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=OiL+xRge; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="OiL+xRge" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 3731F4E421CC; Wed, 21 Jan 2026 17:05:23 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 0AF2F6070A; Wed, 21 Jan 2026 17:05:23 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 94B3B119B17EB; Wed, 21 Jan 2026 18:05:20 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1769015122; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=+kIY2+d5nqykmYBPmHAWFbCHhJxDmjtvUjwEBEl1LRg=; b=OiL+xRge1aqQnB8S8GrCz9ysflX0nUlOu+Zev8BYic+nQ1YVdMZ4Jcm/12CMUr35xlq7uo x58fOF+P5NvTMog948BfS2h4BPy/l8T6eG5Idi10Pe1kPCJqgDY3SMtu57Ow64hHjdo+ul d3T7POxNpjdQByCGiVg9SGlQRbKS++0qKqTvg1bjZd8SD+cnxCaVXQA1iKA+NIDYLTSNlD xUQijJS7K6PKgVCrhDy8vAllkNwHYBRwUQghoJ0fr79fM7YNvKHkQyujEXFDclVPypYPb8 fnYCVcBrvf/5IsliwiBkubLm2nd9SFm79coXwkT0qIrmEIFFBltGBlLA/pmUIQ== From: "Miquel Raynal (Schneider Electric)" Date: Wed, 21 Jan 2026 18:05:02 +0100 Subject: [PATCH v3 06/17] spi: cadence-qspi: Fix style and improve readability Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-schneider-6-19-rc1-qspi-v3-6-43e70fab4444@bootlin.com> References: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> In-Reply-To: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 It took me several seconds to correctly understand this block. I understand the goal: showing that we are in the if, or in one of the two other cases. Improve the organization of the code to both improve readability and fix the style. Suggested-by: Pratyush Yadav Tested-by: Wolfram Sang Signed-off-by: Miquel Raynal (Schneider Electric) --- drivers/spi/spi-cadence-quadspi.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index cc28da7fc686..c0a507953c58 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -374,17 +374,12 @@ static irqreturn_t cqspi_irq_handler(int this_irq, vo= id *dev) /* Clear interrupt */ writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS); =20 - if (cqspi->use_dma_read && ddata && ddata->get_dma_status) { - if (ddata->get_dma_status(cqspi)) { - complete(&cqspi->transfer_complete); - return IRQ_HANDLED; - } - } - - else if (!cqspi->slow_sram) - irq_status &=3D CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR; - else + if (cqspi->use_dma_read && ddata && ddata->get_dma_status) + irq_status =3D ddata->get_dma_status(cqspi); + else if (cqspi->slow_sram) irq_status &=3D CQSPI_IRQ_MASK_RD_SLOW_SRAM | CQSPI_IRQ_MASK_WR; + else + irq_status &=3D CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR; =20 if (irq_status) complete(&cqspi->transfer_complete); --=20 2.51.1 From nobody Mon Feb 9 15:04:41 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 836974D2EF5; Wed, 21 Jan 2026 17:05:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769015128; cv=none; b=OdXg4viPghrPKndpQi+Ep3JA0Xv0tu8tA21Ql5zOhiPfOsJIEmADQvL2+V9jq1ZA6flUs20iy5fL8n/d8nB/8Ox80J1M+zLiFhwAECTrxmplmTvgaUBNh8H2ISUJkgqF624J5fuSfwxpSzAdjzSgOo36dD2o8iRMiR2oXhl1gpM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769015128; c=relaxed/simple; bh=UBxp+mVMENkbjzOOwcVuVl5Ky0LH3WVdPATL+cPvJLw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Wed, 21 Jan 2026 17:05:25 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 690C4119B189F; Wed, 21 Jan 2026 18:05:22 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1769015124; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=fO0SkS9+T7rGUtUKsShIOFxIB6cpqmbBl3frX7gVrxI=; b=Q4IzLQLoRHUKeOoPctDHrTAobYppyWxnB7QetEmeIvYtio6xj+zlrU/VjDm+bsN/JmvITz z/+62aqN6iFcpEEKlH4Kh+2Clzm6fAT+svz6B4gMwEFUPDtOTZPwMCc2Dxjy8q3xvtrYtv L/Zaz7VIVFF0kFQJd19bk63YzQJPX9Do+vklg/2fT4ZvtQsmfr6Zkdr9HKI6Pe6PNPPRW6 0oWWnYZnOVE2qY4pxdmXM6SOLwe51MMk/gzg6KPC1URxfbflXNrRRhkFz7DIxShjRn4rqc UXvB75qN7CdhBEr5aKgcWhQ09oUdpSFfSzUmJ3+IR53u/N/iczkWJkp/awqerQ== From: "Miquel Raynal (Schneider Electric)" Date: Wed, 21 Jan 2026 18:05:03 +0100 Subject: [PATCH v3 07/17] spi: cadence-qspi: Fix ORing style and alignments Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-schneider-6-19-rc1-qspi-v3-7-43e70fab4444@bootlin.com> References: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> In-Reply-To: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 These definitions do not follow the standard patterns. Alignments are incoherent and the logical OR symbols '|' are misplaced. Reorganize these definitions. There is no functional change. Acked-by: Pratyush Yadav Tested-by: Wolfram Sang Signed-off-by: Miquel Raynal (Schneider Electric) --- drivers/spi/spi-cadence-quadspi.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index c0a507953c58..8eb80b4b76eb 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -2130,26 +2130,23 @@ static const struct cqspi_driver_platdata intel_lgm= _qspi =3D { }; =20 static const struct cqspi_driver_platdata socfpga_qspi =3D { - .quirks =3D CQSPI_DISABLE_DAC_MODE - | CQSPI_NO_SUPPORT_WR_COMPLETION - | CQSPI_SLOW_SRAM - | CQSPI_DISABLE_STIG_MODE - | CQSPI_DISABLE_RUNTIME_PM, + .quirks =3D CQSPI_DISABLE_DAC_MODE | CQSPI_NO_SUPPORT_WR_COMPLETION | + CQSPI_SLOW_SRAM | CQSPI_DISABLE_STIG_MODE | + CQSPI_DISABLE_RUNTIME_PM, }; =20 static const struct cqspi_driver_platdata versal_ospi =3D { .hwcaps_mask =3D CQSPI_SUPPORTS_OCTAL, - .quirks =3D CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA - | CQSPI_DMA_SET_MASK, + .quirks =3D CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA | + CQSPI_DMA_SET_MASK, .indirect_read_dma =3D cqspi_versal_indirect_read_dma, .get_dma_status =3D cqspi_get_versal_dma_status, }; =20 static const struct cqspi_driver_platdata versal2_ospi =3D { .hwcaps_mask =3D CQSPI_SUPPORTS_OCTAL, - .quirks =3D CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA - | CQSPI_DMA_SET_MASK - | CQSPI_SUPPORT_DEVICE_RESET, + .quirks =3D CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA | + CQSPI_DMA_SET_MASK | CQSPI_SUPPORT_DEVICE_RESET, .indirect_read_dma =3D cqspi_versal_indirect_read_dma, .get_dma_status =3D cqspi_get_versal_dma_status, }; @@ -2166,7 +2163,7 @@ static const struct cqspi_driver_platdata pensando_cd= ns_qspi =3D { static const struct cqspi_driver_platdata mobileye_eyeq5_ospi =3D { .hwcaps_mask =3D CQSPI_SUPPORTS_OCTAL, .quirks =3D CQSPI_DISABLE_DAC_MODE | CQSPI_NO_SUPPORT_WR_COMPLETION | - CQSPI_RD_NO_IRQ, + CQSPI_RD_NO_IRQ, }; =20 static const struct of_device_id cqspi_dt_ids[] =3D { --=20 2.51.1 From nobody Mon Feb 9 15:04:41 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 79F154D8D84; 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arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="g9yrjLCZ" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id E40F2C21A8F; Wed, 21 Jan 2026 17:04:59 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 2557D6070A; Wed, 21 Jan 2026 17:05:27 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 7A0FB119B17F5; Wed, 21 Jan 2026 18:05:24 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1769015126; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=viq42YFuPmM9zMZsx8Z+unGAElfNEyain450dehUnTs=; b=g9yrjLCZaMcpYTgmSyN+a4pE8PPKLlqxvxpIcvpUL5iACBLZvATo3Er5ZbKeQOPej4Ho7W Yo2+eYU8z81QbYhcuGnjd7Oj4Hd4eKqreBlHBk7X/lSeCEgVTcN1f71Z++rIHYX3r2zKda X0rFc9gNeAfVpIN3nNu8EbnyiCopTmKo/kWXwRaUjSimrHKlQsVplNniglSZjXrSKHdrlB 4IEm/gLxr87hGzdz4CGrdfja3QDADslRWHriUslO2/e3KgBgqfJhY9NfdD7gLlURBEwTjV pFMXUsY+IhP9swCRVzymTlL0OU5WuZdBDHimFzDszVK+LyN04BOu/gtdYX1RcA== From: "Miquel Raynal (Schneider Electric)" Date: Wed, 21 Jan 2026 18:05:04 +0100 Subject: [PATCH v3 08/17] spi: cadence-qspi: Remove an useless operation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-schneider-6-19-rc1-qspi-v3-8-43e70fab4444@bootlin.com> References: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> In-Reply-To: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Right above writing the register value back based on 'div' value, there is the following check: if (div > CQSPI_REG_CONFIG_BAUD_MASK) div =3D CQSPI_REG_CONFIG_BAUD_MASK; which means div does not need to be AND'ed against the bitfield mask. Remove this redundant operation. Reviewed-by: Pratyush Yadav Tested-by: Wolfram Sang Signed-off-by: Miquel Raynal (Schneider Electric) --- drivers/spi/spi-cadence-quadspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 8eb80b4b76eb..06f6c5979229 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1258,7 +1258,7 @@ static void cqspi_config_baudrate_div(struct cqspi_st= *cqspi) =20 reg =3D readl(reg_base + CQSPI_REG_CONFIG); reg &=3D ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); - reg |=3D (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB; + reg |=3D div << CQSPI_REG_CONFIG_BAUD_LSB; writel(reg, reg_base + CQSPI_REG_CONFIG); } =20 --=20 2.51.1 From nobody Mon Feb 9 15:04:41 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A239D4D90A9; Wed, 21 Jan 2026 17:05:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769015132; cv=none; b=axngP8w6RZwFNm/86ISWM94qPtD81kL2wSqqRu+EDwRPOExk0z9cRHmVaV7j+VYujMOuqx2AraejuR93uykHLGZc5ipioiv+dxtl+j12S2TYiq059lHf76hZLegrHxf1SASASd9ETtKSdgRoC1e4XQtU6cL2WrK+GMQU4GXriXM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769015132; c=relaxed/simple; bh=ZQUmRyH3AswY8FGRKszIfF3sz0k1NkGxrNlVU2gJVCk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=V2sAGSx+EMtF91C8XOCoM51V61MJYGkbr5CUFlH2thMG22B3H3+K5rPXYzKkg+vDuqB5IPF3+gt2jhng1oeGsgkHGLNWzy012qhlQeJs2R7crseBQPaYR/bDopXiSQGUrNIg4jO8WufQ0UdVGAiEzIMskHKyWnipYqiJ/NNDvIk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=SJPNe9a/; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="SJPNe9a/" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id EA457C21A90; Wed, 21 Jan 2026 17:05:01 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 2A4286070A; Wed, 21 Jan 2026 17:05:29 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 7659F119B189E; Wed, 21 Jan 2026 18:05:26 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1769015128; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=EMbLn4ztip/MZhDqXh4OQPXIi4Ml+zoGnNkz7bb0Ccs=; b=SJPNe9a/hQnDHzK5IBUuKWjA2y2IE12UaMobjIzT+AUV7FBc9DozolpSjRc3i93H/Vn3/O 5KvJIzdln+vvycfyfXOtz41aOIvCorcTJTylgJ3sTgjdOOjM2escffMF/qSP2sar1fVgBn OhTezcElJ6UDLyHo+0lPR6ySsHpKcE6SBimT1ILQePVpAQGxq76mQa6ZL+lVQ7Fdf0Vddl Pbm4FVmumv8ANvQzE9Vo2bFQfdwgZPKWNTtXobNNRYnYRgPWZkLU2NX5Ma5yUbF5QT7tcT CA1RcL6PD8vHifzLPPC34//osf5sGkuoIzM9pyL+kyV1Vgbc6fSfmIC91ivmUg== From: "Miquel Raynal (Schneider Electric)" Date: Wed, 21 Jan 2026 18:05:05 +0100 Subject: [PATCH v3 09/17] spi: cadence-qspi: Make sure we filter out unsupported ops Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-schneider-6-19-rc1-qspi-v3-9-43e70fab4444@bootlin.com> References: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> In-Reply-To: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The Cadence driver does not support anything else than repeating the command opcode twice while in octal DTR mode. Make this clear by checking for this in the ->supports_op() hook. Reviewed-by: Pratyush Yadav Tested-by: Wolfram Sang Signed-off-by: Miquel Raynal (Schneider Electric) --- drivers/spi/spi-cadence-quadspi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 06f6c5979229..fc9f6e8dd549 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1531,6 +1531,10 @@ static bool cqspi_supports_mem_op(struct spi_mem *me= m, return false; if (op->data.nbytes && op->data.buswidth !=3D 8) return false; + + /* A single opcode is supported, it will be repeated */ + if ((op->cmd.opcode >> 8) !=3D (op->cmd.opcode & 0xFF)) + return false; } else if (!all_false) { /* Mixed DTR modes are not supported. */ return false; --=20 2.51.1 From nobody Mon Feb 9 15:04:41 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59D6E4D2EF5; Wed, 21 Jan 2026 17:05:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769015134; cv=none; b=hc5OiRLtuI+lH/Jz3iie0rD3yWSajtAlOSLE5pDigv5/vcYtEhalqV1Qa2ML19RsuBZF89fncfhSB29+fcBFutAnv7YuzsIbpbSAKezzvlKeAJLxOtwH4u+7ip5Zhy7kJj2XXrUrmxmsDWqHNAh/JtpKc2QxvkuyzXn7uDoA50k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769015134; c=relaxed/simple; bh=wqzgTKFg6ppbuBFV3yXjEvMJbs7TMKIWizW6DK2qIQw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fkvyZz9mIHXNrwib1NIm6Gi7XZezvffLCiLxn1KZ/6btkWUaYBC8fbR7WQSefnF9IE8ulYAaVijjHZhMH+BMsG9bK7IAzP+gusZdjWeC3yD41IkdJPuX6iopM8vw9bemBeV6CYme5hxzQb72PrwYHuunuZgx3OJTx63FkWWJWow= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=FxLSSiiw; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="FxLSSiiw" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 77D2EC21A8F; Wed, 21 Jan 2026 17:05:03 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id AD0966070A; Wed, 21 Jan 2026 17:05:30 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 8AB74119B18A9; Wed, 21 Jan 2026 18:05:28 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1769015129; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=y4t0ZhlqcETe6yz8RMe/Zn2ajMMv2vHDxX8bYifqwF8=; b=FxLSSiiw6RWTVyMA2PNLzSywT1RZ0gFCHZV3OuUyikzYyfrPVAoxtEN828bJvKRvBsiOfA U7tMydIAhfz++FPXhY/PobGinpmrtiVaVEeE1zQ6F4g8WxlODp57CTiMVcaZeWlA5Y09PV Cmza1tahJCpBsKP0s39SWqkKZQA25VJ7G/vU0LpVtswM9nNki2spiWw6frBJjgCfzZRDoZ aPMMEER3HPK5vGUzmu1e6W0EEdkUGX0W9Er20a+accoyZMoydXS3kJqnZCbfeLk/HDDHGl mcAjP0Zkx40l2kutj1JiPNxuLXLVRNSmCXw9kIXvwF1BhArxflIJV+u2hmRvrw== From: "Miquel Raynal (Schneider Electric)" Date: Wed, 21 Jan 2026 18:05:06 +0100 Subject: [PATCH v3 10/17] spi: cadence-qspi: Fix probe error path and remove Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-schneider-6-19-rc1-qspi-v3-10-43e70fab4444@bootlin.com> References: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> In-Reply-To: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The probe has been modified by many different users, it is hard to track history, but for sure its current state is partially broken. One easy rule to follow is to drop/free/release the resources in the opposite order they have been queried. Fix the labels, the order for freeing the resources, and add the missing DMA channel step. Replicate these changes in the remove path as well. Tested-by: Wolfram Sang Signed-off-by: Miquel Raynal (Schneider Electric) --- drivers/spi/spi-cadence-quadspi.c | 44 ++++++++++++++++++++++-------------= ---- 1 file changed, 25 insertions(+), 19 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index fc9f6e8dd549..4bfe65af458e 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1890,7 +1890,7 @@ static int cqspi_probe(struct platform_device *pdev) ret =3D clk_prepare_enable(cqspi->clk); if (ret) { dev_err(dev, "Cannot enable QSPI clock.\n"); - goto probe_clk_failed; + goto disable_rpm; } =20 /* Obtain QSPI reset control */ @@ -1898,14 +1898,14 @@ static int cqspi_probe(struct platform_device *pdev) if (IS_ERR(rstc)) { ret =3D PTR_ERR(rstc); dev_err(dev, "Cannot get QSPI reset.\n"); - goto probe_reset_failed; + goto disable_clk; } =20 rstc_ocp =3D devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); if (IS_ERR(rstc_ocp)) { ret =3D PTR_ERR(rstc_ocp); dev_err(dev, "Cannot get QSPI OCP reset.\n"); - goto probe_reset_failed; + goto disable_clk; } =20 if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) { @@ -1913,7 +1913,7 @@ static int cqspi_probe(struct platform_device *pdev) if (IS_ERR(rstc_ref)) { ret =3D PTR_ERR(rstc_ref); dev_err(dev, "Cannot get QSPI REF reset.\n"); - goto probe_reset_failed; + goto disable_clk; } reset_control_assert(rstc_ref); reset_control_deassert(rstc_ref); @@ -1955,7 +1955,7 @@ static int cqspi_probe(struct platform_device *pdev) if (ddata->jh7110_clk_init) { ret =3D cqspi_jh7110_clk_init(pdev, cqspi); if (ret) - goto probe_reset_failed; + goto disable_clk; } if (ddata->quirks & CQSPI_DISABLE_STIG_MODE) cqspi->disable_stig_mode =3D true; @@ -1963,7 +1963,7 @@ static int cqspi_probe(struct platform_device *pdev) if (ddata->quirks & CQSPI_DMA_SET_MASK) { ret =3D dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); if (ret) - goto probe_reset_failed; + goto disable_clks; } } =20 @@ -1974,7 +1974,7 @@ static int cqspi_probe(struct platform_device *pdev) pdev->name, cqspi); if (ret) { dev_err(dev, "Cannot request IRQ.\n"); - goto probe_reset_failed; + goto disable_clks; } =20 cqspi_wait_idle(cqspi); @@ -2001,31 +2001,36 @@ static int cqspi_probe(struct platform_device *pdev) ret =3D cqspi_request_mmap_dma(cqspi); if (ret =3D=3D -EPROBE_DEFER) { dev_err_probe(&pdev->dev, ret, "Failed to request mmap DMA\n"); - goto probe_setup_failed; + goto disable_controller; } } =20 ret =3D spi_register_controller(host); if (ret) { dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret); - goto probe_setup_failed; + goto release_dma_chan; } =20 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) pm_runtime_put_autosuspend(dev); =20 return 0; -probe_setup_failed: - if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) - pm_runtime_disable(dev); + +release_dma_chan: + if (cqspi->rx_chan) + dma_release_channel(cqspi->rx_chan); +disable_controller: cqspi_controller_enable(cqspi, 0); -probe_reset_failed: +disable_clks: if (cqspi->is_jh7110) cqspi_jh7110_disable_clk(pdev, cqspi); - +disable_clk: if (pm_runtime_get_sync(&pdev->dev) >=3D 0) clk_disable_unprepare(cqspi->clk); -probe_clk_failed: +disable_rpm: + if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) + pm_runtime_disable(dev); + return ret; } =20 @@ -2043,18 +2048,19 @@ static void cqspi_remove(struct platform_device *pd= ev) cqspi_wait_idle(cqspi); =20 spi_unregister_controller(cqspi->host); - cqspi_controller_enable(cqspi, 0); =20 if (cqspi->rx_chan) dma_release_channel(cqspi->rx_chan); =20 - if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) - if (pm_runtime_get_sync(&pdev->dev) >=3D 0) - clk_disable(cqspi->clk); + cqspi_controller_enable(cqspi, 0); =20 if (cqspi->is_jh7110) cqspi_jh7110_disable_clk(pdev, cqspi); =20 + if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) + if (pm_runtime_get_sync(&pdev->dev) >=3D 0) + clk_disable(cqspi->clk); + if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) { pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); --=20 2.51.1 From nobody Mon Feb 9 15:04:41 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 213124D90BA; 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arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Oa/3vuDV" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id BD6CB1A2965; Wed, 21 Jan 2026 17:05:32 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 94DBA6070A; Wed, 21 Jan 2026 17:05:32 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 24726119B18AF; Wed, 21 Jan 2026 18:05:30 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1769015131; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=1dYR1lsf1+/uGCewQmsxVMEPBYVxpmGk/RUoFKBx98M=; b=Oa/3vuDVkLixO+cszqRJW52q8p0WgR9CVLP0eQJ2VatcLv2vRRAIky/lhhRBOe7CkEOpXL nXP8LeZKytELVom3L77genXNHPCPMUM8RxN7CwOuyVfMw2bGpiFhCjy5oXtDVo1qCmw0s4 4FPl/SnvKIoQ22IZhzBi1URW6DATnwI5t/rzitifI+Av6uTQz5MjEzT7Jc+V7byUl++iVB H9jnxjUc/uCpPC62Dr4Zj/rcvZC/SA1OVBd9YAWeX4HmTg1rkqrpRt6uI21q/piJJpYLJ3 gDcW56WruNstbBdQxaCuOdJSf0O8oQp6V9VzAH8kT9hxGQyrgfDIbdiQfXOW0w== From: "Miquel Raynal (Schneider Electric)" Date: Wed, 21 Jan 2026 18:05:07 +0100 Subject: [PATCH v3 11/17] spi: cadence-qspi: Try hard to disable the clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-schneider-6-19-rc1-qspi-v3-11-43e70fab4444@bootlin.com> References: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> In-Reply-To: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 In the remove path, we should try hard to perform all steps as we simply cannot fail. The "no runtime PM" quirk must only alter the state of the RPM core, but the clocks should still be disabled if that is possible. Move the disable call outside of the RPM quirk. Tested-by: Wolfram Sang Signed-off-by: Miquel Raynal (Schneider Electric) --- drivers/spi/spi-cadence-quadspi.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 4bfe65af458e..af0ad24d8d39 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -2039,6 +2039,7 @@ static void cqspi_remove(struct platform_device *pdev) const struct cqspi_driver_platdata *ddata; struct cqspi_st *cqspi =3D platform_get_drvdata(pdev); struct device *dev =3D &pdev->dev; + int ret =3D 0; =20 ddata =3D of_device_get_match_data(dev); =20 @@ -2058,8 +2059,10 @@ static void cqspi_remove(struct platform_device *pde= v) cqspi_jh7110_disable_clk(pdev, cqspi); =20 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) - if (pm_runtime_get_sync(&pdev->dev) >=3D 0) - clk_disable(cqspi->clk); + ret =3D pm_runtime_get_sync(&pdev->dev); + + if (ret >=3D 0) + clk_disable(cqspi->clk); =20 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) { pm_runtime_put_sync(&pdev->dev); --=20 2.51.1 From nobody Mon Feb 9 15:04:41 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 917D94D98F6 for ; Wed, 21 Jan 2026 17:05:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769015137; cv=none; b=uA39uoZlM4er24PavlZLcwv3iBlU9zvC73aQGQBHyLxbvR5akB7/R9+v9jg5z9aySQnwZCv/ydFyFqLVUe31CKzGPv1Fo4KS/xyRglj2sXSx5X6U72s4gOJM0Jw3IzEHvmNdxWSVqAewVXeb1OHZqFYV06xnrZNESMsoavCSv34= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769015137; c=relaxed/simple; bh=NnVfryO6BRSjwQDlJu3rafKK5APBWnzqs4VCTVfznDA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PySLprvwis+SUNno8cb63Le+ROHaoghxaZ8pgzR3zn8VN/iG66G9OQdcq/6+UMqWQy++ytx6CqFXqeY3igkyfA/cyQtTiTy2wQ/fe9oc1Qe+jSscZmX4bdbGsjW1/IS1hTvoXDpbiaz8UA+pibI3lISBb6M5ZX9eAQnhr51NmI8= ARC-Authentication-Results: i=1; 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Wed, 21 Jan 2026 18:05:31 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1769015133; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=XeAHb3gGALFuLZFUyLB8QFGPh0dHR/21fhaGfLuTKSw=; b=ouhs8GsPTn9PuZn9ywHEM3rl/LeYAxbl90A+5v2naIKf9vUVdKUhzn6icY9+TAcprnMLvk d/ak2/3kYfzNl+ONPzIa3IzE8XGJ1ZpVeFRty67c6LA33//3VLM/dxvnvwYF5FZwqlncqA y7EnJl+h5P81ZmkZeh2WNy3WjZcPy5n+Wey/383tLPV6/S1ZWGx9/VAQqclcsPZx73DFEh 1uUvlf24Xu0Gt89sMolojQax0SBgIdYlnXGFcO+rtLMZ2M5i+CQ/dV4g18nbx777hiMSzT kZtBdGCLrwTdTz77zT6kU5lIEVSzpmdHMJNOb/xBeES8qNwV1xiImUpbF0XGfg== From: "Miquel Raynal (Schneider Electric)" Date: Wed, 21 Jan 2026 18:05:08 +0100 Subject: [PATCH v3 12/17] spi: cadence-qspi: Kill cqspi_jh7110_clk_init Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-schneider-6-19-rc1-qspi-v3-12-43e70fab4444@bootlin.com> References: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> In-Reply-To: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 This controller can be fed by either a main "ref" clock, or three clocks ("ref" again, "ahb", "apb"). In practice, it is likely that all controllers have the same inputs, but a single clock feeds the three interfaces (ref is used for controlling the external interface, ahb/apb the internal ones). Handling these clocks is in no way SoC specific, only the number of expected clocks may change. Plus, we will soon be adding another controller requiring an AHB and an APB clock as well, so it is time to align the whole clock handling. Furthermore, the use of the cqspi_jh7110_clk_init() helper, which specifically grabs and enables the "ahb" and "apb" clocks, is a bit convoluted: - only the JH7110 compatible provides the ->jh7110_clk_init() callback, - in the probe, if the above callback is set in the driver data, the driver does not call the callback (!) but instead calls the helper directly (?), - in the helper, the is_jh7110 boolean is set. This logic does not make sense. Instead: - in the probe, set the is_jh7110 boolean based on the compatible, - collect all available clocks with the "bulk" helper, - enable the extra clocks if they are available, - kill the SoC specific cqspi_jh7110_clk_init() helper. This also allows to group the clock handling instead of depending on the driver data pointer, which further simplifies the error path and the remove callback. Tested-by: Wolfram Sang Signed-off-by: Miquel Raynal (Schneider Electric) --- drivers/spi/spi-cadence-quadspi.c | 112 ++++++++++------------------------= ---- 1 file changed, 29 insertions(+), 83 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index af0ad24d8d39..35379546c3b4 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -55,7 +55,8 @@ static_assert(CQSPI_MAX_CHIPSELECT <=3D SPI_DEVICE_CS_CNT= _MAX); #define CQSPI_OP_WIDTH(part) ((part).nbytes ? ilog2((part).buswidth) : 0) =20 enum { - CLK_QSPI_APB =3D 0, + CLK_QSPI_REF =3D 0, + CLK_QSPI_APB, CLK_QSPI_AHB, CLK_QSPI_NUM, }; @@ -76,8 +77,7 @@ struct cqspi_flash_pdata { struct cqspi_st { struct platform_device *pdev; struct spi_controller *host; - struct clk *clk; - struct clk *clks[CLK_QSPI_NUM]; + struct clk_bulk_data clks[CLK_QSPI_NUM]; unsigned int sclk; =20 void __iomem *iobase; @@ -121,8 +121,6 @@ struct cqspi_driver_platdata { int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata, u_char *rxbuf, loff_t from_addr, size_t n_rx); u32 (*get_dma_status)(struct cqspi_st *cqspi); - int (*jh7110_clk_init)(struct platform_device *pdev, - struct cqspi_st *cqspi); }; =20 /* Operation timeout value */ @@ -1763,51 +1761,6 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi) return 0; } =20 -static int cqspi_jh7110_clk_init(struct platform_device *pdev, struct cqsp= i_st *cqspi) -{ - static struct clk_bulk_data qspiclk[] =3D { - { .id =3D "apb" }, - { .id =3D "ahb" }, - }; - - int ret =3D 0; - - ret =3D devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(qspiclk), qspiclk); - if (ret) { - dev_err(&pdev->dev, "%s: failed to get qspi clocks\n", __func__); - return ret; - } - - cqspi->clks[CLK_QSPI_APB] =3D qspiclk[0].clk; - cqspi->clks[CLK_QSPI_AHB] =3D qspiclk[1].clk; - - ret =3D clk_prepare_enable(cqspi->clks[CLK_QSPI_APB]); - if (ret) { - dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_APB\n", __func__); - return ret; - } - - ret =3D clk_prepare_enable(cqspi->clks[CLK_QSPI_AHB]); - if (ret) { - dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_AHB\n", __func__); - goto disable_apb_clk; - } - - cqspi->is_jh7110 =3D true; - - return 0; - -disable_apb_clk: - clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]); - - return ret; -} - -static void cqspi_jh7110_disable_clk(struct platform_device *pdev, struct = cqspi_st *cqspi) -{ - clk_disable_unprepare(cqspi->clks[CLK_QSPI_AHB]); - clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]); -} static int cqspi_probe(struct platform_device *pdev) { const struct cqspi_driver_platdata *ddata; @@ -1816,8 +1769,7 @@ static int cqspi_probe(struct platform_device *pdev) struct spi_controller *host; struct resource *res_ahb; struct cqspi_st *cqspi; - int ret; - int irq; + int ret, irq; =20 host =3D devm_spi_alloc_host(&pdev->dev, sizeof(*cqspi)); if (!host) @@ -1829,10 +1781,11 @@ static int cqspi_probe(struct platform_device *pdev) host->dev.of_node =3D pdev->dev.of_node; =20 cqspi =3D spi_controller_get_devdata(host); + if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) + cqspi->is_jh7110 =3D true; =20 cqspi->pdev =3D pdev; cqspi->host =3D host; - cqspi->is_jh7110 =3D false; cqspi->ddata =3D ddata =3D of_device_get_match_data(dev); platform_set_drvdata(pdev, cqspi); =20 @@ -1849,12 +1802,14 @@ static int cqspi_probe(struct platform_device *pdev) return ret; } =20 - /* Obtain QSPI clock. */ - cqspi->clk =3D devm_clk_get(dev, NULL); - if (IS_ERR(cqspi->clk)) { - dev_err(dev, "Cannot claim QSPI clock.\n"); - ret =3D PTR_ERR(cqspi->clk); - return ret; + /* Obtain QSPI clocks. */ + ret =3D devm_clk_bulk_get_optional(dev, CLK_QSPI_NUM, cqspi->clks); + if (ret) + return dev_err_probe(dev, ret, "Failed to get clocks\n"); + + if (!cqspi->clks[CLK_QSPI_REF].clk) { + dev_err(dev, "Cannot claim mandatory QSPI ref clock.\n"); + return -ENODEV; } =20 /* Obtain and remap controller address. */ @@ -1886,10 +1841,9 @@ static int cqspi_probe(struct platform_device *pdev) if (ret) return ret; =20 - - ret =3D clk_prepare_enable(cqspi->clk); + ret =3D clk_bulk_prepare_enable(CLK_QSPI_NUM, cqspi->clks); if (ret) { - dev_err(dev, "Cannot enable QSPI clock.\n"); + dev_err(dev, "Cannot enable QSPI clocks.\n"); goto disable_rpm; } =20 @@ -1898,22 +1852,22 @@ static int cqspi_probe(struct platform_device *pdev) if (IS_ERR(rstc)) { ret =3D PTR_ERR(rstc); dev_err(dev, "Cannot get QSPI reset.\n"); - goto disable_clk; + goto disable_clks; } =20 rstc_ocp =3D devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); if (IS_ERR(rstc_ocp)) { ret =3D PTR_ERR(rstc_ocp); dev_err(dev, "Cannot get QSPI OCP reset.\n"); - goto disable_clk; + goto disable_clks; } =20 - if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) { + if (cqspi->is_jh7110) { rstc_ref =3D devm_reset_control_get_optional_exclusive(dev, "rstc_ref"); if (IS_ERR(rstc_ref)) { ret =3D PTR_ERR(rstc_ref); dev_err(dev, "Cannot get QSPI REF reset.\n"); - goto disable_clk; + goto disable_clks; } reset_control_assert(rstc_ref); reset_control_deassert(rstc_ref); @@ -1925,7 +1879,7 @@ static int cqspi_probe(struct platform_device *pdev) reset_control_assert(rstc_ocp); reset_control_deassert(rstc_ocp); =20 - cqspi->master_ref_clk_hz =3D clk_get_rate(cqspi->clk); + cqspi->master_ref_clk_hz =3D clk_get_rate(cqspi->clks[CLK_QSPI_REF].clk); host->max_speed_hz =3D cqspi->master_ref_clk_hz; =20 /* write completion is supported by default */ @@ -1951,12 +1905,6 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->slow_sram =3D true; if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) cqspi->apb_ahb_hazard =3D true; - - if (ddata->jh7110_clk_init) { - ret =3D cqspi_jh7110_clk_init(pdev, cqspi); - if (ret) - goto disable_clk; - } if (ddata->quirks & CQSPI_DISABLE_STIG_MODE) cqspi->disable_stig_mode =3D true; =20 @@ -2022,11 +1970,8 @@ static int cqspi_probe(struct platform_device *pdev) disable_controller: cqspi_controller_enable(cqspi, 0); disable_clks: - if (cqspi->is_jh7110) - cqspi_jh7110_disable_clk(pdev, cqspi); -disable_clk: if (pm_runtime_get_sync(&pdev->dev) >=3D 0) - clk_disable_unprepare(cqspi->clk); + clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks); disable_rpm: if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) pm_runtime_disable(dev); @@ -2055,14 +2000,12 @@ static void cqspi_remove(struct platform_device *pd= ev) =20 cqspi_controller_enable(cqspi, 0); =20 - if (cqspi->is_jh7110) - cqspi_jh7110_disable_clk(pdev, cqspi); =20 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) ret =3D pm_runtime_get_sync(&pdev->dev); =20 if (ret >=3D 0) - clk_disable(cqspi->clk); + clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks); =20 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) { pm_runtime_put_sync(&pdev->dev); @@ -2075,15 +2018,19 @@ static int cqspi_runtime_suspend(struct device *dev) struct cqspi_st *cqspi =3D dev_get_drvdata(dev); =20 cqspi_controller_enable(cqspi, 0); - clk_disable_unprepare(cqspi->clk); + clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks); return 0; } =20 static int cqspi_runtime_resume(struct device *dev) { struct cqspi_st *cqspi =3D dev_get_drvdata(dev); + int ret; + + ret =3D clk_bulk_prepare_enable(CLK_QSPI_NUM, cqspi->clks); + if (ret) + return ret; =20 - clk_prepare_enable(cqspi->clk); cqspi_wait_idle(cqspi); cqspi_controller_enable(cqspi, 0); cqspi_controller_init(cqspi); @@ -2166,7 +2113,6 @@ static const struct cqspi_driver_platdata versal2_osp= i =3D { =20 static const struct cqspi_driver_platdata jh7110_qspi =3D { .quirks =3D CQSPI_DISABLE_DAC_MODE, - .jh7110_clk_init =3D cqspi_jh7110_clk_init, }; =20 static const struct cqspi_driver_platdata pensando_cdns_qspi =3D { --=20 2.51.1 From nobody Mon Feb 9 15:04:41 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 53DF34D991E; Wed, 21 Jan 2026 17:05:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769015139; cv=none; b=FPgDcRRmxnBBRbDKsmOtRYg9zb1J4khUPkRkEKHf+RPzsy7DX6gYDOjzcrPP/3F0n5rBlUtomb+T2rLQXzj718gd5NmcMNBocf5wjLgWHNy/nrldB8eiBbbwgstjF2AO7eMtDqOebyHvqdDm4VUlmO6Q0l5xbSYOjzAscGwth7k= ARC-Message-Signature: i=1; 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Wed, 21 Jan 2026 17:05:08 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 0164F6070A; Wed, 21 Jan 2026 17:05:36 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 9C017119B18D4; Wed, 21 Jan 2026 18:05:33 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1769015135; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=WIFqPskiDM9IjrZs85Iqodhn/D6pSUk1OJXi0KZ7anY=; b=JN1wMIaeDUKDCERcrdVvdA9LjV3So1tTmGvPS6HNjf5KaPDaWm0CaeDoXYXv6SecjnZcyv Ht4SZs2EwQATmllbldoBEFLZTaNx+1wHG5odMmYiw5u3pfV0ruv4xUCFowOrzf5nC0mfIk UYf8MKXajxdRi0F0u0WD0boGRtOcYYo2N2bq/AFkfmO7sEJRLjZ2/wwztpXrnvRbhuKrg2 6lGQvGfzD85R5aIt6J8q8+jPZtBUUexLKO4c3kNXrUMBBCT9KNHH8WPdqfjTcwYXKa9AqC WNZ1gLRrybHfDAe/b+J1K4udaqMc8cXMMRj4AAoLMtvICWWaoGpxgyrrNHEb1g== From: "Miquel Raynal (Schneider Electric)" Date: Wed, 21 Jan 2026 18:05:09 +0100 Subject: [PATCH v3 13/17] spi: cadence-qspi: Add a flag for controllers without indirect access support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-schneider-6-19-rc1-qspi-v3-13-43e70fab4444@bootlin.com> References: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> In-Reply-To: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Renesas RZ/N1 QSPI controllers embed the Cadence IP with some limitations/simplifications. One of the is that only direct access is supported, none of the registers related to indirect writes are populated, so create a flag to avoid these accesses and make sure only direct accessors are called. Tested-by: Wolfram Sang Signed-off-by: Miquel Raynal (Schneider Electric) --- drivers/spi/spi-cadence-quadspi.c | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 35379546c3b4..e1ec20684b0a 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -47,6 +47,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <=3D SPI_DEVICE_CS_CNT= _MAX); #define CQSPI_SUPPORT_DEVICE_RESET BIT(8) #define CQSPI_DISABLE_STIG_MODE BIT(9) #define CQSPI_DISABLE_RUNTIME_PM BIT(10) +#define CQSPI_NO_INDIRECT_MODE BIT(11) =20 /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -1423,7 +1424,8 @@ static ssize_t cqspi_read(struct cqspi_flash_pdata *f= _pdata, if (ret) return ret; =20 - if (cqspi->use_direct_mode && ((from + len) <=3D cqspi->ahb_size)) + if ((cqspi->use_direct_mode && ((from + len) <=3D cqspi->ahb_size)) || + (cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) return cqspi_direct_read_execute(f_pdata, buf, from, len); =20 if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma && @@ -1624,19 +1626,20 @@ static void cqspi_controller_init(struct cqspi_st *= cqspi) /* Disable all interrupts. */ writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); =20 - /* Configure the SRAM split to 1:1 . */ - writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); + if (!(cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) { + /* Configure the SRAM split to 1:1 . */ + writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); + /* Load indirect trigger address. */ + writel(cqspi->trigger_address, + cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); =20 - /* Load indirect trigger address. */ - writel(cqspi->trigger_address, - cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); - - /* Program read watermark -- 1/2 of the FIFO. */ - writel(cqspi->fifo_depth * cqspi->fifo_width / 2, - cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); - /* Program write watermark -- 1/8 of the FIFO. */ - writel(cqspi->fifo_depth * cqspi->fifo_width / 8, - cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); + /* Program read watermark -- 1/2 of the FIFO. */ + writel(cqspi->fifo_depth * cqspi->fifo_width / 2, + cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); + /* Program write watermark -- 1/8 of the FIFO. */ + writel(cqspi->fifo_depth * cqspi->fifo_width / 8, + cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); + } =20 /* Disable direct access controller */ if (!cqspi->use_direct_mode) { --=20 2.51.1 From nobody Mon Feb 9 15:04:41 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70A734D9912; Wed, 21 Jan 2026 17:05:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769015141; cv=none; b=NH7DHdY64fA5X2DnwSo5MELtRoXPx7mS6SpYJxheNEc42OoUirzZOjYrwodJt1JH3i50raQNL934EcOms1hkt4N9S59MRktfMJuf4PUSlZhZcyOhX7PhfJfviORUUJeWFoCuQwMZhhu2NV8xAcpKgiBnvnxs8NpOysF49+IqyuM= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-schneider-6-19-rc1-qspi-v3-14-43e70fab4444@bootlin.com> References: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> In-Reply-To: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Renesas RZ/N1 QSPI controllers embed the Cadence IP with some modifications. For instance, they feature a write protection of the direct mapping at the controller level, with this feature all data writes to the AHB region are aborted. Despite the fact that the flag setting write protection is disabled by default, Bootloaders may (and actually do) set it, so mark this feature as being available with a specific flag to, if applicable, make sure it is disabled. Tested-by: Wolfram Sang Signed-off-by: Miquel Raynal (Schneider Electric) --- drivers/spi/spi-cadence-quadspi.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index e1ec20684b0a..e0e4423baed9 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -48,6 +48,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <=3D SPI_DEVICE_CS_CNT= _MAX); #define CQSPI_DISABLE_STIG_MODE BIT(9) #define CQSPI_DISABLE_RUNTIME_PM BIT(10) #define CQSPI_NO_INDIRECT_MODE BIT(11) +#define CQSPI_HAS_WR_PROTECT BIT(12) =20 /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -218,6 +219,8 @@ struct cqspi_driver_platdata { #define CQSPI_REG_IRQSTATUS 0x40 #define CQSPI_REG_IRQMASK 0x44 =20 +#define CQSPI_REG_WR_PROT_CTRL 0x58 + #define CQSPI_REG_INDIRECTRD 0x60 #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1) @@ -1641,6 +1644,10 @@ static void cqspi_controller_init(struct cqspi_st *c= qspi) cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); } =20 + /* Disable write protection at controller level */ + if (cqspi->ddata && cqspi->ddata->quirks & CQSPI_HAS_WR_PROTECT) + writel(0, cqspi->iobase + CQSPI_REG_WR_PROT_CTRL); + /* Disable direct access controller */ if (!cqspi->use_direct_mode) { reg =3D readl(cqspi->iobase + CQSPI_REG_CONFIG); --=20 2.51.1 From nobody Mon Feb 9 15:04:41 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36A264DA55E; Wed, 21 Jan 2026 17:05:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769015143; cv=none; b=p0hkk0MQyylbfFz5eprptNIUiuPoBGHExcH8FqUSgexUa7tuaxLjzqphctgl1iA2OI67CvCPzWudnrq4ZuHJ/vSw6LJKQJhsMQ/Zd1TkT+5shG6186CNIFc/wVfMslZlUalVd/e3VHnbyJ7i/wSDejrDEf5ypfl1vsFh4o2z0Vo= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-schneider-6-19-rc1-qspi-v3-15-43e70fab4444@bootlin.com> References: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> In-Reply-To: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Bindings expect 4 to be the default value for cdns,fifo-width. Said otherwise, if the property (which is not mandatory) is not provided, the OS, in order to comply with the bindings, should not error out and take 4 as default value. Comply with the bindings. This would have slighlty simplyfied my testing if it had been implemented correctly in the first place, but in practice it should have no impact on the existing boards using this controller, as they all set cdns,fifo-width to 4 explicitly in their upstream DTS. Signed-off-by: Miquel Raynal (Schneider Electric) --- drivers/spi/spi-cadence-quadspi.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index e0e4423baed9..5f3a914e45f7 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1596,10 +1596,8 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqspi) cqspi->fifo_depth =3D 0; } =20 - if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) { - dev_err(dev, "couldn't determine fifo-width\n"); - return -ENXIO; - } + if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) + cqspi->fifo_width =3D 4; =20 if (of_property_read_u32(np, "cdns,trigger-address", &cqspi->trigger_address)) { --=20 2.51.1 From nobody Mon Feb 9 15:04:41 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0582D4DB565 for ; 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bh=IVRLNIDnLsBQL3km1y8IbVzR7+9lYxXcsBbu4Y2gsdw=; b=HI46P8sr7DSmtYRX82Edwy4vUCNvgF28x1WkOphxfHP0+RULjOI/gdU+/iAiDSNtoOzd4L xi6TnCqkXB4RyjAydcJxMPlMsgCok3hmYflLcSLJiGe+w8o2VSmWJPJR9ZV5Z2hbtjW2HT /QNO+ibc20O6nM/jM0o8uyRfh5qmgG5d2yIITJOKzRaApRNAUi2BMzhrExYpTXvp1yXX5b pIrfiQHuv4hKiEsWQSnCG7buJWxUf6bop0wdx1b4YytRPqQFUmInn8sQdLW4f8/J5VoS6V MTRIR6438gVTXnH5QffEf1Lkswi7OsI2dy2vMuO6ype7HDCSf4VxRp+tsiUxVQ== From: "Miquel Raynal (Schneider Electric)" Date: Wed, 21 Jan 2026 18:05:12 +0100 Subject: [PATCH v3 16/17] spi: cadence-qspi: Add support for the Renesas RZ/N1 controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-schneider-6-19-rc1-qspi-v3-16-43e70fab4444@bootlin.com> References: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> In-Reply-To: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Renesas RZ/N1 QSPI controllers embed a modified version of the Cadence IP with the following settings: - a limited bus clock range - no DTR support - no DMA - no useful interrupt flag - only direct accesses (no INDAC mode) - write protection The controller has been tested by running the SPI NOR check list with a custom RZ/N1D400 based board mounted with a Spansion s25fl128s1 quad SPI. Tested-by: Wolfram Sang Signed-off-by: Miquel Raynal (Schneider Electric) --- Output of the SPI NOR test procedure: s25fl128s1 0120184d0180 spansion xxd: /sys/bus/spi/devices/spi0.0/spi-nor/sfdp: No such file or directory md5sum: can't open '/sys/bus/spi/devices/spi0.0/spi-nor/sfdp': No such file= or directory 1+0 records in 1+0 records out Copied 65536 bytes from qspi_test to address 0x00000000 in flash Erased 65536 bytes from address 0x00000000 in flash Copied 65536 bytes from address 0x00000000 in flash to qspi_read 0000000 ffff ffff ffff ffff ffff ffff ffff ffff * 0010000 Copied 65536 bytes from qspi_test to address 0x00000000 in flash Copied 65536 bytes from address 0x00000000 in flash to qspi_read 71f8b056a4bf5f51639a972dc9aac55eb8654fdc qspi_test 71f8b056a4bf5f51639a972dc9aac55eb8654fdc qspi_read Read speed: * page read speed is 6464 KiB/s * 2 page read speed is 9014 KiB/s * eraseblock read speed is 14222 KiB/s Write speed: * page write speed is 621 KiB/s * 2 page write speed is 626 KiB/s * eraseblock write speed is 633 KiB/s Erase speed: * erase speed is 617 KiB/s --- drivers/spi/spi-cadence-quadspi.c | 56 +++++++++++++++++++++++++++++------= ---- 1 file changed, 42 insertions(+), 14 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 5f3a914e45f7..6dd14ac37434 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -110,6 +110,7 @@ struct cqspi_st { bool apb_ahb_hazard; =20 bool is_jh7110; /* Flag for StarFive JH7110 SoC */ + bool is_rzn1; /* Flag for Renesas RZN1 SoC */ bool disable_stig_mode; refcount_t refcount; refcount_t inflight_ops; @@ -1337,8 +1338,9 @@ static ssize_t cqspi_write(struct cqspi_flash_pdata *= f_pdata, * mode. So, we can not use direct mode when in DTR mode for writing * data. */ - if (!op->cmd.dtr && cqspi->use_direct_mode && - cqspi->use_direct_mode_wr && ((to + len) <=3D cqspi->ahb_size)) { + if ((!op->cmd.dtr && cqspi->use_direct_mode && + cqspi->use_direct_mode_wr && ((to + len) <=3D cqspi->ahb_size)) || + (cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) { memcpy_toio(cqspi->ahb_base + to, buf, len); return cqspi_wait_idle(cqspi); } @@ -1512,6 +1514,7 @@ static int cqspi_exec_mem_op(struct spi_mem *mem, con= st struct spi_mem_op *op) static bool cqspi_supports_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) { + struct cqspi_st *cqspi =3D spi_controller_get_devdata(mem->spi->controlle= r); bool all_true, all_false; =20 /* @@ -1538,6 +1541,9 @@ static bool cqspi_supports_mem_op(struct spi_mem *mem, /* A single opcode is supported, it will be repeated */ if ((op->cmd.opcode >> 8) !=3D (op->cmd.opcode & 0xFF)) return false; + + if (cqspi->is_rzn1) + return false; } else if (!all_false) { /* Mixed DTR modes are not supported. */ return false; @@ -1591,18 +1597,20 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqsp= i) =20 cqspi->is_decoded_cs =3D of_property_read_bool(np, "cdns,is-decoded-cs"); =20 - if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { - /* Zero signals FIFO depth should be runtime detected. */ - cqspi->fifo_depth =3D 0; - } + if (!(cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) { + if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { + /* Zero signals FIFO depth should be runtime detected. */ + cqspi->fifo_depth =3D 0; + } =20 - if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) - cqspi->fifo_width =3D 4; + if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) + cqspi->fifo_width =3D 4; =20 - if (of_property_read_u32(np, "cdns,trigger-address", - &cqspi->trigger_address)) { - dev_err(dev, "couldn't determine trigger-address\n"); - return -ENXIO; + if (of_property_read_u32(np, "cdns,trigger-address", + &cqspi->trigger_address)) { + dev_err(dev, "couldn't determine trigger-address\n"); + return -ENXIO; + } } =20 if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) @@ -1666,6 +1674,9 @@ static void cqspi_controller_detect_fifo_depth(struct= cqspi_st *cqspi) struct device *dev =3D &cqspi->pdev->dev; u32 reg, fifo_depth; =20 + if (cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE) + return; + /* * Bits N-1:0 are writable while bits 31:N are read as zero, with 2^N * the FIFO depth. @@ -1791,6 +1802,8 @@ static int cqspi_probe(struct platform_device *pdev) cqspi =3D spi_controller_get_devdata(host); if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) cqspi->is_jh7110 =3D true; + if (of_device_is_compatible(pdev->dev.of_node, "renesas,rzn1-qspi")) + cqspi->is_rzn1 =3D true; =20 cqspi->pdev =3D pdev; cqspi->host =3D host; @@ -1888,7 +1901,12 @@ static int cqspi_probe(struct platform_device *pdev) reset_control_deassert(rstc_ocp); =20 cqspi->master_ref_clk_hz =3D clk_get_rate(cqspi->clks[CLK_QSPI_REF].clk); - host->max_speed_hz =3D cqspi->master_ref_clk_hz; + if (!cqspi->is_rzn1) { + host->max_speed_hz =3D cqspi->master_ref_clk_hz; + } else { + host->max_speed_hz =3D cqspi->master_ref_clk_hz / 2; + host->min_speed_hz =3D cqspi->master_ref_clk_hz / 32; + } =20 /* write completion is supported by default */ cqspi->wr_completion =3D true; @@ -1953,7 +1971,7 @@ static int cqspi_probe(struct platform_device *pdev) if (ddata && (ddata->quirks & CQSPI_SUPPORT_DEVICE_RESET)) cqspi_device_reset(cqspi); =20 - if (cqspi->use_direct_mode) { + if (cqspi->use_direct_mode && !cqspi->is_rzn1) { ret =3D cqspi_request_mmap_dma(cqspi); if (ret =3D=3D -EPROBE_DEFER) { dev_err_probe(&pdev->dev, ret, "Failed to request mmap DMA\n"); @@ -2133,6 +2151,12 @@ static const struct cqspi_driver_platdata mobileye_e= yeq5_ospi =3D { CQSPI_RD_NO_IRQ, }; =20 +static const struct cqspi_driver_platdata renesas_rzn1_qspi =3D { + .hwcaps_mask =3D CQSPI_SUPPORTS_QUAD, + .quirks =3D CQSPI_NO_SUPPORT_WR_COMPLETION | CQSPI_RD_NO_IRQ | + CQSPI_HAS_WR_PROTECT | CQSPI_NO_INDIRECT_MODE, +}; + static const struct of_device_id cqspi_dt_ids[] =3D { { .compatible =3D "cdns,qspi-nor", @@ -2174,6 +2198,10 @@ static const struct of_device_id cqspi_dt_ids[] =3D { .compatible =3D "amd,versal2-ospi", .data =3D &versal2_ospi, }, + { + .compatible =3D "renesas,rzn1-qspi", + .data =3D &renesas_rzn1_qspi, + }, { /* end of table */ } }; =20 --=20 2.51.1 From nobody Mon Feb 9 15:04:41 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7AD24DBD68 for ; Wed, 21 Jan 2026 17:05:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769015147; cv=none; b=uKbQS2sZj7oj0HUq9PJ+6tZdELUbU6/zLXgEF3RFNvFKZkgXZ5I+z0DeWHqE/8qkj+PPdUUcLMjCr53USHSHSnZXnQJb7Haq8WQsythOp+0DA/fYwrrTetAZY0Wya8CLUaotrd1xPPcal4qAgsn4Q6fUHGUnoiTnIeAYitF7dk8= ARC-Message-Signature: i=1; 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Wed, 21 Jan 2026 17:05:16 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 68A936070A; Wed, 21 Jan 2026 17:05:43 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id D2B0F119B17F5; Wed, 21 Jan 2026 18:05:40 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1769015142; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=VVRqIRwbr5v98YAdUusQ7vUrAWpnmI4l7K7vSQXWOkg=; b=mwpKwRIdOIo1uBv5nU/pBm6o0qqPb5Rxe5HHwpcQXJx0/ub+1CK+V9GvRNXbiCdDxte6MT kt+3FdiAg0m0Da1j+1tmcVyet0JE6GZwW1JbnHiqVwQ+oD/9yS6sEnarM6+u++nJFWgwEI ly1B7FMLKa22EDctH3OMaQ5xo8XSJvs/9nEHK2YXIR7J9gj6iSp8A95XrOv+TZPEWshdYu 7CpVe31aHW0Y534SiIC6UTygBm2o1RcNZSj0Y5+3PPfGCP2VbGBH1JCJS+NlL0DbSr+Jvm AgC0yWmA3UesYAUYFg6gXlKxXkBCxT4NIZbKVopLpkzNRe93fBhdFhexzJamSw== From: "Miquel Raynal (Schneider Electric)" Date: Wed, 21 Jan 2026 18:05:13 +0100 Subject: [PATCH v3 17/17] ARM: dts: r9a06g032: Describe the QSPI controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-schneider-6-19-rc1-qspi-v3-17-43e70fab4444@bootlin.com> References: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> In-Reply-To: <20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Add a node describing the QSPI controller. There are 2 clocks feeding this controller: - one for the reference clock - one that feeds both the ahb and the apb interfaces As the binding expect either the ref clock, or all three (ref, ahb and apb) clocks, it makes sense to provide the same clock twice. Reviewed-by: Geert Uytterhoeven Tested-by: Wolfram Sang Signed-off-by: Miquel Raynal (Schneider Electric) --- arch/arm/boot/dts/renesas/r9a06g032.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/r= enesas/r9a06g032.dtsi index 8debb77803bb..d20f397dcd96 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -66,6 +66,20 @@ soc { #size-cells =3D <1>; ranges; =20 + qspi0: spi@40005000 { + compatible =3D "renesas,r9a06g032-qspi", "renesas,rzn1-qspi"; + reg =3D <0x40005000 0x1000>, <0x10000000 0x10000000>; + interrupts =3D ; + clocks =3D <&sysctrl R9A06G032_CLK_QSPI0>, <&sysctrl R9A06G032_HCLK_QSP= I0>, + <&sysctrl R9A06G032_HCLK_QSPI0>; + clock-names =3D "ref", "ahb", "apb"; + #address-cells =3D <1>; + #size-cells =3D <0>; + cdns,fifo-width =3D <4>; + cdns,fifo-depth =3D <4>; + status =3D "disabled"; + }; + rtc0: rtc@40006000 { compatible =3D "renesas,r9a06g032-rtc", "renesas,rzn1-rtc"; reg =3D <0x40006000 0x1000>; --=20 2.51.1