From nobody Mon Feb 9 06:49:58 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A143048AE24; Wed, 21 Jan 2026 14:23:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769005436; cv=none; b=oXPhAxYCvQV3Dka8hbhOgvIxpOQjih4zIwKAYgYzsydapnQuXAOkpQRDFhN9bO52BA3WwtHbq8kYcbtn+ObPsU+Wrm/Hof2zg8o6akaZ0uz1l5VbJg0/N4hl9uj5VrkW4HAb+7Koybtl2zuCEysEAdW7putLtzAiM/63Y2qqojI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769005436; c=relaxed/simple; bh=dSeJB80aGJaadYckPLrYHQ6rc38HTer5YOlsuvwWVFc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Tu5L955U80QyN8kwi+DeHQQw5gLGvKD9HbmN9IE80wz8KpMdM56qZLnPpNkXYtEhDlCA9eL9RHlFHaGjqRUpoUy3bu6Oc5zeZyAXqai06Ec8wXMGUR8EVUrzD74Vq8kOyLgw+IYtMfVY5VR85MoLNvc2SBjsBQ89yiMaWWBd38U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=APhCU/do; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="APhCU/do" Received: by smtp.kernel.org (Postfix) with ESMTPS id 46CCCC116D0; Wed, 21 Jan 2026 14:23:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769005436; bh=dSeJB80aGJaadYckPLrYHQ6rc38HTer5YOlsuvwWVFc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=APhCU/doHB3Ry00o3wKKh0RCFPY32fGqbHjhDYQ6wtkDhuVrr3ltcM4LUkSDXEgM9 ZhpH+VwiGWAbJ8fuwNFma9pQveXMLTFcMpgESMAE2TNd4mqJfmxYVuiTO8X/qG5Nj+ Q2dYSAqJqdxsLVRieh7HMGNaG5ik3rdurlwtQD+u+aTvX+1JIYBtnvnJYy+D+HbH/a 1ywro/7qssswArd1zhwqt6vVwKjuqx65T1l4OEMcLtbZ3PPrirZN3OYFPHJt9kvgQ2 tGxeCOzYNEai+Fi9qYlyo+RhZp08UvmLy5Om/cnLdgZeTfjRsdY/xSyVahm/sQolGv Hd+Z/340qHp5g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34BA1D262B5; Wed, 21 Jan 2026 14:23:56 +0000 (UTC) From: Jan Petrous via B4 Relay Date: Wed, 21 Jan 2026 15:23:35 +0100 Subject: [PATCH RFC v2 1/4] net: stmmac: platform: read channels irq Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-dwmac_multi_irq-v2-1-3b829230d071@oss.nxp.com> References: <20260121-dwmac_multi_irq-v2-0-3b829230d071@oss.nxp.com> In-Reply-To: <20260121-dwmac_multi_irq-v2-0-3b829230d071@oss.nxp.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, "Jan Petrous (OSS)" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769005434; l=2216; i=jan.petrous@oss.nxp.com; s=20240922; h=from:subject:message-id; bh=iVDjqjFRysTRLVGIZGhOKQsFaPM0aMu1efGJgmkieas=; b=mItJ15227Tlx2qbVRKvFGaG5LPZXO5mGMtGbZVHeZhtXgpqJ2HZOeH2awrE75tS2AetxrGmrS FLoGjWbzHqlBHKeReEph8zhXlU26s1TiQYz1NnAvlanCn0eVoChUC/i X-Developer-Key: i=jan.petrous@oss.nxp.com; a=ed25519; pk=Ke3wwK7rb2Me9UQRf6vR8AsfJZfhTyoDaxkUCqmSWYY= X-Endpoint-Received: by B4 Relay for jan.petrous@oss.nxp.com/20240922 with auth_id=217 X-Original-From: "Jan Petrous (OSS)" Reply-To: jan.petrous@oss.nxp.com From: "Jan Petrous (OSS)" Read IRQ resources for all rx/tx channels, to allow Multi-IRQ mode for platform glue drivers. Signed-off-by: Jan Petrous (OSS) Reviewed-by: Matthias Brugger --- .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 38 ++++++++++++++++++= +++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/driver= s/net/ethernet/stmicro/stmmac/stmmac_platform.c index 8979a50b5507..f10a691b8add 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -700,6 +700,9 @@ EXPORT_SYMBOL_GPL(stmmac_pltfr_find_clk); int stmmac_get_platform_resources(struct platform_device *pdev, struct stmmac_resources *stmmac_res) { + char name[16]; + int i; + memset(stmmac_res, 0, sizeof(*stmmac_res)); =20 /* Get IRQ information early to have an ability to ask for deferred @@ -743,7 +746,40 @@ int stmmac_get_platform_resources(struct platform_devi= ce *pdev, =20 stmmac_res->addr =3D devm_platform_ioremap_resource(pdev, 0); =20 - return PTR_ERR_OR_ZERO(stmmac_res->addr); + if (IS_ERR(stmmac_res->addr)) + return PTR_ERR(stmmac_res->addr); + + /* RX channels irq */ + for (i =3D 0; i < MTL_MAX_RX_QUEUES; i++) { + scnprintf(name, sizeof(name), "rx-queue-%d", i); + stmmac_res->rx_irq[i] =3D platform_get_irq_byname_optional(pdev, + name); + if (stmmac_res->rx_irq[i] < 0) { + if (stmmac_res->rx_irq[i] =3D=3D -EPROBE_DEFER) + return -EPROBE_DEFER; + dev_dbg(&pdev->dev, "IRQ rx-queue-%d not found\n", i); + + /* Stop on first unset rx-queue-%i property member */ + break; + } + } + + /* TX channels irq */ + for (i =3D 0; i < MTL_MAX_TX_QUEUES; i++) { + scnprintf(name, sizeof(name), "tx-queue-%d", i); + stmmac_res->tx_irq[i] =3D platform_get_irq_byname_optional(pdev, + name); + if (stmmac_res->tx_irq[i] < 0) { + if (stmmac_res->tx_irq[i] =3D=3D -EPROBE_DEFER) + return -EPROBE_DEFER; + dev_dbg(&pdev->dev, "IRQ tx-queue-%d not found\n", i); + + /* Stop on first unset tx-queue-%i property member */ + break; + } + } + + return 0; } EXPORT_SYMBOL_GPL(stmmac_get_platform_resources); =20 --=20 2.47.0 From nobody Mon Feb 9 06:49:58 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A138148AE21; Wed, 21 Jan 2026 14:23:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769005436; cv=none; b=OFprBdprw3iWENQMuLV500ZrhfIkiOEcHhHk0ys65Dvx+5t0NLCr3SRoZn58UkeZw2BQ6qhiXCeSJf/FUFKTR9+q97uyYstoy5zY9pv4tEjksObR3GlUri5zODmpar6Ad+0xgj8061nh3b4DdU6fnws323isuSMhdPwjkL3pn5o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769005436; c=relaxed/simple; bh=bDsa5qr79ONQyLB8IWcNyqXU1o6S3KzvbCNukf7liXQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TzLWyZOrfPXpPVhXmpVIsqHoHP01ZyVIB3hXcCT41Xq/cWohqEWW5t10OpCtVgSmwwOKUj9SeccB6ypCUfwBqN+K2BwwkJcxNuawYGacHQY5qdpV7PH7e96WBrxc6R288NCzriGlRzXsgfDeV3P7MxQQeTcJ6rPeFf2xn8gMQHs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=f1ULJnrF; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="f1ULJnrF" Received: by smtp.kernel.org (Postfix) with ESMTPS id 51D5FC19425; Wed, 21 Jan 2026 14:23:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769005436; bh=bDsa5qr79ONQyLB8IWcNyqXU1o6S3KzvbCNukf7liXQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=f1ULJnrFWRK2oIYY+AkPZt7+jDEIrep0EbMb2kPzctwEvLUySDijOstfftQ5v24RC vztc+aot8Ftxr8/asdU0AbAxOzpa1SgfpfvvhhKPIYn8HWEshFtoFyQOr7HiG1ADdM nOIxpWCp3SsTuTGRK+7aC7+olluzvWrjqmeAsf6rwzPRDCUlDA5JqUykfslSSSUCGx YzJT+8LOonhNATO5TxRV3auzRVvRIstgsDTmhkwI062wL0f5/CWC4/98mCOKZf6ZPT JgzcG91UL5pUAom+0AlBevBNjRyJoI8lb9Z24Qf+pEZyEUewTizgA332WDsUD9EfVa 6Tt2kVhosq4/Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 492CED2ECF9; Wed, 21 Jan 2026 14:23:56 +0000 (UTC) From: Jan Petrous via B4 Relay Date: Wed, 21 Jan 2026 15:23:36 +0100 Subject: [PATCH RFC v2 2/4] dt-bindings: net: nxp,s32-dwmac: Declare per-queue interrupts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-dwmac_multi_irq-v2-2-3b829230d071@oss.nxp.com> References: <20260121-dwmac_multi_irq-v2-0-3b829230d071@oss.nxp.com> In-Reply-To: <20260121-dwmac_multi_irq-v2-0-3b829230d071@oss.nxp.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, "Jan Petrous (OSS)" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769005434; l=3038; i=jan.petrous@oss.nxp.com; s=20240922; h=from:subject:message-id; bh=FKbkDY6yPX+AkAtZztOM7Nw6IaGU94yLN0TxsfuzqXA=; b=ICCzzPbRwQTsDldkrmty0eQwlypncRsjY/LZ6AnF9Tj9xGncFlNqpjVGOEFLu6K1tABzJJiBw cFS2eB87LWNCG5WV80R5y5xInl2JdG5ny08mfpXlxCNb895qs7n2oV0 X-Developer-Key: i=jan.petrous@oss.nxp.com; a=ed25519; pk=Ke3wwK7rb2Me9UQRf6vR8AsfJZfhTyoDaxkUCqmSWYY= X-Endpoint-Received: by B4 Relay for jan.petrous@oss.nxp.com/20240922 with auth_id=217 X-Original-From: "Jan Petrous (OSS)" Reply-To: jan.petrous@oss.nxp.com From: "Jan Petrous (OSS)" The DWMAC IP on NXP S32G/R SoCs has connected queue-based IRQ lines, set them to allow using Multi-IRQ mode when supported. Signed-off-by: Jan Petrous (OSS) Reviewed-by: Matthias Brugger --- .../devicetree/bindings/net/nxp,s32-dwmac.yaml | 42 ++++++++++++++++++= +--- 1 file changed, 37 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Doc= umentation/devicetree/bindings/net/nxp,s32-dwmac.yaml index 2b8b74c5feec..e1ebc3bea095 100644 --- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -# Copyright 2021-2024 NXP +# Copyright 2021-2026 NXP %YAML 1.2 --- $id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml# @@ -33,10 +33,22 @@ properties: - description: GMAC PHY mode control register =20 interrupts: - maxItems: 1 + minItems: 1 + maxItems: 11 =20 interrupt-names: - const: macirq + - items: + - const: macirq + - const: rx-queue-0 + - const: tx-queue-0 + - const: rx-queue-1 + - const: tx-queue-1 + - const: rx-queue-2 + - const: tx-queue-2 + - const: rx-queue-3 + - const: tx-queue-3 + - const: rx-queue-4 + - const: tx-queue-4 =20 clocks: items: @@ -75,8 +87,28 @@ examples: reg =3D <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */ <0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */ interrupt-parent =3D <&gic>; - interrupts =3D ; - interrupt-names =3D "macirq"; + interrupts =3D , + /* CHN 0: tx, rx */ + , + , + /* CHN 1: tx, rx */ + , + , + /* CHN 2: tx, rx */ + , + , + /* CHN 3: tx, rx */ + , + , + /* CHN 4: tx, rx */ + , + ; + interrupt-names =3D "macirq", + "tx-queue-0", "rx-queue-0", + "tx-queue-1", "rx-queue-1", + "tx-queue-2", "rx-queue-2", + "tx-queue-3", "rx-queue-3", + "tx-queue-4", "rx-queue-4"; snps,mtl-rx-config =3D <&mtl_rx_setup>; snps,mtl-tx-config =3D <&mtl_tx_setup>; clocks =3D <&clks 24>, <&clks 17>, <&clks 16>, <&clks 15>; --=20 2.47.0 From nobody Mon Feb 9 06:49:58 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2B9D48AE2A; Wed, 21 Jan 2026 14:23:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769005436; cv=none; b=rR5PCx24f9O08ViCoDxUuDBHY7yLrgaOZDe318fBYeXsC5j4xuibLRqwm5tqlT0D3SzCikMMSv2rIEWmx9dSX3A6Adw0V3izubJIAI0b/9xnw0PRcV5eFT25DMY5GsKFB1GziJXj6ew7dgZ/q67Yj1pn5od+YYire+WvPH1dmIM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769005436; c=relaxed/simple; bh=1G4QNoSdpDOOHQBAE/8iIqmBtuzD+hs+kX0DiVSBS5o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=m2kU59j876Z7GK+QTGmoJYmrdIceJ4n7g8k+7Tp5pGEqggpdRx9AgZN5p6k2GGe/A7wJzvc4G5mXI+E7IkAq5C0dP36Vq0070qAq6NqFTIY28kspmH+AO/iznJOAH3nLb65xhIkxbY0//typvvBtnq7j7x9vlEjvDZiwIcQEpg0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NskCwUQX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NskCwUQX" Received: by smtp.kernel.org (Postfix) with ESMTPS id 65BC8C19421; Wed, 21 Jan 2026 14:23:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769005436; bh=1G4QNoSdpDOOHQBAE/8iIqmBtuzD+hs+kX0DiVSBS5o=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=NskCwUQX+fcDyNzIMhMwl17Wu+X42rKjaW/kW+j4K3Z2mNQfD3CK2dGCEADfAycFi yZr+wAHNvhPqa3uczwPRYa2LxSgT5yGOXDe91dMQ9ukpNH5o4fU3ww4WmIQSl5J5CG ZtAPxtJzDBFwHty8mE9UJ8UFBR8g9cxkxDkuMSAZnGYH39ELywYffDmQSnNj5F/eU5 Ba8XcQrdPygXTmjTZbdbplO17CgtQRU8ohdA1AZq81ilJWFcYF7j1bUUBGB6ta9gwp +Nt50grdoP1udXcDj/9b3rZITpd8Xfh02O5OKxJKKb18U22txCTHHa7FXl630GvzU0 N9Pr1CCUphzwA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B21AC44536; Wed, 21 Jan 2026 14:23:56 +0000 (UTC) From: Jan Petrous via B4 Relay Date: Wed, 21 Jan 2026 15:23:37 +0100 Subject: [PATCH RFC v2 3/4] arm64: dts: s32: set Ethernet channel irqs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-dwmac_multi_irq-v2-3-3b829230d071@oss.nxp.com> References: <20260121-dwmac_multi_irq-v2-0-3b829230d071@oss.nxp.com> In-Reply-To: <20260121-dwmac_multi_irq-v2-0-3b829230d071@oss.nxp.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, "Jan Petrous (OSS)" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769005434; l=4112; i=jan.petrous@oss.nxp.com; s=20240922; h=from:subject:message-id; bh=QF/lW5lX77Fa01ihHWQd/U6fxIDc8LrPTzohhR75xyE=; b=XZNcB7XEbpixmd88Uz9Qqf172oLZNlYBK/BTrtEmkbD5Ds+iqRali+refQ//1Ve4RSXO1zCui ZlD5gArT6oQCZ4LESP44iFsd5/HNxOS6F101GAZXfCEWqo57wxwXHmT X-Developer-Key: i=jan.petrous@oss.nxp.com; a=ed25519; pk=Ke3wwK7rb2Me9UQRf6vR8AsfJZfhTyoDaxkUCqmSWYY= X-Endpoint-Received: by B4 Relay for jan.petrous@oss.nxp.com/20240922 with auth_id=217 X-Original-From: "Jan Petrous (OSS)" Reply-To: jan.petrous@oss.nxp.com From: "Jan Petrous (OSS)" The GMAC Ethernet controller found on S32G2/S32G3 and S32R45 contains up to 5 RX and 5 TX channels. It can operate in two interrupt modes: 1) Sharing IRQ mode: only MAC IRQ line is used for all channels. 2) Multiple IRQ mode: every channel uses two IRQ lines, one for RX and second for TX. Specify all IRQ twins for all channels. Signed-off-by: Jan Petrous (OSS) Reviewed-by: Matthias Brugger --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 26 +++++++++++++++++++++++--- arch/arm64/boot/dts/freescale/s32g3.dtsi | 26 +++++++++++++++++++++++--- 2 files changed, 46 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts= /freescale/s32g2.dtsi index 51d00dac12de..5a553d503137 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -3,7 +3,7 @@ * NXP S32G2 SoC family * * Copyright (c) 2021 SUSE LLC - * Copyright 2017-2021, 2024-2025 NXP + * Copyright 2017-2021, 2024-2026 NXP */ =20 #include @@ -732,8 +732,28 @@ gmac0: ethernet@4033c000 { reg =3D <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ interrupt-parent =3D <&gic>; - interrupts =3D ; - interrupt-names =3D "macirq"; + interrupts =3D , + /* CHN 0: tx, rx */ + , + , + /* CHN 1: tx, rx */ + , + , + /* CHN 2: tx, rx */ + , + , + /* CHN 3: tx, rx */ + , + , + /* CHN 4: tx, rx */ + , + ; + interrupt-names =3D "macirq", + "tx-queue-0", "rx-queue-0", + "tx-queue-1", "rx-queue-1", + "tx-queue-2", "rx-queue-2", + "tx-queue-3", "rx-queue-3", + "tx-queue-4", "rx-queue-4"; snps,mtl-rx-config =3D <&mtl_rx_setup>; snps,mtl-tx-config =3D <&mtl_tx_setup>; status =3D "disabled"; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts= /freescale/s32g3.dtsi index eff7673e7f34..e1f248d3aedb 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright 2021-2025 NXP + * Copyright 2021-2026 NXP * * Authors: Ghennadi Procopciuc * Ciprian Costea @@ -809,8 +809,28 @@ gmac0: ethernet@4033c000 { reg =3D <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ interrupt-parent =3D <&gic>; - interrupts =3D ; - interrupt-names =3D "macirq"; + interrupts =3D , + /* CHN 0: tx, rx */ + , + , + /* CHN 1: tx, rx */ + , + , + /* CHN 2: tx, rx */ + , + , + /* CHN 3: tx, rx */ + , + , + /* CHN 4: tx, rx */ + , + ; + interrupt-names =3D "macirq", + "tx-queue-0", "rx-queue-0", + "tx-queue-1", "rx-queue-1", + "tx-queue-2", "rx-queue-2", + "tx-queue-3", "rx-queue-3", + "tx-queue-4", "rx-queue-4"; snps,mtl-rx-config =3D <&mtl_rx_setup>; snps,mtl-tx-config =3D <&mtl_tx_setup>; status =3D "disabled"; --=20 2.47.0 From nobody Mon Feb 9 06:49:58 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2C3348AE31; Wed, 21 Jan 2026 14:23:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769005436; cv=none; b=e63M0KE4gVOkfKXVFVt55ZAYXYYVDqV1LUmFtkN5oE33yCHTILaNWZ+gms1bb0P1UhomvUsud2PRdfBUANJomfYYIjglLEh5SiwnSiruYtAk6cQM0e3JsuqrykSrMnUn0Azes6b94WyVr11pIoxUm5EjIcPo+dgqeQfIYNQJ+yI= ARC-Message-Signature: i=1; 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b=FheyfuLIziWi7CMjBus/rfzNVexMVJ7LJu+Ns9iM6aqx2jFQFierCkP2zElqOthHb 2jpUWhfrr4jiRGeWFvOOn3DsfmVklqjviI++JdLdrGZrr3w/c9jPzxh0zLX9TZ9WEi 5/5YTSHWu20XCRCBMLmM8N/cPZ9KdNmowzywRQxHVO3319AV911GzHzN00goJZWs26 /LUkKTC5g4SACH6C3QD4BqHQ9H+wRYLZPpnTayZTLnzjOK/nLZJeIj/6WsPf5Iknnj NgZPPez7vdfXg1qsWNpGH1iIyfwSAhifFO7nLcPwDB9wz3dxzl6dqRB10CoCwd+Nrm 5zcHMB1bMa91Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BB28C44502; Wed, 21 Jan 2026 14:23:56 +0000 (UTC) From: Jan Petrous via B4 Relay Date: Wed, 21 Jan 2026 15:23:38 +0100 Subject: [PATCH RFC v2 4/4] stmmac: s32: enable support for Multi-IRQ mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-dwmac_multi_irq-v2-4-3b829230d071@oss.nxp.com> References: <20260121-dwmac_multi_irq-v2-0-3b829230d071@oss.nxp.com> In-Reply-To: <20260121-dwmac_multi_irq-v2-0-3b829230d071@oss.nxp.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, "Jan Petrous (OSS)" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769005434; l=3819; i=jan.petrous@oss.nxp.com; s=20240922; h=from:subject:message-id; bh=74RGaLzoIg2YFHeU0p/CYWs0Z4X8UBwxCJa13xx0UtQ=; b=4z1wA8YyOVge2MlsBDwF1filHqTcxO5qznswuu0BITrfqUPgdk93OuCEkArMPFXgcvZlVS6AI TLRe0UhnAHxAA0luNGhNxlnDvcIPyq4Zn8SWLEgzaFIErg1hMXJJLpB X-Developer-Key: i=jan.petrous@oss.nxp.com; a=ed25519; pk=Ke3wwK7rb2Me9UQRf6vR8AsfJZfhTyoDaxkUCqmSWYY= X-Endpoint-Received: by B4 Relay for jan.petrous@oss.nxp.com/20240922 with auth_id=217 X-Original-From: "Jan Petrous (OSS)" Reply-To: jan.petrous@oss.nxp.com From: "Jan Petrous (OSS)" To get enabled Multi-IRQ mode, the driver checks: 1) property of 'snps,mtl-xx-config' subnode defines 'snps,xx-queues-to-use' bigger then one, ie: ethernet@4033c000 { compatible =3D "nxp,s32g2-dwmac"; ... snps,mtl-rx-config =3D <&mtl_rx_setup>; ... mtl_rx_setup: rx-queues-config { snps,rx-queues-to-use =3D <2>; }; 2) queue based IRQs are set, ie: ethernet@4033c000 { compatible =3D "nxp,s32g2-dwmac"; ... interrupts =3D , /* CHN 0: tx, rx */ , , /* CHN 1: tx, rx */ , ; interrupt-names =3D "macirq", "tx-queue-0", "rx-queue-0", "tx-queue-1", "rx-queue-1"; If those prerequisites are met, the driver switch to Multi-IRQ mode, using per-queue IRQs for rx/tx data pathr: [ 1.387045] s32-dwmac 4033c000.ethernet: Multi-IRQ mode (per queue IRQ) = selected Now the driver owns all queues IRQs: root@s32g399aevb3:~# grep eth /proc/interrupts 29: 0 0 0 0 0 0 0 0 GICv3 89 Level eth0:mac 30: 0 0 0 0 0 0 0 0 GICv3 91 Level eth0:rx-0 31: 0 0 0 0 0 0 0 0 GICv3 93 Level eth0:rx-1 32: 0 0 0 0 0 0 0 0 GICv3 95 Level eth0:rx-2 33: 0 0 0 0 0 0 0 0 GICv3 97 Level eth0:rx-3 34: 0 0 0 0 0 0 0 0 GICv3 99 Level eth0:rx-4 35: 0 0 0 0 0 0 0 0 GICv3 90 Level eth0:tx-0 36: 0 0 0 0 0 0 0 0 GICv3 92 Level eth0:tx-1 37: 0 0 0 0 0 0 0 0 GICv3 94 Level eth0:tx-2 38: 0 0 0 0 0 0 0 0 GICv3 96 Level eth0:tx-3 39: 0 0 0 0 0 0 0 0 GICv3 98 Level eth0:tx-4 Otherwise, if one of the prerequisite don't met, the driver continue with MAC IRQ mode: [ 1.387045] s32-dwmac 4033c000.ethernet: MAC IRQ mode selected And only MAC IRQ will be attached: root@s32g399aevb3:~# grep eth /proc/interrupts 29: 0 0 0 0 0 0 0 0 GICv3 89 Level eth0:mac What represents the original MAC IRQ mode and is fully backward compatible. Signed-off-by: Jan Petrous (OSS) Reviewed-by: Matthias Brugger --- drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c b/drivers/net/= ethernet/stmicro/stmmac/dwmac-s32.c index 5a485ee98fa7..823700219534 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c @@ -2,7 +2,7 @@ /* * NXP S32G/R GMAC glue layer * - * Copyright 2019-2024 NXP + * Copyright 2019-2026 NXP * */ =20 @@ -149,6 +149,17 @@ static int s32_dwmac_probe(struct platform_device *pde= v) plat->core_type =3D DWMAC_CORE_GMAC4; plat->pmt =3D 1; plat->flags |=3D STMMAC_FLAG_SPH_DISABLE; + + /* Check for multi-IRQ config. Assumption: symetrical rx/tx queues */ + if (plat->rx_queues_to_use > 1 && + (res.rx_irq[0] >=3D 0 || res.tx_irq[0] >=3D 0)) { + plat->flags |=3D STMMAC_FLAG_MULTI_MSI_EN; + dev_info(dev, "Multi-IRQ mode (per queue IRQ) selected\n"); + } else { + dev_info(dev, "MAC IRQ mode selected\n"); + } + + plat->flags |=3D STMMAC_FLAG_MULTI_MSI_EN; plat->rx_fifo_size =3D 20480; plat->tx_fifo_size =3D 20480; =20 --=20 2.47.0