From nobody Sun Feb 8 17:13:34 2026 Received: from sender4-op-o16.zoho.com (sender4-op-o16.zoho.com [136.143.188.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8708A322C6D; Wed, 21 Jan 2026 11:03:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.16 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768993433; cv=pass; b=hSppgHFfGpfuRJzklR1osR0AJinUHCPp0ZSRIyBRc02hwEK5g4cawEItB/or5NXb+sJBtAaSE70Y5rNuHqNeddbSCKKRGoNqpdOForUkdd8a1ebWgS2sFjzAhB2bCAu++rCp7W0OTzRo8b/fgkoh9GavVMlbAeh3UV7CJ164jys= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768993433; c=relaxed/simple; bh=FwhOWdAgFS7+1O1ZbgLX/1vXBMUsUQ0bukUjcITrw1g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mpP8UBQ00njghWUo5hUQYc75SGTB4PjHcTic0SRNe3etG+HoHv8rSFPUZ6K4ySJ2KYl+/Kz0uLaoCjnry8Pkb9xwb75nJ4hL+JVwt0lKW20FeJn5PcUah9jm3GMKM4twrfA8Gt2KP+b49tivawJmnoG3HFfGHkVwrAFY/w1e5uQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech; spf=pass smtp.mailfrom=pigmoral.tech; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b=pChYFRql; arc=pass smtp.client-ip=136.143.188.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b="pChYFRql" ARC-Seal: i=1; a=rsa-sha256; t=1768993411; cv=none; d=zohomail.com; s=zohoarc; b=jMX5cUVOd6K11rH+ruCUDSkyR1Bahv+y4wCNnUtdJtfnPzPTdHSVWp6vCtytGaNH5F8LpJsbn1sNYDRXnps7+qMmZm11LKS7/7zf4Xmo4lLCpAMVhAT06NnfXEEPV9qyxvZQKR4VT+wWqOBREXXz1v/TactnXGpxec4ZCTE3qkk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768993411; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=Wy04XAmCKMPl7NSQXKqkGhuam6Urng2cs2pZpGeZnEw=; b=U6Z2QUsbWQ/5Ia1uzbqgkG1ZjNt6uT6e9NNeGb1wbFwFp3asMqtgHfBJGcWmnhcWzqlAzWzdDKJLptrCvl5nIxGj3vaw7tRArDOoc+EVFxYynP0KRinS6ZoKxXn7PsY8rxq7lFanRLt5BL9Biqyi4FHbtfWLLyrP7RN/d4sZgPY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1768993411; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=Wy04XAmCKMPl7NSQXKqkGhuam6Urng2cs2pZpGeZnEw=; b=pChYFRqlT8PNsDosS1Hc3NkVL/6iHYsE7XTwMtI55pusKLZ2sT9w1+b4JHPuwfEk ZU31ZxS9nQY3m5WnxFZqWWW42etIQkFlTckMBIfw6niNlZpHSN5pJsNllkCNh8KjA4P 5EXAHGxJWqjM92AgA5KAvdY6cmZw1mxTo6mZmNMQ= Received: by mx.zohomail.com with SMTPS id 1768993407771767.779557047111; Wed, 21 Jan 2026 03:03:27 -0800 (PST) From: Junhui Liu Date: Wed, 21 Jan 2026 18:59:07 +0800 Subject: [PATCH 1/7] dt-bindings: rtc: sun6i: Add Allwinner A733 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-a733-rtc-v1-1-d359437f23a7@pigmoral.tech> References: <20260121-a733-rtc-v1-0-d359437f23a7@pigmoral.tech> In-Reply-To: <20260121-a733-rtc-v1-0-d359437f23a7@pigmoral.tech> To: Michael Turquette , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, Junhui Liu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768993386; l=3681; i=junhui.liu@pigmoral.tech; s=20251228; h=from:subject:message-id; bh=FwhOWdAgFS7+1O1ZbgLX/1vXBMUsUQ0bukUjcITrw1g=; b=0ke5sPzNYqFQyETLieeUmRmQylGENypMyuQeatPZiHgBSQaGCkg7KqpCR6pWwix6YSup66/g3 nQ7yVRAvF7zCq+LE3B9kfLdmj8zStNvm+WkGSSqTGOObZEmYG4XAyU4 X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=3vU0qIPJAH8blXmLyqBhKx+nLOjcLwwYhZXelEpw7h4= X-ZohoMailClient: External The RTC module in the Allwinner A733 SoC is functionally compatible with the sun6i RTC, but its internal Clock Control Unit (CCU) has significant changes. The A733 supports selecting the oscillator between three frequencies: 19.2MHz, 24MHz, and 26MHz. The RTC CCU relies on hardware to detect which frequency is actually used on the board. By defining all three frequencies as fixed-clocks in the device tree, the driver can identify the hardware-detected frequency and expose it to the rest of the system. Additionally, the A733 RTC CCU provides several new DCXO gate clocks for specific modules, including SerDes, HDMI, and UFS. Signed-off-by: Junhui Liu Reviewed-by: Rob Herring (Arm) --- .../bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 38 ++++++++++++++++++= ++-- include/dt-bindings/clock/sun60i-a733-rtc.h | 16 +++++++++ 2 files changed, 52 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.= yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml index 9df5cdb6f63f..b18431955783 100644 --- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml @@ -26,6 +26,7 @@ properties: - allwinner,sun50i-h6-rtc - allwinner,sun50i-h616-rtc - allwinner,sun50i-r329-rtc + - allwinner,sun60i-a733-rtc - items: - const: allwinner,sun50i-a64-rtc - const: allwinner,sun8i-h3-rtc @@ -46,11 +47,11 @@ properties: =20 clocks: minItems: 1 - maxItems: 4 + maxItems: 6 =20 clock-names: minItems: 1 - maxItems: 4 + maxItems: 6 =20 clock-output-names: minItems: 1 @@ -156,6 +157,38 @@ allOf: - clocks - clock-names =20 + - if: + properties: + compatible: + contains: + const: allwinner,sun60i-a733-rtc + + then: + properties: + clocks: + minItems: 5 + items: + - description: Bus clock for register access + - description: 19.2 MHz oscillator + - description: 24 MHz oscillator + - description: 26 MHz oscillator + - description: AHB parent for internal SPI clock + - description: External 32768 Hz oscillator + + clock-names: + minItems: 5 + items: + - const: bus + - const: osc19M + - const: osc24M + - const: osc26M + - const: ahb + - const: ext-osc32k + + required: + - clocks + - clock-names + - if: properties: compatible: @@ -164,6 +197,7 @@ allOf: - allwinner,sun8i-r40-rtc - allwinner,sun50i-h616-rtc - allwinner,sun50i-r329-rtc + - allwinner,sun60i-a733-rtc =20 then: properties: diff --git a/include/dt-bindings/clock/sun60i-a733-rtc.h b/include/dt-bindi= ngs/clock/sun60i-a733-rtc.h new file mode 100644 index 000000000000..8a2b5facad73 --- /dev/null +++ b/include/dt-bindings/clock/sun60i-a733-rtc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef _DT_BINDINGS_CLK_SUN60I_A733_RTC_H_ +#define _DT_BINDINGS_CLK_SUN60I_A733_RTC_H_ + +#define CLK_IOSC 0 +#define CLK_OSC32K 1 +#define CLK_HOSC 2 +#define CLK_RTC_32K 3 +#define CLK_OSC32K_FANOUT 4 +#define CLK_HOSC_SERDES1 5 +#define CLK_HOSC_SERDES0 6 +#define CLK_HOSC_HDMI 7 +#define CLK_HOSC_UFS 8 + +#endif /* _DT_BINDINGS_CLK_SUN60I_A733_RTC_H_ */ --=20 2.52.0 From nobody Sun Feb 8 17:13:34 2026 Received: from sender4-op-o16.zoho.com (sender4-op-o16.zoho.com [136.143.188.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F5F33C00B4; Wed, 21 Jan 2026 11:04:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.16 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768993447; cv=pass; b=rOEBJTsCE2xBUb/30oZsR2EkgX5p/j7V0u5Ma7UI/1nx2y2W27c1p3RFi7NF/FiMSBkrJs4Q7opt5DTyw7iPcbpan2zMpcwH9lPwyC4B5kVGcXcVZGKHR4nbGZ5t+BrxIzJTBRjMYziqgpR0KnEWY0mIHiRHQCfrKLwTOfe93mQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768993447; c=relaxed/simple; bh=XrhXYqswxIwIvROOe902KdWGRTTB1HlGHLw5IfuBL9M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OTIp4/irsHnnJiTyG3ihZi2VVG9vT2MgBWcNDMJ1qr8bhoxt5EVjoqwidqMPdJ2cXNakjcs7bY+NAE7uKZ8ysN+ayCE7pCA5GjrefBgQmDlVQpirHQIKAv4Rc1zdfNN8G5ompxOXKwZUXH2jDLmkFynj8I/3huB8nPHk8ydlnM4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech; spf=pass smtp.mailfrom=pigmoral.tech; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b=Oh4tjiMt; arc=pass smtp.client-ip=136.143.188.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b="Oh4tjiMt" ARC-Seal: i=1; a=rsa-sha256; t=1768993427; cv=none; d=zohomail.com; s=zohoarc; b=X8xcatVEFgI3WgDr7sY8+YugmN0FU4LiK2KvwBNEVyG2OAi4OrVm0tE0EHoyaRPvVgwiw/m/p2sM+DVnwIslpO5nkODrPlPP92zQRaxRLIwoEY+iK1Ixsh5X7ss7ZlDyuoG4QE9MeGKDFdhzouHN14MdTBE8Wgg9Nc2mTDzRSug= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768993427; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=PvHOvd99B0k7tzuarHMyRWVeaES9UJpKYnUM8t+KeLA=; b=Y7ob6IWjXSLFUCkPGic3DXfrinTPsDGtrNc5AmT6MYtJfBzn4qIcfE/CTAyY6p1I724lASU8hjDYStPwF2vHssa3CSJ+m+aJZcJZtTJ5Z3zvKjngJP8WWg/vnSE4YQBmSATSvYoooCJlJpUvo5bIQTLK0oUsTpU96UaQRkntn+Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1768993427; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=PvHOvd99B0k7tzuarHMyRWVeaES9UJpKYnUM8t+KeLA=; b=Oh4tjiMt3dNTcDzTwbnYI9QL1WdjCyMlXmKtB638z1RwwNpCimLkDP4OgSPEw5BT ABdLLK9PdSraqyZPg91BMyrQ9ebhXYfk6odUcLmqS7f9gpRyeddwi789yL2ZScIBs0o JXXBC2xFP5EA1WijPVL5B13HiezrI1dWu7fy9+3U= Received: by mx.zohomail.com with SMTPS id 1768993424817370.07718841329984; Wed, 21 Jan 2026 03:03:44 -0800 (PST) From: Junhui Liu Date: Wed, 21 Jan 2026 18:59:08 +0800 Subject: [PATCH 2/7] rtc: sun6i: Bind internal CCU via auxiliary bus Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-a733-rtc-v1-2-d359437f23a7@pigmoral.tech> References: <20260121-a733-rtc-v1-0-d359437f23a7@pigmoral.tech> In-Reply-To: <20260121-a733-rtc-v1-0-d359437f23a7@pigmoral.tech> To: Michael Turquette , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, Junhui Liu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768993386; l=6782; i=junhui.liu@pigmoral.tech; s=20251228; h=from:subject:message-id; bh=XrhXYqswxIwIvROOe902KdWGRTTB1HlGHLw5IfuBL9M=; b=79FxhVb8WHnaGsdnfzjPoMgq5oPS7LsgpMPXplBqQ4erQG4lEvglmFrRtYZqZMkgcMopkxuj9 6hXDNVB3STDDGA/6p1WI5oyKVyQhQxGuNx+p1lMrafR6s3V8TR6GSs/ X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=3vU0qIPJAH8blXmLyqBhKx+nLOjcLwwYhZXelEpw7h4= X-ZohoMailClient: External The sun6i RTC block contains an internal clock control unit (CCU). Currently, the RTC driver binds this CCU part by directly calling a probe function exported by the clock framework. This creates a tight coupling between the RTC and clock drivers and makes it difficult to add internal CCU support for new SoCs. Switch to use the auxiliary bus for binding the internal CCU to decouple the drivers. Signed-off-by: Junhui Liu --- drivers/clk/sunxi-ng/ccu-sun6i-rtc.c | 29 +++++++++++++++++++++++------ drivers/rtc/rtc-sun6i.c | 31 +++++++++++++++++++++++-------- include/linux/clk/sunxi-ng.h | 2 -- 3 files changed, 46 insertions(+), 16 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c b/drivers/clk/sunxi-ng/cc= u-sun6i-rtc.c index f6bfeba009e8..3088f247d927 100644 --- a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c +++ b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c @@ -3,6 +3,7 @@ // Copyright (c) 2021 Samuel Holland // =20 +#include #include #include #include @@ -11,8 +12,6 @@ #include #include =20 -#include - #include "ccu_common.h" =20 #include "ccu_div.h" @@ -44,6 +43,8 @@ #define DCXO_CTRL_REG 0x160 #define DCXO_CTRL_CLK16M_RC_EN BIT(0) =20 +#define SUN6I_RTC_AUX_ID(_name) "rtc_sun6i." #_name + struct sun6i_rtc_match_data { bool have_ext_osc32k : 1; bool have_iosc_calibration : 1; @@ -349,14 +350,18 @@ static const struct of_device_id sun6i_rtc_ccu_match[= ] =3D { }; MODULE_DEVICE_TABLE(of, sun6i_rtc_ccu_match); =20 -int sun6i_rtc_ccu_probe(struct device *dev, void __iomem *reg) +static int sun6i_rtc_ccu_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) { const struct sun6i_rtc_match_data *data; struct clk *ext_osc32k_clk =3D NULL; const struct of_device_id *match; + struct device *dev =3D &adev->dev; + void __iomem *reg =3D dev->platform_data; + struct device *parent =3D dev->parent; =20 /* This driver is only used for newer variants of the hardware. */ - match =3D of_match_device(sun6i_rtc_ccu_match, dev); + match =3D of_match_device(sun6i_rtc_ccu_match, parent); if (!match) return 0; =20 @@ -367,9 +372,9 @@ int sun6i_rtc_ccu_probe(struct device *dev, void __iome= m *reg) const char *fw_name; =20 /* ext-osc32k was the only input clock in the old binding. */ - fw_name =3D of_property_present(dev->of_node, "clock-names") + fw_name =3D of_property_present(parent->of_node, "clock-names") ? "ext-osc32k" : NULL; - ext_osc32k_clk =3D devm_clk_get_optional(dev, fw_name); + ext_osc32k_clk =3D devm_clk_get_optional(parent, fw_name); if (IS_ERR(ext_osc32k_clk)) return PTR_ERR(ext_osc32k_clk); } @@ -392,6 +397,18 @@ int sun6i_rtc_ccu_probe(struct device *dev, void __iom= em *reg) return devm_sunxi_ccu_probe(dev, reg, &sun6i_rtc_ccu_desc); } =20 +static const struct auxiliary_device_id sun6i_ccu_rtc_ids[] =3D { + { .name =3D SUN6I_RTC_AUX_ID(sun6i) }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(auxiliary, sun6i_ccu_rtc_ids); + +static struct auxiliary_driver sun6i_ccu_rtc_driver =3D { + .probe =3D sun6i_rtc_ccu_probe, + .id_table =3D sun6i_ccu_rtc_ids, +}; +module_auxiliary_driver(sun6i_ccu_rtc_driver); + MODULE_IMPORT_NS("SUNXI_CCU"); MODULE_DESCRIPTION("Support for the Allwinner H616/R329 RTC CCU"); MODULE_LICENSE("GPL"); diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c index e5e6013d080e..b4489e0a09ce 100644 --- a/drivers/rtc/rtc-sun6i.c +++ b/drivers/rtc/rtc-sun6i.c @@ -11,9 +11,9 @@ * Copyright (c) 2013, Carlo Caione */ =20 +#include #include #include -#include #include #include #include @@ -141,6 +141,11 @@ struct sun6i_rtc_clk_data { =20 #define RTC_LINEAR_DAY BIT(0) =20 +struct sun6i_rtc_match_data { + const char *adev_name; + unsigned long flags; +}; + struct sun6i_rtc_dev { struct rtc_device *rtc; const struct sun6i_rtc_clk_data *data; @@ -745,8 +750,10 @@ static void sun6i_rtc_bus_clk_cleanup(void *data) =20 static int sun6i_rtc_probe(struct platform_device *pdev) { + const struct sun6i_rtc_match_data *data; struct sun6i_rtc_dev *chip =3D sun6i_rtc; struct device *dev =3D &pdev->dev; + struct auxiliary_device *adev; struct clk *bus_clk; int ret; =20 @@ -765,6 +772,8 @@ static int sun6i_rtc_probe(struct platform_device *pdev) return ret; } =20 + data =3D of_device_get_match_data(&pdev->dev); + if (!chip) { chip =3D devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); if (!chip) @@ -776,16 +785,17 @@ static int sun6i_rtc_probe(struct platform_device *pd= ev) if (IS_ERR(chip->base)) return PTR_ERR(chip->base); =20 - if (IS_REACHABLE(CONFIG_SUN6I_RTC_CCU)) { - ret =3D sun6i_rtc_ccu_probe(dev, chip->base); - if (ret) - return ret; + if (data && data->adev_name) { + adev =3D devm_auxiliary_device_create(dev, data->adev_name, chip->base); + if (!adev) + return -ENODEV; } } =20 platform_set_drvdata(pdev, chip); =20 - chip->flags =3D (unsigned long)of_device_get_match_data(&pdev->dev); + if (data) + chip->flags =3D data->flags; =20 chip->irq =3D platform_get_irq(pdev, 0); if (chip->irq < 0) @@ -850,6 +860,11 @@ static int sun6i_rtc_probe(struct platform_device *pde= v) return 0; } =20 +static const struct sun6i_rtc_match_data sun6i_rtc_match_data =3D { + .adev_name =3D "sun6i", + .flags =3D RTC_LINEAR_DAY, +}; + /* * As far as RTC functionality goes, all models are the same. The * datasheets claim that different models have different number of @@ -865,9 +880,9 @@ static const struct of_device_id sun6i_rtc_dt_ids[] =3D= { { .compatible =3D "allwinner,sun50i-h5-rtc" }, { .compatible =3D "allwinner,sun50i-h6-rtc" }, { .compatible =3D "allwinner,sun50i-h616-rtc", - .data =3D (void *)RTC_LINEAR_DAY }, + .data =3D &sun6i_rtc_match_data }, { .compatible =3D "allwinner,sun50i-r329-rtc", - .data =3D (void *)RTC_LINEAR_DAY }, + .data =3D &sun6i_rtc_match_data }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids); diff --git a/include/linux/clk/sunxi-ng.h b/include/linux/clk/sunxi-ng.h index 57c8ec44ab4e..cf32123b39f5 100644 --- a/include/linux/clk/sunxi-ng.h +++ b/include/linux/clk/sunxi-ng.h @@ -9,6 +9,4 @@ int sunxi_ccu_set_mmc_timing_mode(struct clk *clk, bool new_mode); int sunxi_ccu_get_mmc_timing_mode(struct clk *clk); =20 -int sun6i_rtc_ccu_probe(struct device *dev, void __iomem *reg); - #endif --=20 2.52.0 From nobody Sun Feb 8 17:13:34 2026 Received: from sender4-op-o16.zoho.com (sender4-op-o16.zoho.com [136.143.188.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A4F638B7B8; Wed, 21 Jan 2026 11:04:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.16 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768993464; cv=pass; b=eWf5vkcaS1GG9FSdJrnqBTideFtTb007fqDWBHlJBQxQLCKdmt+b+lrYInjgpfrHrEHgnPlvpIhkPv4ebDIQGEq05d55ouhk/0qJ/Bt26K/RukOTj7lpsYqmbX3po38/xvRBrfGG1tLgk1Rttj/5Ac2Qo+oMpGKo8AwwL94e7wY= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768993464; c=relaxed/simple; bh=EaZwUZOL/6KRK5E3haLUyKQNLv0B7SELQtluH9yrJLU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=az07kmLIIF7WwLa+Y+sROg9t/6cybFSQfw5Rtryzi+HTG0KwMlb3iiS7WXEFAiWyBdNqvEZsajVRaOuSRCtkva+bwrbnWKTQDA2cWVvjXj4eyeVK2AIzfIJtrdP3W4Ecd1VZzfj1cacglMicXkDPu0lnLx8xPvYQMCvD+zPFGzo= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech; spf=pass smtp.mailfrom=pigmoral.tech; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b=TgZjJLE+; arc=pass smtp.client-ip=136.143.188.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b="TgZjJLE+" ARC-Seal: i=1; a=rsa-sha256; t=1768993443; cv=none; d=zohomail.com; s=zohoarc; b=iDTfN+GYmWGpF1sSZ11lnR14TiFZh3OC/Ih137nMp+2sefu85bBNBwzzDbiFNG8yoXOJoWAZSXyxlPIxpMCcfx7uloVHPnJwAruq2ltCeWN3Nz1KEjm1Z4k9MTKFDASaRf4dVQq5UdFNCAkcuWvM/BddIewSoGBcwI1vRLzkzCI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768993443; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=Q9xJi6VAHCUEzm3dN054EmcisgXFfpIHGR5lwkOb/cw=; b=Ca78poVEBiD+NghCzY024n0Gv3UYAjMHSAWWfc/+i4W38Rpued1SsOqXx1Tl3w9J4pLuT46KQGvSN+i7gGkbm1hePKWX+NJKy24h+dsRvfFmAOPVmXquxqS/RHHDI3Rcy9R0sFKXQWR1kNDqCJ35XTjuAyrZ8IuDxfBTmJidy8E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1768993443; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=Q9xJi6VAHCUEzm3dN054EmcisgXFfpIHGR5lwkOb/cw=; b=TgZjJLE+/3LfqohAS1g2WUBUaPANu6Boa3mjmtk1FrjvQlXjMxrB29QNHs3y+71N NEMROp13HrdHf9vnuQHEotkvK74UfKweRhU8uykp2y17Gf02Wq+x73sEP/hOB0PiK3l uSWtvZ/fK5vNBPWeur3uS8OkaKHaa2CSSwwoKnUI= Received: by mx.zohomail.com with SMTPS id 1768993442305964.352987418435; Wed, 21 Jan 2026 03:04:02 -0800 (PST) From: Junhui Liu Date: Wed, 21 Jan 2026 18:59:09 +0800 Subject: [PATCH 3/7] clk: sunxi-ng: sun6i-rtc: Add feature bit for IOSC calibration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-a733-rtc-v1-3-d359437f23a7@pigmoral.tech> References: <20260121-a733-rtc-v1-0-d359437f23a7@pigmoral.tech> In-Reply-To: <20260121-a733-rtc-v1-0-d359437f23a7@pigmoral.tech> To: Michael Turquette , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, Junhui Liu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768993386; l=3422; i=junhui.liu@pigmoral.tech; s=20251228; h=from:subject:message-id; bh=EaZwUZOL/6KRK5E3haLUyKQNLv0B7SELQtluH9yrJLU=; b=UOl1J6qZ2N2m3kr+ssXubB+UY59HWZGQsOMSAIyLazGm1HLOdoP/dR/8xP4BC17QNEHm6JzQ6 NTr7syE0uSxBbQsuBFT80Y6HLE/5dwOBOzNIwmT0u96arwwE7OQLsKN X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=3vU0qIPJAH8blXmLyqBhKx+nLOjcLwwYhZXelEpw7h4= X-ZohoMailClient: External The sun6i-rtc CCU driver currently uses a global static variable to denote whether calibration is supported, which makes IOSC operations tightly coupled to this file. Convert this into a feature bit to decouple the logic. This allows the IOSC clock code to be moved into a shared module for reuse by other SoCs. Signed-off-by: Junhui Liu --- drivers/clk/sunxi-ng/ccu-sun6i-rtc.c | 17 +++++++++-------- drivers/clk/sunxi-ng/ccu_common.h | 1 + 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c b/drivers/clk/sunxi-ng/cc= u-sun6i-rtc.c index 3088f247d927..6f888169412c 100644 --- a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c +++ b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c @@ -53,8 +53,6 @@ struct sun6i_rtc_match_data { u8 osc32k_fanout_nparents; }; =20 -static bool have_iosc_calibration; - static int ccu_iosc_enable(struct clk_hw *hw) { struct ccu_common *cm =3D hw_to_ccu_common(hw); @@ -81,7 +79,7 @@ static unsigned long ccu_iosc_recalc_rate(struct clk_hw *= hw, { struct ccu_common *cm =3D hw_to_ccu_common(hw); =20 - if (have_iosc_calibration) { + if (cm->features & CCU_FEATURE_IOSC_CALIBRATION) { u32 reg =3D readl(cm->base + IOSC_CLK_CALI_REG); =20 /* @@ -120,7 +118,7 @@ static int ccu_iosc_32k_prepare(struct clk_hw *hw) struct ccu_common *cm =3D hw_to_ccu_common(hw); u32 val; =20 - if (!have_iosc_calibration) + if (!(cm->features & CCU_FEATURE_IOSC_CALIBRATION)) return 0; =20 val =3D readl(cm->base + IOSC_CLK_CALI_REG); @@ -135,7 +133,7 @@ static void ccu_iosc_32k_unprepare(struct clk_hw *hw) struct ccu_common *cm =3D hw_to_ccu_common(hw); u32 val; =20 - if (!have_iosc_calibration) + if (!(cm->features & CCU_FEATURE_IOSC_CALIBRATION)) return; =20 val =3D readl(cm->base + IOSC_CLK_CALI_REG); @@ -149,7 +147,7 @@ static unsigned long ccu_iosc_32k_recalc_rate(struct cl= k_hw *hw, struct ccu_common *cm =3D hw_to_ccu_common(hw); u32 val; =20 - if (have_iosc_calibration) { + if (cm->features & CCU_FEATURE_IOSC_CALIBRATION) { val =3D readl(cm->base + IOSC_CLK_CALI_REG); =20 /* Assume the calibrated 32k clock is accurate. */ @@ -168,7 +166,7 @@ static unsigned long ccu_iosc_32k_recalc_accuracy(struc= t clk_hw *hw, struct ccu_common *cm =3D hw_to_ccu_common(hw); u32 val; =20 - if (have_iosc_calibration) { + if (cm->features & CCU_FEATURE_IOSC_CALIBRATION) { val =3D readl(cm->base + IOSC_CLK_CALI_REG); =20 /* Assume the calibrated 32k clock is accurate. */ @@ -366,7 +364,10 @@ static int sun6i_rtc_ccu_probe(struct auxiliary_device= *adev, return 0; =20 data =3D match->data; - have_iosc_calibration =3D data->have_iosc_calibration; + if (data->have_iosc_calibration) { + iosc_clk.features |=3D CCU_FEATURE_IOSC_CALIBRATION; + iosc_32k_clk.features |=3D CCU_FEATURE_IOSC_CALIBRATION; + } =20 if (data->have_ext_osc32k) { const char *fw_name; diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-ng/ccu_c= ommon.h index bbec283b9d99..d9dc24ad5503 100644 --- a/drivers/clk/sunxi-ng/ccu_common.h +++ b/drivers/clk/sunxi-ng/ccu_common.h @@ -21,6 +21,7 @@ #define CCU_FEATURE_CLOSEST_RATE BIT(9) #define CCU_FEATURE_DUAL_DIV BIT(10) #define CCU_FEATURE_UPDATE_BIT BIT(11) +#define CCU_FEATURE_IOSC_CALIBRATION BIT(12) =20 /* MMC timing mode switch bit */ #define CCU_MMC_NEW_TIMING_MODE BIT(30) --=20 2.52.0 From nobody Sun Feb 8 17:13:34 2026 Received: from sender4-op-o16.zoho.com (sender4-op-o16.zoho.com [136.143.188.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26F5B396B94; Wed, 21 Jan 2026 11:04:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.16 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768993481; cv=pass; b=FKnuDJR+acYs8T6bv960pXVmS+Vq8p8r7m48wfJfCubQB+Ips4vrx/o0G4xhDnYY6EZXWs24wr68wKr1vRNZz1OycaGr9G7ktt6WTeGe4oJ8ETs6Xs2L6u7bmF1yMZG0EVOreeF5vdVhXW4M+kyLDc2yaQNbI6kqZNced4AEfHY= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768993481; c=relaxed/simple; bh=bhCaIAht/co8lZYVs9DHT3cS4FdFKeAxhuztNHtGFjI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tfiNfLokcECM7ziElXmRT2JhEY1OaG/b2p9DlxbLsTSxFbtTMmwqyF115DRvjSgv6g8TsEth83WTT+o5DDFLPD+7k/Y1uGu9LrEeec8tLopFx9zdilGgH6imiwEIm4KdA+y0IGhQJHUCJ8eVomRl1kUalOhFwb0qL5L8aeEmtvw= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech; spf=pass smtp.mailfrom=pigmoral.tech; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b=OJATXfY1; arc=pass smtp.client-ip=136.143.188.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b="OJATXfY1" ARC-Seal: i=1; a=rsa-sha256; t=1768993457; cv=none; d=zohomail.com; s=zohoarc; b=nBMfEg+OrdU1PPnnF9xDo9EjQ6DU6IYBBTdp06f4d5U8lJ9/9Nt6bbYiEPYoQ6nUFmZIwYmdV0iEsP5pVU48yKs7/bBOdn4tjthFKcj8JGExMMMSU6gyguKZdckvCzQJ1CeSVs1J91atjhWYtm5WHuEe8egjNQQ+vsf5gadtzms= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768993457; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=+fF0XjaNHARVRqmcYLQANfY/8iC+KZIfurQnVod+Mvk=; b=liwi9V2Fl9WqHSyb5Jfp4T776Se99R37em4wLWEVFAeA41Dlh3WX7FHYfYPsQhhg3vvLcdOChE5/h3Ilrjy+sYlVabGxEOBOhLOjzAXs7n8q9iCG0cqH6PQ0+IETN9Z6UprlISw02VuUb/eAmEdrwxTrKxpw3TNdukCVKIWFIa4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1768993457; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=+fF0XjaNHARVRqmcYLQANfY/8iC+KZIfurQnVod+Mvk=; b=OJATXfY1eSHN85Fjf7GdVCvVG7SS8YD3LTZ+zbvnyiXm4MA910byLk3hT26JcbdH XRP3IDbCQZsw5iWqNHbFsxzaofzCsIN8ZAelpbYLkC9rHaDaF8WWOqbGaCcpHbdMQiy sQpweecHhPaFavHHe06Z00Be7oyxijtGF4sX6jK8= Received: by mx.zohomail.com with SMTPS id 1768993455150886.2521745289004; Wed, 21 Jan 2026 03:04:15 -0800 (PST) From: Junhui Liu Date: Wed, 21 Jan 2026 18:59:10 +0800 Subject: [PATCH 4/7] clk: sunxi-ng: Extract common RTC CCU clock logic Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-a733-rtc-v1-4-d359437f23a7@pigmoral.tech> References: <20260121-a733-rtc-v1-0-d359437f23a7@pigmoral.tech> In-Reply-To: <20260121-a733-rtc-v1-0-d359437f23a7@pigmoral.tech> To: Michael Turquette , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, Junhui Liu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768993386; l=10958; i=junhui.liu@pigmoral.tech; s=20251228; h=from:subject:message-id; bh=bhCaIAht/co8lZYVs9DHT3cS4FdFKeAxhuztNHtGFjI=; b=eDTPf/PRUkhj9sCH/yyKm5xgbPPLRHtmynqmDhTCfxglTpMIb2gSLcO9THWZ7CZR0RDu39aH8 XpELLgI581sDgwsNydcSH2bLUaQQ7SGf11u8gKWXIhXkXG/XB3Hc+sJ X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=3vU0qIPJAH8blXmLyqBhKx+nLOjcLwwYhZXelEpw7h4= X-ZohoMailClient: External Extract the IOSC and 32k clock logic from ccu-sun6i-rtc into a shared module to simplify adding RTC CCU support for new SoCs. This is needed because newer Allwinner SoCs introduce additional DCXO/HOSC logic that prevents direct reuse of the existing driver. Signed-off-by: Junhui Liu --- drivers/clk/sunxi-ng/Makefile | 3 + drivers/clk/sunxi-ng/ccu-sun6i-rtc.c | 152 +------------------------------= ---- drivers/clk/sunxi-ng/ccu_rtc.c | 136 +++++++++++++++++++++++++++++++ drivers/clk/sunxi-ng/ccu_rtc.h | 37 +++++++++ 4 files changed, 177 insertions(+), 151 deletions(-) diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index a1c4087d7241..c3f810a025a8 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -23,6 +23,9 @@ sunxi-ccu-y +=3D ccu_nkmp.o sunxi-ccu-y +=3D ccu_nm.o sunxi-ccu-y +=3D ccu_mp.o =20 +# RTC clocks +sunxi-ccu-y +=3D ccu_rtc.o + # SoC support obj-$(CONFIG_SUNIV_F1C100S_CCU) +=3D suniv-f1c100s-ccu.o obj-$(CONFIG_SUN20I_D1_CCU) +=3D sun20i-d1-ccu.o diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c b/drivers/clk/sunxi-ng/cc= u-sun6i-rtc.c index 6f888169412c..562ba752bcec 100644 --- a/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c +++ b/drivers/clk/sunxi-ng/ccu-sun6i-rtc.c @@ -14,37 +14,12 @@ =20 #include "ccu_common.h" =20 -#include "ccu_div.h" #include "ccu_gate.h" #include "ccu_mux.h" +#include "ccu_rtc.h" =20 #include "ccu-sun6i-rtc.h" =20 -#define IOSC_ACCURACY 300000000 /* 30% */ -#define IOSC_RATE 16000000 - -#define LOSC_RATE 32768 -#define LOSC_RATE_SHIFT 15 - -#define LOSC_CTRL_REG 0x0 -#define LOSC_CTRL_KEY 0x16aa0000 - -#define IOSC_32K_CLK_DIV_REG 0x8 -#define IOSC_32K_CLK_DIV GENMASK(4, 0) -#define IOSC_32K_PRE_DIV 32 - -#define IOSC_CLK_CALI_REG 0xc -#define IOSC_CLK_CALI_DIV_ONES 22 -#define IOSC_CLK_CALI_EN BIT(1) -#define IOSC_CLK_CALI_SRC_SEL BIT(0) - -#define LOSC_OUT_GATING_REG 0x60 - -#define DCXO_CTRL_REG 0x160 -#define DCXO_CTRL_CLK16M_RC_EN BIT(0) - -#define SUN6I_RTC_AUX_ID(_name) "rtc_sun6i." #_name - struct sun6i_rtc_match_data { bool have_ext_osc32k : 1; bool have_iosc_calibration : 1; @@ -53,137 +28,12 @@ struct sun6i_rtc_match_data { u8 osc32k_fanout_nparents; }; =20 -static int ccu_iosc_enable(struct clk_hw *hw) -{ - struct ccu_common *cm =3D hw_to_ccu_common(hw); - - return ccu_gate_helper_enable(cm, DCXO_CTRL_CLK16M_RC_EN); -} - -static void ccu_iosc_disable(struct clk_hw *hw) -{ - struct ccu_common *cm =3D hw_to_ccu_common(hw); - - return ccu_gate_helper_disable(cm, DCXO_CTRL_CLK16M_RC_EN); -} - -static int ccu_iosc_is_enabled(struct clk_hw *hw) -{ - struct ccu_common *cm =3D hw_to_ccu_common(hw); - - return ccu_gate_helper_is_enabled(cm, DCXO_CTRL_CLK16M_RC_EN); -} - -static unsigned long ccu_iosc_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct ccu_common *cm =3D hw_to_ccu_common(hw); - - if (cm->features & CCU_FEATURE_IOSC_CALIBRATION) { - u32 reg =3D readl(cm->base + IOSC_CLK_CALI_REG); - - /* - * Recover the IOSC frequency by shifting the ones place of - * (fixed-point divider * 32768) into bit zero. - */ - if (reg & IOSC_CLK_CALI_EN) - return reg >> (IOSC_CLK_CALI_DIV_ONES - LOSC_RATE_SHIFT); - } - - return IOSC_RATE; -} - -static unsigned long ccu_iosc_recalc_accuracy(struct clk_hw *hw, - unsigned long parent_accuracy) -{ - return IOSC_ACCURACY; -} - -static const struct clk_ops ccu_iosc_ops =3D { - .enable =3D ccu_iosc_enable, - .disable =3D ccu_iosc_disable, - .is_enabled =3D ccu_iosc_is_enabled, - .recalc_rate =3D ccu_iosc_recalc_rate, - .recalc_accuracy =3D ccu_iosc_recalc_accuracy, -}; - static struct ccu_common iosc_clk =3D { .reg =3D DCXO_CTRL_REG, .hw.init =3D CLK_HW_INIT_NO_PARENT("iosc", &ccu_iosc_ops, CLK_GET_RATE_NOCACHE), }; =20 -static int ccu_iosc_32k_prepare(struct clk_hw *hw) -{ - struct ccu_common *cm =3D hw_to_ccu_common(hw); - u32 val; - - if (!(cm->features & CCU_FEATURE_IOSC_CALIBRATION)) - return 0; - - val =3D readl(cm->base + IOSC_CLK_CALI_REG); - writel(val | IOSC_CLK_CALI_EN | IOSC_CLK_CALI_SRC_SEL, - cm->base + IOSC_CLK_CALI_REG); - - return 0; -} - -static void ccu_iosc_32k_unprepare(struct clk_hw *hw) -{ - struct ccu_common *cm =3D hw_to_ccu_common(hw); - u32 val; - - if (!(cm->features & CCU_FEATURE_IOSC_CALIBRATION)) - return; - - val =3D readl(cm->base + IOSC_CLK_CALI_REG); - writel(val & ~(IOSC_CLK_CALI_EN | IOSC_CLK_CALI_SRC_SEL), - cm->base + IOSC_CLK_CALI_REG); -} - -static unsigned long ccu_iosc_32k_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct ccu_common *cm =3D hw_to_ccu_common(hw); - u32 val; - - if (cm->features & CCU_FEATURE_IOSC_CALIBRATION) { - val =3D readl(cm->base + IOSC_CLK_CALI_REG); - - /* Assume the calibrated 32k clock is accurate. */ - if (val & IOSC_CLK_CALI_SRC_SEL) - return LOSC_RATE; - } - - val =3D readl(cm->base + IOSC_32K_CLK_DIV_REG) & IOSC_32K_CLK_DIV; - - return parent_rate / IOSC_32K_PRE_DIV / (val + 1); -} - -static unsigned long ccu_iosc_32k_recalc_accuracy(struct clk_hw *hw, - unsigned long parent_accuracy) -{ - struct ccu_common *cm =3D hw_to_ccu_common(hw); - u32 val; - - if (cm->features & CCU_FEATURE_IOSC_CALIBRATION) { - val =3D readl(cm->base + IOSC_CLK_CALI_REG); - - /* Assume the calibrated 32k clock is accurate. */ - if (val & IOSC_CLK_CALI_SRC_SEL) - return 0; - } - - return parent_accuracy; -} - -static const struct clk_ops ccu_iosc_32k_ops =3D { - .prepare =3D ccu_iosc_32k_prepare, - .unprepare =3D ccu_iosc_32k_unprepare, - .recalc_rate =3D ccu_iosc_32k_recalc_rate, - .recalc_accuracy =3D ccu_iosc_32k_recalc_accuracy, -}; - static struct ccu_common iosc_32k_clk =3D { .hw.init =3D CLK_HW_INIT_HW("iosc-32k", &iosc_clk.hw, &ccu_iosc_32k_ops, diff --git a/drivers/clk/sunxi-ng/ccu_rtc.c b/drivers/clk/sunxi-ng/ccu_rtc.c new file mode 100644 index 000000000000..cfc10218517c --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu_rtc.c @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 Samuel Holland + */ + +#include +#include + +#include "ccu_common.h" + +#include "ccu_gate.h" +#include "ccu_rtc.h" + +static int ccu_iosc_enable(struct clk_hw *hw) +{ + struct ccu_common *cm =3D hw_to_ccu_common(hw); + + return ccu_gate_helper_enable(cm, DCXO_CTRL_CLK16M_RC_EN); +} + +static void ccu_iosc_disable(struct clk_hw *hw) +{ + struct ccu_common *cm =3D hw_to_ccu_common(hw); + + return ccu_gate_helper_disable(cm, DCXO_CTRL_CLK16M_RC_EN); +} + +static int ccu_iosc_is_enabled(struct clk_hw *hw) +{ + struct ccu_common *cm =3D hw_to_ccu_common(hw); + + return ccu_gate_helper_is_enabled(cm, DCXO_CTRL_CLK16M_RC_EN); +} + +static unsigned long ccu_iosc_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ccu_common *cm =3D hw_to_ccu_common(hw); + + if (cm->features & CCU_FEATURE_IOSC_CALIBRATION) { + u32 reg =3D readl(cm->base + IOSC_CLK_CALI_REG); + /* + * Recover the IOSC frequency by shifting the ones place of + * (fixed-point divider * 32768) into bit zero. + */ + if (reg & IOSC_CLK_CALI_EN) + return reg >> (IOSC_CLK_CALI_DIV_ONES - LOSC_RATE_SHIFT); + } + + return IOSC_RATE; +} + +static unsigned long ccu_iosc_recalc_accuracy(struct clk_hw *hw, + unsigned long parent_accuracy) +{ + return IOSC_ACCURACY; +} + +const struct clk_ops ccu_iosc_ops =3D { + .enable =3D ccu_iosc_enable, + .disable =3D ccu_iosc_disable, + .is_enabled =3D ccu_iosc_is_enabled, + .recalc_rate =3D ccu_iosc_recalc_rate, + .recalc_accuracy =3D ccu_iosc_recalc_accuracy, +}; + +static int ccu_iosc_32k_prepare(struct clk_hw *hw) +{ + struct ccu_common *cm =3D hw_to_ccu_common(hw); + u32 val; + + if (!(cm->features & CCU_FEATURE_IOSC_CALIBRATION)) + return 0; + + val =3D readl(cm->base + IOSC_CLK_CALI_REG); + writel(val | IOSC_CLK_CALI_EN | IOSC_CLK_CALI_SRC_SEL, + cm->base + IOSC_CLK_CALI_REG); + + return 0; +} + +static void ccu_iosc_32k_unprepare(struct clk_hw *hw) +{ + struct ccu_common *cm =3D hw_to_ccu_common(hw); + u32 val; + + if (!(cm->features & CCU_FEATURE_IOSC_CALIBRATION)) + return; + + val =3D readl(cm->base + IOSC_CLK_CALI_REG); + writel(val & ~(IOSC_CLK_CALI_EN | IOSC_CLK_CALI_SRC_SEL), + cm->base + IOSC_CLK_CALI_REG); +} + +static unsigned long ccu_iosc_32k_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ccu_common *cm =3D hw_to_ccu_common(hw); + u32 val; + + if (cm->features & CCU_FEATURE_IOSC_CALIBRATION) { + val =3D readl(cm->base + IOSC_CLK_CALI_REG); + + /* Assume the calibrated 32k clock is accurate. */ + if (val & IOSC_CLK_CALI_SRC_SEL) + return LOSC_RATE; + } + + val =3D readl(cm->base + IOSC_32K_CLK_DIV_REG) & IOSC_32K_CLK_DIV; + + return parent_rate / IOSC_32K_PRE_DIV / (val + 1); +} + +static unsigned long ccu_iosc_32k_recalc_accuracy(struct clk_hw *hw, + unsigned long parent_accuracy) +{ + struct ccu_common *cm =3D hw_to_ccu_common(hw); + u32 val; + + if (cm->features & CCU_FEATURE_IOSC_CALIBRATION) { + val =3D readl(cm->base + IOSC_CLK_CALI_REG); + + /* Assume the calibrated 32k clock is accurate. */ + if (val & IOSC_CLK_CALI_SRC_SEL) + return 0; + } + + return parent_accuracy; +} + +const struct clk_ops ccu_iosc_32k_ops =3D { + .prepare =3D ccu_iosc_32k_prepare, + .unprepare =3D ccu_iosc_32k_unprepare, + .recalc_rate =3D ccu_iosc_32k_recalc_rate, + .recalc_accuracy =3D ccu_iosc_32k_recalc_accuracy, +}; diff --git a/drivers/clk/sunxi-ng/ccu_rtc.h b/drivers/clk/sunxi-ng/ccu_rtc.h new file mode 100644 index 000000000000..1c44c2206a25 --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu_rtc.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 Samuel Holland + */ + +#ifndef _CCU_RTC_H_ +#define _CCU_RTC_H_ + +#define IOSC_ACCURACY 300000000 /* 30% */ +#define IOSC_RATE 16000000 + +#define LOSC_RATE 32768 +#define LOSC_RATE_SHIFT 15 + +#define LOSC_CTRL_REG 0x0 +#define LOSC_CTRL_KEY 0x16aa0000 + +#define IOSC_32K_CLK_DIV_REG 0x8 +#define IOSC_32K_CLK_DIV GENMASK(4, 0) +#define IOSC_32K_PRE_DIV 32 + +#define IOSC_CLK_CALI_REG 0xc +#define IOSC_CLK_CALI_DIV_ONES 22 +#define IOSC_CLK_CALI_EN BIT(1) +#define IOSC_CLK_CALI_SRC_SEL BIT(0) + +#define LOSC_OUT_GATING_REG 0x60 + +#define DCXO_CTRL_REG 0x160 +#define DCXO_CTRL_CLK16M_RC_EN BIT(0) + +#define SUN6I_RTC_AUX_ID(_name) "rtc_sun6i." #_name + +extern const struct clk_ops ccu_iosc_ops; +extern const struct clk_ops ccu_iosc_32k_ops; + +#endif /* _CCU_RTC_H_ */ --=20 2.52.0 From nobody Sun Feb 8 17:13:34 2026 Received: from sender4-op-o16.zoho.com (sender4-op-o16.zoho.com [136.143.188.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB09A466B4B; Wed, 21 Jan 2026 11:04:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.16 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768993485; cv=pass; b=P9ygdLa/U8iN0LKNfS8bCNd6Panik0uBbblJes+O/mjNVZ+MJZwJCwM3DQXsz/ilBUv6beRETYfx92v6kkmuMUVOHAdkMXK3AC7G12ZPPrc50G1zFP84C+0yQO6H6is4sMyxglBCoXU87hpHR2Jxk6FHbIAiDhIgxnIIWqln5+g= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768993485; c=relaxed/simple; bh=yie5eDb9BUEl0Aid6eA7yIm0Tl3wT/Y7FXEWcLOUikU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GMhnXK/Rrofe8FgaKSrLQ+vlvCtFLbkW/StfokOxP0YjB1HSnzAwCTIaarr3fG35cYS2vrnf8pVXT7b0WIU7zrK8UiJFiZFiys44EBHPcfMLmhHkgKogvSuQwisvv4810qxgbvOFbjBvL5wc12pzIXqo68X3m9ceJk3QVkEkiHM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech; spf=pass smtp.mailfrom=pigmoral.tech; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b=ZLE+eB6r; arc=pass smtp.client-ip=136.143.188.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b="ZLE+eB6r" ARC-Seal: i=1; a=rsa-sha256; t=1768993466; cv=none; d=zohomail.com; s=zohoarc; b=eb3hiUC5Koqr6vPcmvWzPJdUAk915tMpGc9bHh6mTEzVZkdNkI31Kcb+a+cCH5VnoYmKFQIwzhMb0b1Dio0W7MDZFwVU1OlmBR6phV+BJRTQ0utXykSc8s9eprViyX1tSDUrkPqaeOkrT0QqYyb7B6S8HyURO7yhiuh7lQoge6E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768993466; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=RJub5ZPZsJzcOi4zRa+ExZyiUH46huzX/t4vX9Ke4aw=; b=La7j1YqmWwPHritPc1rW6d/gW2BBoLpO4JJYoav6aSKBh1omjZ4y4uQeLAUgXtBoU+9MQXqpxw8veqsAOe+Zi6quU3R7uYasONH6y8PKKrrFqbc8Pkzln5PUE7AWVGUsLBBXZnejcw/zZ3yvoumWJqEuIMxOP6vUZlW/liUilTI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1768993466; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=RJub5ZPZsJzcOi4zRa+ExZyiUH46huzX/t4vX9Ke4aw=; b=ZLE+eB6rErOyEkMgFBto2im1xQ1ZOrIIEN34eLu/sMWlIkv2VW5LwlIj5xzxTMMp +I3O7gh+WN7qfM92e2T+qc5HoIGZ2V+GYb4wz6CG14JooRAdyFVBNv0ltE/NR+n7H1m 0y2fSfg/P2MYgqKb/mi197s87zrNNAss3Xqzu5W8= Received: by mx.zohomail.com with SMTPS id 1768993464430169.99826292706462; Wed, 21 Jan 2026 03:04:24 -0800 (PST) From: Junhui Liu Date: Wed, 21 Jan 2026 18:59:11 +0800 Subject: [PATCH 5/7] clk: sunxi-ng: mux: Add mux read-only clock operations Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-a733-rtc-v1-5-d359437f23a7@pigmoral.tech> References: <20260121-a733-rtc-v1-0-d359437f23a7@pigmoral.tech> In-Reply-To: <20260121-a733-rtc-v1-0-d359437f23a7@pigmoral.tech> To: Michael Turquette , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, Junhui Liu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768993386; l=1825; i=junhui.liu@pigmoral.tech; s=20251228; h=from:subject:message-id; bh=yie5eDb9BUEl0Aid6eA7yIm0Tl3wT/Y7FXEWcLOUikU=; b=9BCMuiNZQfMjro/P67t39fZX/nmh4DdJ8jFx/n3oo2WozsR3OdLUMu9+Ny/e+pHwGOx4vg8F3 MQI2nQiRjoaBkyMIgonRuwoTrp3vuKfvUKFUaHVZ6FdvzaIXv7d+5eW X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=3vU0qIPJAH8blXmLyqBhKx+nLOjcLwwYhZXelEpw7h4= X-ZohoMailClient: External The Allwinner A733 SoC introduces some mux clocks (such as the one indicating the DCXO frequency) that use read-only registers to report their current hardware configuration. Writing to these registers is not supported by hardware and should be avoided. Add ccu_mux_ro_ops to support these clocks, which omit .set_parent() and .determine_rate() to prevent changing the mux state. Signed-off-by: Junhui Liu --- drivers/clk/sunxi-ng/ccu_mux.c | 11 +++++++++++ drivers/clk/sunxi-ng/ccu_mux.h | 1 + 2 files changed, 12 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c index 74f9e98a5d35..d48e7c3e065d 100644 --- a/drivers/clk/sunxi-ng/ccu_mux.c +++ b/drivers/clk/sunxi-ng/ccu_mux.c @@ -277,6 +277,17 @@ const struct clk_ops ccu_mux_ops =3D { }; EXPORT_SYMBOL_NS_GPL(ccu_mux_ops, "SUNXI_CCU"); =20 +const struct clk_ops ccu_mux_ro_ops =3D { + .disable =3D ccu_mux_disable, + .enable =3D ccu_mux_enable, + .is_enabled =3D ccu_mux_is_enabled, + + .get_parent =3D ccu_mux_get_parent, + + .recalc_rate =3D ccu_mux_recalc_rate, +}; +EXPORT_SYMBOL_NS_GPL(ccu_mux_ro_ops, "SUNXI_CCU"); + /* * This clock notifier is called when the frequency of the of the parent * PLL clock is to be changed. The idea is to switch the parent to a diff --git a/drivers/clk/sunxi-ng/ccu_mux.h b/drivers/clk/sunxi-ng/ccu_mux.h index eb1172ebbd94..887c164d00f4 100644 --- a/drivers/clk/sunxi-ng/ccu_mux.h +++ b/drivers/clk/sunxi-ng/ccu_mux.h @@ -129,6 +129,7 @@ static inline struct ccu_mux *hw_to_ccu_mux(struct clk_= hw *hw) } =20 extern const struct clk_ops ccu_mux_ops; +extern const struct clk_ops ccu_mux_ro_ops; =20 unsigned long ccu_mux_helper_apply_prediv(struct ccu_common *common, struct ccu_mux_internal *cm, --=20 2.52.0 From nobody Sun Feb 8 17:13:34 2026 Received: from sender4-op-o16.zoho.com (sender4-op-o16.zoho.com [136.143.188.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4EF447D920; Wed, 21 Jan 2026 11:04:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.16 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768993496; cv=pass; b=qmbx0UAlAn+MkcbLOJ7t75U2y9ssvCdRZCYgwshPoFqv9GOaZ/tHn5D+WTyJeqiRMWitKyNatBGhKd3u9qM1SQ4nonxDHPJ8hSnjBwWL9zvPNFOPE+KJK0+A8YCyzeJlSaaITRkfrnZncBfcbX+gQ9rhA/F8hx1KPvVSr3U6Fdw= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768993496; c=relaxed/simple; bh=SE3KCwAGdCuYIMUpUjVkwvvnkVL1syEZpjMdM6ORN2A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mkQIlkD5SBdngA46iN/QVZXzJb9eaKaYPBcb3RLyeVkI+x+1YyMcHIIoW0tRyJSNunHpyptfwMMW6BVjRoqcvAfVJREhU5cti/PQ0ngY8W/CHN9KeDf66GTHrNNvvzQ9taNc1TWC+n/MKJyqRZj2q0JdHS3JnaiUhPrxlznITOQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech; spf=pass smtp.mailfrom=pigmoral.tech; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b=mSkMXvzM; arc=pass smtp.client-ip=136.143.188.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b="mSkMXvzM" ARC-Seal: i=1; a=rsa-sha256; t=1768993480; cv=none; d=zohomail.com; s=zohoarc; b=U33vu7XTEIYnxNSHVFZUqS2pG/Gpyc9ErTZRdQLff9Xht602lfg0z5pnw4AwyTkfMH39KPa8XqTyaShouSI8MlhyjUrI6pmd6GiIA4MQRWh1c8Pax22LofyS0lBct5C1yoZcER08mgUfKwIt8pDh3rF+z9sbfiy+rqhuGbevnZ8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768993480; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=NBVXFEdaRJcEH9atfPBKtguvTBweusReAnDHX35/2Us=; b=e8FiM8Qtqsc5GJaw51cbBqeiYu0yl9Kpn9RhUdnS1XCGuiwxVpLQwrmT2sVQH/P2mrhJ7WZKLpaEN9Ijl6Nq7j1gSeQSLXkj0KKHvI9UxUJ6noNAxcMeiramPnQGUXGdzzx9etGE/xQ6hwslpayu9wv2fpuBJfktLza0I/4PrGI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1768993480; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=NBVXFEdaRJcEH9atfPBKtguvTBweusReAnDHX35/2Us=; b=mSkMXvzMKCUW3GyUCnc2/eZsmCaLWZf/Ww5TJbnZgJ23hrYvwssYnitkEdSLBY1S h7n6E77YIwfPMhexn9zfkVJMtfruCD9ya373pjlmnxpOuvR0WjdttUgGWBljHhLKTJx 6/C8eugEkdhRzsUicjMjQ646Y6a72nEXz2PSQkOU= Received: by mx.zohomail.com with SMTPS id 1768993478453725.0311405076129; Wed, 21 Jan 2026 03:04:38 -0800 (PST) From: Junhui Liu Date: Wed, 21 Jan 2026 18:59:12 +0800 Subject: [PATCH 6/7] rtc: sun6i: Add support for A733 RTC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-a733-rtc-v1-6-d359437f23a7@pigmoral.tech> References: <20260121-a733-rtc-v1-0-d359437f23a7@pigmoral.tech> In-Reply-To: <20260121-a733-rtc-v1-0-d359437f23a7@pigmoral.tech> To: Michael Turquette , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, Junhui Liu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768993386; l=1343; i=junhui.liu@pigmoral.tech; s=20251228; h=from:subject:message-id; bh=SE3KCwAGdCuYIMUpUjVkwvvnkVL1syEZpjMdM6ORN2A=; b=+oew59MDiDNmLqVNHNSZRel5WMMQ8wzQ4Ax7fokTiWUGO5MTiRDxhQyHSanz6R7PE3FDXKsE1 V56D26wPYD8AlSwWH93Pq9IG7p9gktp+y/S18aav2ViWHcDX693hM8v X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=3vU0qIPJAH8blXmLyqBhKx+nLOjcLwwYhZXelEpw7h4= X-ZohoMailClient: External The RTC in the Allwinner A733 SoC is compatible with the H616 in terms of its time storage and alarm functionality. However, its internal CCU is different, with additional DCXO handling logic. Add new match data to register a new auxiliary device for its CCU part. Signed-off-by: Junhui Liu --- drivers/rtc/rtc-sun6i.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c index b4489e0a09ce..a58d9c6b917c 100644 --- a/drivers/rtc/rtc-sun6i.c +++ b/drivers/rtc/rtc-sun6i.c @@ -865,6 +865,11 @@ static const struct sun6i_rtc_match_data sun6i_rtc_mat= ch_data =3D { .flags =3D RTC_LINEAR_DAY, }; =20 +static const struct sun6i_rtc_match_data sun60i_rtc_match_data =3D { + .adev_name =3D "sun60i", + .flags =3D RTC_LINEAR_DAY, +}; + /* * As far as RTC functionality goes, all models are the same. The * datasheets claim that different models have different number of @@ -883,6 +888,8 @@ static const struct of_device_id sun6i_rtc_dt_ids[] =3D= { .data =3D &sun6i_rtc_match_data }, { .compatible =3D "allwinner,sun50i-r329-rtc", .data =3D &sun6i_rtc_match_data }, + { .compatible =3D "allwinner,sun60i-a733-rtc", + .data =3D &sun60i_rtc_match_data }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids); --=20 2.52.0 From nobody Sun Feb 8 17:13:34 2026 Received: from sender4-op-o16.zoho.com (sender4-op-o16.zoho.com [136.143.188.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 114F247ECCB; Wed, 21 Jan 2026 11:05:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.16 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768993510; cv=pass; b=UWV3f3bhTyassX3N+SY1ZM4SLOn+BzFCSJFpX5OwIv3zK7OqEuoOgWyN8WnSPNmujpudsRriemfOslhIVl8ULsihueiLQS5/t3ipKs2r3YINTrW62WHxB6qJBnRVjBD87d/2O8abZjcn9KSn8QpDM+Yu2Wq4rrORFmRXvMhQ59E= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768993510; c=relaxed/simple; bh=XzyKX1iXhjH/xe6SwbPUU2TPiS68z964fkgnLa/Ll7U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=h59/JSmMs+UzQwbtPYmfUPW+P69GyorHc73+GjmWxYedeuXMqbK9ti/jr/CSPl82g40+QdToHlk5+H0gikIbX/mo4M/BTG5XO5phh5OkgjsKPCDjsFasBli0ZD3mryUqQ3lOwtZh5L6Z33rPTP+YLoVXUJ9nm19QnxkW0t8Shnw= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech; spf=pass smtp.mailfrom=pigmoral.tech; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b=VwcMeXZs; arc=pass smtp.client-ip=136.143.188.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b="VwcMeXZs" ARC-Seal: i=1; a=rsa-sha256; t=1768993490; cv=none; d=zohomail.com; s=zohoarc; b=CnmSDABxcOhHqfA89YMjM7rS8TBHbSfyJtkC0E2Ocxunxj81oT5Mznny52K1c3/HWQ1hYkV3LhIoOKxSqBXNpJOdJ29zat1+HPf5mhtt7SbE2ok93TR4YnIg/oSFp0pI7ICcrcdoK/eBE2fCKkRnVAWmvj3QsSSrf/WuRAlgHcI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768993490; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=c+vBV4VT1dMjsTAU9tsfPgC8rjnBjBQSGpwb/wpSV2s=; b=npwVALibQKN7qOrX1A002P2CXw+xmBWvEDswr6yxXYApGVbH+NwmAusZcDCSeapkh6kKBBkQXqfSASeNAJsfSAQaeohqOWlzCGVR9EbPrvG9hQvDCRhVOF2XHLNZH7zgkLLmx8o45Hu7btXlZP/pzFhNFQZodcScSVOusPG35Lw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1768993490; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=c+vBV4VT1dMjsTAU9tsfPgC8rjnBjBQSGpwb/wpSV2s=; b=VwcMeXZs8A2M9bULzdko8GAaqWCwf+mUEITdtkXoVVqqJ+A5pVUTDkkPkBJE0wQZ TZdJrcLTqxo41HD7j6oGYIb/DkaAoFLYQNJlnm+vbn1DKdF4GuqOOYr4dCgcDOiuxuY SgehDodgCmb4wvVOjdMyI+OPkgbjhq8JJ8hDjN4k= Received: by mx.zohomail.com with SMTPS id 1768993486830785.6868370776832; Wed, 21 Jan 2026 03:04:46 -0800 (PST) From: Junhui Liu Date: Wed, 21 Jan 2026 18:59:13 +0800 Subject: [PATCH 7/7] clk: sunxi-ng: Add Allwinner A733 RTC CCU support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260121-a733-rtc-v1-7-d359437f23a7@pigmoral.tech> References: <20260121-a733-rtc-v1-0-d359437f23a7@pigmoral.tech> In-Reply-To: <20260121-a733-rtc-v1-0-d359437f23a7@pigmoral.tech> To: Michael Turquette , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, Junhui Liu X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768993386; l=10406; i=junhui.liu@pigmoral.tech; s=20251228; h=from:subject:message-id; bh=XzyKX1iXhjH/xe6SwbPUU2TPiS68z964fkgnLa/Ll7U=; b=b3o2BSCLMzB6Z0pr+Id6k3NBkfOa2eF/19I1MilbZG3CXD9a9RyaTnEkxci/Tc9KoV401PqlJ 43O28YMPUdjBktQNZ+pnuzGTdv0Vd+zXnkhvII5PThTjnoTTTwFRW1a X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=3vU0qIPJAH8blXmLyqBhKx+nLOjcLwwYhZXelEpw7h4= X-ZohoMailClient: External Add support for the internal CCU found in the RTC module of the Allwinner A733 SoC. While the basic 16MHz (IOSC) and 32kHz logic remains compatible with older SoCs like the sun6i, the A733 introduces several new features. The A733 RTC CCU supports choosing one of three external crystal frequencies: 19.2MHz, 24MHz, and 26MHz. It features hardware detection logic to automatically identify the frequency used on the board and exports this DCXO signal as the "hosc" clock. Furthermore, the driver implements logic to derive a 32kHz reference from the HOSC. This is achieved through a muxed clock path using fixed pre-dividers to normalize the different crystal frequencies to ~32kHz. This path reuses the same hardware mux registers as the HOSC clock. Additionally, this CCU provides several gate clocks for specific peripherals, including SerDes, HDMI, and UFS. The driver is implemented as an auxiliary driver to be bound to the sun6i-rtc driver. Signed-off-by: Junhui Liu --- drivers/clk/sunxi-ng/Kconfig | 5 + drivers/clk/sunxi-ng/Makefile | 2 + drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.c | 204 +++++++++++++++++++++++++= ++++ drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.h | 18 +++ drivers/clk/sunxi-ng/ccu_rtc.h | 7 + 5 files changed, 236 insertions(+) diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 6af2d020e03e..16afbf249f26 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -67,6 +67,11 @@ config SUN55I_A523_R_CCU default ARCH_SUNXI depends on ARM64 || COMPILE_TEST =20 +config SUN60I_A733_RTC_CCU + tristate "Support for the Allwinner A733 RTC CCU" + default ARCH_SUNXI + depends on ARM64 || COMPILE_TEST + config SUN4I_A10_CCU tristate "Support for the Allwinner A10/A20 CCU" default ARCH_SUNXI diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index c3f810a025a8..b0d823440c33 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_SUN50I_H616_CCU) +=3D sun50i-h616-ccu.o obj-$(CONFIG_SUN55I_A523_CCU) +=3D sun55i-a523-ccu.o obj-$(CONFIG_SUN55I_A523_MCU_CCU) +=3D sun55i-a523-mcu-ccu.o obj-$(CONFIG_SUN55I_A523_R_CCU) +=3D sun55i-a523-r-ccu.o +obj-$(CONFIG_SUN60I_A733_RTC_CCU) +=3D sun60i-a733-rtc-ccu.o obj-$(CONFIG_SUN4I_A10_CCU) +=3D sun4i-a10-ccu.o obj-$(CONFIG_SUN5I_CCU) +=3D sun5i-ccu.o obj-$(CONFIG_SUN6I_A31_CCU) +=3D sun6i-a31-ccu.o @@ -67,6 +68,7 @@ sun50i-h616-ccu-y +=3D ccu-sun50i-h616.o sun55i-a523-ccu-y +=3D ccu-sun55i-a523.o sun55i-a523-mcu-ccu-y +=3D ccu-sun55i-a523-mcu.o sun55i-a523-r-ccu-y +=3D ccu-sun55i-a523-r.o +sun60i-a733-rtc-ccu-y +=3D ccu-sun60i-a733-rtc.o sun4i-a10-ccu-y +=3D ccu-sun4i-a10.o sun5i-ccu-y +=3D ccu-sun5i.o sun6i-a31-ccu-y +=3D ccu-sun6i-a31.o diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.c b/drivers/clk/sunxi= -ng/ccu-sun60i-a733-rtc.c new file mode 100644 index 000000000000..d17aceffa16e --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.c @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 Junhui Liu + */ + +#include +#include +#include +#include +#include + +#include "ccu_common.h" + +#include "ccu_gate.h" +#include "ccu_mux.h" +#include "ccu_rtc.h" + +#include "ccu-sun60i-a733-rtc.h" + +static struct ccu_common iosc_clk =3D { + .reg =3D DCXO_CTRL_REG, + .features =3D CCU_FEATURE_IOSC_CALIBRATION, + .hw.init =3D CLK_HW_INIT_NO_PARENT("iosc", &ccu_iosc_ops, + CLK_GET_RATE_NOCACHE), +}; + +static struct ccu_common iosc_32k_clk =3D { + .features =3D CCU_FEATURE_IOSC_CALIBRATION, + .hw.init =3D CLK_HW_INIT_HW("iosc-32k", &iosc_clk.hw, + &ccu_iosc_32k_ops, + CLK_GET_RATE_NOCACHE), +}; + +static SUNXI_CCU_GATE_FW(ext_osc32k_gate_clk, "ext-osc32k-gate", + "ext-osc32k", 0x0, BIT(4), 0); + +static const struct clk_hw *osc32k_parents[] =3D { + &iosc_32k_clk.hw, + &ext_osc32k_gate_clk.common.hw, +}; + +static struct ccu_mux osc32k_clk =3D { + .mux =3D _SUNXI_CCU_MUX(0, 1), + .common =3D { + .reg =3D LOSC_CTRL_REG, + .features =3D CCU_FEATURE_KEY_FIELD, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("osc32k", + osc32k_parents, + &ccu_mux_ops, + 0), + }, +}; + +static const struct clk_parent_data hosc_parents[] =3D { + { .fw_name =3D "osc24M" }, + { .fw_name =3D "osc19M" }, + { .fw_name =3D "osc26M" }, + { .fw_name =3D "osc24M" }, +}; + +struct ccu_mux hosc_clk =3D { + .enable =3D DCXO_CTRL_DCXO_EN, + .mux =3D _SUNXI_CCU_MUX(14, 2), + .common =3D { + .reg =3D DCXO_CTRL_REG, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("hosc", + hosc_parents, + &ccu_mux_ro_ops, + 0), + }, +}; + +static const struct ccu_mux_fixed_prediv hosc_32k_predivs[] =3D { + { .index =3D 0, .div =3D 732 }, + { .index =3D 1, .div =3D 586 }, + { .index =3D 2, .div =3D 793 }, + { .index =3D 3, .div =3D 732 }, +}; + +static struct ccu_mux hosc_32k_mux_clk =3D { + .enable =3D DCXO_CTRL_DCXO_EN, + .mux =3D { + .shift =3D 14, + .width =3D 2, + .fixed_predivs =3D hosc_32k_predivs, + .n_predivs =3D ARRAY_SIZE(hosc_32k_predivs), + }, + .common =3D { + .reg =3D DCXO_CTRL_REG, + .features =3D CCU_FEATURE_FIXED_PREDIV, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("hosc-32k-mux", + hosc_parents, + &ccu_mux_ro_ops, + 0), + }, +}; + +static SUNXI_CCU_GATE_HW(hosc_32k_clk, "hosc-32k", &hosc_32k_mux_clk.commo= n.hw, + LOSC_OUT_GATING_REG, BIT(16), 0); + +static const struct clk_hw *rtc_32k_parents[] =3D { + &osc32k_clk.common.hw, + &hosc_32k_clk.common.hw, +}; + +static struct ccu_mux rtc_32k_clk =3D { + .mux =3D _SUNXI_CCU_MUX(1, 1), + .common =3D { + .reg =3D LOSC_CTRL_REG, + .features =3D CCU_FEATURE_KEY_FIELD, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("rtc-32k", + rtc_32k_parents, + &ccu_mux_ops, + 0), + }, +}; + +static const struct clk_parent_data osc32k_fanout_parents[] =3D { + { .hw =3D &osc32k_clk.common.hw }, + { .hw =3D &ext_osc32k_gate_clk.common.hw }, + { .hw =3D &hosc_32k_clk.common.hw }, +}; + +static SUNXI_CCU_MUX_DATA_WITH_GATE(osc32k_fanout_clk, "osc32k-fanout", os= c32k_fanout_parents, + LOSC_OUT_GATING_REG, + 1, 2, /* mux */ + BIT(0), /* gate */ + 0); + +static SUNXI_CCU_GATE_HW(hosc_serdes1_clk, "hosc-serdes1", &hosc_clk.commo= n.hw, + DCXO_GATING_REG, DCXO_SERDES1_GATING, 0); +static SUNXI_CCU_GATE_HW(hosc_serdes0_clk, "hosc-serdes0", &hosc_clk.commo= n.hw, + DCXO_GATING_REG, DCXO_SERDES0_GATING, 0); +static SUNXI_CCU_GATE_HW(hosc_hdmi_clk, "hosc-hdmi", &hosc_clk.common.hw, + DCXO_GATING_REG, DCXO_HDMI_GATING, 0); +static SUNXI_CCU_GATE_HW(hosc_ufs_clk, "hosc-ufs", &hosc_clk.common.hw, + DCXO_GATING_REG, DCXO_UFS_GATING, 0); + +static struct ccu_common *sun60i_rtc_ccu_clks[] =3D { + &iosc_clk, + &iosc_32k_clk, + &ext_osc32k_gate_clk.common, + &osc32k_clk.common, + &hosc_clk.common, + &hosc_32k_mux_clk.common, + &hosc_32k_clk.common, + &rtc_32k_clk.common, + &osc32k_fanout_clk.common, + &hosc_serdes1_clk.common, + &hosc_serdes0_clk.common, + &hosc_hdmi_clk.common, + &hosc_ufs_clk.common, +}; + +static struct clk_hw_onecell_data sun60i_rtc_ccu_hw_clks =3D { + .num =3D CLK_NUMBER, + .hws =3D { + [CLK_IOSC] =3D &iosc_clk.hw, + [CLK_OSC32K] =3D &osc32k_clk.common.hw, + [CLK_HOSC] =3D &hosc_clk.common.hw, + [CLK_RTC_32K] =3D &rtc_32k_clk.common.hw, + [CLK_OSC32K_FANOUT] =3D &osc32k_fanout_clk.common.hw, + [CLK_HOSC_SERDES1] =3D &hosc_serdes1_clk.common.hw, + [CLK_HOSC_SERDES0] =3D &hosc_serdes0_clk.common.hw, + [CLK_HOSC_HDMI] =3D &hosc_hdmi_clk.common.hw, + [CLK_HOSC_UFS] =3D &hosc_ufs_clk.common.hw, + [CLK_IOSC_32K] =3D &iosc_32k_clk.hw, + [CLK_EXT_OSC32K_GATE] =3D &ext_osc32k_gate_clk.common.hw, + [CLK_HOSC_32K_MUX] =3D &hosc_32k_mux_clk.common.hw, + [CLK_HOSC_32K] =3D &hosc_32k_clk.common.hw, + }, +}; + +static const struct sunxi_ccu_desc sun60i_rtc_ccu_desc =3D { + .ccu_clks =3D sun60i_rtc_ccu_clks, + .num_ccu_clks =3D ARRAY_SIZE(sun60i_rtc_ccu_clks), + + .hw_clks =3D &sun60i_rtc_ccu_hw_clks, +}; + +static int sun60i_rtc_ccu_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct device *dev =3D &adev->dev; + void __iomem *reg =3D dev->platform_data; + + return devm_sunxi_ccu_probe(dev, reg, &sun60i_rtc_ccu_desc); +} + +static const struct auxiliary_device_id sun60i_ccu_rtc_ids[] =3D { + { .name =3D SUN6I_RTC_AUX_ID(sun60i) }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(auxiliary, sun60i_ccu_rtc_ids); + +static struct auxiliary_driver sun60i_ccu_rtc_driver =3D { + .probe =3D sun60i_rtc_ccu_probe, + .id_table =3D sun60i_ccu_rtc_ids, +}; +module_auxiliary_driver(sun60i_ccu_rtc_driver); + +MODULE_IMPORT_NS("SUNXI_CCU"); +MODULE_DESCRIPTION("Support for the Allwinner A733 RTC CCU"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.h b/drivers/clk/sunxi= -ng/ccu-sun60i-a733-rtc.h new file mode 100644 index 000000000000..41ec6195b5e7 --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733-rtc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 Junhui Liu + */ + +#ifndef _CCU_SUN60I_A733_RTC_H_ +#define _CCU_SUN60I_A733_RTC_H_ + +#include + +#define CLK_IOSC_32K 9 +#define CLK_EXT_OSC32K_GATE 10 +#define CLK_HOSC_32K_MUX 11 +#define CLK_HOSC_32K 12 + +#define CLK_NUMBER (CLK_HOSC_32K + 1) + +#endif /* _CCU_SUN60I_A733_RTC_H_ */ diff --git a/drivers/clk/sunxi-ng/ccu_rtc.h b/drivers/clk/sunxi-ng/ccu_rtc.h index 1c44c2206a25..665162723796 100644 --- a/drivers/clk/sunxi-ng/ccu_rtc.h +++ b/drivers/clk/sunxi-ng/ccu_rtc.h @@ -27,8 +27,15 @@ #define LOSC_OUT_GATING_REG 0x60 =20 #define DCXO_CTRL_REG 0x160 +#define DCXO_CTRL_DCXO_EN BIT(1) #define DCXO_CTRL_CLK16M_RC_EN BIT(0) =20 +#define DCXO_GATING_REG 0x16c +#define DCXO_SERDES1_GATING BIT(5) +#define DCXO_SERDES0_GATING BIT(4) +#define DCXO_HDMI_GATING BIT(1) +#define DCXO_UFS_GATING BIT(0) + #define SUN6I_RTC_AUX_ID(_name) "rtc_sun6i." #_name =20 extern const struct clk_ops ccu_iosc_ops; --=20 2.52.0