From nobody Mon Feb 9 03:45:47 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 461913D3311; Tue, 20 Jan 2026 23:49:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768952974; cv=none; b=ElrEoiGV4FsDwP90WtVVleXelRM4vU/akOhcbIGvE/dizKuRGcZxUbYIANxK6xE0gQAGq6JO4I4rAhlqlr1AvxmqxUC95Iv2eX+fuOhx77I22j4KVtoy7Eu404YJyTDvknvgAv99GEZU0HtZ1nUQ9KjErZdTaF0qGrsZ6aImwzc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768952974; c=relaxed/simple; bh=tr5aqXtXqDIqs/AOyqWvJ4kVK8DQjii3mFT06ss72IY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HhwXHLJY2ET/C28NKOhDJoHXvCDnnzdQgo/CmpgyfPYESCOk02WDRbRo2fk4+Rkd+qXYbBEoIgCjSOh2LTru3ks9T804jCSmK5h7ede9f/muW7M+gDx6Cd/7RS7+/wgXnTMHOPpMkPaTFPr7T45US+2iwOsbcEXyEiDWMQjCOuw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=KSf2NYIo; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="KSf2NYIo" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768952972; x=1800488972; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tr5aqXtXqDIqs/AOyqWvJ4kVK8DQjii3mFT06ss72IY=; b=KSf2NYIoDvg2rwjGVg9Ldy+i76AXobt5BzAviqwaq2OzSRo73t1fgkwL +HAPieS13Xi0U9zUAXeHJWOaFmgU6GX45CmwB1+q13vuaHFlHYLrIou53 dPfXy/LLGVQ4Me+uECGKGPmChy7oxCqGCO2Ex/1Sd1idPBbW6PsGow+fD qgHcABEPG7DOJvzkLDTZL4VACLL1LOArIGYjoQbFdEofCZpT/ioHBBC8E 7GXYUa7ijVQQO26vwzKk1xYB3MF/ZpGTsxybx7awbdfhrstr/4aCQHJF6 jRlNWEeQ4TRgwT6ynIhDXSg0J7LcbnkgXGG1C+EXOBjF1Yi35l4mZ/zgV g==; X-CSE-ConnectionGUID: oECmQO4KSN6sHOJw6dEb1w== X-CSE-MsgGUID: jBVJevYORBeyDs/ef6Lfdg== X-IronPort-AV: E=McAfee;i="6800,10657,11677"; a="87752958" X-IronPort-AV: E=Sophos;i="6.21,241,1763452800"; d="scan'208";a="87752958" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2026 15:49:31 -0800 X-CSE-ConnectionGUID: BiVEscOqRI2FUHD8Tc5RpQ== X-CSE-MsgGUID: 1HeeOkkzQOCYPiSIpNC7Rg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,241,1763452800"; d="scan'208";a="236932647" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by orviesa002.jf.intel.com with ESMTP; 20 Jan 2026 15:49:30 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Ard Biesheuvel Cc: "H . Peter Anvin" , Andy Lutomirski , Peter Zijlstra , "Kirill A . Shutemov" , Sohil Mehta , Rick Edgecombe , Andrew Cooper , Tony Luck , Alexander Shishkin , linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org Subject: [PATCH v2 2/3] x86/efi: Disable LASS while executing runtime services Date: Tue, 20 Jan 2026 15:47:29 -0800 Message-ID: <20260120234730.2215498-3-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120234730.2215498-1-sohil.mehta@intel.com> References: <20260120234730.2215498-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Ideally, EFI runtime services should switch to kernel virtual addresses after SetVirtualAddressMap(). However, firmware implementations are known to be buggy in this regard and continue to access physical addresses. The kernel maintains a 1:1 mapping of all runtime services code and data regions to avoid breaking such firmware. LASS enforcement relies on bit 63 of the virtual address, which would block such accesses to the lower half. Unfortunately, not doing anything could lead to #GP faults when users update to a kernel with LASS enabled. One option is to use a STAC/CLAC pair to temporarily disable LASS data enforcement. However, there is no guarantee that the stray accesses would only touch data and not perform instruction fetches. Also, relying on the AC bit would depend on the runtime calls preserving RFLAGS, which is highly unlikely in practice. Instead, use the big hammer and switch off the entire LASS mechanism temporarily by clearing CR4.LASS. Runtime services are called in the context of efi_mm, which has explicitly unmapped any memory EFI isn't allowed to touch (including userspace). So, do this right after switching to efi_mm to avoid any security impact. Some runtime services can be invoked during boot when LASS isn't active. Use a global variable (similar to efi_mm) to save and restore the correct CR4.LASS state. The runtime calls are serialized with the efi_runtime_lock, so no concurrency issues are expected. Signed-off-by: Sohil Mehta --- v2: - Improve commit message and code comments. --- arch/x86/platform/efi/efi_64.c | 35 ++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/x86/platform/efi/efi_64.c b/arch/x86/platform/efi/efi_64.c index b4409df2105a..5861008eab22 100644 --- a/arch/x86/platform/efi/efi_64.c +++ b/arch/x86/platform/efi/efi_64.c @@ -55,6 +55,7 @@ */ static u64 efi_va =3D EFI_VA_START; static struct mm_struct *efi_prev_mm; +static unsigned long efi_cr4_lass; =20 /* * We need our own copy of the higher levels of the page tables @@ -443,16 +444,50 @@ static void efi_leave_mm(void) unuse_temporary_mm(efi_prev_mm); } =20 +/* + * Toggle LASS to allow EFI to access any 1:1 mapped region in the lower + * half. + * + * Disable LASS only after switching to EFI-mm, as userspace is not + * mapped in it. Similar to EFI-mm, these rely on preemption being + * disabled and the calls being serialized. + */ + +static void efi_disable_lass(void) +{ + if (!cpu_feature_enabled(X86_FEATURE_LASS)) + return; + + lockdep_assert_preemption_disabled(); + + /* Save current CR4.LASS state */ + efi_cr4_lass =3D cr4_read_shadow() & X86_CR4_LASS; + cr4_clear_bits(efi_cr4_lass); +} + +static void efi_enable_lass(void) +{ + if (!cpu_feature_enabled(X86_FEATURE_LASS)) + return; + + lockdep_assert_preemption_disabled(); + + /* Reprogram CR4.LASS only if it was set earlier */ + cr4_set_bits(efi_cr4_lass); +} + void arch_efi_call_virt_setup(void) { efi_sync_low_kernel_mappings(); efi_fpu_begin(); firmware_restrict_branch_speculation_start(); efi_enter_mm(); + efi_disable_lass(); } =20 void arch_efi_call_virt_teardown(void) { + efi_enable_lass(); efi_leave_mm(); firmware_restrict_branch_speculation_end(); efi_fpu_end(); --=20 2.43.0