From nobody Sun Feb 8 09:32:51 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013025.outbound.protection.outlook.com [40.93.201.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE34738BDCC; Tue, 20 Jan 2026 20:43:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.201.25 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941824; cv=fail; b=lcMicMaX0pUPQyrJ7IGBqm2Y4OKU86Pjvk9GumSWuOCg56qieFjh/1bXURkPG3rlm98nVoOB3HT/rvEzbVkMQjIYAENyF8DOZgq2guVL9Nl2c0qLTPAtV1AbWTrZbODmp1bxMl2YpTo4m7+M/QTB+An+3ve71wY+SMkAd6xoUO8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941824; c=relaxed/simple; bh=9bt+4BOIOZNKLffG5QWHHHrBOuDhmPmAUUCXe6IM2hM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=eZZkd6ToDXkWFhuL+CGm580M/5VY0Mqpxv6CESjoUQRLToc+mSGMSXXbzE4AcPQ1bU0N95sp7Xp7wsg/SqB3AF7gext1tq37ikpUankZYYmPgjC76F/hExX+NE7UhKVDrvb5zT2Y5wTAptn6OvMUSW28b3ZrNKMC+IQpoCEpY+Q= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=G4mk6Npi; arc=fail smtp.client-ip=40.93.201.25 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="G4mk6Npi" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=O9ydnogvx6KZgl0bkPY3h28+J8nTa6JWzZjx+rrm4WHfnqHrTgNyPkd757MPdMxaH3RDo3H/p/EdijnOH8KNE9t1vt2bgpKDnWrlv+5F8rHouZqWHZ+Yft6d3E60fbbZeY4b2htESrZziJDYoS2OxiORTTMezgNhImYcxGL8+tDN4i25dzqSBioHeo/TyI2q2fWQ598QYdMz2aAwbDZu8PPSkaRh4+kktkeaWTv9iGgexCAmrkQ6TwpBwdZuXOJzJT+2Z5b5SNNdhP+UUZlLUIjyeE4NpX1G4fwCh197/sAdtxVzcBJJuwRyS8R/Bj8TNLkeuk9Bq9zPrHNDNciXgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=hUBZ6L+/xZVS1Ji2XUB+n8k6WjuNk14WaceTCfHlB9A=; b=GRJYP6QOxP7eEdk8JVYmrJ1IR2RZegfsMCfHNkSurJ782Jhh7lKfokUo+4gw55sx1DVx3dV5A7Y1aVtYTV/DXCt63vaEaIKe2AOTIm744jAo7dSueJge+zTZT8nKBk1dV17SZFghhajQ+Xtqo3eHX7JfG5ZhRPbz5IeEj5NRcQH2z942WeTNn4SW9wnEufUwhKHQLoQzDJGPnjb6Lux3cvCaDp8CAkjlOrp7UB1SvGkC/aFaUF1nQWeYkGxOgy7AOl1bmRwnXzBTe31h7SAuAfvQ+fcqvc+Bi8VF+UX1wPW2dLAYE4cZeGqdPixZW9CMIsenDqUsoaANd6GuY/+cPg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hUBZ6L+/xZVS1Ji2XUB+n8k6WjuNk14WaceTCfHlB9A=; b=G4mk6NpiofxK5lDZ+BgWU801jRfwrpj1K6av5d576iGycIyLD5gcAVqUR4g9ODjNm0Tny3hOCt1bjnMtVb3pZIBA/ZdLnm5q7hfONo+HDukWWiuhXjfkOH15WXO84lH/cxMVcz52Nr52RmwYb0hSaNw6G82yN9QIcV1KhaYjpRbOxP0rhoCDZ6TqosQO5kRcL/aHCTGSWaCSGh9E2tfZiif3fhzgNdnY8EE6P1Viop+97pIrOOzRgBS+L/do19SKnHjbTHT1jx8ILCTr1elMgWSrbRLBDq1n4dnNP0BJYLEAGgY4eyVRlkYEXMwAHADXWqGvT9IpD/ZG86Lfa/M2YA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by PH7PR12MB6809.namprd12.prod.outlook.com (2603:10b6:510:1af::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.12; Tue, 20 Jan 2026 20:43:34 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9542.008; Tue, 20 Jan 2026 20:43:34 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jonathan Corbet , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Huang Rui , Matthew Auld , Matthew Brost , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Helge Deller , Danilo Krummrich , Alice Ryhl , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Alexey Ivanov , Balbir Singh , Philipp Stanner , Elle Rhumsaa , Daniel Almeida , joel@joelfernandes.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, linux-doc@vger.kernel.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-fbdev@vger.kernel.org, Joel Fernandes Subject: [PATCH RFC v6 01/26] rust: clist: Add support to interface with C linked lists Date: Tue, 20 Jan 2026 15:42:38 -0500 Message-Id: <20260120204303.3229303-2-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120204303.3229303-1-joelagnelf@nvidia.com> References: <20260120204303.3229303-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BL1PR13CA0279.namprd13.prod.outlook.com (2603:10b6:208:2bc::14) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|PH7PR12MB6809:EE_ X-MS-Office365-Filtering-Correlation-Id: 59bf7c39-03ab-4bb7-b455-08de5864939b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|7416014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?zedivzF8LOtonffT6d+08jkNUh9aCZ8lBfNIuVMWMdgZAwShuUJz3mQgluCD?= =?us-ascii?Q?4w+jp1bXUNyNzDhkr/uyGAcKy/1cpb1LL9fDGaqNVP7vsf3WkTiO/SaxWpEH?= =?us-ascii?Q?JXnj1O7BEJsM48gweg0qz7pcNMEsxmAm/upJuZcm4lvqeYgMpEivFIUH+OB6?= =?us-ascii?Q?6Bk8DhYly9mWzprp5PzU+oBmaRk2XE0QXqDTgJLFljjPbwhu4XZPtkfPFnye?= =?us-ascii?Q?iaAUu76wMAyhHHdHiP3OovQ+LibKKp48cCWCw04szBAUiIl4vyAOXPLoRIfd?= =?us-ascii?Q?HKAsJ55CmRb5gMfFEP5hsg4p9CyeTp69dSIhNm/tzIRBU2JDGBsad5LTZcVL?= =?us-ascii?Q?HBSSGPZWf78rgut3L8sHwvDYvY+oVlpy1jA/VjPSyVu36fyCWqyStkIW8/1X?= =?us-ascii?Q?ODqB0KHYtedOoR9gyIDdUgC51Ly0mg52xDaxKZcbhpPscrnRfGXEFCclMUHe?= =?us-ascii?Q?jWtqogArpk2fnTLfLq2OVsQgdnL6WVq9SF1+UzqEFfKtYzoBh4rgror3198U?= =?us-ascii?Q?nO/crLetqYnPbi0WixDRlGUvQWNW4RrstbvyeNrt9t4+Xt1dCkSa6Xlwf4da?= =?us-ascii?Q?KFafbH5P7bF0BfnHEpt0IteYxaUOJ083Um9u3rbffBACtmWWvryxLOwipymU?= =?us-ascii?Q?v+OLNzLqd9I5tZXWf1oT1qFtWP4JGy4YoE+pVUehrtwad2TE0Tpu3hA7aaOU?= =?us-ascii?Q?it5YvdPZYQfnFI9vEk2ehWlsgayhTGFILN0FnlYd7vCUpwKKUTnItM+Dhm0W?= =?us-ascii?Q?NkZB1PsooYTfMWhgU97or0IrobgkpJvcD/yGE5ybiM2Bm5lon6NM6nZczQ3q?= =?us-ascii?Q?iSNuRX/iY91dnor/cKDc5B+STKb4IfyqwacvYJb6ky1EfENXUvR7LCD/1sLc?= =?us-ascii?Q?upD6vqdmsSvhtD050A0j2z+Q3uOxsux5jrUwHnn8wNVS/h3eo5B9jXDjSnwL?= =?us-ascii?Q?n3cvCT/FVaF0HanKlASLtrFsTyPI55g3zTgm1vDL/0fKr0+jX0bOoaJH2IZ4?= =?us-ascii?Q?S/df5BzkZpud3Ga0HKF0SdGJpQQIFKA+khb7MYn96L7l9yVISwG3qjxhAdyg?= =?us-ascii?Q?C6NuVY6s1sB/NdTKdkfAjqIB6mfuWxK1iAqwyrAMEXPAOxXCaKi4cBajxskN?= =?us-ascii?Q?NUfA8oY4WU4bc/U5Vsxbm46CyCXopADdFiupApOx9uhoPkKcBs5fq9oTLiWi?= =?us-ascii?Q?zht7suMNnDwrmqFxqNSKfQy+Yy1yYOyzKbyPukBzcDoTAAo7oIOT+V30RF4p?= =?us-ascii?Q?gWHdI7zgtt06Ro/VykUqiUZlsXX3NLNeowJVEbmTxeCPWte6Yj990whrlKwz?= =?us-ascii?Q?eVFNvdx17XuJQEPSv3FlATntYzWLJRA9ZdlSjS0IqQVlDooVpeKloQfqSfT6?= =?us-ascii?Q?hW0xl9B3iZMxuTdRGKxzC5maeJLdvfaVrzN+JDVozs3wBk3cUyS0C3V/aRbf?= =?us-ascii?Q?Yv2aRnoWKM235P1Vum+eYBkWZhhe8HBD5fNKUqlAgjEsFbWhOJR2HUK45Z4a?= =?us-ascii?Q?M7643SSfxGpHEHdJdFfNtPPdQCONtwTkaLtfZzI/My6/9HrmNur3UEx1bHHA?= =?us-ascii?Q?aix+0hXtDBRySRqR7tM=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR12MB6486.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(376014)(7416014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?9EvbWrNr8ZKcT4TEP4c6u8dxWeGiKq3TMp7fCuxOLDhaQxeyLe1vY4XHb78+?= =?us-ascii?Q?ZuJtTN7qLcgGbbnXLxZ1Qu0Nq/bRJSG+rn53c8DYC6fwbaqRfbvTDXDUMroD?= =?us-ascii?Q?cVaW86H2LH/U0EfKEp0kzwq+IyNwK475vBUCM8RuO1mHtC++M9nhbhTugrgj?= =?us-ascii?Q?G/2lTNWQYeo8lv/W9A2vTW2yHAp6FbHOp1Kn81/UTjOmFmLaDbuW6kln+hRa?= =?us-ascii?Q?eThECKNd15cMbvAlClmrNboVpQAjYlUwj3N/RpdLwuDEtF9znRY3roz57VKq?= =?us-ascii?Q?ZxDdI64DhoRnkKi57yNzIJpguHQQ1R9Ca6ulD/8Oy9pWBGoPnoPsIL4Dl0sa?= =?us-ascii?Q?klVilPWzK7PfBZLlTf7vEeyp/LEwS4T3XaxFVmlDJC8A7NO1sZXdZ2yTV5w1?= =?us-ascii?Q?9fWy2MfyQfKr1jqsOFBLsjI9RR14M6dqVyxGmXlOtEMfeWuKLnSJbbRZVKKv?= =?us-ascii?Q?p51UKC9sw+tzqP9OjmE37YsxJIsJxVBKMDkdDg/x8QkOEwgL8ZQTIdM8ehCZ?= =?us-ascii?Q?4Fq6cvrbp+hR68nKR2uW1WpolJK1SWNQmcSWGnjZ9QY2eWWLhaNAg1XbnBBt?= =?us-ascii?Q?bMhZcFG0TvSgtwnuVwSPAueBysaMKQ6aPKGsOY1DQQc9t+F9l22QM6ko35mk?= =?us-ascii?Q?c69XkAnw6g2iwGLkX1aF4VtTOd+kXMR0B7zMAAnCiu8LnvHh/ETGr3CJSUVD?= =?us-ascii?Q?Ua99jHY5ton7KVXgdQmnuTh1iORG1bRtT6aCcjeCvj3IlWo82UvRjZAuQ+am?= =?us-ascii?Q?5wmXwH7oP33ZETnMbroysUkEyT6NTtEbJx6n0NILzhunLUgrcUMyQZxhpKOq?= =?us-ascii?Q?md+U0zRi9Jq+M5ZKWy6b9y8OLWNE5l613893xXKwUy4O7G9WrjQ32qkLh+UE?= =?us-ascii?Q?i6W/9K9t+A3mHyn1+9qiE9ICsZkBsDKQgHCNkfwC/gtCuXWcG9IJ6FW9YHIu?= =?us-ascii?Q?O6AcdmwnzyOccB8sCY4hNSqS35/IKMUEzx9agIvkAO+3y6ABPtNEV0CGpt52?= =?us-ascii?Q?1YBg6VJ7PFki2gHbHDPhmbe55zpYD9+dOdHLflJKYjOGt/E5YBIFOnSAkAss?= =?us-ascii?Q?ZB+vCituvcRP1KZq47eXZ4H1Zcxkh68TnvJ1AQ3YIZLcUDRGFUUHB9Kb8KhK?= =?us-ascii?Q?RdxNO0hwTxSTQ69PdXp5NhdtL4iL2tElwI6AVUmluP9phWX3qUKFTNJAI0wQ?= =?us-ascii?Q?xltqsOQS2tKo6y57/j3htXoTSjpGbZnvzC/kdDJ87LfiwlGQBV84oOCN+nlb?= =?us-ascii?Q?+jrJOJS14yTCW3rqaiocEfWxYlqlvnCUYXcUvjwWBUHS7RansHI25fNnIL1S?= =?us-ascii?Q?AN+XStKrYURX3mMUvlpMpdqcEzuC5dX0ROwSzOOzjnS+X0qC8EPMTEomts+X?= =?us-ascii?Q?Y/gOzj0blWdwb6dcN49DHRYcZnZOCz7ODZu93OYb60BfsIiguyFYRkD+VZf9?= =?us-ascii?Q?Ur6Ktq0EjGroeZEXw32FVx5QOmhbU7LpskVpryRn8UoexthiLssDjUE+ATdO?= =?us-ascii?Q?vWzINVrbN512OZRq9X92V3Ej1/HYYU8huypveNiYlkPwp1evLSiMXifj3pwc?= =?us-ascii?Q?gdKc6k1kFUXTde5rApryS00Cri1wRZ0Re6LlxETRYTRH3I16ddBnxTZK8Ap1?= =?us-ascii?Q?ioBwsnYO76ueb8J3+OsJHMln7E5l2D3qqEZf0RoSP/NCZTC8Y9BfHwMYdFWg?= =?us-ascii?Q?6dCiis96pXXC0PQJC+btomS0f4jWhBXoxtXNr18YuEj9GxO3MoQvpxJzwcsC?= =?us-ascii?Q?ygYEird9ZQ=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 59bf7c39-03ab-4bb7-b455-08de5864939b X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB6486.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 20:43:33.1205 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: kQytbN0oYIyUuAMqku4BMl7g0cGoCWn8ODRUFNROZeMisghTo5bI2Kv6ACSCX0XCTqH1k5UwhAMYLApQPEZwBA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6809 Content-Type: text/plain; charset="utf-8" Add a new module `clist` for working with C's doubly circular linked lists. Provide low-level iteration over list nodes. Typed iteration over actual items is provided with a `clist_create` macro to assist in creation of the `Clist` type. Signed-off-by: Joel Fernandes --- MAINTAINERS | 7 + rust/helpers/helpers.c | 1 + rust/helpers/list.c | 12 ++ rust/kernel/clist.rs | 357 +++++++++++++++++++++++++++++++++++++++++ rust/kernel/lib.rs | 1 + 5 files changed, 378 insertions(+) create mode 100644 rust/helpers/list.c create mode 100644 rust/kernel/clist.rs diff --git a/MAINTAINERS b/MAINTAINERS index 0d044a58cbfe..b76988c38045 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22936,6 +22936,13 @@ F: rust/kernel/init.rs F: rust/pin-init/ K: \bpin-init\b|pin_init\b|PinInit =20 +RUST TO C LIST INTERFACES +M: Joel Fernandes +M: Alexandre Courbot +L: rust-for-linux@vger.kernel.org +S: Maintained +F: rust/kernel/clist.rs + RXRPC SOCKETS (AF_RXRPC) M: David Howells M: Marc Dionne diff --git a/rust/helpers/helpers.c b/rust/helpers/helpers.c index 79c72762ad9c..634fa2386bbb 100644 --- a/rust/helpers/helpers.c +++ b/rust/helpers/helpers.c @@ -32,6 +32,7 @@ #include "io.c" #include "jump_label.c" #include "kunit.c" +#include "list.c" #include "maple_tree.c" #include "mm.c" #include "mutex.c" diff --git a/rust/helpers/list.c b/rust/helpers/list.c new file mode 100644 index 000000000000..6044979c7a2e --- /dev/null +++ b/rust/helpers/list.c @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Helpers for C Circular doubly linked list implementation. + */ + +#include + +void rust_helper_list_add_tail(struct list_head *new, struct list_head *he= ad) +{ + list_add_tail(new, head); +} diff --git a/rust/kernel/clist.rs b/rust/kernel/clist.rs new file mode 100644 index 000000000000..91754ae721b9 --- /dev/null +++ b/rust/kernel/clist.rs @@ -0,0 +1,357 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! A C doubly circular intrusive linked list interface for rust code. +//! +//! # Examples +//! +//! ``` +//! use kernel::{ +//! bindings, +//! clist::init_list_head, +//! clist_create, +//! types::Opaque, // +//! }; +//! # // Create test list with values (0, 10, 20) - normally done by C cod= e but it is +//! # // emulated here for doctests using the C bindings. +//! # use core::mem::MaybeUninit; +//! # +//! # /// C struct with embedded `list_head` (typically will be allocated = by C code). +//! # #[repr(C)] +//! # pub(crate) struct SampleItemC { +//! # pub value: i32, +//! # pub link: bindings::list_head, +//! # } +//! # +//! # let mut head =3D MaybeUninit::::uninit(); +//! # +//! # let head =3D head.as_mut_ptr(); +//! # // SAFETY: head and all the items are test objects allocated in this= scope. +//! # unsafe { init_list_head(head) }; +//! # +//! # let mut items =3D [ +//! # MaybeUninit::::uninit(), +//! # MaybeUninit::::uninit(), +//! # MaybeUninit::::uninit(), +//! # ]; +//! # +//! # for (i, item) in items.iter_mut().enumerate() { +//! # let ptr =3D item.as_mut_ptr(); +//! # // SAFETY: pointers are to allocated test objects with a list_he= ad field. +//! # unsafe { +//! # (*ptr).value =3D i as i32 * 10; +//! # // addr_of_mut!() computes address of link directly as link = is uninitialized. +//! # init_list_head(core::ptr::addr_of_mut!((*ptr).link)); +//! # bindings::list_add_tail(&mut (*ptr).link, head); +//! # } +//! # } +//! +//! // Rust wrapper for the C struct. +//! // The list item struct in this example is defined in C code as: +//! // struct SampleItemC { +//! // int value; +//! // struct list_head link; +//! // }; +//! // +//! #[repr(transparent)] +//! pub(crate) struct Item(Opaque); +//! +//! impl Item { +//! pub(crate) fn value(&self) -> i32 { +//! // SAFETY: [`Item`] has same layout as [`SampleItemC`]. +//! unsafe { (*self.0.get()).value } +//! } +//! } +//! +//! // Create typed [`CList`] from sentinel head. +//! // SAFETY: head is valid, items are [`SampleItemC`] with embedded `lin= k` field. +//! let list =3D unsafe { clist_create!(head, Item, SampleItemC, link) }; +//! +//! // Iterate directly over typed items. +//! let mut found_0 =3D false; +//! let mut found_10 =3D false; +//! let mut found_20 =3D false; +//! +//! for item in list.iter() { +//! let val =3D item.value(); +//! if val =3D=3D 0 { found_0 =3D true; } +//! if val =3D=3D 10 { found_10 =3D true; } +//! if val =3D=3D 20 { found_20 =3D true; } +//! } +//! +//! assert!(found_0 && found_10 && found_20); +//! ``` + +use core::{ + iter::FusedIterator, + marker::PhantomData, // +}; + +use crate::{ + bindings, + types::Opaque, // +}; + +use pin_init::PinInit; + +/// Initialize a `list_head` object to point to itself. +/// +/// # Safety +/// +/// `list` must be a valid pointer to a `list_head` object. +#[inline] +pub unsafe fn init_list_head(list: *mut bindings::list_head) { + // SAFETY: Caller guarantees `list` is a valid pointer to a `list_head= `. + unsafe { + (*list).next =3D list; + (*list).prev =3D list; + } +} + +/// Wraps a `list_head` object for use in intrusive linked lists. +/// +/// # Invariants +/// +/// - [`CListHead`] represents an allocated and valid `list_head` structur= e. +/// - Once a [`CListHead`] is created in Rust, it will not be modified by = non-Rust code. +/// - All `list_head` for individual items are not modified for the lifeti= me of [`CListHead`]. +#[repr(transparent)] +pub struct CListHead(Opaque); + +impl CListHead { + /// Create a `&CListHead` reference from a raw `list_head` pointer. + /// + /// # Safety + /// + /// - `ptr` must be a valid pointer to an allocated and initialized `l= ist_head` structure. + /// - `ptr` must remain valid and unmodified for the lifetime `'a`. + #[inline] + pub unsafe fn from_raw<'a>(ptr: *mut bindings::list_head) -> &'a Self { + // SAFETY: + // - [`CListHead`] has same layout as `list_head`. + // - `ptr` is valid and unmodified for 'a. + unsafe { &*ptr.cast() } + } + + /// Get the raw `list_head` pointer. + #[inline] + pub fn as_raw(&self) -> *mut bindings::list_head { + self.0.get() + } + + /// Get the next [`CListHead`] in the list. + #[inline] + pub fn next(&self) -> &Self { + let raw =3D self.as_raw(); + // SAFETY: + // - `self.as_raw()` is valid per type invariants. + // - The `next` pointer is guaranteed to be non-NULL. + unsafe { Self::from_raw((*raw).next) } + } + + /// Get the previous [`CListHead`] in the list. + #[inline] + pub fn prev(&self) -> &Self { + let raw =3D self.as_raw(); + // SAFETY: + // - self.as_raw() is valid per type invariants. + // - The `prev` pointer is guaranteed to be non-NULL. + unsafe { Self::from_raw((*raw).prev) } + } + + /// Check if this node is linked in a list (not isolated). + #[inline] + pub fn is_linked(&self) -> bool { + let raw =3D self.as_raw(); + // SAFETY: self.as_raw() is valid per type invariants. + unsafe { (*raw).next !=3D raw && (*raw).prev !=3D raw } + } + + /// Fallible pin-initializer that initializes and then calls user clos= ure. + /// + /// Initializes the list head first, then passes `&CListHead` to the c= losure. + /// This hides the raw FFI pointer from the user. + pub fn try_init( + init_func: impl FnOnce(&CListHead) -> Result<(), E>, + ) -> impl PinInit { + // SAFETY: init_list_head initializes the list_head to point to it= self. + // After initialization, we create a reference to pass to the clos= ure. + unsafe { + pin_init::pin_init_from_closure(move |slot: *mut Self| { + init_list_head(slot.cast()); + // SAFETY: slot is now initialized, safe to create referen= ce. + init_func(&*slot) + }) + } + } +} + +// SAFETY: [`CListHead`] can be sent to any thread. +unsafe impl Send for CListHead {} + +// SAFETY: [`CListHead`] can be shared among threads as it is not modified +// by non-Rust code per type invariants. +unsafe impl Sync for CListHead {} + +impl PartialEq for CListHead { + fn eq(&self, other: &Self) -> bool { + self.as_raw() =3D=3D other.as_raw() + } +} + +impl Eq for CListHead {} + +/// Low-level iterator over `list_head` nodes. +/// +/// An iterator used to iterate over a C intrusive linked list (`list_head= `). Caller has to +/// perform conversion of returned [`CListHead`] to an item (using `contai= ner_of` macro or similar). +/// +/// # Invariants +/// +/// [`CListHeadIter`] is iterating over an allocated, initialized and vali= d list. +struct CListHeadIter<'a> { + current_head: &'a CListHead, + list_head: &'a CListHead, +} + +impl<'a> Iterator for CListHeadIter<'a> { + type Item =3D &'a CListHead; + + #[inline] + fn next(&mut self) -> Option { + // Advance to next node. + let next =3D self.current_head.next(); + + // Check if we've circled back to the sentinel head. + if next =3D=3D self.list_head { + None + } else { + self.current_head =3D next; + Some(self.current_head) + } + } +} + +impl<'a> FusedIterator for CListHeadIter<'a> {} + +/// A typed C linked list with a sentinel head. +/// +/// A sentinel head represents the entire linked list and can be used for +/// iteration over items of type `T`, it is not associated with a specific= item. +/// +/// The const generic `OFFSET` specifies the byte offset of the `list_head= ` field within +/// the struct that `T` wraps. +/// +/// # Invariants +/// +/// - `head` is an allocated and valid C `list_head` structure that is the= list's sentinel. +/// - `OFFSET` is the byte offset of the `list_head` field within the stru= ct that `T` wraps. +/// - All the list's `list_head` nodes are allocated and have valid next/p= rev pointers. +/// - The underlying `list_head` (and entire list) is not modified for the= lifetime `'a`. +pub struct CList<'a, T, const OFFSET: usize> { + head: &'a CListHead, + _phantom: PhantomData<&'a T>, +} + +impl<'a, T, const OFFSET: usize> CList<'a, T, OFFSET> { + /// Create a typed [`CList`] from a raw sentinel `list_head` pointer. + /// + /// # Safety + /// + /// - `ptr` must be a valid pointer to an allocated and initialized `l= ist_head` structure + /// representing a list sentinel. + /// - `ptr` must remain valid and unmodified for the lifetime `'a`. + /// - The list must contain items where the `list_head` field is at by= te offset `OFFSET`. + /// - `T` must be `#[repr(transparent)]` over the C struct. + #[inline] + pub unsafe fn from_raw(ptr: *mut bindings::list_head) -> Self { + Self { + // SAFETY: Caller guarantees `ptr` is a valid, sentinel `list_= head` object. + head: unsafe { CListHead::from_raw(ptr) }, + _phantom: PhantomData, + } + } + + /// Get the raw sentinel `list_head` pointer. + #[inline] + pub fn as_raw(&self) -> *mut bindings::list_head { + self.head.as_raw() + } + + /// Check if the list is empty. + #[inline] + pub fn is_empty(&self) -> bool { + let raw =3D self.as_raw(); + // SAFETY: self.as_raw() is valid per type invariants. + unsafe { (*raw).next =3D=3D raw } + } + + /// Create an iterator over typed items. + #[inline] + pub fn iter(&self) -> CListIter<'a, T, OFFSET> { + CListIter { + head_iter: CListHeadIter { + current_head: self.head, + list_head: self.head, + }, + _phantom: PhantomData, + } + } +} + +/// High-level iterator over typed list items. +pub struct CListIter<'a, T, const OFFSET: usize> { + head_iter: CListHeadIter<'a>, + _phantom: PhantomData<&'a T>, +} + +impl<'a, T, const OFFSET: usize> Iterator for CListIter<'a, T, OFFSET> { + type Item =3D &'a T; + + fn next(&mut self) -> Option { + let head =3D self.head_iter.next()?; + + // Convert to item using OFFSET. + // SAFETY: `item_ptr` calculation from `OFFSET` (calculated using = offset_of!) + // is valid per invariants. + Some(unsafe { &*head.as_raw().byte_sub(OFFSET).cast::() }) + } +} + +impl<'a, T, const OFFSET: usize> FusedIterator for CListIter<'a, T, OFFSET= > {} + +/// Create a C doubly-circular linked list interface [`CList`] from a raw = `list_head` pointer. +/// +/// This macro creates a [`CList`] that can iterate over items = of type `$rust_type` +/// linked via the `$field` field in the underlying C struct `$c_type`. +/// +/// # Arguments +/// +/// - `$head`: Raw pointer to the sentinel `list_head` object (`*mut bindi= ngs::list_head`). +/// - `$rust_type`: Each item's rust wrapper type. +/// - `$c_type`: Each item's C struct type that contains the embedded `lis= t_head`. +/// - `$field`: The name of the `list_head` field within the C struct. +/// +/// # Safety +/// +/// The caller must ensure: +/// - `$head` is a valid, initialized sentinel `list_head` pointing to a l= ist that remains +/// unmodified for the lifetime of the rust [`CList`]. +/// - The list contains items of type `$c_type` linked via an embedded `$f= ield`. +/// - `$rust_type` is `#[repr(transparent)]` over `$c_type` or has compati= ble layout. +/// - The macro is called from an unsafe block. +/// +/// # Examples +/// +/// Refer to the examples in the [`crate::clist`] module documentation. +#[macro_export] +macro_rules! clist_create { + ($head:expr, $rust_type:ty, $c_type:ty, $($field:tt).+) =3D> {{ + // Compile-time check that field path is a list_head. + let _: fn(*const $c_type) -> *const $crate::bindings::list_head = =3D + |p| ::core::ptr::addr_of!((*p).$($field).+); + + // Calculate offset and create `CList`. + const OFFSET: usize =3D ::core::mem::offset_of!($c_type, $($field)= .+); + $crate::clist::CList::<$rust_type, OFFSET>::from_raw($head) + }}; +} diff --git a/rust/kernel/lib.rs b/rust/kernel/lib.rs index f812cf120042..cd7e6a1055b0 100644 --- a/rust/kernel/lib.rs +++ b/rust/kernel/lib.rs @@ -75,6 +75,7 @@ pub mod bug; #[doc(hidden)] pub mod build_assert; +pub mod clist; pub mod clk; #[cfg(CONFIG_CONFIGFS_FS)] pub mod configfs; --=20 2.34.1 From nobody Sun Feb 8 09:32:51 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013036.outbound.protection.outlook.com [40.93.201.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15EFD3B8D6A; Tue, 20 Jan 2026 20:44:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.201.36 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941860; cv=fail; b=aS49By5GAK8NiIMKnqdJ9PQru1fVLSSPHpyyUvjFvfswhT4AI6fFlMZz0mSpUXiHBhI0Gjngop3C9ThkI/OGOwxS4U7iBFGe+qil5QDppVw7amFG71S60eTcvsT+qe0UyICAcGMCS3cRtR/BLcqEc/E6sW3pVBh1Uwj7IldXOcE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941860; c=relaxed/simple; bh=Js/4b+iOqksz7iuEkoEgDiaxAt1B8JmrELTJNPWyBXs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=C0VlGtmjT38BIk20JoGE0ARIF8Kfw9SNXsalTf4nuj3yDwDL7n4SZ1w3NAm2tufm89tdJXXGPYrmQxFuHPGrO3jZC/IOZr2Z0GUvL89HxpYUly0GXOTFdsleMR+3zs4o6YqSk+CRhnr1K7k+RzzkX9bv8X122uJZtbl+uYw4+Lw= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=Oc2vfXPt; arc=fail smtp.client-ip=40.93.201.36 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Oc2vfXPt" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=DW+C8cujIU8eYNBzO4LFprmBwwqD7vI+A/slIEAeBeK1F7Ws5mKD7W3Z7NemHHIXb3Ke0+ucMl6AYAi0hx//WjL3COq7IrKihTEkqBmYB8v+6wZntUDOdR2zPbsdIUsVb+7EBhXB3gLpn7X/VdUBWAuM0orOSt+ZlCwf0m3OszRDPMWPDo/QWdQjYuuZ6S3tcYGsnjpHYtxRODqMX5ho8LtUyG+yI7w0rSgdPM5aVnOgMSbRxz3PS/9AW4tJke97iFfKEOmAesvGg37TaM3ltsYAbJwS0/bY3oAbuwYSFPb5ZFmn3G79HOXbr0TVt2ZPG8/AVHMRj3fEjfbwkBs+PQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=hCoX3m0a8BNmBdWOS1fjnahEMCuEa2wOA99OrFp/3aM=; b=pWPWIHThFwn5uESfRWVTiIBV+N1AK4x1orE/2wTAzwUwVMU5FLxckraLir4SK/eQEXC4hcf646wAf91famc5C0J3yEFRK7m2KGPR8n1gYLin62AXjlpe1hDaAeWTMUxcLzJGgNCCWt3g+fhZ/bm2UVrxREpjyRWdPJft2BD2/gCuDQNyhGjqhOZYaqBdPCamTuPqA7HOVrj5/mKllrAsKdI4BBVhJEmDd5SLMADx1KyCowM+JWK8R5WrNI7V5O62APfiGpA1LDBJ4jJnjinYUHWymbvdRNN7WIsipKwIG94zSf86P7XouzmwMQG2fL+BgDbza57EQgMg0gExb922GQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hCoX3m0a8BNmBdWOS1fjnahEMCuEa2wOA99OrFp/3aM=; b=Oc2vfXPtV88VhVA9yGyoE8G7NxaWnG/QPXQvojcDhz3DaEWNkWh2hH+kzhyQ4W300EIgVNcNFyyMspbt/DIpXHVKkvSLLW0r65n3R1dYmrp8dbjYPSx1cuJj9Bs1eF+/GpKFUOaD/sZRRFBmx49QWSv0bU/A8nSbsLmx4QnPskKq3mrX+9d+Uu4xijdpCZKjTriBynk69kQYHaCjvg3XAlASFKjzgpLtM74NQV9poDMtPR1kdA8wTnMf4H40W/5AbVS6DuR8tnMIzObXhC8Q57rdIRfn8yj5PZw/jo2Lrd0O16UZwaWnxeFe/y4JrM/wPFHAqkVcW1uaDD3cxi0qSg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by PH7PR12MB6809.namprd12.prod.outlook.com (2603:10b6:510:1af::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.12; Tue, 20 Jan 2026 20:43:35 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9542.008; Tue, 20 Jan 2026 20:43:35 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jonathan Corbet , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Huang Rui , Matthew Auld , Matthew Brost , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Helge Deller , Danilo Krummrich , Alice Ryhl , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Alexey Ivanov , Balbir Singh , Philipp Stanner , Elle Rhumsaa , Daniel Almeida , joel@joelfernandes.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, linux-doc@vger.kernel.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-fbdev@vger.kernel.org, Joel Fernandes Subject: [PATCH RFC v6 02/26] gpu: Move DRM buddy allocator one level up Date: Tue, 20 Jan 2026 15:42:39 -0500 Message-Id: <20260120204303.3229303-3-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120204303.3229303-1-joelagnelf@nvidia.com> References: <20260120204303.3229303-1-joelagnelf@nvidia.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BL0PR0102CA0015.prod.exchangelabs.com (2603:10b6:207:18::28) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|PH7PR12MB6809:EE_ X-MS-Office365-Filtering-Correlation-Id: 458e1d60-121b-4d6a-83bd-08de5864946f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|7416014|1800799024; X-Microsoft-Antispam-Message-Info: =?utf-8?B?c093eDA4Nk1jRVdOT1Vjd3ZNODRJNE9tZUFoUkxRTU1YMEhBUHR4YjBzTFlP?= =?utf-8?B?VzJtTHdsaS9QUVpMdTVyVktOb3FqbG9PSUpkYjRVeWJsRUdjaWQ2eVJ4T0Qz?= =?utf-8?B?Q1BVMmNkejFucGZDc0QvcDRvbEFHd04zbFdieHlJeVJUOFhQYVN1QndueFdu?= =?utf-8?B?dDFlU1k2V0orVlc0c3habXdxdXlDbURzVWVDclREK0pwY2o5V2VYeDROZWw5?= =?utf-8?B?b2NmL2V2Vm5HL05OQVdkTEZYczNQOUZLemNwTHVOTW9kTFBmaDdycG9xQjdW?= =?utf-8?B?NHRqcGsydXRQNkVENGNjalBPZzdOaWlrak1sVjkydzZjYkFCc1FXZjJTYWhi?= =?utf-8?B?RGdNSm5NMlUzUnZ6aVB0K3B1clBpTmx5VEhNWDNnV3FmVjNJSStTb1daWTlU?= =?utf-8?B?ZWNodm0vOEt4Uk9LRVIyOG4veWs2ZWtFbFowcnNpbmpyYTZyaVo2K2F1bXVG?= =?utf-8?B?R25FZHhvdU5zdGROOXhjcTl2R2dHeGNwSTMwemFDWWl6UjJ4M1NtYlBRREpJ?= =?utf-8?B?ZGUzdTFCRlgyOGo2VWp2Umg5Znl5QlgwYytrK1VYb05OcHk5R084Q242LzFq?= =?utf-8?B?bjhKa3R0YThDRm1ZaVdhSXJmWkFISzB6SFlnYWxJcFdSN0Zabis1VzBubXRK?= =?utf-8?B?TzBGRGl4bHhmL2NPSnZCWWQvbHZ6SHAzSWtBbExhNGJBU290UlQzVVZOMHBW?= =?utf-8?B?b085WFBDUVpuRFdSSWZoV2pCajZLREZBUXVlZGlQNDNEUy92bGdqZWQwYWF3?= =?utf-8?B?UE1TTnRwNC9qS1FyMmIzL1dILzdXWTV0TGZsSm5hOWFaVzdHeDR3SzR3SUdz?= =?utf-8?B?eXB0R1c4SlFDRUN0dVdadEJSNEhscmd5OGt4S2V1bXdqaXJpUW1zUWhhc21X?= =?utf-8?B?d3gzMG5jQnhqNUlIKzQ0WS9ZSjJnZ21NNHk4MjZkT0Y3Ulh1L0s3SitXZHpa?= =?utf-8?B?NFoxcWVDZitRTzU4SjNoWjJMdlNpYktZNmkzcnd2cllaQjFvdnVZQytqdHlz?= =?utf-8?B?cklmSTJzNE9ZbldNWGdnNUJEeUZ0OGY1MzB1WnErMFZFamw3NUJTZ2xDcE5R?= =?utf-8?B?Uzdwc09UK2YxT3JPQU5KeW8zbVRQN0VrN2NCK0tNdlVrRCtzSys3ZEZTb3Qz?= =?utf-8?B?azY4UGRMTWRqUEhacVNodTF5K2lzQldaakdhRFBDbXVzREx0eUozS3Y0eG1K?= =?utf-8?B?cmZsb3JCWmJwSWVvL1Qrb3poamdnL2ZVZXY3SmtNRjhSTENtTEk3ZFUyMU9i?= =?utf-8?B?ZmpYelJCZjBTODlQbktXbm9KRWI4bHlPMVl3ZjQ3OGNVRWFnK2pjckdmTE55?= =?utf-8?B?K1RwNzcyMm56ejVtbkZ6MjVpTWJMYVh6angvYUlWRmNuSlFXbXVFVW00UjB1?= =?utf-8?B?d2xyQ2p3S1VpTmR3TzdZbmsyOGJEckNkYW5ITC9FdDJvbGV4K0tEd1dYdTcr?= =?utf-8?B?WXR3RHNVTWJ2MTdvTHFvN2xPZzRUNFpiRW13WW5RZksrZXZBT1EzcGJVYmxx?= =?utf-8?B?c21uVmxXN3UyVUtFSytlbzBVRWlIK2tDV0hFUjRCblVMQWN1OEpLcG01bnlv?= =?utf-8?B?WkFxcWNRYW1zR2ZLN0MrRUZWWXU5VTFxK2xyWlJYcGlQRUVNRXV4TzBsdkVU?= =?utf-8?B?YUQ4K3RlbjNJaVovVEVkWW9GeXJWYkJaOTJuQllSM1BuQ2NIS2Z0Vm1xb09w?= =?utf-8?B?Q1o3bWF3ODZIeEFtOTdpMStSTG5OUUQwWEhtK3hFdFJla2RWdjNRcmphNGpI?= =?utf-8?B?T1U4RnRmZG1hcyt4NnR0WlRpc09jZXNRelhZbkl3V3pCUHdBbnNMa3FvQUVi?= =?utf-8?B?RzQzajdtdDkyaWt0NWRTcysrWkNpbTFGczlVd1MwU2xaQnA3T1hXdWF2OWwv?= =?utf-8?B?ZURYaWVxbTNnVS9mZDh2NU44QmRjb20wTzVKUHRCNGtSQU5lYUZVamRXN3py?= =?utf-8?B?VmdWNm5ObzBLWWF4N21DWUYvZThJWnF1QTlscC9iSno1YzRjR1F1cmdKcGRk?= =?utf-8?B?M1hwVFJiTC90dE9tbzFtUGNYbW5WL3pKUmk4MFhVdlk1azlUUGhJeXUxZnZv?= =?utf-8?B?bjlUT0gwalNsR25LaVNSK3Jkbjl2K3BYck9DbG9UVmJtdERrcHpHWVFmTVE0?= =?utf-8?Q?pmuc=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR12MB6486.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(376014)(7416014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?K20wSHE4Q1M2MGNQTkM2NjdFZUVKTkdyUk5ieFlWdEFycDNLVVJWL0xua1BJ?= =?utf-8?B?bTVFd2ZpUUdsM0NqWjRyd2dEQXNUeC9WMXcvSGVaNnNCM3JkR0x0OVZ4anNh?= =?utf-8?B?SkpaY1RPeEgwc01ZcW0rZkg2OUIwVC9STWp6OUpMck9LMFpIVHpVWFh2SFl2?= =?utf-8?B?amtHYkFQd2s0dk15NXYwYmtaNm5IU1ExWkd1KzdlYmEySEI3YXFKalg1RWw3?= =?utf-8?B?bVlRV0FvRHQxR1Jyc25mWmlGL0lOQTQzalZPUjJ4eXNLUzdrazQ0V3lWOGVk?= =?utf-8?B?UGYxZjhrVUZRNG9vZi9nOHpPdHBRUk82U3BDZmJqaWpCbkRBZTZ0dDJaQzZk?= =?utf-8?B?cW1tRmJoZTJOMU9Wck40Q05OWHY0ODJ3N3Flb3NZLzVtM0R1eXFRRXR3UnBh?= =?utf-8?B?cm5OWmpJQVhoU3U4L01qbE9sUzJIdGxESFBOaHRUakdtRjVGWnMyOXhSUTZR?= =?utf-8?B?ZVl6UnQxbGFFMjUyQlc1cTZqdk5WNDN0cHRFTVNoZ0o4SjA2Q211REJtYnRZ?= =?utf-8?B?THU2VE9ITnIrdGlzYVNQRFA4NWVWWmhHNXFIYVJoRllmMituTEtwOEEybmFB?= =?utf-8?B?dVBhVXh6MTI2TmFCSzBRMXAwOWJFWVZRMFhUWm9Ma0o4MzhpVlB5TGl2U2Va?= =?utf-8?B?Q0FUTkJrYVdMMW5OTkFmdm1wcytBc0o5WldVZlc3dXAvUVcvbnJING1rK3BG?= =?utf-8?B?OUVXNG9KY3cxUjVjS2xoYkFLa1lyYnZSa3Zwa0ZWajA1TWJ3Tm9HdU5ZckZ5?= =?utf-8?B?eUw4UmxFRGFhQm42QVVvb1BRMmVocnZORFdqZC81cmdFbjVDZ0NhS2tzYlEw?= =?utf-8?B?aEY2MlhrVUJmbnoveitHQkJaV2lLclE0dWFxQUVDTndvU0JoV1pBTllOWnE3?= =?utf-8?B?ZmVkN0ZIQkwxQlFhR0NtNW1ScU1WTWd4L3A0dUg4MTV2QlZrU3ZqUTJhZmxJ?= =?utf-8?B?Rk91cDZSY2ZGYWt6cnUzbWJFVUdrbWUxM0ZkOUwrVFplRVBXMDU2Nlc0OUJF?= =?utf-8?B?OEV0dFNFSGtxek1GVGtFU1hrRGZ4bmNYMVZ6Sml5ekExNEpYTFZkdnJ2UWhU?= =?utf-8?B?N0NnVmw5WmZyUkdjS04xbjNURWY0Yyt2S0hkSm42L01YcFE2Umo2THZWYVR6?= =?utf-8?B?R2pEZUJzK2FDNkdXU2ZNbjIzUFZMY0hyemd1MzUxR2FQR2VNSk9MWXBndzNn?= =?utf-8?B?TUpIbjRTNGZ3YVFObG44cnlRNk56Wk9wRERFQkVlelg5LzZpY1FMb1lEdlgr?= =?utf-8?B?dDFDZ09KZmZkWkVLZVF3OFpTVTFBbUF6ck9DeC9pY0dSNnBXNHJ4c2hKeUNI?= =?utf-8?B?ZlRmR292eldKL1prRmdXcmo0LzcyQ0toMkpONTFRZGhEUjlVUlZrd0RpVGFP?= =?utf-8?B?cXdPNHdlYzFWUHByam9aeGVTcHFUbVZiRjNMMHVtUnZMUnozZlJjZHh4a2xB?= =?utf-8?B?eGh6clZHZi81Ymt3NHIxWlpxb0FUMmJXazhJeHFJbSs2UEp2d0w5S3lLaGhT?= =?utf-8?B?a1Q5ZU1ob2lCR3Ruc0hGRURsa3cyeWlPczN5RDR3ak9jM3pIVmZxV0lXVlh0?= =?utf-8?B?RWFjMWs4WUthZmUva243Q1JnQmwyVFc5dEtMVkFUREVsM2xiWSt0Q3lhRXdu?= =?utf-8?B?ZzI2K2hiZnF0dWRoZGtsczlXN1RGR1prTUZ4c1Y5em5WQ2lkaDdCempxY3pp?= =?utf-8?B?Qi9SSVZQcW9oVlBqLzE3MTl5TDd5emFLa2xBYVBUVTlsTGtrbkxuNE5tN1VN?= =?utf-8?B?N3ZEM21Edk85MTA1R0Q3ZTNCQlU2SW9xeUZKQ3VuS3NFRVJ6Um1iQ2RudlZF?= =?utf-8?B?Y2ZZR3UwOGlqTk5vdFpWS3FyU2liNzQ1WSt0VDJpeXd5WXR2d0hjNU0zWWwy?= =?utf-8?B?YkxmMlE4VVNORHlBeTVpZFZuU2ErZGI4NmVUbnFQMytubWdTK3BoeUZxcHhQ?= =?utf-8?B?UHhmalhIZDZFTzAyWkVVbGZOZWM3L2lMVitadWhJTXc5Yk8xakZPWHo5WXMz?= =?utf-8?B?NE90KzRWUFI4U1o1eWZjdENySzBQSXBaQVN1YjM4eitybmVEMDM3NkQwUnZW?= =?utf-8?B?b3crY3JjTmx2Z1FuR2IzRVpyeE12alZkQXhLS0I3Q3c0eXpweHZIQjRic29O?= =?utf-8?B?UGJKNnd1bnU3M050cy9tTmhBVVpOVEVuM2Z2TmgyNlRUQ1p3MHRuckUwREpB?= =?utf-8?B?OVpCMmZVcUdtRU5XbHFIQStIUUJSWEMxWllPWVIwOVA0MFdHK2kzNEhMOER0?= =?utf-8?B?dFV5RWVVOWtML2FqUTd4dXVVQ0tMODd2MkVwVUFaMklhUHc1NGJOQ1J6aVhP?= =?utf-8?B?ZDUwTUwyVWhCK2JFMHc1ZHpoVWE3NzJEM1V6STBtMVlodk5CdWhWQT09?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 458e1d60-121b-4d6a-83bd-08de5864946f X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB6486.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 20:43:34.6649 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: L6URZc21QEGYEtj895VCq3U/z+v5p4iTIFlbt2EMPynWYR/qWqYQ539iEs+CodZCf/Z5F/WLBaurrlj6hPKMvA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6809 Move the DRM buddy allocator one level up so that it can be used by GPU drivers (example, nova-core) that have usecases other than DRM (such as VFIO vGPU support). Modify the API, structures and Kconfigs to use "gpu_buddy" terminology. Adapt the drivers and tests to use the new API. The commit cannot be split due to bisectability, however no functional change is intended. Verified by running K-UNIT tests and build tested various configurations. Signed-off-by: Joel Fernandes Reviewed-by: Dave Airlie --- Documentation/gpu/drm-mm.rst | 10 +- drivers/gpu/Kconfig | 13 + drivers/gpu/Makefile | 2 + drivers/gpu/buddy.c | 1310 +++++++++++++++++ drivers/gpu/drm/Kconfig | 1 + drivers/gpu/drm/Kconfig.debug | 4 +- drivers/gpu/drm/amd/amdgpu/Kconfig | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- .../gpu/drm/amd/amdgpu/amdgpu_res_cursor.h | 12 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 80 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h | 20 +- drivers/gpu/drm/drm_buddy.c | 1284 +--------------- drivers/gpu/drm/i915/Kconfig | 1 + drivers/gpu/drm/i915/i915_scatterlist.c | 10 +- drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 55 +- drivers/gpu/drm/i915/i915_ttm_buddy_manager.h | 6 +- .../drm/i915/selftests/intel_memory_region.c | 20 +- drivers/gpu/drm/tests/Makefile | 1 - .../gpu/drm/ttm/tests/ttm_bo_validate_test.c | 5 +- drivers/gpu/drm/ttm/tests/ttm_mock_manager.c | 18 +- drivers/gpu/drm/ttm/tests/ttm_mock_manager.h | 4 +- drivers/gpu/drm/xe/Kconfig | 1 + drivers/gpu/drm/xe/xe_res_cursor.h | 34 +- drivers/gpu/drm/xe/xe_svm.c | 12 +- drivers/gpu/drm/xe/xe_ttm_vram_mgr.c | 73 +- drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h | 4 +- drivers/gpu/tests/Makefile | 3 + .../gpu_buddy_test.c} | 390 ++--- drivers/gpu/tests/gpu_random.c | 48 + drivers/gpu/tests/gpu_random.h | 28 + drivers/video/Kconfig | 2 + include/drm/drm_buddy.h | 163 +- include/linux/gpu_buddy.h | 177 +++ 33 files changed, 1995 insertions(+), 1799 deletions(-) create mode 100644 drivers/gpu/Kconfig create mode 100644 drivers/gpu/buddy.c create mode 100644 drivers/gpu/tests/Makefile rename drivers/gpu/{drm/tests/drm_buddy_test.c =3D> tests/gpu_buddy_test.c= } (68%) create mode 100644 drivers/gpu/tests/gpu_random.c create mode 100644 drivers/gpu/tests/gpu_random.h create mode 100644 include/linux/gpu_buddy.h diff --git a/Documentation/gpu/drm-mm.rst b/Documentation/gpu/drm-mm.rst index d55751cad67c..8e0d31230b29 100644 --- a/Documentation/gpu/drm-mm.rst +++ b/Documentation/gpu/drm-mm.rst @@ -509,8 +509,14 @@ DRM GPUVM Function References DRM Buddy Allocator =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 -DRM Buddy Function References ------------------------------ +Buddy Allocator Function References (GPU buddy) +----------------------------------------------- + +.. kernel-doc:: drivers/gpu/buddy.c + :export: + +DRM Buddy Specific Logging Function References +---------------------------------------------- =20 .. kernel-doc:: drivers/gpu/drm/drm_buddy.c :export: diff --git a/drivers/gpu/Kconfig b/drivers/gpu/Kconfig new file mode 100644 index 000000000000..22dd29cd50b5 --- /dev/null +++ b/drivers/gpu/Kconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0 + +config GPU_BUDDY + bool + help + A page based buddy allocator for GPU memory. + +config GPU_BUDDY_KUNIT_TEST + tristate "KUnit tests for GPU buddy allocator" if !KUNIT_ALL_TESTS + depends on GPU_BUDDY && KUNIT + default KUNIT_ALL_TESTS + help + KUnit tests for the GPU buddy allocator. diff --git a/drivers/gpu/Makefile b/drivers/gpu/Makefile index 36a54d456630..5063caccabdf 100644 --- a/drivers/gpu/Makefile +++ b/drivers/gpu/Makefile @@ -6,3 +6,5 @@ obj-y +=3D host1x/ drm/ vga/ obj-$(CONFIG_IMX_IPUV3_CORE) +=3D ipu-v3/ obj-$(CONFIG_TRACE_GPU_MEM) +=3D trace/ obj-$(CONFIG_NOVA_CORE) +=3D nova-core/ +obj-$(CONFIG_GPU_BUDDY) +=3D buddy.o +obj-y +=3D tests/ diff --git a/drivers/gpu/buddy.c b/drivers/gpu/buddy.c new file mode 100644 index 000000000000..1347c0436617 --- /dev/null +++ b/drivers/gpu/buddy.c @@ -0,0 +1,1310 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright =C2=A9 2021 Intel Corporation + */ + +#include + +#include +#include +#include +#include +#include + +static struct kmem_cache *slab_blocks; + +static struct gpu_buddy_block *gpu_block_alloc(struct gpu_buddy *mm, + struct gpu_buddy_block *parent, + unsigned int order, + u64 offset) +{ + struct gpu_buddy_block *block; + + BUG_ON(order > GPU_BUDDY_MAX_ORDER); + + block =3D kmem_cache_zalloc(slab_blocks, GFP_KERNEL); + if (!block) + return NULL; + + block->header =3D offset; + block->header |=3D order; + block->parent =3D parent; + + RB_CLEAR_NODE(&block->rb); + + BUG_ON(block->header & GPU_BUDDY_HEADER_UNUSED); + return block; +} + +static void gpu_block_free(struct gpu_buddy *mm, + struct gpu_buddy_block *block) +{ + kmem_cache_free(slab_blocks, block); +} + +static enum gpu_buddy_free_tree +get_block_tree(struct gpu_buddy_block *block) +{ + return gpu_buddy_block_is_clear(block) ? + GPU_BUDDY_CLEAR_TREE : GPU_BUDDY_DIRTY_TREE; +} + +static struct gpu_buddy_block * +rbtree_get_free_block(const struct rb_node *node) +{ + return node ? rb_entry(node, struct gpu_buddy_block, rb) : NULL; +} + +static struct gpu_buddy_block * +rbtree_last_free_block(struct rb_root *root) +{ + return rbtree_get_free_block(rb_last(root)); +} + +static bool rbtree_is_empty(struct rb_root *root) +{ + return RB_EMPTY_ROOT(root); +} + +static bool gpu_buddy_block_offset_less(const struct gpu_buddy_block *bloc= k, + const struct gpu_buddy_block *node) +{ + return gpu_buddy_block_offset(block) < gpu_buddy_block_offset(node); +} + +static bool rbtree_block_offset_less(struct rb_node *block, + const struct rb_node *node) +{ + return gpu_buddy_block_offset_less(rbtree_get_free_block(block), + rbtree_get_free_block(node)); +} + +static void rbtree_insert(struct gpu_buddy *mm, + struct gpu_buddy_block *block, + enum gpu_buddy_free_tree tree) +{ + rb_add(&block->rb, + &mm->free_trees[tree][gpu_buddy_block_order(block)], + rbtree_block_offset_less); +} + +static void rbtree_remove(struct gpu_buddy *mm, + struct gpu_buddy_block *block) +{ + unsigned int order =3D gpu_buddy_block_order(block); + enum gpu_buddy_free_tree tree; + struct rb_root *root; + + tree =3D get_block_tree(block); + root =3D &mm->free_trees[tree][order]; + + rb_erase(&block->rb, root); + RB_CLEAR_NODE(&block->rb); +} + +static void clear_reset(struct gpu_buddy_block *block) +{ + block->header &=3D ~GPU_BUDDY_HEADER_CLEAR; +} + +static void mark_cleared(struct gpu_buddy_block *block) +{ + block->header |=3D GPU_BUDDY_HEADER_CLEAR; +} + +static void mark_allocated(struct gpu_buddy *mm, + struct gpu_buddy_block *block) +{ + block->header &=3D ~GPU_BUDDY_HEADER_STATE; + block->header |=3D GPU_BUDDY_ALLOCATED; + + rbtree_remove(mm, block); +} + +static void mark_free(struct gpu_buddy *mm, + struct gpu_buddy_block *block) +{ + enum gpu_buddy_free_tree tree; + + block->header &=3D ~GPU_BUDDY_HEADER_STATE; + block->header |=3D GPU_BUDDY_FREE; + + tree =3D get_block_tree(block); + rbtree_insert(mm, block, tree); +} + +static void mark_split(struct gpu_buddy *mm, + struct gpu_buddy_block *block) +{ + block->header &=3D ~GPU_BUDDY_HEADER_STATE; + block->header |=3D GPU_BUDDY_SPLIT; + + rbtree_remove(mm, block); +} + +static inline bool overlaps(u64 s1, u64 e1, u64 s2, u64 e2) +{ + return s1 <=3D e2 && e1 >=3D s2; +} + +static inline bool contains(u64 s1, u64 e1, u64 s2, u64 e2) +{ + return s1 <=3D s2 && e1 >=3D e2; +} + +static struct gpu_buddy_block * +__get_buddy(struct gpu_buddy_block *block) +{ + struct gpu_buddy_block *parent; + + parent =3D block->parent; + if (!parent) + return NULL; + + if (parent->left =3D=3D block) + return parent->right; + + return parent->left; +} + +static unsigned int __gpu_buddy_free(struct gpu_buddy *mm, + struct gpu_buddy_block *block, + bool force_merge) +{ + struct gpu_buddy_block *parent; + unsigned int order; + + while ((parent =3D block->parent)) { + struct gpu_buddy_block *buddy; + + buddy =3D __get_buddy(block); + + if (!gpu_buddy_block_is_free(buddy)) + break; + + if (!force_merge) { + /* + * Check the block and its buddy clear state and exit + * the loop if they both have the dissimilar state. + */ + if (gpu_buddy_block_is_clear(block) !=3D + gpu_buddy_block_is_clear(buddy)) + break; + + if (gpu_buddy_block_is_clear(block)) + mark_cleared(parent); + } + + rbtree_remove(mm, buddy); + if (force_merge && gpu_buddy_block_is_clear(buddy)) + mm->clear_avail -=3D gpu_buddy_block_size(mm, buddy); + + gpu_block_free(mm, block); + gpu_block_free(mm, buddy); + + block =3D parent; + } + + order =3D gpu_buddy_block_order(block); + mark_free(mm, block); + + return order; +} + +static int __force_merge(struct gpu_buddy *mm, + u64 start, + u64 end, + unsigned int min_order) +{ + unsigned int tree, order; + int i; + + if (!min_order) + return -ENOMEM; + + if (min_order > mm->max_order) + return -EINVAL; + + for_each_free_tree(tree) { + for (i =3D min_order - 1; i >=3D 0; i--) { + struct rb_node *iter =3D rb_last(&mm->free_trees[tree][i]); + + while (iter) { + struct gpu_buddy_block *block, *buddy; + u64 block_start, block_end; + + block =3D rbtree_get_free_block(iter); + iter =3D rb_prev(iter); + + if (!block || !block->parent) + continue; + + block_start =3D gpu_buddy_block_offset(block); + block_end =3D block_start + gpu_buddy_block_size(mm, block) - 1; + + if (!contains(start, end, block_start, block_end)) + continue; + + buddy =3D __get_buddy(block); + if (!gpu_buddy_block_is_free(buddy)) + continue; + + WARN_ON(gpu_buddy_block_is_clear(block) =3D=3D + gpu_buddy_block_is_clear(buddy)); + + /* + * Advance to the next node when the current node is the buddy, + * as freeing the block will also remove its buddy from the tree. + */ + if (iter =3D=3D &buddy->rb) + iter =3D rb_prev(iter); + + rbtree_remove(mm, block); + if (gpu_buddy_block_is_clear(block)) + mm->clear_avail -=3D gpu_buddy_block_size(mm, block); + + order =3D __gpu_buddy_free(mm, block, true); + if (order >=3D min_order) + return 0; + } + } + } + + return -ENOMEM; +} + +/** + * gpu_buddy_init - init memory manager + * + * @mm: GPU buddy manager to initialize + * @size: size in bytes to manage + * @chunk_size: minimum page size in bytes for our allocations + * + * Initializes the memory manager and its resources. + * + * Returns: + * 0 on success, error code on failure. + */ +int gpu_buddy_init(struct gpu_buddy *mm, u64 size, u64 chunk_size) +{ + unsigned int i, j, root_count =3D 0; + u64 offset =3D 0; + + if (size < chunk_size) + return -EINVAL; + + if (chunk_size < SZ_4K) + return -EINVAL; + + if (!is_power_of_2(chunk_size)) + return -EINVAL; + + size =3D round_down(size, chunk_size); + + mm->size =3D size; + mm->avail =3D size; + mm->clear_avail =3D 0; + mm->chunk_size =3D chunk_size; + mm->max_order =3D ilog2(size) - ilog2(chunk_size); + + BUG_ON(mm->max_order > GPU_BUDDY_MAX_ORDER); + + mm->free_trees =3D kmalloc_array(GPU_BUDDY_MAX_FREE_TREES, + sizeof(*mm->free_trees), + GFP_KERNEL); + if (!mm->free_trees) + return -ENOMEM; + + for_each_free_tree(i) { + mm->free_trees[i] =3D kmalloc_array(mm->max_order + 1, + sizeof(struct rb_root), + GFP_KERNEL); + if (!mm->free_trees[i]) + goto out_free_tree; + + for (j =3D 0; j <=3D mm->max_order; ++j) + mm->free_trees[i][j] =3D RB_ROOT; + } + + mm->n_roots =3D hweight64(size); + + mm->roots =3D kmalloc_array(mm->n_roots, + sizeof(struct gpu_buddy_block *), + GFP_KERNEL); + if (!mm->roots) + goto out_free_tree; + + /* + * Split into power-of-two blocks, in case we are given a size that is + * not itself a power-of-two. + */ + do { + struct gpu_buddy_block *root; + unsigned int order; + u64 root_size; + + order =3D ilog2(size) - ilog2(chunk_size); + root_size =3D chunk_size << order; + + root =3D gpu_block_alloc(mm, NULL, order, offset); + if (!root) + goto out_free_roots; + + mark_free(mm, root); + + BUG_ON(root_count > mm->max_order); + BUG_ON(gpu_buddy_block_size(mm, root) < chunk_size); + + mm->roots[root_count] =3D root; + + offset +=3D root_size; + size -=3D root_size; + root_count++; + } while (size); + + return 0; + +out_free_roots: + while (root_count--) + gpu_block_free(mm, mm->roots[root_count]); + kfree(mm->roots); +out_free_tree: + while (i--) + kfree(mm->free_trees[i]); + kfree(mm->free_trees); + return -ENOMEM; +} +EXPORT_SYMBOL(gpu_buddy_init); + +/** + * gpu_buddy_fini - tear down the memory manager + * + * @mm: GPU buddy manager to free + * + * Cleanup memory manager resources and the freetree + */ +void gpu_buddy_fini(struct gpu_buddy *mm) +{ + u64 root_size, size, start; + unsigned int order; + int i; + + size =3D mm->size; + + for (i =3D 0; i < mm->n_roots; ++i) { + order =3D ilog2(size) - ilog2(mm->chunk_size); + start =3D gpu_buddy_block_offset(mm->roots[i]); + __force_merge(mm, start, start + size, order); + + if (WARN_ON(!gpu_buddy_block_is_free(mm->roots[i]))) + kunit_fail_current_test("buddy_fini() root"); + + gpu_block_free(mm, mm->roots[i]); + + root_size =3D mm->chunk_size << order; + size -=3D root_size; + } + + WARN_ON(mm->avail !=3D mm->size); + + for_each_free_tree(i) + kfree(mm->free_trees[i]); + kfree(mm->roots); +} +EXPORT_SYMBOL(gpu_buddy_fini); + +static int split_block(struct gpu_buddy *mm, + struct gpu_buddy_block *block) +{ + unsigned int block_order =3D gpu_buddy_block_order(block) - 1; + u64 offset =3D gpu_buddy_block_offset(block); + + BUG_ON(!gpu_buddy_block_is_free(block)); + BUG_ON(!gpu_buddy_block_order(block)); + + block->left =3D gpu_block_alloc(mm, block, block_order, offset); + if (!block->left) + return -ENOMEM; + + block->right =3D gpu_block_alloc(mm, block, block_order, + offset + (mm->chunk_size << block_order)); + if (!block->right) { + gpu_block_free(mm, block->left); + return -ENOMEM; + } + + mark_split(mm, block); + + if (gpu_buddy_block_is_clear(block)) { + mark_cleared(block->left); + mark_cleared(block->right); + clear_reset(block); + } + + mark_free(mm, block->left); + mark_free(mm, block->right); + + return 0; +} + +/** + * gpu_get_buddy - get buddy address + * + * @block: GPU buddy block + * + * Returns the corresponding buddy block for @block, or NULL + * if this is a root block and can't be merged further. + * Requires some kind of locking to protect against + * any concurrent allocate and free operations. + */ +struct gpu_buddy_block * +gpu_get_buddy(struct gpu_buddy_block *block) +{ + return __get_buddy(block); +} +EXPORT_SYMBOL(gpu_get_buddy); + +/** + * gpu_buddy_reset_clear - reset blocks clear state + * + * @mm: GPU buddy manager + * @is_clear: blocks clear state + * + * Reset the clear state based on @is_clear value for each block + * in the freetree. + */ +void gpu_buddy_reset_clear(struct gpu_buddy *mm, bool is_clear) +{ + enum gpu_buddy_free_tree src_tree, dst_tree; + u64 root_size, size, start; + unsigned int order; + int i; + + size =3D mm->size; + for (i =3D 0; i < mm->n_roots; ++i) { + order =3D ilog2(size) - ilog2(mm->chunk_size); + start =3D gpu_buddy_block_offset(mm->roots[i]); + __force_merge(mm, start, start + size, order); + + root_size =3D mm->chunk_size << order; + size -=3D root_size; + } + + src_tree =3D is_clear ? GPU_BUDDY_DIRTY_TREE : GPU_BUDDY_CLEAR_TREE; + dst_tree =3D is_clear ? GPU_BUDDY_CLEAR_TREE : GPU_BUDDY_DIRTY_TREE; + + for (i =3D 0; i <=3D mm->max_order; ++i) { + struct rb_root *root =3D &mm->free_trees[src_tree][i]; + struct gpu_buddy_block *block, *tmp; + + rbtree_postorder_for_each_entry_safe(block, tmp, root, rb) { + rbtree_remove(mm, block); + if (is_clear) { + mark_cleared(block); + mm->clear_avail +=3D gpu_buddy_block_size(mm, block); + } else { + clear_reset(block); + mm->clear_avail -=3D gpu_buddy_block_size(mm, block); + } + + rbtree_insert(mm, block, dst_tree); + } + } +} +EXPORT_SYMBOL(gpu_buddy_reset_clear); + +/** + * gpu_buddy_free_block - free a block + * + * @mm: GPU buddy manager + * @block: block to be freed + */ +void gpu_buddy_free_block(struct gpu_buddy *mm, + struct gpu_buddy_block *block) +{ + BUG_ON(!gpu_buddy_block_is_allocated(block)); + mm->avail +=3D gpu_buddy_block_size(mm, block); + if (gpu_buddy_block_is_clear(block)) + mm->clear_avail +=3D gpu_buddy_block_size(mm, block); + + __gpu_buddy_free(mm, block, false); +} +EXPORT_SYMBOL(gpu_buddy_free_block); + +static void __gpu_buddy_free_list(struct gpu_buddy *mm, + struct list_head *objects, + bool mark_clear, + bool mark_dirty) +{ + struct gpu_buddy_block *block, *on; + + WARN_ON(mark_dirty && mark_clear); + + list_for_each_entry_safe(block, on, objects, link) { + if (mark_clear) + mark_cleared(block); + else if (mark_dirty) + clear_reset(block); + gpu_buddy_free_block(mm, block); + cond_resched(); + } + INIT_LIST_HEAD(objects); +} + +static void gpu_buddy_free_list_internal(struct gpu_buddy *mm, + struct list_head *objects) +{ + /* + * Don't touch the clear/dirty bit, since allocation is still internal + * at this point. For example we might have just failed part of the + * allocation. + */ + __gpu_buddy_free_list(mm, objects, false, false); +} + +/** + * gpu_buddy_free_list - free blocks + * + * @mm: GPU buddy manager + * @objects: input list head to free blocks + * @flags: optional flags like GPU_BUDDY_CLEARED + */ +void gpu_buddy_free_list(struct gpu_buddy *mm, + struct list_head *objects, + unsigned int flags) +{ + bool mark_clear =3D flags & GPU_BUDDY_CLEARED; + + __gpu_buddy_free_list(mm, objects, mark_clear, !mark_clear); +} +EXPORT_SYMBOL(gpu_buddy_free_list); + +static bool block_incompatible(struct gpu_buddy_block *block, unsigned int= flags) +{ + bool needs_clear =3D flags & GPU_BUDDY_CLEAR_ALLOCATION; + + return needs_clear !=3D gpu_buddy_block_is_clear(block); +} + +static struct gpu_buddy_block * +__alloc_range_bias(struct gpu_buddy *mm, + u64 start, u64 end, + unsigned int order, + unsigned long flags, + bool fallback) +{ + u64 req_size =3D mm->chunk_size << order; + struct gpu_buddy_block *block; + struct gpu_buddy_block *buddy; + LIST_HEAD(dfs); + int err; + int i; + + end =3D end - 1; + + for (i =3D 0; i < mm->n_roots; ++i) + list_add_tail(&mm->roots[i]->tmp_link, &dfs); + + do { + u64 block_start; + u64 block_end; + + block =3D list_first_entry_or_null(&dfs, + struct gpu_buddy_block, + tmp_link); + if (!block) + break; + + list_del(&block->tmp_link); + + if (gpu_buddy_block_order(block) < order) + continue; + + block_start =3D gpu_buddy_block_offset(block); + block_end =3D block_start + gpu_buddy_block_size(mm, block) - 1; + + if (!overlaps(start, end, block_start, block_end)) + continue; + + if (gpu_buddy_block_is_allocated(block)) + continue; + + if (block_start < start || block_end > end) { + u64 adjusted_start =3D max(block_start, start); + u64 adjusted_end =3D min(block_end, end); + + if (round_down(adjusted_end + 1, req_size) <=3D + round_up(adjusted_start, req_size)) + continue; + } + + if (!fallback && block_incompatible(block, flags)) + continue; + + if (contains(start, end, block_start, block_end) && + order =3D=3D gpu_buddy_block_order(block)) { + /* + * Find the free block within the range. + */ + if (gpu_buddy_block_is_free(block)) + return block; + + continue; + } + + if (!gpu_buddy_block_is_split(block)) { + err =3D split_block(mm, block); + if (unlikely(err)) + goto err_undo; + } + + list_add(&block->right->tmp_link, &dfs); + list_add(&block->left->tmp_link, &dfs); + } while (1); + + return ERR_PTR(-ENOSPC); + +err_undo: + /* + * We really don't want to leave around a bunch of split blocks, since + * bigger is better, so make sure we merge everything back before we + * free the allocated blocks. + */ + buddy =3D __get_buddy(block); + if (buddy && + (gpu_buddy_block_is_free(block) && + gpu_buddy_block_is_free(buddy))) + __gpu_buddy_free(mm, block, false); + return ERR_PTR(err); +} + +static struct gpu_buddy_block * +__gpu_buddy_alloc_range_bias(struct gpu_buddy *mm, + u64 start, u64 end, + unsigned int order, + unsigned long flags) +{ + struct gpu_buddy_block *block; + bool fallback =3D false; + + block =3D __alloc_range_bias(mm, start, end, order, + flags, fallback); + if (IS_ERR(block)) + return __alloc_range_bias(mm, start, end, order, + flags, !fallback); + + return block; +} + +static struct gpu_buddy_block * +get_maxblock(struct gpu_buddy *mm, + unsigned int order, + enum gpu_buddy_free_tree tree) +{ + struct gpu_buddy_block *max_block =3D NULL, *block =3D NULL; + struct rb_root *root; + unsigned int i; + + for (i =3D order; i <=3D mm->max_order; ++i) { + root =3D &mm->free_trees[tree][i]; + block =3D rbtree_last_free_block(root); + if (!block) + continue; + + if (!max_block) { + max_block =3D block; + continue; + } + + if (gpu_buddy_block_offset(block) > + gpu_buddy_block_offset(max_block)) { + max_block =3D block; + } + } + + return max_block; +} + +static struct gpu_buddy_block * +alloc_from_freetree(struct gpu_buddy *mm, + unsigned int order, + unsigned long flags) +{ + struct gpu_buddy_block *block =3D NULL; + struct rb_root *root; + enum gpu_buddy_free_tree tree; + unsigned int tmp; + int err; + + tree =3D (flags & GPU_BUDDY_CLEAR_ALLOCATION) ? + GPU_BUDDY_CLEAR_TREE : GPU_BUDDY_DIRTY_TREE; + + if (flags & GPU_BUDDY_TOPDOWN_ALLOCATION) { + block =3D get_maxblock(mm, order, tree); + if (block) + /* Store the obtained block order */ + tmp =3D gpu_buddy_block_order(block); + } else { + for (tmp =3D order; tmp <=3D mm->max_order; ++tmp) { + /* Get RB tree root for this order and tree */ + root =3D &mm->free_trees[tree][tmp]; + block =3D rbtree_last_free_block(root); + if (block) + break; + } + } + + if (!block) { + /* Try allocating from the other tree */ + tree =3D (tree =3D=3D GPU_BUDDY_CLEAR_TREE) ? + GPU_BUDDY_DIRTY_TREE : GPU_BUDDY_CLEAR_TREE; + + for (tmp =3D order; tmp <=3D mm->max_order; ++tmp) { + root =3D &mm->free_trees[tree][tmp]; + block =3D rbtree_last_free_block(root); + if (block) + break; + } + + if (!block) + return ERR_PTR(-ENOSPC); + } + + BUG_ON(!gpu_buddy_block_is_free(block)); + + while (tmp !=3D order) { + err =3D split_block(mm, block); + if (unlikely(err)) + goto err_undo; + + block =3D block->right; + tmp--; + } + return block; + +err_undo: + if (tmp !=3D order) + __gpu_buddy_free(mm, block, false); + return ERR_PTR(err); +} + +static int __alloc_range(struct gpu_buddy *mm, + struct list_head *dfs, + u64 start, u64 size, + struct list_head *blocks, + u64 *total_allocated_on_err) +{ + struct gpu_buddy_block *block; + struct gpu_buddy_block *buddy; + u64 total_allocated =3D 0; + LIST_HEAD(allocated); + u64 end; + int err; + + end =3D start + size - 1; + + do { + u64 block_start; + u64 block_end; + + block =3D list_first_entry_or_null(dfs, + struct gpu_buddy_block, + tmp_link); + if (!block) + break; + + list_del(&block->tmp_link); + + block_start =3D gpu_buddy_block_offset(block); + block_end =3D block_start + gpu_buddy_block_size(mm, block) - 1; + + if (!overlaps(start, end, block_start, block_end)) + continue; + + if (gpu_buddy_block_is_allocated(block)) { + err =3D -ENOSPC; + goto err_free; + } + + if (contains(start, end, block_start, block_end)) { + if (gpu_buddy_block_is_free(block)) { + mark_allocated(mm, block); + total_allocated +=3D gpu_buddy_block_size(mm, block); + mm->avail -=3D gpu_buddy_block_size(mm, block); + if (gpu_buddy_block_is_clear(block)) + mm->clear_avail -=3D gpu_buddy_block_size(mm, block); + list_add_tail(&block->link, &allocated); + continue; + } else if (!mm->clear_avail) { + err =3D -ENOSPC; + goto err_free; + } + } + + if (!gpu_buddy_block_is_split(block)) { + err =3D split_block(mm, block); + if (unlikely(err)) + goto err_undo; + } + + list_add(&block->right->tmp_link, dfs); + list_add(&block->left->tmp_link, dfs); + } while (1); + + if (total_allocated < size) { + err =3D -ENOSPC; + goto err_free; + } + + list_splice_tail(&allocated, blocks); + + return 0; + +err_undo: + /* + * We really don't want to leave around a bunch of split blocks, since + * bigger is better, so make sure we merge everything back before we + * free the allocated blocks. + */ + buddy =3D __get_buddy(block); + if (buddy && + (gpu_buddy_block_is_free(block) && + gpu_buddy_block_is_free(buddy))) + __gpu_buddy_free(mm, block, false); + +err_free: + if (err =3D=3D -ENOSPC && total_allocated_on_err) { + list_splice_tail(&allocated, blocks); + *total_allocated_on_err =3D total_allocated; + } else { + gpu_buddy_free_list_internal(mm, &allocated); + } + + return err; +} + +static int __gpu_buddy_alloc_range(struct gpu_buddy *mm, + u64 start, + u64 size, + u64 *total_allocated_on_err, + struct list_head *blocks) +{ + LIST_HEAD(dfs); + int i; + + for (i =3D 0; i < mm->n_roots; ++i) + list_add_tail(&mm->roots[i]->tmp_link, &dfs); + + return __alloc_range(mm, &dfs, start, size, + blocks, total_allocated_on_err); +} + +static int __alloc_contig_try_harder(struct gpu_buddy *mm, + u64 size, + u64 min_block_size, + struct list_head *blocks) +{ + u64 rhs_offset, lhs_offset, lhs_size, filled; + struct gpu_buddy_block *block; + unsigned int tree, order; + LIST_HEAD(blocks_lhs); + unsigned long pages; + u64 modify_size; + int err; + + modify_size =3D rounddown_pow_of_two(size); + pages =3D modify_size >> ilog2(mm->chunk_size); + order =3D fls(pages) - 1; + if (order =3D=3D 0) + return -ENOSPC; + + for_each_free_tree(tree) { + struct rb_root *root; + struct rb_node *iter; + + root =3D &mm->free_trees[tree][order]; + if (rbtree_is_empty(root)) + continue; + + iter =3D rb_last(root); + while (iter) { + block =3D rbtree_get_free_block(iter); + + /* Allocate blocks traversing RHS */ + rhs_offset =3D gpu_buddy_block_offset(block); + err =3D __gpu_buddy_alloc_range(mm, rhs_offset, size, + &filled, blocks); + if (!err || err !=3D -ENOSPC) + return err; + + lhs_size =3D max((size - filled), min_block_size); + if (!IS_ALIGNED(lhs_size, min_block_size)) + lhs_size =3D round_up(lhs_size, min_block_size); + + /* Allocate blocks traversing LHS */ + lhs_offset =3D gpu_buddy_block_offset(block) - lhs_size; + err =3D __gpu_buddy_alloc_range(mm, lhs_offset, lhs_size, + NULL, &blocks_lhs); + if (!err) { + list_splice(&blocks_lhs, blocks); + return 0; + } else if (err !=3D -ENOSPC) { + gpu_buddy_free_list_internal(mm, blocks); + return err; + } + /* Free blocks for the next iteration */ + gpu_buddy_free_list_internal(mm, blocks); + + iter =3D rb_prev(iter); + } + } + + return -ENOSPC; +} + +/** + * gpu_buddy_block_trim - free unused pages + * + * @mm: GPU buddy manager + * @start: start address to begin the trimming. + * @new_size: original size requested + * @blocks: Input and output list of allocated blocks. + * MUST contain single block as input to be trimmed. + * On success will contain the newly allocated blocks + * making up the @new_size. Blocks always appear in + * ascending order + * + * For contiguous allocation, we round up the size to the nearest + * power of two value, drivers consume *actual* size, so remaining + * portions are unused and can be optionally freed with this function + * + * Returns: + * 0 on success, error code on failure. + */ +int gpu_buddy_block_trim(struct gpu_buddy *mm, + u64 *start, + u64 new_size, + struct list_head *blocks) +{ + struct gpu_buddy_block *parent; + struct gpu_buddy_block *block; + u64 block_start, block_end; + LIST_HEAD(dfs); + u64 new_start; + int err; + + if (!list_is_singular(blocks)) + return -EINVAL; + + block =3D list_first_entry(blocks, + struct gpu_buddy_block, + link); + + block_start =3D gpu_buddy_block_offset(block); + block_end =3D block_start + gpu_buddy_block_size(mm, block); + + if (WARN_ON(!gpu_buddy_block_is_allocated(block))) + return -EINVAL; + + if (new_size > gpu_buddy_block_size(mm, block)) + return -EINVAL; + + if (!new_size || !IS_ALIGNED(new_size, mm->chunk_size)) + return -EINVAL; + + if (new_size =3D=3D gpu_buddy_block_size(mm, block)) + return 0; + + new_start =3D block_start; + if (start) { + new_start =3D *start; + + if (new_start < block_start) + return -EINVAL; + + if (!IS_ALIGNED(new_start, mm->chunk_size)) + return -EINVAL; + + if (range_overflows(new_start, new_size, block_end)) + return -EINVAL; + } + + list_del(&block->link); + mark_free(mm, block); + mm->avail +=3D gpu_buddy_block_size(mm, block); + if (gpu_buddy_block_is_clear(block)) + mm->clear_avail +=3D gpu_buddy_block_size(mm, block); + + /* Prevent recursively freeing this node */ + parent =3D block->parent; + block->parent =3D NULL; + + list_add(&block->tmp_link, &dfs); + err =3D __alloc_range(mm, &dfs, new_start, new_size, blocks, NULL); + if (err) { + mark_allocated(mm, block); + mm->avail -=3D gpu_buddy_block_size(mm, block); + if (gpu_buddy_block_is_clear(block)) + mm->clear_avail -=3D gpu_buddy_block_size(mm, block); + list_add(&block->link, blocks); + } + + block->parent =3D parent; + return err; +} +EXPORT_SYMBOL(gpu_buddy_block_trim); + +static struct gpu_buddy_block * +__gpu_buddy_alloc_blocks(struct gpu_buddy *mm, + u64 start, u64 end, + unsigned int order, + unsigned long flags) +{ + if (flags & GPU_BUDDY_RANGE_ALLOCATION) + /* Allocate traversing within the range */ + return __gpu_buddy_alloc_range_bias(mm, start, end, + order, flags); + else + /* Allocate from freetree */ + return alloc_from_freetree(mm, order, flags); +} + +/** + * gpu_buddy_alloc_blocks - allocate power-of-two blocks + * + * @mm: GPU buddy manager to allocate from + * @start: start of the allowed range for this block + * @end: end of the allowed range for this block + * @size: size of the allocation in bytes + * @min_block_size: alignment of the allocation + * @blocks: output list head to add allocated blocks + * @flags: GPU_BUDDY_*_ALLOCATION flags + * + * alloc_range_bias() called on range limitations, which traverses + * the tree and returns the desired block. + * + * alloc_from_freetree() called when *no* range restrictions + * are enforced, which picks the block from the freetree. + * + * Returns: + * 0 on success, error code on failure. + */ +int gpu_buddy_alloc_blocks(struct gpu_buddy *mm, + u64 start, u64 end, u64 size, + u64 min_block_size, + struct list_head *blocks, + unsigned long flags) +{ + struct gpu_buddy_block *block =3D NULL; + u64 original_size, original_min_size; + unsigned int min_order, order; + LIST_HEAD(allocated); + unsigned long pages; + int err; + + if (size < mm->chunk_size) + return -EINVAL; + + if (min_block_size < mm->chunk_size) + return -EINVAL; + + if (!is_power_of_2(min_block_size)) + return -EINVAL; + + if (!IS_ALIGNED(start | end | size, mm->chunk_size)) + return -EINVAL; + + if (end > mm->size) + return -EINVAL; + + if (range_overflows(start, size, mm->size)) + return -EINVAL; + + /* Actual range allocation */ + if (start + size =3D=3D end) { + if (!IS_ALIGNED(start | end, min_block_size)) + return -EINVAL; + + return __gpu_buddy_alloc_range(mm, start, size, NULL, blocks); + } + + original_size =3D size; + original_min_size =3D min_block_size; + + /* Roundup the size to power of 2 */ + if (flags & GPU_BUDDY_CONTIGUOUS_ALLOCATION) { + size =3D roundup_pow_of_two(size); + min_block_size =3D size; + /* Align size value to min_block_size */ + } else if (!IS_ALIGNED(size, min_block_size)) { + size =3D round_up(size, min_block_size); + } + + pages =3D size >> ilog2(mm->chunk_size); + order =3D fls(pages) - 1; + min_order =3D ilog2(min_block_size) - ilog2(mm->chunk_size); + + do { + order =3D min(order, (unsigned int)fls(pages) - 1); + BUG_ON(order > mm->max_order); + BUG_ON(order < min_order); + + do { + block =3D __gpu_buddy_alloc_blocks(mm, start, + end, + order, + flags); + if (!IS_ERR(block)) + break; + + if (order-- =3D=3D min_order) { + /* Try allocation through force merge method */ + if (mm->clear_avail && + !__force_merge(mm, start, end, min_order)) { + block =3D __gpu_buddy_alloc_blocks(mm, start, + end, + min_order, + flags); + if (!IS_ERR(block)) { + order =3D min_order; + break; + } + } + + /* + * Try contiguous block allocation through + * try harder method. + */ + if (flags & GPU_BUDDY_CONTIGUOUS_ALLOCATION && + !(flags & GPU_BUDDY_RANGE_ALLOCATION)) + return __alloc_contig_try_harder(mm, + original_size, + original_min_size, + blocks); + err =3D -ENOSPC; + goto err_free; + } + } while (1); + + mark_allocated(mm, block); + mm->avail -=3D gpu_buddy_block_size(mm, block); + if (gpu_buddy_block_is_clear(block)) + mm->clear_avail -=3D gpu_buddy_block_size(mm, block); + kmemleak_update_trace(block); + list_add_tail(&block->link, &allocated); + + pages -=3D BIT(order); + + if (!pages) + break; + } while (1); + + /* Trim the allocated block to the required size */ + if (!(flags & GPU_BUDDY_TRIM_DISABLE) && + original_size !=3D size) { + struct list_head *trim_list; + LIST_HEAD(temp); + u64 trim_size; + + trim_list =3D &allocated; + trim_size =3D original_size; + + if (!list_is_singular(&allocated)) { + block =3D list_last_entry(&allocated, typeof(*block), link); + list_move(&block->link, &temp); + trim_list =3D &temp; + trim_size =3D gpu_buddy_block_size(mm, block) - + (size - original_size); + } + + gpu_buddy_block_trim(mm, + NULL, + trim_size, + trim_list); + + if (!list_empty(&temp)) + list_splice_tail(trim_list, &allocated); + } + + list_splice_tail(&allocated, blocks); + return 0; + +err_free: + gpu_buddy_free_list_internal(mm, &allocated); + return err; +} +EXPORT_SYMBOL(gpu_buddy_alloc_blocks); + +/** + * gpu_buddy_block_print - print block information + * + * @mm: GPU buddy manager + * @block: GPU buddy block + */ +void gpu_buddy_block_print(struct gpu_buddy *mm, + struct gpu_buddy_block *block) +{ + u64 start =3D gpu_buddy_block_offset(block); + u64 size =3D gpu_buddy_block_size(mm, block); + + pr_info("%#018llx-%#018llx: %llu\n", start, start + size, size); +} +EXPORT_SYMBOL(gpu_buddy_block_print); + +/** + * gpu_buddy_print - print allocator state + * + * @mm: GPU buddy manager + */ +void gpu_buddy_print(struct gpu_buddy *mm) +{ + int order; + + pr_info("chunk_size: %lluKiB, total: %lluMiB, free: %lluMiB, clear_free: = %lluMiB\n", + mm->chunk_size >> 10, mm->size >> 20, mm->avail >> 20, mm->clear_avail >= > 20); + + for (order =3D mm->max_order; order >=3D 0; order--) { + struct gpu_buddy_block *block, *tmp; + struct rb_root *root; + u64 count =3D 0, free; + unsigned int tree; + + for_each_free_tree(tree) { + root =3D &mm->free_trees[tree][order]; + + rbtree_postorder_for_each_entry_safe(block, tmp, root, rb) { + BUG_ON(!gpu_buddy_block_is_free(block)); + count++; + } + } + + free =3D count * (mm->chunk_size << order); + if (free < SZ_1M) + pr_info("order-%2d free: %8llu KiB, blocks: %llu\n", + order, free >> 10, count); + else + pr_info("order-%2d free: %8llu MiB, blocks: %llu\n", + order, free >> 20, count); + } +} +EXPORT_SYMBOL(gpu_buddy_print); + +static void gpu_buddy_module_exit(void) +{ + kmem_cache_destroy(slab_blocks); +} + +static int __init gpu_buddy_module_init(void) +{ + slab_blocks =3D KMEM_CACHE(gpu_buddy_block, 0); + if (!slab_blocks) + return -ENOMEM; + + return 0; +} + +module_init(gpu_buddy_module_init); +module_exit(gpu_buddy_module_exit); + +MODULE_DESCRIPTION("GPU Buddy Allocator"); +MODULE_LICENSE("Dual MIT/GPL"); diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index 7e6bc0b3a589..0475defb37f0 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -220,6 +220,7 @@ config DRM_GPUSVM config DRM_BUDDY tristate depends on DRM + select GPU_BUDDY help A page based buddy allocator =20 diff --git a/drivers/gpu/drm/Kconfig.debug b/drivers/gpu/drm/Kconfig.debug index 05dc43c0b8c5..1f4c408c7920 100644 --- a/drivers/gpu/drm/Kconfig.debug +++ b/drivers/gpu/drm/Kconfig.debug @@ -71,6 +71,7 @@ config DRM_KUNIT_TEST select DRM_KUNIT_TEST_HELPERS select DRM_LIB_RANDOM select DRM_SYSFB_HELPER + select GPU_BUDDY select PRIME_NUMBERS default KUNIT_ALL_TESTS help @@ -88,10 +89,11 @@ config DRM_TTM_KUNIT_TEST tristate "KUnit tests for TTM" if !KUNIT_ALL_TESTS default n depends on DRM && KUNIT && MMU && (UML || COMPILE_TEST) - select DRM_TTM select DRM_BUDDY + select DRM_TTM select DRM_EXPORT_FOR_TESTS if m select DRM_KUNIT_TEST_HELPERS + select GPU_BUDDY default KUNIT_ALL_TESTS help Enables unit tests for TTM, a GPU memory manager subsystem used diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig b/drivers/gpu/drm/amd/amdgp= u/Kconfig index 7f515be5185d..bb131543e1d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/Kconfig +++ b/drivers/gpu/drm/amd/amdgpu/Kconfig @@ -23,6 +23,7 @@ config DRM_AMDGPU select CRC16 select BACKLIGHT_CLASS_DEVICE select INTERVAL_TREE + select GPU_BUDDY select DRM_BUDDY select DRM_SUBALLOC_HELPER select DRM_EXEC diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_ras.c index 2a6cf7963dde..e0bd8a68877f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -5654,7 +5654,7 @@ int amdgpu_ras_add_critical_region(struct amdgpu_devi= ce *adev, struct amdgpu_ras *con =3D amdgpu_ras_get_context(adev); struct amdgpu_vram_mgr_resource *vres; struct ras_critical_region *region; - struct drm_buddy_block *block; + struct gpu_buddy_block *block; int ret =3D 0; =20 if (!bo || !bo->tbo.resource) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h b/drivers/gpu/d= rm/amd/amdgpu/amdgpu_res_cursor.h index be2e56ce1355..8908d9e08a30 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h @@ -55,7 +55,7 @@ static inline void amdgpu_res_first(struct ttm_resource *= res, uint64_t start, uint64_t size, struct amdgpu_res_cursor *cur) { - struct drm_buddy_block *block; + struct gpu_buddy_block *block; struct list_head *head, *next; struct drm_mm_node *node; =20 @@ -71,7 +71,7 @@ static inline void amdgpu_res_first(struct ttm_resource *= res, head =3D &to_amdgpu_vram_mgr_resource(res)->blocks; =20 block =3D list_first_entry_or_null(head, - struct drm_buddy_block, + struct gpu_buddy_block, link); if (!block) goto fallback; @@ -81,7 +81,7 @@ static inline void amdgpu_res_first(struct ttm_resource *= res, =20 next =3D block->link.next; if (next !=3D head) - block =3D list_entry(next, struct drm_buddy_block, link); + block =3D list_entry(next, struct gpu_buddy_block, link); } =20 cur->start =3D amdgpu_vram_mgr_block_start(block) + start; @@ -125,7 +125,7 @@ static inline void amdgpu_res_first(struct ttm_resource= *res, */ static inline void amdgpu_res_next(struct amdgpu_res_cursor *cur, uint64_t= size) { - struct drm_buddy_block *block; + struct gpu_buddy_block *block; struct drm_mm_node *node; struct list_head *next; =20 @@ -146,7 +146,7 @@ static inline void amdgpu_res_next(struct amdgpu_res_cu= rsor *cur, uint64_t size) block =3D cur->node; =20 next =3D block->link.next; - block =3D list_entry(next, struct drm_buddy_block, link); + block =3D list_entry(next, struct gpu_buddy_block, link); =20 cur->node =3D block; cur->start =3D amdgpu_vram_mgr_block_start(block); @@ -175,7 +175,7 @@ static inline void amdgpu_res_next(struct amdgpu_res_cu= rsor *cur, uint64_t size) */ static inline bool amdgpu_res_cleared(struct amdgpu_res_cursor *cur) { - struct drm_buddy_block *block; + struct gpu_buddy_block *block; =20 switch (cur->mem_type) { case TTM_PL_VRAM: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm= /amd/amdgpu/amdgpu_vram_mgr.c index 9d934c07fa6b..6c06a9c9b13f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -23,6 +23,8 @@ */ =20 #include + +#include #include #include =20 @@ -52,15 +54,15 @@ to_amdgpu_device(struct amdgpu_vram_mgr *mgr) return container_of(mgr, struct amdgpu_device, mman.vram_mgr); } =20 -static inline struct drm_buddy_block * +static inline struct gpu_buddy_block * amdgpu_vram_mgr_first_block(struct list_head *list) { - return list_first_entry_or_null(list, struct drm_buddy_block, link); + return list_first_entry_or_null(list, struct gpu_buddy_block, link); } =20 static inline bool amdgpu_is_vram_mgr_blocks_contiguous(struct list_head *= head) { - struct drm_buddy_block *block; + struct gpu_buddy_block *block; u64 start, size; =20 block =3D amdgpu_vram_mgr_first_block(head); @@ -71,7 +73,7 @@ static inline bool amdgpu_is_vram_mgr_blocks_contiguous(s= truct list_head *head) start =3D amdgpu_vram_mgr_block_start(block); size =3D amdgpu_vram_mgr_block_size(block); =20 - block =3D list_entry(block->link.next, struct drm_buddy_block, link); + block =3D list_entry(block->link.next, struct gpu_buddy_block, link); if (start + size !=3D amdgpu_vram_mgr_block_start(block)) return false; } @@ -81,7 +83,7 @@ static inline bool amdgpu_is_vram_mgr_blocks_contiguous(s= truct list_head *head) =20 static inline u64 amdgpu_vram_mgr_blocks_size(struct list_head *head) { - struct drm_buddy_block *block; + struct gpu_buddy_block *block; u64 size =3D 0; =20 list_for_each_entry(block, head, link) @@ -254,7 +256,7 @@ const struct attribute_group amdgpu_vram_mgr_attr_group= =3D { * Calculate how many bytes of the DRM BUDDY block are inside visible VRAM */ static u64 amdgpu_vram_mgr_vis_size(struct amdgpu_device *adev, - struct drm_buddy_block *block) + struct gpu_buddy_block *block) { u64 start =3D amdgpu_vram_mgr_block_start(block); u64 end =3D start + amdgpu_vram_mgr_block_size(block); @@ -279,7 +281,7 @@ u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *b= o) struct amdgpu_device *adev =3D amdgpu_ttm_adev(bo->tbo.bdev); struct ttm_resource *res =3D bo->tbo.resource; struct amdgpu_vram_mgr_resource *vres =3D to_amdgpu_vram_mgr_resource(res= ); - struct drm_buddy_block *block; + struct gpu_buddy_block *block; u64 usage =3D 0; =20 if (amdgpu_gmc_vram_full_visible(&adev->gmc)) @@ -299,15 +301,15 @@ static void amdgpu_vram_mgr_do_reserve(struct ttm_res= ource_manager *man) { struct amdgpu_vram_mgr *mgr =3D to_vram_mgr(man); struct amdgpu_device *adev =3D to_amdgpu_device(mgr); - struct drm_buddy *mm =3D &mgr->mm; + struct gpu_buddy *mm =3D &mgr->mm; struct amdgpu_vram_reservation *rsv, *temp; - struct drm_buddy_block *block; + struct gpu_buddy_block *block; uint64_t vis_usage; =20 list_for_each_entry_safe(rsv, temp, &mgr->reservations_pending, blocks) { - if (drm_buddy_alloc_blocks(mm, rsv->start, rsv->start + rsv->size, + if (gpu_buddy_alloc_blocks(mm, rsv->start, rsv->start + rsv->size, rsv->size, mm->chunk_size, &rsv->allocated, - DRM_BUDDY_RANGE_ALLOCATION)) + GPU_BUDDY_RANGE_ALLOCATION)) continue; =20 block =3D amdgpu_vram_mgr_first_block(&rsv->allocated); @@ -403,7 +405,7 @@ int amdgpu_vram_mgr_query_address_block_info(struct amd= gpu_vram_mgr *mgr, uint64_t address, struct amdgpu_vram_block_info *info) { struct amdgpu_vram_mgr_resource *vres; - struct drm_buddy_block *block; + struct gpu_buddy_block *block; u64 start, size; int ret =3D -ENOENT; =20 @@ -450,8 +452,8 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_mana= ger *man, struct amdgpu_vram_mgr_resource *vres; u64 size, remaining_size, lpfn, fpfn; unsigned int adjust_dcc_size =3D 0; - struct drm_buddy *mm =3D &mgr->mm; - struct drm_buddy_block *block; + struct gpu_buddy *mm =3D &mgr->mm; + struct gpu_buddy_block *block; unsigned long pages_per_block; int r; =20 @@ -493,17 +495,17 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_ma= nager *man, INIT_LIST_HEAD(&vres->blocks); =20 if (place->flags & TTM_PL_FLAG_TOPDOWN) - vres->flags |=3D DRM_BUDDY_TOPDOWN_ALLOCATION; + vres->flags |=3D GPU_BUDDY_TOPDOWN_ALLOCATION; =20 if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) - vres->flags |=3D DRM_BUDDY_CONTIGUOUS_ALLOCATION; + vres->flags |=3D GPU_BUDDY_CONTIGUOUS_ALLOCATION; =20 if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED) - vres->flags |=3D DRM_BUDDY_CLEAR_ALLOCATION; + vres->flags |=3D GPU_BUDDY_CLEAR_ALLOCATION; =20 if (fpfn || lpfn !=3D mgr->mm.size) /* Allocate blocks in desired range */ - vres->flags |=3D DRM_BUDDY_RANGE_ALLOCATION; + vres->flags |=3D GPU_BUDDY_RANGE_ALLOCATION; =20 if (bo->flags & AMDGPU_GEM_CREATE_GFX12_DCC && adev->gmc.gmc_funcs->get_dcc_alignment) @@ -516,7 +518,7 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_mana= ger *man, dcc_size =3D roundup_pow_of_two(vres->base.size + adjust_dcc_size); remaining_size =3D (u64)dcc_size; =20 - vres->flags |=3D DRM_BUDDY_TRIM_DISABLE; + vres->flags |=3D GPU_BUDDY_TRIM_DISABLE; } =20 mutex_lock(&mgr->lock); @@ -536,7 +538,7 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_mana= ger *man, =20 BUG_ON(min_block_size < mm->chunk_size); =20 - r =3D drm_buddy_alloc_blocks(mm, fpfn, + r =3D gpu_buddy_alloc_blocks(mm, fpfn, lpfn, size, min_block_size, @@ -545,7 +547,7 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_mana= ger *man, =20 if (unlikely(r =3D=3D -ENOSPC) && pages_per_block =3D=3D ~0ul && !(place->flags & TTM_PL_FLAG_CONTIGUOUS)) { - vres->flags &=3D ~DRM_BUDDY_CONTIGUOUS_ALLOCATION; + vres->flags &=3D ~GPU_BUDDY_CONTIGUOUS_ALLOCATION; pages_per_block =3D max_t(u32, 2UL << (20UL - PAGE_SHIFT), tbo->page_alignment); =20 @@ -566,7 +568,7 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_mana= ger *man, list_add_tail(&vres->vres_node, &mgr->allocated_vres_list); =20 if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS && adjust_dcc_size) { - struct drm_buddy_block *dcc_block; + struct gpu_buddy_block *dcc_block; unsigned long dcc_start; u64 trim_start; =20 @@ -576,7 +578,7 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_mana= ger *man, roundup((unsigned long)amdgpu_vram_mgr_block_start(dcc_block), adjust_dcc_size); trim_start =3D (u64)dcc_start; - drm_buddy_block_trim(mm, &trim_start, + gpu_buddy_block_trim(mm, &trim_start, (u64)vres->base.size, &vres->blocks); } @@ -614,7 +616,7 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_mana= ger *man, return 0; =20 error_free_blocks: - drm_buddy_free_list(mm, &vres->blocks, 0); + gpu_buddy_free_list(mm, &vres->blocks, 0); mutex_unlock(&mgr->lock); error_fini: ttm_resource_fini(man, &vres->base); @@ -637,8 +639,8 @@ static void amdgpu_vram_mgr_del(struct ttm_resource_man= ager *man, struct amdgpu_vram_mgr_resource *vres =3D to_amdgpu_vram_mgr_resource(res= ); struct amdgpu_vram_mgr *mgr =3D to_vram_mgr(man); struct amdgpu_device *adev =3D to_amdgpu_device(mgr); - struct drm_buddy *mm =3D &mgr->mm; - struct drm_buddy_block *block; + struct gpu_buddy *mm =3D &mgr->mm; + struct gpu_buddy_block *block; uint64_t vis_usage =3D 0; =20 mutex_lock(&mgr->lock); @@ -649,7 +651,7 @@ static void amdgpu_vram_mgr_del(struct ttm_resource_man= ager *man, list_for_each_entry(block, &vres->blocks, link) vis_usage +=3D amdgpu_vram_mgr_vis_size(adev, block); =20 - drm_buddy_free_list(mm, &vres->blocks, vres->flags); + gpu_buddy_free_list(mm, &vres->blocks, vres->flags); amdgpu_vram_mgr_do_reserve(man); mutex_unlock(&mgr->lock); =20 @@ -688,7 +690,7 @@ int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *ade= v, if (!*sgt) return -ENOMEM; =20 - /* Determine the number of DRM_BUDDY blocks to export */ + /* Determine the number of GPU_BUDDY blocks to export */ amdgpu_res_first(res, offset, length, &cursor); while (cursor.remaining) { num_entries++; @@ -704,10 +706,10 @@ int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *a= dev, sg->length =3D 0; =20 /* - * Walk down DRM_BUDDY blocks to populate scatterlist nodes - * @note: Use iterator api to get first the DRM_BUDDY block + * Walk down GPU_BUDDY blocks to populate scatterlist nodes + * @note: Use iterator api to get first the GPU_BUDDY block * and the number of bytes from it. Access the following - * DRM_BUDDY block(s) if more buffer needs to exported + * GPU_BUDDY block(s) if more buffer needs to exported */ amdgpu_res_first(res, offset, length, &cursor); for_each_sgtable_sg((*sgt), sg, i) { @@ -792,10 +794,10 @@ uint64_t amdgpu_vram_mgr_vis_usage(struct amdgpu_vram= _mgr *mgr) void amdgpu_vram_mgr_clear_reset_blocks(struct amdgpu_device *adev) { struct amdgpu_vram_mgr *mgr =3D &adev->mman.vram_mgr; - struct drm_buddy *mm =3D &mgr->mm; + struct gpu_buddy *mm =3D &mgr->mm; =20 mutex_lock(&mgr->lock); - drm_buddy_reset_clear(mm, false); + gpu_buddy_reset_clear(mm, false); mutex_unlock(&mgr->lock); } =20 @@ -815,7 +817,7 @@ static bool amdgpu_vram_mgr_intersects(struct ttm_resou= rce_manager *man, size_t size) { struct amdgpu_vram_mgr_resource *mgr =3D to_amdgpu_vram_mgr_resource(res); - struct drm_buddy_block *block; + struct gpu_buddy_block *block; =20 /* Check each drm buddy block individually */ list_for_each_entry(block, &mgr->blocks, link) { @@ -848,7 +850,7 @@ static bool amdgpu_vram_mgr_compatible(struct ttm_resou= rce_manager *man, size_t size) { struct amdgpu_vram_mgr_resource *mgr =3D to_amdgpu_vram_mgr_resource(res); - struct drm_buddy_block *block; + struct gpu_buddy_block *block; =20 /* Check each drm buddy block individually */ list_for_each_entry(block, &mgr->blocks, link) { @@ -877,7 +879,7 @@ static void amdgpu_vram_mgr_debug(struct ttm_resource_m= anager *man, struct drm_printer *printer) { struct amdgpu_vram_mgr *mgr =3D to_vram_mgr(man); - struct drm_buddy *mm =3D &mgr->mm; + struct gpu_buddy *mm =3D &mgr->mm; struct amdgpu_vram_reservation *rsv; =20 drm_printf(printer, " vis usage:%llu\n", @@ -930,7 +932,7 @@ int amdgpu_vram_mgr_init(struct amdgpu_device *adev) mgr->default_page_size =3D PAGE_SIZE; =20 man->func =3D &amdgpu_vram_mgr_func; - err =3D drm_buddy_init(&mgr->mm, man->size, PAGE_SIZE); + err =3D gpu_buddy_init(&mgr->mm, man->size, PAGE_SIZE); if (err) return err; =20 @@ -965,11 +967,11 @@ void amdgpu_vram_mgr_fini(struct amdgpu_device *adev) kfree(rsv); =20 list_for_each_entry_safe(rsv, temp, &mgr->reserved_pages, blocks) { - drm_buddy_free_list(&mgr->mm, &rsv->allocated, 0); + gpu_buddy_free_list(&mgr->mm, &rsv->allocated, 0); kfree(rsv); } if (!adev->gmc.is_app_apu) - drm_buddy_fini(&mgr->mm); + gpu_buddy_fini(&mgr->mm); mutex_unlock(&mgr->lock); =20 ttm_resource_manager_cleanup(man); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h b/drivers/gpu/drm= /amd/amdgpu/amdgpu_vram_mgr.h index 5f5fd9a911c2..429a21a2e9b2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h @@ -24,11 +24,11 @@ #ifndef __AMDGPU_VRAM_MGR_H__ #define __AMDGPU_VRAM_MGR_H__ =20 -#include +#include =20 struct amdgpu_vram_mgr { struct ttm_resource_manager manager; - struct drm_buddy mm; + struct gpu_buddy mm; /* protects access to buffer objects */ struct mutex lock; struct list_head reservations_pending; @@ -57,19 +57,19 @@ struct amdgpu_vram_mgr_resource { struct amdgpu_vres_task task; }; =20 -static inline u64 amdgpu_vram_mgr_block_start(struct drm_buddy_block *bloc= k) +static inline u64 amdgpu_vram_mgr_block_start(struct gpu_buddy_block *bloc= k) { - return drm_buddy_block_offset(block); + return gpu_buddy_block_offset(block); } =20 -static inline u64 amdgpu_vram_mgr_block_size(struct drm_buddy_block *block) +static inline u64 amdgpu_vram_mgr_block_size(struct gpu_buddy_block *block) { - return (u64)PAGE_SIZE << drm_buddy_block_order(block); + return (u64)PAGE_SIZE << gpu_buddy_block_order(block); } =20 -static inline bool amdgpu_vram_mgr_is_cleared(struct drm_buddy_block *bloc= k) +static inline bool amdgpu_vram_mgr_is_cleared(struct gpu_buddy_block *bloc= k) { - return drm_buddy_block_is_clear(block); + return gpu_buddy_block_is_clear(block); } =20 static inline struct amdgpu_vram_mgr_resource * @@ -82,8 +82,8 @@ static inline void amdgpu_vram_mgr_set_cleared(struct ttm= _resource *res) { struct amdgpu_vram_mgr_resource *ares =3D to_amdgpu_vram_mgr_resource(res= ); =20 - WARN_ON(ares->flags & DRM_BUDDY_CLEARED); - ares->flags |=3D DRM_BUDDY_CLEARED; + WARN_ON(ares->flags & GPU_BUDDY_CLEARED); + ares->flags |=3D GPU_BUDDY_CLEARED; } =20 int amdgpu_vram_mgr_query_address_block_info(struct amdgpu_vram_mgr *mgr, diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c index 2f279b46bd2c..188b36054e59 100644 --- a/drivers/gpu/drm/drm_buddy.c +++ b/drivers/gpu/drm/drm_buddy.c @@ -3,1262 +3,25 @@ * Copyright =C2=A9 2021 Intel Corporation */ =20 -#include - #include -#include #include #include =20 #include #include =20 -enum drm_buddy_free_tree { - DRM_BUDDY_CLEAR_TREE =3D 0, - DRM_BUDDY_DIRTY_TREE, - DRM_BUDDY_MAX_FREE_TREES, -}; - -static struct kmem_cache *slab_blocks; - -#define for_each_free_tree(tree) \ - for ((tree) =3D 0; (tree) < DRM_BUDDY_MAX_FREE_TREES; (tree)++) - -static struct drm_buddy_block *drm_block_alloc(struct drm_buddy *mm, - struct drm_buddy_block *parent, - unsigned int order, - u64 offset) -{ - struct drm_buddy_block *block; - - BUG_ON(order > DRM_BUDDY_MAX_ORDER); - - block =3D kmem_cache_zalloc(slab_blocks, GFP_KERNEL); - if (!block) - return NULL; - - block->header =3D offset; - block->header |=3D order; - block->parent =3D parent; - - RB_CLEAR_NODE(&block->rb); - - BUG_ON(block->header & DRM_BUDDY_HEADER_UNUSED); - return block; -} - -static void drm_block_free(struct drm_buddy *mm, - struct drm_buddy_block *block) -{ - kmem_cache_free(slab_blocks, block); -} - -static enum drm_buddy_free_tree -get_block_tree(struct drm_buddy_block *block) -{ - return drm_buddy_block_is_clear(block) ? - DRM_BUDDY_CLEAR_TREE : DRM_BUDDY_DIRTY_TREE; -} - -static struct drm_buddy_block * -rbtree_get_free_block(const struct rb_node *node) -{ - return node ? rb_entry(node, struct drm_buddy_block, rb) : NULL; -} - -static struct drm_buddy_block * -rbtree_last_free_block(struct rb_root *root) -{ - return rbtree_get_free_block(rb_last(root)); -} - -static bool rbtree_is_empty(struct rb_root *root) -{ - return RB_EMPTY_ROOT(root); -} - -static bool drm_buddy_block_offset_less(const struct drm_buddy_block *bloc= k, - const struct drm_buddy_block *node) -{ - return drm_buddy_block_offset(block) < drm_buddy_block_offset(node); -} - -static bool rbtree_block_offset_less(struct rb_node *block, - const struct rb_node *node) -{ - return drm_buddy_block_offset_less(rbtree_get_free_block(block), - rbtree_get_free_block(node)); -} - -static void rbtree_insert(struct drm_buddy *mm, - struct drm_buddy_block *block, - enum drm_buddy_free_tree tree) -{ - rb_add(&block->rb, - &mm->free_trees[tree][drm_buddy_block_order(block)], - rbtree_block_offset_less); -} - -static void rbtree_remove(struct drm_buddy *mm, - struct drm_buddy_block *block) -{ - unsigned int order =3D drm_buddy_block_order(block); - enum drm_buddy_free_tree tree; - struct rb_root *root; - - tree =3D get_block_tree(block); - root =3D &mm->free_trees[tree][order]; - - rb_erase(&block->rb, root); - RB_CLEAR_NODE(&block->rb); -} - -static void clear_reset(struct drm_buddy_block *block) -{ - block->header &=3D ~DRM_BUDDY_HEADER_CLEAR; -} - -static void mark_cleared(struct drm_buddy_block *block) -{ - block->header |=3D DRM_BUDDY_HEADER_CLEAR; -} - -static void mark_allocated(struct drm_buddy *mm, - struct drm_buddy_block *block) -{ - block->header &=3D ~DRM_BUDDY_HEADER_STATE; - block->header |=3D DRM_BUDDY_ALLOCATED; - - rbtree_remove(mm, block); -} - -static void mark_free(struct drm_buddy *mm, - struct drm_buddy_block *block) -{ - enum drm_buddy_free_tree tree; - - block->header &=3D ~DRM_BUDDY_HEADER_STATE; - block->header |=3D DRM_BUDDY_FREE; - - tree =3D get_block_tree(block); - rbtree_insert(mm, block, tree); -} - -static void mark_split(struct drm_buddy *mm, - struct drm_buddy_block *block) -{ - block->header &=3D ~DRM_BUDDY_HEADER_STATE; - block->header |=3D DRM_BUDDY_SPLIT; - - rbtree_remove(mm, block); -} - -static inline bool overlaps(u64 s1, u64 e1, u64 s2, u64 e2) -{ - return s1 <=3D e2 && e1 >=3D s2; -} - -static inline bool contains(u64 s1, u64 e1, u64 s2, u64 e2) -{ - return s1 <=3D s2 && e1 >=3D e2; -} - -static struct drm_buddy_block * -__get_buddy(struct drm_buddy_block *block) -{ - struct drm_buddy_block *parent; - - parent =3D block->parent; - if (!parent) - return NULL; - - if (parent->left =3D=3D block) - return parent->right; - - return parent->left; -} - -static unsigned int __drm_buddy_free(struct drm_buddy *mm, - struct drm_buddy_block *block, - bool force_merge) -{ - struct drm_buddy_block *parent; - unsigned int order; - - while ((parent =3D block->parent)) { - struct drm_buddy_block *buddy; - - buddy =3D __get_buddy(block); - - if (!drm_buddy_block_is_free(buddy)) - break; - - if (!force_merge) { - /* - * Check the block and its buddy clear state and exit - * the loop if they both have the dissimilar state. - */ - if (drm_buddy_block_is_clear(block) !=3D - drm_buddy_block_is_clear(buddy)) - break; - - if (drm_buddy_block_is_clear(block)) - mark_cleared(parent); - } - - rbtree_remove(mm, buddy); - if (force_merge && drm_buddy_block_is_clear(buddy)) - mm->clear_avail -=3D drm_buddy_block_size(mm, buddy); - - drm_block_free(mm, block); - drm_block_free(mm, buddy); - - block =3D parent; - } - - order =3D drm_buddy_block_order(block); - mark_free(mm, block); - - return order; -} - -static int __force_merge(struct drm_buddy *mm, - u64 start, - u64 end, - unsigned int min_order) -{ - unsigned int tree, order; - int i; - - if (!min_order) - return -ENOMEM; - - if (min_order > mm->max_order) - return -EINVAL; - - for_each_free_tree(tree) { - for (i =3D min_order - 1; i >=3D 0; i--) { - struct rb_node *iter =3D rb_last(&mm->free_trees[tree][i]); - - while (iter) { - struct drm_buddy_block *block, *buddy; - u64 block_start, block_end; - - block =3D rbtree_get_free_block(iter); - iter =3D rb_prev(iter); - - if (!block || !block->parent) - continue; - - block_start =3D drm_buddy_block_offset(block); - block_end =3D block_start + drm_buddy_block_size(mm, block) - 1; - - if (!contains(start, end, block_start, block_end)) - continue; - - buddy =3D __get_buddy(block); - if (!drm_buddy_block_is_free(buddy)) - continue; - - WARN_ON(drm_buddy_block_is_clear(block) =3D=3D - drm_buddy_block_is_clear(buddy)); - - /* - * Advance to the next node when the current node is the buddy, - * as freeing the block will also remove its buddy from the tree. - */ - if (iter =3D=3D &buddy->rb) - iter =3D rb_prev(iter); - - rbtree_remove(mm, block); - if (drm_buddy_block_is_clear(block)) - mm->clear_avail -=3D drm_buddy_block_size(mm, block); - - order =3D __drm_buddy_free(mm, block, true); - if (order >=3D min_order) - return 0; - } - } - } - - return -ENOMEM; -} - -/** - * drm_buddy_init - init memory manager - * - * @mm: DRM buddy manager to initialize - * @size: size in bytes to manage - * @chunk_size: minimum page size in bytes for our allocations - * - * Initializes the memory manager and its resources. - * - * Returns: - * 0 on success, error code on failure. - */ -int drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size) -{ - unsigned int i, j, root_count =3D 0; - u64 offset =3D 0; - - if (size < chunk_size) - return -EINVAL; - - if (chunk_size < SZ_4K) - return -EINVAL; - - if (!is_power_of_2(chunk_size)) - return -EINVAL; - - size =3D round_down(size, chunk_size); - - mm->size =3D size; - mm->avail =3D size; - mm->clear_avail =3D 0; - mm->chunk_size =3D chunk_size; - mm->max_order =3D ilog2(size) - ilog2(chunk_size); - - BUG_ON(mm->max_order > DRM_BUDDY_MAX_ORDER); - - mm->free_trees =3D kmalloc_array(DRM_BUDDY_MAX_FREE_TREES, - sizeof(*mm->free_trees), - GFP_KERNEL); - if (!mm->free_trees) - return -ENOMEM; - - for_each_free_tree(i) { - mm->free_trees[i] =3D kmalloc_array(mm->max_order + 1, - sizeof(struct rb_root), - GFP_KERNEL); - if (!mm->free_trees[i]) - goto out_free_tree; - - for (j =3D 0; j <=3D mm->max_order; ++j) - mm->free_trees[i][j] =3D RB_ROOT; - } - - mm->n_roots =3D hweight64(size); - - mm->roots =3D kmalloc_array(mm->n_roots, - sizeof(struct drm_buddy_block *), - GFP_KERNEL); - if (!mm->roots) - goto out_free_tree; - - /* - * Split into power-of-two blocks, in case we are given a size that is - * not itself a power-of-two. - */ - do { - struct drm_buddy_block *root; - unsigned int order; - u64 root_size; - - order =3D ilog2(size) - ilog2(chunk_size); - root_size =3D chunk_size << order; - - root =3D drm_block_alloc(mm, NULL, order, offset); - if (!root) - goto out_free_roots; - - mark_free(mm, root); - - BUG_ON(root_count > mm->max_order); - BUG_ON(drm_buddy_block_size(mm, root) < chunk_size); - - mm->roots[root_count] =3D root; - - offset +=3D root_size; - size -=3D root_size; - root_count++; - } while (size); - - return 0; - -out_free_roots: - while (root_count--) - drm_block_free(mm, mm->roots[root_count]); - kfree(mm->roots); -out_free_tree: - while (i--) - kfree(mm->free_trees[i]); - kfree(mm->free_trees); - return -ENOMEM; -} -EXPORT_SYMBOL(drm_buddy_init); - -/** - * drm_buddy_fini - tear down the memory manager - * - * @mm: DRM buddy manager to free - * - * Cleanup memory manager resources and the freetree - */ -void drm_buddy_fini(struct drm_buddy *mm) -{ - u64 root_size, size, start; - unsigned int order; - int i; - - size =3D mm->size; - - for (i =3D 0; i < mm->n_roots; ++i) { - order =3D ilog2(size) - ilog2(mm->chunk_size); - start =3D drm_buddy_block_offset(mm->roots[i]); - __force_merge(mm, start, start + size, order); - - if (WARN_ON(!drm_buddy_block_is_free(mm->roots[i]))) - kunit_fail_current_test("buddy_fini() root"); - - drm_block_free(mm, mm->roots[i]); - - root_size =3D mm->chunk_size << order; - size -=3D root_size; - } - - WARN_ON(mm->avail !=3D mm->size); - - for_each_free_tree(i) - kfree(mm->free_trees[i]); - kfree(mm->roots); -} -EXPORT_SYMBOL(drm_buddy_fini); - -static int split_block(struct drm_buddy *mm, - struct drm_buddy_block *block) -{ - unsigned int block_order =3D drm_buddy_block_order(block) - 1; - u64 offset =3D drm_buddy_block_offset(block); - - BUG_ON(!drm_buddy_block_is_free(block)); - BUG_ON(!drm_buddy_block_order(block)); - - block->left =3D drm_block_alloc(mm, block, block_order, offset); - if (!block->left) - return -ENOMEM; - - block->right =3D drm_block_alloc(mm, block, block_order, - offset + (mm->chunk_size << block_order)); - if (!block->right) { - drm_block_free(mm, block->left); - return -ENOMEM; - } - - mark_split(mm, block); - - if (drm_buddy_block_is_clear(block)) { - mark_cleared(block->left); - mark_cleared(block->right); - clear_reset(block); - } - - mark_free(mm, block->left); - mark_free(mm, block->right); - - return 0; -} - -/** - * drm_get_buddy - get buddy address - * - * @block: DRM buddy block - * - * Returns the corresponding buddy block for @block, or NULL - * if this is a root block and can't be merged further. - * Requires some kind of locking to protect against - * any concurrent allocate and free operations. - */ -struct drm_buddy_block * -drm_get_buddy(struct drm_buddy_block *block) -{ - return __get_buddy(block); -} -EXPORT_SYMBOL(drm_get_buddy); - -/** - * drm_buddy_reset_clear - reset blocks clear state - * - * @mm: DRM buddy manager - * @is_clear: blocks clear state - * - * Reset the clear state based on @is_clear value for each block - * in the freetree. - */ -void drm_buddy_reset_clear(struct drm_buddy *mm, bool is_clear) -{ - enum drm_buddy_free_tree src_tree, dst_tree; - u64 root_size, size, start; - unsigned int order; - int i; - - size =3D mm->size; - for (i =3D 0; i < mm->n_roots; ++i) { - order =3D ilog2(size) - ilog2(mm->chunk_size); - start =3D drm_buddy_block_offset(mm->roots[i]); - __force_merge(mm, start, start + size, order); - - root_size =3D mm->chunk_size << order; - size -=3D root_size; - } - - src_tree =3D is_clear ? DRM_BUDDY_DIRTY_TREE : DRM_BUDDY_CLEAR_TREE; - dst_tree =3D is_clear ? DRM_BUDDY_CLEAR_TREE : DRM_BUDDY_DIRTY_TREE; - - for (i =3D 0; i <=3D mm->max_order; ++i) { - struct rb_root *root =3D &mm->free_trees[src_tree][i]; - struct drm_buddy_block *block, *tmp; - - rbtree_postorder_for_each_entry_safe(block, tmp, root, rb) { - rbtree_remove(mm, block); - if (is_clear) { - mark_cleared(block); - mm->clear_avail +=3D drm_buddy_block_size(mm, block); - } else { - clear_reset(block); - mm->clear_avail -=3D drm_buddy_block_size(mm, block); - } - - rbtree_insert(mm, block, dst_tree); - } - } -} -EXPORT_SYMBOL(drm_buddy_reset_clear); - -/** - * drm_buddy_free_block - free a block - * - * @mm: DRM buddy manager - * @block: block to be freed - */ -void drm_buddy_free_block(struct drm_buddy *mm, - struct drm_buddy_block *block) -{ - BUG_ON(!drm_buddy_block_is_allocated(block)); - mm->avail +=3D drm_buddy_block_size(mm, block); - if (drm_buddy_block_is_clear(block)) - mm->clear_avail +=3D drm_buddy_block_size(mm, block); - - __drm_buddy_free(mm, block, false); -} -EXPORT_SYMBOL(drm_buddy_free_block); - -static void __drm_buddy_free_list(struct drm_buddy *mm, - struct list_head *objects, - bool mark_clear, - bool mark_dirty) -{ - struct drm_buddy_block *block, *on; - - WARN_ON(mark_dirty && mark_clear); - - list_for_each_entry_safe(block, on, objects, link) { - if (mark_clear) - mark_cleared(block); - else if (mark_dirty) - clear_reset(block); - drm_buddy_free_block(mm, block); - cond_resched(); - } - INIT_LIST_HEAD(objects); -} - -static void drm_buddy_free_list_internal(struct drm_buddy *mm, - struct list_head *objects) -{ - /* - * Don't touch the clear/dirty bit, since allocation is still internal - * at this point. For example we might have just failed part of the - * allocation. - */ - __drm_buddy_free_list(mm, objects, false, false); -} - -/** - * drm_buddy_free_list - free blocks - * - * @mm: DRM buddy manager - * @objects: input list head to free blocks - * @flags: optional flags like DRM_BUDDY_CLEARED - */ -void drm_buddy_free_list(struct drm_buddy *mm, - struct list_head *objects, - unsigned int flags) -{ - bool mark_clear =3D flags & DRM_BUDDY_CLEARED; - - __drm_buddy_free_list(mm, objects, mark_clear, !mark_clear); -} -EXPORT_SYMBOL(drm_buddy_free_list); - -static bool block_incompatible(struct drm_buddy_block *block, unsigned int= flags) -{ - bool needs_clear =3D flags & DRM_BUDDY_CLEAR_ALLOCATION; - - return needs_clear !=3D drm_buddy_block_is_clear(block); -} - -static struct drm_buddy_block * -__alloc_range_bias(struct drm_buddy *mm, - u64 start, u64 end, - unsigned int order, - unsigned long flags, - bool fallback) -{ - u64 req_size =3D mm->chunk_size << order; - struct drm_buddy_block *block; - struct drm_buddy_block *buddy; - LIST_HEAD(dfs); - int err; - int i; - - end =3D end - 1; - - for (i =3D 0; i < mm->n_roots; ++i) - list_add_tail(&mm->roots[i]->tmp_link, &dfs); - - do { - u64 block_start; - u64 block_end; - - block =3D list_first_entry_or_null(&dfs, - struct drm_buddy_block, - tmp_link); - if (!block) - break; - - list_del(&block->tmp_link); - - if (drm_buddy_block_order(block) < order) - continue; - - block_start =3D drm_buddy_block_offset(block); - block_end =3D block_start + drm_buddy_block_size(mm, block) - 1; - - if (!overlaps(start, end, block_start, block_end)) - continue; - - if (drm_buddy_block_is_allocated(block)) - continue; - - if (block_start < start || block_end > end) { - u64 adjusted_start =3D max(block_start, start); - u64 adjusted_end =3D min(block_end, end); - - if (round_down(adjusted_end + 1, req_size) <=3D - round_up(adjusted_start, req_size)) - continue; - } - - if (!fallback && block_incompatible(block, flags)) - continue; - - if (contains(start, end, block_start, block_end) && - order =3D=3D drm_buddy_block_order(block)) { - /* - * Find the free block within the range. - */ - if (drm_buddy_block_is_free(block)) - return block; - - continue; - } - - if (!drm_buddy_block_is_split(block)) { - err =3D split_block(mm, block); - if (unlikely(err)) - goto err_undo; - } - - list_add(&block->right->tmp_link, &dfs); - list_add(&block->left->tmp_link, &dfs); - } while (1); - - return ERR_PTR(-ENOSPC); - -err_undo: - /* - * We really don't want to leave around a bunch of split blocks, since - * bigger is better, so make sure we merge everything back before we - * free the allocated blocks. - */ - buddy =3D __get_buddy(block); - if (buddy && - (drm_buddy_block_is_free(block) && - drm_buddy_block_is_free(buddy))) - __drm_buddy_free(mm, block, false); - return ERR_PTR(err); -} - -static struct drm_buddy_block * -__drm_buddy_alloc_range_bias(struct drm_buddy *mm, - u64 start, u64 end, - unsigned int order, - unsigned long flags) -{ - struct drm_buddy_block *block; - bool fallback =3D false; - - block =3D __alloc_range_bias(mm, start, end, order, - flags, fallback); - if (IS_ERR(block)) - return __alloc_range_bias(mm, start, end, order, - flags, !fallback); - - return block; -} - -static struct drm_buddy_block * -get_maxblock(struct drm_buddy *mm, - unsigned int order, - enum drm_buddy_free_tree tree) -{ - struct drm_buddy_block *max_block =3D NULL, *block =3D NULL; - struct rb_root *root; - unsigned int i; - - for (i =3D order; i <=3D mm->max_order; ++i) { - root =3D &mm->free_trees[tree][i]; - block =3D rbtree_last_free_block(root); - if (!block) - continue; - - if (!max_block) { - max_block =3D block; - continue; - } - - if (drm_buddy_block_offset(block) > - drm_buddy_block_offset(max_block)) { - max_block =3D block; - } - } - - return max_block; -} - -static struct drm_buddy_block * -alloc_from_freetree(struct drm_buddy *mm, - unsigned int order, - unsigned long flags) -{ - struct drm_buddy_block *block =3D NULL; - struct rb_root *root; - enum drm_buddy_free_tree tree; - unsigned int tmp; - int err; - - tree =3D (flags & DRM_BUDDY_CLEAR_ALLOCATION) ? - DRM_BUDDY_CLEAR_TREE : DRM_BUDDY_DIRTY_TREE; - - if (flags & DRM_BUDDY_TOPDOWN_ALLOCATION) { - block =3D get_maxblock(mm, order, tree); - if (block) - /* Store the obtained block order */ - tmp =3D drm_buddy_block_order(block); - } else { - for (tmp =3D order; tmp <=3D mm->max_order; ++tmp) { - /* Get RB tree root for this order and tree */ - root =3D &mm->free_trees[tree][tmp]; - block =3D rbtree_last_free_block(root); - if (block) - break; - } - } - - if (!block) { - /* Try allocating from the other tree */ - tree =3D (tree =3D=3D DRM_BUDDY_CLEAR_TREE) ? - DRM_BUDDY_DIRTY_TREE : DRM_BUDDY_CLEAR_TREE; - - for (tmp =3D order; tmp <=3D mm->max_order; ++tmp) { - root =3D &mm->free_trees[tree][tmp]; - block =3D rbtree_last_free_block(root); - if (block) - break; - } - - if (!block) - return ERR_PTR(-ENOSPC); - } - - BUG_ON(!drm_buddy_block_is_free(block)); - - while (tmp !=3D order) { - err =3D split_block(mm, block); - if (unlikely(err)) - goto err_undo; - - block =3D block->right; - tmp--; - } - return block; - -err_undo: - if (tmp !=3D order) - __drm_buddy_free(mm, block, false); - return ERR_PTR(err); -} - -static int __alloc_range(struct drm_buddy *mm, - struct list_head *dfs, - u64 start, u64 size, - struct list_head *blocks, - u64 *total_allocated_on_err) -{ - struct drm_buddy_block *block; - struct drm_buddy_block *buddy; - u64 total_allocated =3D 0; - LIST_HEAD(allocated); - u64 end; - int err; - - end =3D start + size - 1; - - do { - u64 block_start; - u64 block_end; - - block =3D list_first_entry_or_null(dfs, - struct drm_buddy_block, - tmp_link); - if (!block) - break; - - list_del(&block->tmp_link); - - block_start =3D drm_buddy_block_offset(block); - block_end =3D block_start + drm_buddy_block_size(mm, block) - 1; - - if (!overlaps(start, end, block_start, block_end)) - continue; - - if (drm_buddy_block_is_allocated(block)) { - err =3D -ENOSPC; - goto err_free; - } - - if (contains(start, end, block_start, block_end)) { - if (drm_buddy_block_is_free(block)) { - mark_allocated(mm, block); - total_allocated +=3D drm_buddy_block_size(mm, block); - mm->avail -=3D drm_buddy_block_size(mm, block); - if (drm_buddy_block_is_clear(block)) - mm->clear_avail -=3D drm_buddy_block_size(mm, block); - list_add_tail(&block->link, &allocated); - continue; - } else if (!mm->clear_avail) { - err =3D -ENOSPC; - goto err_free; - } - } - - if (!drm_buddy_block_is_split(block)) { - err =3D split_block(mm, block); - if (unlikely(err)) - goto err_undo; - } - - list_add(&block->right->tmp_link, dfs); - list_add(&block->left->tmp_link, dfs); - } while (1); - - if (total_allocated < size) { - err =3D -ENOSPC; - goto err_free; - } - - list_splice_tail(&allocated, blocks); - - return 0; - -err_undo: - /* - * We really don't want to leave around a bunch of split blocks, since - * bigger is better, so make sure we merge everything back before we - * free the allocated blocks. - */ - buddy =3D __get_buddy(block); - if (buddy && - (drm_buddy_block_is_free(block) && - drm_buddy_block_is_free(buddy))) - __drm_buddy_free(mm, block, false); - -err_free: - if (err =3D=3D -ENOSPC && total_allocated_on_err) { - list_splice_tail(&allocated, blocks); - *total_allocated_on_err =3D total_allocated; - } else { - drm_buddy_free_list_internal(mm, &allocated); - } - - return err; -} - -static int __drm_buddy_alloc_range(struct drm_buddy *mm, - u64 start, - u64 size, - u64 *total_allocated_on_err, - struct list_head *blocks) -{ - LIST_HEAD(dfs); - int i; - - for (i =3D 0; i < mm->n_roots; ++i) - list_add_tail(&mm->roots[i]->tmp_link, &dfs); - - return __alloc_range(mm, &dfs, start, size, - blocks, total_allocated_on_err); -} - -static int __alloc_contig_try_harder(struct drm_buddy *mm, - u64 size, - u64 min_block_size, - struct list_head *blocks) -{ - u64 rhs_offset, lhs_offset, lhs_size, filled; - struct drm_buddy_block *block; - unsigned int tree, order; - LIST_HEAD(blocks_lhs); - unsigned long pages; - u64 modify_size; - int err; - - modify_size =3D rounddown_pow_of_two(size); - pages =3D modify_size >> ilog2(mm->chunk_size); - order =3D fls(pages) - 1; - if (order =3D=3D 0) - return -ENOSPC; - - for_each_free_tree(tree) { - struct rb_root *root; - struct rb_node *iter; - - root =3D &mm->free_trees[tree][order]; - if (rbtree_is_empty(root)) - continue; - - iter =3D rb_last(root); - while (iter) { - block =3D rbtree_get_free_block(iter); - - /* Allocate blocks traversing RHS */ - rhs_offset =3D drm_buddy_block_offset(block); - err =3D __drm_buddy_alloc_range(mm, rhs_offset, size, - &filled, blocks); - if (!err || err !=3D -ENOSPC) - return err; - - lhs_size =3D max((size - filled), min_block_size); - if (!IS_ALIGNED(lhs_size, min_block_size)) - lhs_size =3D round_up(lhs_size, min_block_size); - - /* Allocate blocks traversing LHS */ - lhs_offset =3D drm_buddy_block_offset(block) - lhs_size; - err =3D __drm_buddy_alloc_range(mm, lhs_offset, lhs_size, - NULL, &blocks_lhs); - if (!err) { - list_splice(&blocks_lhs, blocks); - return 0; - } else if (err !=3D -ENOSPC) { - drm_buddy_free_list_internal(mm, blocks); - return err; - } - /* Free blocks for the next iteration */ - drm_buddy_free_list_internal(mm, blocks); - - iter =3D rb_prev(iter); - } - } - - return -ENOSPC; -} - -/** - * drm_buddy_block_trim - free unused pages - * - * @mm: DRM buddy manager - * @start: start address to begin the trimming. - * @new_size: original size requested - * @blocks: Input and output list of allocated blocks. - * MUST contain single block as input to be trimmed. - * On success will contain the newly allocated blocks - * making up the @new_size. Blocks always appear in - * ascending order - * - * For contiguous allocation, we round up the size to the nearest - * power of two value, drivers consume *actual* size, so remaining - * portions are unused and can be optionally freed with this function - * - * Returns: - * 0 on success, error code on failure. - */ -int drm_buddy_block_trim(struct drm_buddy *mm, - u64 *start, - u64 new_size, - struct list_head *blocks) -{ - struct drm_buddy_block *parent; - struct drm_buddy_block *block; - u64 block_start, block_end; - LIST_HEAD(dfs); - u64 new_start; - int err; - - if (!list_is_singular(blocks)) - return -EINVAL; - - block =3D list_first_entry(blocks, - struct drm_buddy_block, - link); - - block_start =3D drm_buddy_block_offset(block); - block_end =3D block_start + drm_buddy_block_size(mm, block); - - if (WARN_ON(!drm_buddy_block_is_allocated(block))) - return -EINVAL; - - if (new_size > drm_buddy_block_size(mm, block)) - return -EINVAL; - - if (!new_size || !IS_ALIGNED(new_size, mm->chunk_size)) - return -EINVAL; - - if (new_size =3D=3D drm_buddy_block_size(mm, block)) - return 0; - - new_start =3D block_start; - if (start) { - new_start =3D *start; - - if (new_start < block_start) - return -EINVAL; - - if (!IS_ALIGNED(new_start, mm->chunk_size)) - return -EINVAL; - - if (range_overflows(new_start, new_size, block_end)) - return -EINVAL; - } - - list_del(&block->link); - mark_free(mm, block); - mm->avail +=3D drm_buddy_block_size(mm, block); - if (drm_buddy_block_is_clear(block)) - mm->clear_avail +=3D drm_buddy_block_size(mm, block); - - /* Prevent recursively freeing this node */ - parent =3D block->parent; - block->parent =3D NULL; - - list_add(&block->tmp_link, &dfs); - err =3D __alloc_range(mm, &dfs, new_start, new_size, blocks, NULL); - if (err) { - mark_allocated(mm, block); - mm->avail -=3D drm_buddy_block_size(mm, block); - if (drm_buddy_block_is_clear(block)) - mm->clear_avail -=3D drm_buddy_block_size(mm, block); - list_add(&block->link, blocks); - } - - block->parent =3D parent; - return err; -} -EXPORT_SYMBOL(drm_buddy_block_trim); - -static struct drm_buddy_block * -__drm_buddy_alloc_blocks(struct drm_buddy *mm, - u64 start, u64 end, - unsigned int order, - unsigned long flags) -{ - if (flags & DRM_BUDDY_RANGE_ALLOCATION) - /* Allocate traversing within the range */ - return __drm_buddy_alloc_range_bias(mm, start, end, - order, flags); - else - /* Allocate from freetree */ - return alloc_from_freetree(mm, order, flags); -} - -/** - * drm_buddy_alloc_blocks - allocate power-of-two blocks - * - * @mm: DRM buddy manager to allocate from - * @start: start of the allowed range for this block - * @end: end of the allowed range for this block - * @size: size of the allocation in bytes - * @min_block_size: alignment of the allocation - * @blocks: output list head to add allocated blocks - * @flags: DRM_BUDDY_*_ALLOCATION flags - * - * alloc_range_bias() called on range limitations, which traverses - * the tree and returns the desired block. - * - * alloc_from_freetree() called when *no* range restrictions - * are enforced, which picks the block from the freetree. - * - * Returns: - * 0 on success, error code on failure. - */ -int drm_buddy_alloc_blocks(struct drm_buddy *mm, - u64 start, u64 end, u64 size, - u64 min_block_size, - struct list_head *blocks, - unsigned long flags) -{ - struct drm_buddy_block *block =3D NULL; - u64 original_size, original_min_size; - unsigned int min_order, order; - LIST_HEAD(allocated); - unsigned long pages; - int err; - - if (size < mm->chunk_size) - return -EINVAL; - - if (min_block_size < mm->chunk_size) - return -EINVAL; - - if (!is_power_of_2(min_block_size)) - return -EINVAL; - - if (!IS_ALIGNED(start | end | size, mm->chunk_size)) - return -EINVAL; - - if (end > mm->size) - return -EINVAL; - - if (range_overflows(start, size, mm->size)) - return -EINVAL; - - /* Actual range allocation */ - if (start + size =3D=3D end) { - if (!IS_ALIGNED(start | end, min_block_size)) - return -EINVAL; - - return __drm_buddy_alloc_range(mm, start, size, NULL, blocks); - } - - original_size =3D size; - original_min_size =3D min_block_size; - - /* Roundup the size to power of 2 */ - if (flags & DRM_BUDDY_CONTIGUOUS_ALLOCATION) { - size =3D roundup_pow_of_two(size); - min_block_size =3D size; - /* Align size value to min_block_size */ - } else if (!IS_ALIGNED(size, min_block_size)) { - size =3D round_up(size, min_block_size); - } - - pages =3D size >> ilog2(mm->chunk_size); - order =3D fls(pages) - 1; - min_order =3D ilog2(min_block_size) - ilog2(mm->chunk_size); - - do { - order =3D min(order, (unsigned int)fls(pages) - 1); - BUG_ON(order > mm->max_order); - BUG_ON(order < min_order); - - do { - block =3D __drm_buddy_alloc_blocks(mm, start, - end, - order, - flags); - if (!IS_ERR(block)) - break; - - if (order-- =3D=3D min_order) { - /* Try allocation through force merge method */ - if (mm->clear_avail && - !__force_merge(mm, start, end, min_order)) { - block =3D __drm_buddy_alloc_blocks(mm, start, - end, - min_order, - flags); - if (!IS_ERR(block)) { - order =3D min_order; - break; - } - } - - /* - * Try contiguous block allocation through - * try harder method. - */ - if (flags & DRM_BUDDY_CONTIGUOUS_ALLOCATION && - !(flags & DRM_BUDDY_RANGE_ALLOCATION)) - return __alloc_contig_try_harder(mm, - original_size, - original_min_size, - blocks); - err =3D -ENOSPC; - goto err_free; - } - } while (1); - - mark_allocated(mm, block); - mm->avail -=3D drm_buddy_block_size(mm, block); - if (drm_buddy_block_is_clear(block)) - mm->clear_avail -=3D drm_buddy_block_size(mm, block); - kmemleak_update_trace(block); - list_add_tail(&block->link, &allocated); - - pages -=3D BIT(order); - - if (!pages) - break; - } while (1); - - /* Trim the allocated block to the required size */ - if (!(flags & DRM_BUDDY_TRIM_DISABLE) && - original_size !=3D size) { - struct list_head *trim_list; - LIST_HEAD(temp); - u64 trim_size; - - trim_list =3D &allocated; - trim_size =3D original_size; - - if (!list_is_singular(&allocated)) { - block =3D list_last_entry(&allocated, typeof(*block), link); - list_move(&block->link, &temp); - trim_list =3D &temp; - trim_size =3D drm_buddy_block_size(mm, block) - - (size - original_size); - } - - drm_buddy_block_trim(mm, - NULL, - trim_size, - trim_list); - - if (!list_empty(&temp)) - list_splice_tail(trim_list, &allocated); - } - - list_splice_tail(&allocated, blocks); - return 0; - -err_free: - drm_buddy_free_list_internal(mm, &allocated); - return err; -} -EXPORT_SYMBOL(drm_buddy_alloc_blocks); - /** * drm_buddy_block_print - print block information * - * @mm: DRM buddy manager - * @block: DRM buddy block + * @mm: GPU buddy manager + * @block: GPU buddy block * @p: DRM printer to use */ -void drm_buddy_block_print(struct drm_buddy *mm, - struct drm_buddy_block *block, +void drm_buddy_block_print(struct gpu_buddy *mm, struct gpu_buddy_block *b= lock, struct drm_printer *p) { - u64 start =3D drm_buddy_block_offset(block); - u64 size =3D drm_buddy_block_size(mm, block); + u64 start =3D gpu_buddy_block_offset(block); + u64 size =3D gpu_buddy_block_size(mm, block); =20 drm_printf(p, "%#018llx-%#018llx: %llu\n", start, start + size, size); } @@ -1267,18 +30,21 @@ EXPORT_SYMBOL(drm_buddy_block_print); /** * drm_buddy_print - print allocator state * - * @mm: DRM buddy manager + * @mm: GPU buddy manager * @p: DRM printer to use */ -void drm_buddy_print(struct drm_buddy *mm, struct drm_printer *p) +void drm_buddy_print(struct gpu_buddy *mm, struct drm_printer *p) { int order; =20 - drm_printf(p, "chunk_size: %lluKiB, total: %lluMiB, free: %lluMiB, clear_= free: %lluMiB\n", - mm->chunk_size >> 10, mm->size >> 20, mm->avail >> 20, mm->clear_avai= l >> 20); + drm_printf( + p, + "chunk_size: %lluKiB, total: %lluMiB, free: %lluMiB, clear_free: %lluMiB= \n", + mm->chunk_size >> 10, mm->size >> 20, mm->avail >> 20, + mm->clear_avail >> 20); =20 for (order =3D mm->max_order; order >=3D 0; order--) { - struct drm_buddy_block *block, *tmp; + struct gpu_buddy_block *block, *tmp; struct rb_root *root; u64 count =3D 0, free; unsigned int tree; @@ -1286,8 +52,9 @@ void drm_buddy_print(struct drm_buddy *mm, struct drm_p= rinter *p) for_each_free_tree(tree) { root =3D &mm->free_trees[tree][order]; =20 - rbtree_postorder_for_each_entry_safe(block, tmp, root, rb) { - BUG_ON(!drm_buddy_block_is_free(block)); + rbtree_postorder_for_each_entry_safe(block, tmp, root, + rb) { + BUG_ON(!gpu_buddy_block_is_free(block)); count++; } } @@ -1305,22 +72,5 @@ void drm_buddy_print(struct drm_buddy *mm, struct drm_= printer *p) } EXPORT_SYMBOL(drm_buddy_print); =20 -static void drm_buddy_module_exit(void) -{ - kmem_cache_destroy(slab_blocks); -} - -static int __init drm_buddy_module_init(void) -{ - slab_blocks =3D KMEM_CACHE(drm_buddy_block, 0); - if (!slab_blocks) - return -ENOMEM; - - return 0; -} - -module_init(drm_buddy_module_init); -module_exit(drm_buddy_module_exit); - -MODULE_DESCRIPTION("DRM Buddy Allocator"); +MODULE_DESCRIPTION("DRM-specific GPU Buddy Allocator Print Helpers"); MODULE_LICENSE("Dual MIT/GPL"); diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig index 5e939004b646..859aeca87c19 100644 --- a/drivers/gpu/drm/i915/Kconfig +++ b/drivers/gpu/drm/i915/Kconfig @@ -38,6 +38,7 @@ config DRM_I915 select CEC_CORE if CEC_NOTIFIER select VMAP_PFN select DRM_TTM + select GPU_BUDDY select DRM_BUDDY select AUXILIARY_BUS help diff --git a/drivers/gpu/drm/i915/i915_scatterlist.c b/drivers/gpu/drm/i915= /i915_scatterlist.c index 4d830740946d..6a34dae13769 100644 --- a/drivers/gpu/drm/i915/i915_scatterlist.c +++ b/drivers/gpu/drm/i915/i915_scatterlist.c @@ -7,7 +7,7 @@ #include "i915_scatterlist.h" #include "i915_ttm_buddy_manager.h" =20 -#include +#include #include =20 #include @@ -167,9 +167,9 @@ struct i915_refct_sgt *i915_rsgt_from_buddy_resource(st= ruct ttm_resource *res, struct i915_ttm_buddy_resource *bman_res =3D to_ttm_buddy_resource(res); const u64 size =3D res->size; const u32 max_segment =3D round_down(UINT_MAX, page_alignment); - struct drm_buddy *mm =3D bman_res->mm; + struct gpu_buddy *mm =3D bman_res->mm; struct list_head *blocks =3D &bman_res->blocks; - struct drm_buddy_block *block; + struct gpu_buddy_block *block; struct i915_refct_sgt *rsgt; struct scatterlist *sg; struct sg_table *st; @@ -202,8 +202,8 @@ struct i915_refct_sgt *i915_rsgt_from_buddy_resource(st= ruct ttm_resource *res, list_for_each_entry(block, blocks, link) { u64 block_size, offset; =20 - block_size =3D min_t(u64, size, drm_buddy_block_size(mm, block)); - offset =3D drm_buddy_block_offset(block); + block_size =3D min_t(u64, size, gpu_buddy_block_size(mm, block)); + offset =3D gpu_buddy_block_offset(block); =20 while (block_size) { u64 len; diff --git a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c b/drivers/gpu/dr= m/i915/i915_ttm_buddy_manager.c index d5c6e6605086..f43d7f2771ad 100644 --- a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c +++ b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c @@ -4,6 +4,7 @@ */ =20 #include +#include =20 #include #include @@ -16,7 +17,7 @@ =20 struct i915_ttm_buddy_manager { struct ttm_resource_manager manager; - struct drm_buddy mm; + struct gpu_buddy mm; struct list_head reserved; struct mutex lock; unsigned long visible_size; @@ -38,7 +39,7 @@ static int i915_ttm_buddy_man_alloc(struct ttm_resource_m= anager *man, { struct i915_ttm_buddy_manager *bman =3D to_buddy_manager(man); struct i915_ttm_buddy_resource *bman_res; - struct drm_buddy *mm =3D &bman->mm; + struct gpu_buddy *mm =3D &bman->mm; unsigned long n_pages, lpfn; u64 min_page_size; u64 size; @@ -57,13 +58,13 @@ static int i915_ttm_buddy_man_alloc(struct ttm_resource= _manager *man, bman_res->mm =3D mm; =20 if (place->flags & TTM_PL_FLAG_TOPDOWN) - bman_res->flags |=3D DRM_BUDDY_TOPDOWN_ALLOCATION; + bman_res->flags |=3D GPU_BUDDY_TOPDOWN_ALLOCATION; =20 if (place->flags & TTM_PL_FLAG_CONTIGUOUS) - bman_res->flags |=3D DRM_BUDDY_CONTIGUOUS_ALLOCATION; + bman_res->flags |=3D GPU_BUDDY_CONTIGUOUS_ALLOCATION; =20 if (place->fpfn || lpfn !=3D man->size) - bman_res->flags |=3D DRM_BUDDY_RANGE_ALLOCATION; + bman_res->flags |=3D GPU_BUDDY_RANGE_ALLOCATION; =20 GEM_BUG_ON(!bman_res->base.size); size =3D bman_res->base.size; @@ -89,7 +90,7 @@ static int i915_ttm_buddy_man_alloc(struct ttm_resource_m= anager *man, goto err_free_res; } =20 - err =3D drm_buddy_alloc_blocks(mm, (u64)place->fpfn << PAGE_SHIFT, + err =3D gpu_buddy_alloc_blocks(mm, (u64)place->fpfn << PAGE_SHIFT, (u64)lpfn << PAGE_SHIFT, (u64)n_pages << PAGE_SHIFT, min_page_size, @@ -101,15 +102,15 @@ static int i915_ttm_buddy_man_alloc(struct ttm_resour= ce_manager *man, if (lpfn <=3D bman->visible_size) { bman_res->used_visible_size =3D PFN_UP(bman_res->base.size); } else { - struct drm_buddy_block *block; + struct gpu_buddy_block *block; =20 list_for_each_entry(block, &bman_res->blocks, link) { unsigned long start =3D - drm_buddy_block_offset(block) >> PAGE_SHIFT; + gpu_buddy_block_offset(block) >> PAGE_SHIFT; =20 if (start < bman->visible_size) { unsigned long end =3D start + - (drm_buddy_block_size(mm, block) >> PAGE_SHIFT); + (gpu_buddy_block_size(mm, block) >> PAGE_SHIFT); =20 bman_res->used_visible_size +=3D min(end, bman->visible_size) - start; @@ -126,7 +127,7 @@ static int i915_ttm_buddy_man_alloc(struct ttm_resource= _manager *man, return 0; =20 err_free_blocks: - drm_buddy_free_list(mm, &bman_res->blocks, 0); + gpu_buddy_free_list(mm, &bman_res->blocks, 0); mutex_unlock(&bman->lock); err_free_res: ttm_resource_fini(man, &bman_res->base); @@ -141,7 +142,7 @@ static void i915_ttm_buddy_man_free(struct ttm_resource= _manager *man, struct i915_ttm_buddy_manager *bman =3D to_buddy_manager(man); =20 mutex_lock(&bman->lock); - drm_buddy_free_list(&bman->mm, &bman_res->blocks, 0); + gpu_buddy_free_list(&bman->mm, &bman_res->blocks, 0); bman->visible_avail +=3D bman_res->used_visible_size; mutex_unlock(&bman->lock); =20 @@ -156,8 +157,8 @@ static bool i915_ttm_buddy_man_intersects(struct ttm_re= source_manager *man, { struct i915_ttm_buddy_resource *bman_res =3D to_ttm_buddy_resource(res); struct i915_ttm_buddy_manager *bman =3D to_buddy_manager(man); - struct drm_buddy *mm =3D &bman->mm; - struct drm_buddy_block *block; + struct gpu_buddy *mm =3D &bman->mm; + struct gpu_buddy_block *block; =20 if (!place->fpfn && !place->lpfn) return true; @@ -176,9 +177,9 @@ static bool i915_ttm_buddy_man_intersects(struct ttm_re= source_manager *man, /* Check each drm buddy block individually */ list_for_each_entry(block, &bman_res->blocks, link) { unsigned long fpfn =3D - drm_buddy_block_offset(block) >> PAGE_SHIFT; + gpu_buddy_block_offset(block) >> PAGE_SHIFT; unsigned long lpfn =3D fpfn + - (drm_buddy_block_size(mm, block) >> PAGE_SHIFT); + (gpu_buddy_block_size(mm, block) >> PAGE_SHIFT); =20 if (place->fpfn < lpfn && place->lpfn > fpfn) return true; @@ -194,8 +195,8 @@ static bool i915_ttm_buddy_man_compatible(struct ttm_re= source_manager *man, { struct i915_ttm_buddy_resource *bman_res =3D to_ttm_buddy_resource(res); struct i915_ttm_buddy_manager *bman =3D to_buddy_manager(man); - struct drm_buddy *mm =3D &bman->mm; - struct drm_buddy_block *block; + struct gpu_buddy *mm =3D &bman->mm; + struct gpu_buddy_block *block; =20 if (!place->fpfn && !place->lpfn) return true; @@ -209,9 +210,9 @@ static bool i915_ttm_buddy_man_compatible(struct ttm_re= source_manager *man, /* Check each drm buddy block individually */ list_for_each_entry(block, &bman_res->blocks, link) { unsigned long fpfn =3D - drm_buddy_block_offset(block) >> PAGE_SHIFT; + gpu_buddy_block_offset(block) >> PAGE_SHIFT; unsigned long lpfn =3D fpfn + - (drm_buddy_block_size(mm, block) >> PAGE_SHIFT); + (gpu_buddy_block_size(mm, block) >> PAGE_SHIFT); =20 if (fpfn < place->fpfn || lpfn > place->lpfn) return false; @@ -224,7 +225,7 @@ static void i915_ttm_buddy_man_debug(struct ttm_resourc= e_manager *man, struct drm_printer *printer) { struct i915_ttm_buddy_manager *bman =3D to_buddy_manager(man); - struct drm_buddy_block *block; + struct gpu_buddy_block *block; =20 mutex_lock(&bman->lock); drm_printf(printer, "default_page_size: %lluKiB\n", @@ -293,7 +294,7 @@ int i915_ttm_buddy_man_init(struct ttm_device *bdev, if (!bman) return -ENOMEM; =20 - err =3D drm_buddy_init(&bman->mm, size, chunk_size); + err =3D gpu_buddy_init(&bman->mm, size, chunk_size); if (err) goto err_free_bman; =20 @@ -333,7 +334,7 @@ int i915_ttm_buddy_man_fini(struct ttm_device *bdev, un= signed int type) { struct ttm_resource_manager *man =3D ttm_manager_type(bdev, type); struct i915_ttm_buddy_manager *bman =3D to_buddy_manager(man); - struct drm_buddy *mm =3D &bman->mm; + struct gpu_buddy *mm =3D &bman->mm; int ret; =20 ttm_resource_manager_set_used(man, false); @@ -345,8 +346,8 @@ int i915_ttm_buddy_man_fini(struct ttm_device *bdev, un= signed int type) ttm_set_driver_manager(bdev, type, NULL); =20 mutex_lock(&bman->lock); - drm_buddy_free_list(mm, &bman->reserved, 0); - drm_buddy_fini(mm); + gpu_buddy_free_list(mm, &bman->reserved, 0); + gpu_buddy_fini(mm); bman->visible_avail +=3D bman->visible_reserved; WARN_ON_ONCE(bman->visible_avail !=3D bman->visible_size); mutex_unlock(&bman->lock); @@ -371,15 +372,15 @@ int i915_ttm_buddy_man_reserve(struct ttm_resource_ma= nager *man, u64 start, u64 size) { struct i915_ttm_buddy_manager *bman =3D to_buddy_manager(man); - struct drm_buddy *mm =3D &bman->mm; + struct gpu_buddy *mm =3D &bman->mm; unsigned long fpfn =3D start >> PAGE_SHIFT; unsigned long flags =3D 0; int ret; =20 - flags |=3D DRM_BUDDY_RANGE_ALLOCATION; + flags |=3D GPU_BUDDY_RANGE_ALLOCATION; =20 mutex_lock(&bman->lock); - ret =3D drm_buddy_alloc_blocks(mm, start, + ret =3D gpu_buddy_alloc_blocks(mm, start, start + size, size, mm->chunk_size, &bman->reserved, diff --git a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.h b/drivers/gpu/dr= m/i915/i915_ttm_buddy_manager.h index d64620712830..4a92dcf09766 100644 --- a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.h +++ b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.h @@ -13,14 +13,14 @@ =20 struct ttm_device; struct ttm_resource_manager; -struct drm_buddy; +struct gpu_buddy; =20 /** * struct i915_ttm_buddy_resource * * @base: struct ttm_resource base class we extend * @blocks: the list of struct i915_buddy_block for this resource/allocati= on - * @flags: DRM_BUDDY_*_ALLOCATION flags + * @flags: GPU_BUDDY_*_ALLOCATION flags * @used_visible_size: How much of this resource, if any, uses the CPU vis= ible * portion, in pages. * @mm: the struct i915_buddy_mm for this resource @@ -33,7 +33,7 @@ struct i915_ttm_buddy_resource { struct list_head blocks; unsigned long flags; unsigned long used_visible_size; - struct drm_buddy *mm; + struct gpu_buddy *mm; }; =20 /** diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c b/drivers= /gpu/drm/i915/selftests/intel_memory_region.c index 7b856b5090f9..8307390943a2 100644 --- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c +++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c @@ -6,7 +6,7 @@ #include #include =20 -#include +#include =20 #include "../i915_selftest.h" =20 @@ -371,7 +371,7 @@ static int igt_mock_splintered_region(void *arg) struct drm_i915_private *i915 =3D mem->i915; struct i915_ttm_buddy_resource *res; struct drm_i915_gem_object *obj; - struct drm_buddy *mm; + struct gpu_buddy *mm; unsigned int expected_order; LIST_HEAD(objects); u64 size; @@ -447,8 +447,8 @@ static int igt_mock_max_segment(void *arg) struct drm_i915_private *i915 =3D mem->i915; struct i915_ttm_buddy_resource *res; struct drm_i915_gem_object *obj; - struct drm_buddy_block *block; - struct drm_buddy *mm; + struct gpu_buddy_block *block; + struct gpu_buddy *mm; struct list_head *blocks; struct scatterlist *sg; I915_RND_STATE(prng); @@ -487,8 +487,8 @@ static int igt_mock_max_segment(void *arg) mm =3D res->mm; size =3D 0; list_for_each_entry(block, blocks, link) { - if (drm_buddy_block_size(mm, block) > size) - size =3D drm_buddy_block_size(mm, block); + if (gpu_buddy_block_size(mm, block) > size) + size =3D gpu_buddy_block_size(mm, block); } if (size < max_segment) { pr_err("%s: Failed to create a huge contiguous block [> %u], largest blo= ck %lld\n", @@ -527,14 +527,14 @@ static u64 igt_object_mappable_total(struct drm_i915_= gem_object *obj) struct intel_memory_region *mr =3D obj->mm.region; struct i915_ttm_buddy_resource *bman_res =3D to_ttm_buddy_resource(obj->mm.res); - struct drm_buddy *mm =3D bman_res->mm; - struct drm_buddy_block *block; + struct gpu_buddy *mm =3D bman_res->mm; + struct gpu_buddy_block *block; u64 total; =20 total =3D 0; list_for_each_entry(block, &bman_res->blocks, link) { - u64 start =3D drm_buddy_block_offset(block); - u64 end =3D start + drm_buddy_block_size(mm, block); + u64 start =3D gpu_buddy_block_offset(block); + u64 end =3D start + gpu_buddy_block_size(mm, block); =20 if (start < resource_size(&mr->io)) total +=3D min_t(u64, end, resource_size(&mr->io)) - start; diff --git a/drivers/gpu/drm/tests/Makefile b/drivers/gpu/drm/tests/Makefile index 87d5d5f9332a..d2e2e3d8349a 100644 --- a/drivers/gpu/drm/tests/Makefile +++ b/drivers/gpu/drm/tests/Makefile @@ -7,7 +7,6 @@ obj-$(CONFIG_DRM_KUNIT_TEST) +=3D \ drm_atomic_test.o \ drm_atomic_state_test.o \ drm_bridge_test.o \ - drm_buddy_test.o \ drm_cmdline_parser_test.o \ drm_connector_test.o \ drm_damage_helper_test.o \ diff --git a/drivers/gpu/drm/ttm/tests/ttm_bo_validate_test.c b/drivers/gpu= /drm/ttm/tests/ttm_bo_validate_test.c index 2eda87882e65..ffa12473077c 100644 --- a/drivers/gpu/drm/ttm/tests/ttm_bo_validate_test.c +++ b/drivers/gpu/drm/ttm/tests/ttm_bo_validate_test.c @@ -3,6 +3,7 @@ * Copyright =C2=A9 2023 Intel Corporation */ #include +#include #include =20 #include @@ -251,7 +252,7 @@ static void ttm_bo_validate_basic(struct kunit *test) NULL, &dummy_ttm_bo_destroy); KUNIT_EXPECT_EQ(test, err, 0); =20 - snd_place =3D ttm_place_kunit_init(test, snd_mem, DRM_BUDDY_TOPDOWN_ALLOC= ATION); + snd_place =3D ttm_place_kunit_init(test, snd_mem, GPU_BUDDY_TOPDOWN_ALLOC= ATION); snd_placement =3D ttm_placement_kunit_init(test, snd_place, 1); =20 err =3D ttm_bo_validate(bo, snd_placement, &ctx_val); @@ -263,7 +264,7 @@ static void ttm_bo_validate_basic(struct kunit *test) KUNIT_EXPECT_TRUE(test, ttm_tt_is_populated(bo->ttm)); KUNIT_EXPECT_EQ(test, bo->resource->mem_type, snd_mem); KUNIT_EXPECT_EQ(test, bo->resource->placement, - DRM_BUDDY_TOPDOWN_ALLOCATION); + GPU_BUDDY_TOPDOWN_ALLOCATION); =20 ttm_bo_fini(bo); ttm_mock_manager_fini(priv->ttm_dev, snd_mem); diff --git a/drivers/gpu/drm/ttm/tests/ttm_mock_manager.c b/drivers/gpu/drm= /ttm/tests/ttm_mock_manager.c index dd395229e388..294d56d9067e 100644 --- a/drivers/gpu/drm/ttm/tests/ttm_mock_manager.c +++ b/drivers/gpu/drm/ttm/tests/ttm_mock_manager.c @@ -31,7 +31,7 @@ static int ttm_mock_manager_alloc(struct ttm_resource_man= ager *man, { struct ttm_mock_manager *manager =3D to_mock_mgr(man); struct ttm_mock_resource *mock_res; - struct drm_buddy *mm =3D &manager->mm; + struct gpu_buddy *mm =3D &manager->mm; u64 lpfn, fpfn, alloc_size; int err; =20 @@ -47,14 +47,14 @@ static int ttm_mock_manager_alloc(struct ttm_resource_m= anager *man, INIT_LIST_HEAD(&mock_res->blocks); =20 if (place->flags & TTM_PL_FLAG_TOPDOWN) - mock_res->flags |=3D DRM_BUDDY_TOPDOWN_ALLOCATION; + mock_res->flags |=3D GPU_BUDDY_TOPDOWN_ALLOCATION; =20 if (place->flags & TTM_PL_FLAG_CONTIGUOUS) - mock_res->flags |=3D DRM_BUDDY_CONTIGUOUS_ALLOCATION; + mock_res->flags |=3D GPU_BUDDY_CONTIGUOUS_ALLOCATION; =20 alloc_size =3D (uint64_t)mock_res->base.size; mutex_lock(&manager->lock); - err =3D drm_buddy_alloc_blocks(mm, fpfn, lpfn, alloc_size, + err =3D gpu_buddy_alloc_blocks(mm, fpfn, lpfn, alloc_size, manager->default_page_size, &mock_res->blocks, mock_res->flags); @@ -67,7 +67,7 @@ static int ttm_mock_manager_alloc(struct ttm_resource_man= ager *man, return 0; =20 error_free_blocks: - drm_buddy_free_list(mm, &mock_res->blocks, 0); + gpu_buddy_free_list(mm, &mock_res->blocks, 0); ttm_resource_fini(man, &mock_res->base); mutex_unlock(&manager->lock); =20 @@ -79,10 +79,10 @@ static void ttm_mock_manager_free(struct ttm_resource_m= anager *man, { struct ttm_mock_manager *manager =3D to_mock_mgr(man); struct ttm_mock_resource *mock_res =3D to_mock_mgr_resource(res); - struct drm_buddy *mm =3D &manager->mm; + struct gpu_buddy *mm =3D &manager->mm; =20 mutex_lock(&manager->lock); - drm_buddy_free_list(mm, &mock_res->blocks, 0); + gpu_buddy_free_list(mm, &mock_res->blocks, 0); mutex_unlock(&manager->lock); =20 ttm_resource_fini(man, res); @@ -106,7 +106,7 @@ int ttm_mock_manager_init(struct ttm_device *bdev, u32 = mem_type, u32 size) =20 mutex_init(&manager->lock); =20 - err =3D drm_buddy_init(&manager->mm, size, PAGE_SIZE); + err =3D gpu_buddy_init(&manager->mm, size, PAGE_SIZE); =20 if (err) { kfree(manager); @@ -142,7 +142,7 @@ void ttm_mock_manager_fini(struct ttm_device *bdev, u32= mem_type) ttm_resource_manager_set_used(man, false); =20 mutex_lock(&mock_man->lock); - drm_buddy_fini(&mock_man->mm); + gpu_buddy_fini(&mock_man->mm); mutex_unlock(&mock_man->lock); =20 ttm_set_driver_manager(bdev, mem_type, NULL); diff --git a/drivers/gpu/drm/ttm/tests/ttm_mock_manager.h b/drivers/gpu/drm= /ttm/tests/ttm_mock_manager.h index e4c95f86a467..08710756fd8e 100644 --- a/drivers/gpu/drm/ttm/tests/ttm_mock_manager.h +++ b/drivers/gpu/drm/ttm/tests/ttm_mock_manager.h @@ -5,11 +5,11 @@ #ifndef TTM_MOCK_MANAGER_H #define TTM_MOCK_MANAGER_H =20 -#include +#include =20 struct ttm_mock_manager { struct ttm_resource_manager man; - struct drm_buddy mm; + struct gpu_buddy mm; u64 default_page_size; /* protects allocations of mock buffer objects */ struct mutex lock; diff --git a/drivers/gpu/drm/xe/Kconfig b/drivers/gpu/drm/xe/Kconfig index 4b288eb3f5b0..982ef754742e 100644 --- a/drivers/gpu/drm/xe/Kconfig +++ b/drivers/gpu/drm/xe/Kconfig @@ -11,6 +11,7 @@ config DRM_XE # the shmem_readpage() which depends upon tmpfs select SHMEM select TMPFS + select GPU_BUDDY select DRM_BUDDY select DRM_CLIENT_SELECTION select DRM_KMS_HELPER diff --git a/drivers/gpu/drm/xe/xe_res_cursor.h b/drivers/gpu/drm/xe/xe_res= _cursor.h index 4e00008b7081..5f4ab08c0686 100644 --- a/drivers/gpu/drm/xe/xe_res_cursor.h +++ b/drivers/gpu/drm/xe/xe_res_cursor.h @@ -58,7 +58,7 @@ struct xe_res_cursor { /** @dma_addr: Current element in a struct drm_pagemap_addr array */ const struct drm_pagemap_addr *dma_addr; /** @mm: Buddy allocator for VRAM cursor */ - struct drm_buddy *mm; + struct gpu_buddy *mm; /** * @dma_start: DMA start address for the current segment. * This may be different to @dma_addr.addr since elements in @@ -69,7 +69,7 @@ struct xe_res_cursor { u64 dma_seg_size; }; =20 -static struct drm_buddy *xe_res_get_buddy(struct ttm_resource *res) +static struct gpu_buddy *xe_res_get_buddy(struct ttm_resource *res) { struct ttm_resource_manager *mgr; =20 @@ -104,30 +104,30 @@ static inline void xe_res_first(struct ttm_resource *= res, case XE_PL_STOLEN: case XE_PL_VRAM0: case XE_PL_VRAM1: { - struct drm_buddy_block *block; + struct gpu_buddy_block *block; struct list_head *head, *next; - struct drm_buddy *mm =3D xe_res_get_buddy(res); + struct gpu_buddy *mm =3D xe_res_get_buddy(res); =20 head =3D &to_xe_ttm_vram_mgr_resource(res)->blocks; =20 block =3D list_first_entry_or_null(head, - struct drm_buddy_block, + struct gpu_buddy_block, link); if (!block) goto fallback; =20 - while (start >=3D drm_buddy_block_size(mm, block)) { - start -=3D drm_buddy_block_size(mm, block); + while (start >=3D gpu_buddy_block_size(mm, block)) { + start -=3D gpu_buddy_block_size(mm, block); =20 next =3D block->link.next; if (next !=3D head) - block =3D list_entry(next, struct drm_buddy_block, + block =3D list_entry(next, struct gpu_buddy_block, link); } =20 cur->mm =3D mm; - cur->start =3D drm_buddy_block_offset(block) + start; - cur->size =3D min(drm_buddy_block_size(mm, block) - start, + cur->start =3D gpu_buddy_block_offset(block) + start; + cur->size =3D min(gpu_buddy_block_size(mm, block) - start, size); cur->remaining =3D size; cur->node =3D block; @@ -259,7 +259,7 @@ static inline void xe_res_first_dma(const struct drm_pa= gemap_addr *dma_addr, */ static inline void xe_res_next(struct xe_res_cursor *cur, u64 size) { - struct drm_buddy_block *block; + struct gpu_buddy_block *block; struct list_head *next; u64 start; =20 @@ -295,18 +295,18 @@ static inline void xe_res_next(struct xe_res_cursor *= cur, u64 size) block =3D cur->node; =20 next =3D block->link.next; - block =3D list_entry(next, struct drm_buddy_block, link); + block =3D list_entry(next, struct gpu_buddy_block, link); =20 =20 - while (start >=3D drm_buddy_block_size(cur->mm, block)) { - start -=3D drm_buddy_block_size(cur->mm, block); + while (start >=3D gpu_buddy_block_size(cur->mm, block)) { + start -=3D gpu_buddy_block_size(cur->mm, block); =20 next =3D block->link.next; - block =3D list_entry(next, struct drm_buddy_block, link); + block =3D list_entry(next, struct gpu_buddy_block, link); } =20 - cur->start =3D drm_buddy_block_offset(block) + start; - cur->size =3D min(drm_buddy_block_size(cur->mm, block) - start, + cur->start =3D gpu_buddy_block_offset(block) + start; + cur->size =3D min(gpu_buddy_block_size(cur->mm, block) - start, cur->remaining); cur->node =3D block; break; diff --git a/drivers/gpu/drm/xe/xe_svm.c b/drivers/gpu/drm/xe/xe_svm.c index f97e0af6a9b0..2b7e266f9bdd 100644 --- a/drivers/gpu/drm/xe/xe_svm.c +++ b/drivers/gpu/drm/xe/xe_svm.c @@ -688,7 +688,7 @@ static u64 block_offset_to_pfn(struct xe_vram_region *v= r, u64 offset) return PHYS_PFN(offset + vr->hpa_base); } =20 -static struct drm_buddy *vram_to_buddy(struct xe_vram_region *vram) +static struct gpu_buddy *vram_to_buddy(struct xe_vram_region *vram) { return &vram->ttm.mm; } @@ -699,16 +699,16 @@ static int xe_svm_populate_devmem_pfn(struct drm_page= map_devmem *devmem_allocati struct xe_bo *bo =3D to_xe_bo(devmem_allocation); struct ttm_resource *res =3D bo->ttm.resource; struct list_head *blocks =3D &to_xe_ttm_vram_mgr_resource(res)->blocks; - struct drm_buddy_block *block; + struct gpu_buddy_block *block; int j =3D 0; =20 list_for_each_entry(block, blocks, link) { struct xe_vram_region *vr =3D block->private; - struct drm_buddy *buddy =3D vram_to_buddy(vr); - u64 block_pfn =3D block_offset_to_pfn(vr, drm_buddy_block_offset(block)); + struct gpu_buddy *buddy =3D vram_to_buddy(vr); + u64 block_pfn =3D block_offset_to_pfn(vr, gpu_buddy_block_offset(block)); int i; =20 - for (i =3D 0; i < drm_buddy_block_size(buddy, block) >> PAGE_SHIFT; ++i) + for (i =3D 0; i < gpu_buddy_block_size(buddy, block) >> PAGE_SHIFT; ++i) pfn[j++] =3D block_pfn + i; } =20 @@ -876,7 +876,7 @@ static int xe_drm_pagemap_populate_mm(struct drm_pagema= p *dpagemap, struct dma_fence *pre_migrate_fence =3D NULL; struct xe_device *xe =3D vr->xe; struct device *dev =3D xe->drm.dev; - struct drm_buddy_block *block; + struct gpu_buddy_block *block; struct xe_validation_ctx vctx; struct list_head *blocks; struct drm_exec exec; diff --git a/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c b/drivers/gpu/drm/xe/xe_t= tm_vram_mgr.c index 9f70802fce92..8192957261e8 100644 --- a/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c +++ b/drivers/gpu/drm/xe/xe_ttm_vram_mgr.c @@ -4,8 +4,9 @@ * Copyright (C) 2021-2022 Red Hat */ =20 -#include +#include #include +#include =20 #include #include @@ -17,16 +18,16 @@ #include "xe_ttm_vram_mgr.h" #include "xe_vram_types.h" =20 -static inline struct drm_buddy_block * +static inline struct gpu_buddy_block * xe_ttm_vram_mgr_first_block(struct list_head *list) { - return list_first_entry_or_null(list, struct drm_buddy_block, link); + return list_first_entry_or_null(list, struct gpu_buddy_block, link); } =20 -static inline bool xe_is_vram_mgr_blocks_contiguous(struct drm_buddy *mm, +static inline bool xe_is_vram_mgr_blocks_contiguous(struct gpu_buddy *mm, struct list_head *head) { - struct drm_buddy_block *block; + struct gpu_buddy_block *block; u64 start, size; =20 block =3D xe_ttm_vram_mgr_first_block(head); @@ -34,12 +35,12 @@ static inline bool xe_is_vram_mgr_blocks_contiguous(str= uct drm_buddy *mm, return false; =20 while (head !=3D block->link.next) { - start =3D drm_buddy_block_offset(block); - size =3D drm_buddy_block_size(mm, block); + start =3D gpu_buddy_block_offset(block); + size =3D gpu_buddy_block_size(mm, block); =20 - block =3D list_entry(block->link.next, struct drm_buddy_block, + block =3D list_entry(block->link.next, struct gpu_buddy_block, link); - if (start + size !=3D drm_buddy_block_offset(block)) + if (start + size !=3D gpu_buddy_block_offset(block)) return false; } =20 @@ -53,7 +54,7 @@ static int xe_ttm_vram_mgr_new(struct ttm_resource_manage= r *man, { struct xe_ttm_vram_mgr *mgr =3D to_xe_ttm_vram_mgr(man); struct xe_ttm_vram_mgr_resource *vres; - struct drm_buddy *mm =3D &mgr->mm; + struct gpu_buddy *mm =3D &mgr->mm; u64 size, min_page_size; unsigned long lpfn; int err; @@ -80,10 +81,10 @@ static int xe_ttm_vram_mgr_new(struct ttm_resource_mana= ger *man, INIT_LIST_HEAD(&vres->blocks); =20 if (place->flags & TTM_PL_FLAG_TOPDOWN) - vres->flags |=3D DRM_BUDDY_TOPDOWN_ALLOCATION; + vres->flags |=3D GPU_BUDDY_TOPDOWN_ALLOCATION; =20 if (place->fpfn || lpfn !=3D man->size >> PAGE_SHIFT) - vres->flags |=3D DRM_BUDDY_RANGE_ALLOCATION; + vres->flags |=3D GPU_BUDDY_RANGE_ALLOCATION; =20 if (WARN_ON(!vres->base.size)) { err =3D -EINVAL; @@ -119,27 +120,27 @@ static int xe_ttm_vram_mgr_new(struct ttm_resource_ma= nager *man, lpfn =3D max_t(unsigned long, place->fpfn + (size >> PAGE_SHIFT), lpfn); } =20 - err =3D drm_buddy_alloc_blocks(mm, (u64)place->fpfn << PAGE_SHIFT, + err =3D gpu_buddy_alloc_blocks(mm, (u64)place->fpfn << PAGE_SHIFT, (u64)lpfn << PAGE_SHIFT, size, min_page_size, &vres->blocks, vres->flags); if (err) goto error_unlock; =20 if (place->flags & TTM_PL_FLAG_CONTIGUOUS) { - if (!drm_buddy_block_trim(mm, NULL, vres->base.size, &vres->blocks)) + if (!gpu_buddy_block_trim(mm, NULL, vres->base.size, &vres->blocks)) size =3D vres->base.size; } =20 if (lpfn <=3D mgr->visible_size >> PAGE_SHIFT) { vres->used_visible_size =3D size; } else { - struct drm_buddy_block *block; + struct gpu_buddy_block *block; =20 list_for_each_entry(block, &vres->blocks, link) { - u64 start =3D drm_buddy_block_offset(block); + u64 start =3D gpu_buddy_block_offset(block); =20 if (start < mgr->visible_size) { - u64 end =3D start + drm_buddy_block_size(mm, block); + u64 end =3D start + gpu_buddy_block_size(mm, block); =20 vres->used_visible_size +=3D min(end, mgr->visible_size) - start; @@ -159,11 +160,11 @@ static int xe_ttm_vram_mgr_new(struct ttm_resource_ma= nager *man, * the object. */ if (vres->base.placement & TTM_PL_FLAG_CONTIGUOUS) { - struct drm_buddy_block *block =3D list_first_entry(&vres->blocks, + struct gpu_buddy_block *block =3D list_first_entry(&vres->blocks, typeof(*block), link); =20 - vres->base.start =3D drm_buddy_block_offset(block) >> PAGE_SHIFT; + vres->base.start =3D gpu_buddy_block_offset(block) >> PAGE_SHIFT; } else { vres->base.start =3D XE_BO_INVALID_OFFSET; } @@ -185,10 +186,10 @@ static void xe_ttm_vram_mgr_del(struct ttm_resource_m= anager *man, struct xe_ttm_vram_mgr_resource *vres =3D to_xe_ttm_vram_mgr_resource(res); struct xe_ttm_vram_mgr *mgr =3D to_xe_ttm_vram_mgr(man); - struct drm_buddy *mm =3D &mgr->mm; + struct gpu_buddy *mm =3D &mgr->mm; =20 mutex_lock(&mgr->lock); - drm_buddy_free_list(mm, &vres->blocks, 0); + gpu_buddy_free_list(mm, &vres->blocks, 0); mgr->visible_avail +=3D vres->used_visible_size; mutex_unlock(&mgr->lock); =20 @@ -201,7 +202,7 @@ static void xe_ttm_vram_mgr_debug(struct ttm_resource_m= anager *man, struct drm_printer *printer) { struct xe_ttm_vram_mgr *mgr =3D to_xe_ttm_vram_mgr(man); - struct drm_buddy *mm =3D &mgr->mm; + struct gpu_buddy *mm =3D &mgr->mm; =20 mutex_lock(&mgr->lock); drm_printf(printer, "default_page_size: %lluKiB\n", @@ -224,8 +225,8 @@ static bool xe_ttm_vram_mgr_intersects(struct ttm_resou= rce_manager *man, struct xe_ttm_vram_mgr *mgr =3D to_xe_ttm_vram_mgr(man); struct xe_ttm_vram_mgr_resource *vres =3D to_xe_ttm_vram_mgr_resource(res); - struct drm_buddy *mm =3D &mgr->mm; - struct drm_buddy_block *block; + struct gpu_buddy *mm =3D &mgr->mm; + struct gpu_buddy_block *block; =20 if (!place->fpfn && !place->lpfn) return true; @@ -235,9 +236,9 @@ static bool xe_ttm_vram_mgr_intersects(struct ttm_resou= rce_manager *man, =20 list_for_each_entry(block, &vres->blocks, link) { unsigned long fpfn =3D - drm_buddy_block_offset(block) >> PAGE_SHIFT; + gpu_buddy_block_offset(block) >> PAGE_SHIFT; unsigned long lpfn =3D fpfn + - (drm_buddy_block_size(mm, block) >> PAGE_SHIFT); + (gpu_buddy_block_size(mm, block) >> PAGE_SHIFT); =20 if (place->fpfn < lpfn && place->lpfn > fpfn) return true; @@ -254,8 +255,8 @@ static bool xe_ttm_vram_mgr_compatible(struct ttm_resou= rce_manager *man, struct xe_ttm_vram_mgr *mgr =3D to_xe_ttm_vram_mgr(man); struct xe_ttm_vram_mgr_resource *vres =3D to_xe_ttm_vram_mgr_resource(res); - struct drm_buddy *mm =3D &mgr->mm; - struct drm_buddy_block *block; + struct gpu_buddy *mm =3D &mgr->mm; + struct gpu_buddy_block *block; =20 if (!place->fpfn && !place->lpfn) return true; @@ -265,9 +266,9 @@ static bool xe_ttm_vram_mgr_compatible(struct ttm_resou= rce_manager *man, =20 list_for_each_entry(block, &vres->blocks, link) { unsigned long fpfn =3D - drm_buddy_block_offset(block) >> PAGE_SHIFT; + gpu_buddy_block_offset(block) >> PAGE_SHIFT; unsigned long lpfn =3D fpfn + - (drm_buddy_block_size(mm, block) >> PAGE_SHIFT); + (gpu_buddy_block_size(mm, block) >> PAGE_SHIFT); =20 if (fpfn < place->fpfn || lpfn > place->lpfn) return false; @@ -297,7 +298,7 @@ static void xe_ttm_vram_mgr_fini(struct drm_device *dev= , void *arg) =20 WARN_ON_ONCE(mgr->visible_avail !=3D mgr->visible_size); =20 - drm_buddy_fini(&mgr->mm); + gpu_buddy_fini(&mgr->mm); =20 ttm_resource_manager_cleanup(&mgr->manager); =20 @@ -328,7 +329,7 @@ int __xe_ttm_vram_mgr_init(struct xe_device *xe, struct= xe_ttm_vram_mgr *mgr, mgr->visible_avail =3D io_size; =20 ttm_resource_manager_init(man, &xe->ttm, size); - err =3D drm_buddy_init(&mgr->mm, man->size, default_page_size); + err =3D gpu_buddy_init(&mgr->mm, man->size, default_page_size); if (err) return err; =20 @@ -376,7 +377,7 @@ int xe_ttm_vram_mgr_alloc_sgt(struct xe_device *xe, if (!*sgt) return -ENOMEM; =20 - /* Determine the number of DRM_BUDDY blocks to export */ + /* Determine the number of GPU_BUDDY blocks to export */ xe_res_first(res, offset, length, &cursor); while (cursor.remaining) { num_entries++; @@ -393,10 +394,10 @@ int xe_ttm_vram_mgr_alloc_sgt(struct xe_device *xe, sg->length =3D 0; =20 /* - * Walk down DRM_BUDDY blocks to populate scatterlist nodes - * @note: Use iterator api to get first the DRM_BUDDY block + * Walk down GPU_BUDDY blocks to populate scatterlist nodes + * @note: Use iterator api to get first the GPU_BUDDY block * and the number of bytes from it. Access the following - * DRM_BUDDY block(s) if more buffer needs to exported + * GPU_BUDDY block(s) if more buffer needs to exported */ xe_res_first(res, offset, length, &cursor); for_each_sgtable_sg((*sgt), sg, i) { diff --git a/drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h b/drivers/gpu/drm/x= e/xe_ttm_vram_mgr_types.h index a71e14818ec2..9106da056b49 100644 --- a/drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h +++ b/drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h @@ -6,7 +6,7 @@ #ifndef _XE_TTM_VRAM_MGR_TYPES_H_ #define _XE_TTM_VRAM_MGR_TYPES_H_ =20 -#include +#include #include =20 /** @@ -18,7 +18,7 @@ struct xe_ttm_vram_mgr { /** @manager: Base TTM resource manager */ struct ttm_resource_manager manager; /** @mm: DRM buddy allocator which manages the VRAM */ - struct drm_buddy mm; + struct gpu_buddy mm; /** @visible_size: Proped size of the CPU visible portion */ u64 visible_size; /** @visible_avail: CPU visible portion still unallocated */ diff --git a/drivers/gpu/tests/Makefile b/drivers/gpu/tests/Makefile new file mode 100644 index 000000000000..31a5ff44cb4e --- /dev/null +++ b/drivers/gpu/tests/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_GPU_BUDDY_KUNIT_TEST) +=3D gpu_buddy_test.o gpu_random.o diff --git a/drivers/gpu/drm/tests/drm_buddy_test.c b/drivers/gpu/tests/gpu= _buddy_test.c similarity index 68% rename from drivers/gpu/drm/tests/drm_buddy_test.c rename to drivers/gpu/tests/gpu_buddy_test.c index 5f40b5343bd8..dcd4741a905d 100644 --- a/drivers/gpu/drm/tests/drm_buddy_test.c +++ b/drivers/gpu/tests/gpu_buddy_test.c @@ -10,9 +10,9 @@ #include #include =20 -#include +#include =20 -#include "../lib/drm_random.h" +#include "gpu_random.h" =20 static unsigned int random_seed; =20 @@ -21,9 +21,9 @@ static inline u64 get_size(int order, u64 chunk_size) return (1 << order) * chunk_size; } =20 -static void drm_test_buddy_fragmentation_performance(struct kunit *test) +static void gpu_test_buddy_fragmentation_performance(struct kunit *test) { - struct drm_buddy_block *block, *tmp; + struct gpu_buddy_block *block, *tmp; int num_blocks, i, ret, count =3D 0; LIST_HEAD(allocated_blocks); unsigned long elapsed_ms; @@ -32,7 +32,7 @@ static void drm_test_buddy_fragmentation_performance(stru= ct kunit *test) LIST_HEAD(clear_list); LIST_HEAD(dirty_list); LIST_HEAD(free_list); - struct drm_buddy mm; + struct gpu_buddy mm; u64 mm_size =3D SZ_4G; ktime_t start, end; =20 @@ -47,7 +47,7 @@ static void drm_test_buddy_fragmentation_performance(stru= ct kunit *test) * quickly the allocator can satisfy larger, aligned requests from a pool= of * highly fragmented space. */ - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_init(&mm, mm_size, SZ_4K), + KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_init(&mm, mm_size, SZ_4K), "buddy_init failed\n"); =20 num_blocks =3D mm_size / SZ_64K; @@ -55,7 +55,7 @@ static void drm_test_buddy_fragmentation_performance(stru= ct kunit *test) start =3D ktime_get(); /* Allocate with maximum fragmentation - 8K blocks with 64K alignment */ for (i =3D 0; i < num_blocks; i++) - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, 0, mm_size, SZ_= 8K, SZ_64K, + KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_alloc_blocks(&mm, 0, mm_size, SZ_= 8K, SZ_64K, &allocated_blocks, 0), "buddy_alloc hit an error size=3D%u\n", SZ_8K); =20 @@ -68,21 +68,21 @@ static void drm_test_buddy_fragmentation_performance(st= ruct kunit *test) } =20 /* Free with different flags to ensure no coalescing */ - drm_buddy_free_list(&mm, &clear_list, DRM_BUDDY_CLEARED); - drm_buddy_free_list(&mm, &dirty_list, 0); + gpu_buddy_free_list(&mm, &clear_list, GPU_BUDDY_CLEARED); + gpu_buddy_free_list(&mm, &dirty_list, 0); =20 for (i =3D 0; i < num_blocks; i++) - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, 0, mm_size, SZ_= 64K, SZ_64K, + KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_alloc_blocks(&mm, 0, mm_size, SZ_= 64K, SZ_64K, &test_blocks, 0), "buddy_alloc hit an error size=3D%u\n", SZ_64K); - drm_buddy_free_list(&mm, &test_blocks, 0); + gpu_buddy_free_list(&mm, &test_blocks, 0); =20 end =3D ktime_get(); elapsed_ms =3D ktime_to_ms(ktime_sub(end, start)); =20 kunit_info(test, "Fragmented allocation took %lu ms\n", elapsed_ms); =20 - drm_buddy_fini(&mm); + gpu_buddy_fini(&mm); =20 /* * Reverse free order under fragmentation @@ -96,13 +96,13 @@ static void drm_test_buddy_fragmentation_performance(st= ruct kunit *test) * deallocation occurs in the opposite order of allocation, exposing the * cost difference between a linear freelist scan and an ordered tree loo= kup. */ - ret =3D drm_buddy_init(&mm, mm_size, SZ_4K); + ret =3D gpu_buddy_init(&mm, mm_size, SZ_4K); KUNIT_ASSERT_EQ(test, ret, 0); =20 start =3D ktime_get(); /* Allocate maximum fragmentation */ for (i =3D 0; i < num_blocks; i++) - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, 0, mm_size, SZ_= 8K, SZ_64K, + KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_alloc_blocks(&mm, 0, mm_size, SZ_= 8K, SZ_64K, &allocated_blocks, 0), "buddy_alloc hit an error size=3D%u\n", SZ_8K); =20 @@ -111,28 +111,28 @@ static void drm_test_buddy_fragmentation_performance(= struct kunit *test) list_move_tail(&block->link, &free_list); count++; } - drm_buddy_free_list(&mm, &free_list, DRM_BUDDY_CLEARED); + gpu_buddy_free_list(&mm, &free_list, GPU_BUDDY_CLEARED); =20 list_for_each_entry_safe_reverse(block, tmp, &allocated_blocks, link) list_move(&block->link, &reverse_list); - drm_buddy_free_list(&mm, &reverse_list, DRM_BUDDY_CLEARED); + gpu_buddy_free_list(&mm, &reverse_list, GPU_BUDDY_CLEARED); =20 end =3D ktime_get(); elapsed_ms =3D ktime_to_ms(ktime_sub(end, start)); =20 kunit_info(test, "Reverse-ordered free took %lu ms\n", elapsed_ms); =20 - drm_buddy_fini(&mm); + gpu_buddy_fini(&mm); } =20 -static void drm_test_buddy_alloc_range_bias(struct kunit *test) +static void gpu_test_buddy_alloc_range_bias(struct kunit *test) { u32 mm_size, size, ps, bias_size, bias_start, bias_end, bias_rem; - DRM_RND_STATE(prng, random_seed); + GPU_RND_STATE(prng, random_seed); unsigned int i, count, *order; - struct drm_buddy_block *block; + struct gpu_buddy_block *block; unsigned long flags; - struct drm_buddy mm; + struct gpu_buddy mm; LIST_HEAD(allocated); =20 bias_size =3D SZ_1M; @@ -142,11 +142,11 @@ static void drm_test_buddy_alloc_range_bias(struct ku= nit *test) =20 kunit_info(test, "mm_size=3D%u, ps=3D%u\n", mm_size, ps); =20 - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_init(&mm, mm_size, ps), + KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_init(&mm, mm_size, ps), "buddy_init failed\n"); =20 count =3D mm_size / bias_size; - order =3D drm_random_order(count, &prng); + order =3D gpu_random_order(count, &prng); KUNIT_EXPECT_TRUE(test, order); =20 /* @@ -166,79 +166,79 @@ static void drm_test_buddy_alloc_range_bias(struct ku= nit *test) =20 /* internal round_up too big */ KUNIT_ASSERT_TRUE_MSG(test, - drm_buddy_alloc_blocks(&mm, bias_start, + gpu_buddy_alloc_blocks(&mm, bias_start, bias_end, bias_size + ps, bias_size, &allocated, - DRM_BUDDY_RANGE_ALLOCATION), + GPU_BUDDY_RANGE_ALLOCATION), "buddy_alloc failed with bias(%x-%x), size=3D%u, ps=3D%u\n", bias_start, bias_end, bias_size, bias_size); =20 /* size too big */ KUNIT_ASSERT_TRUE_MSG(test, - drm_buddy_alloc_blocks(&mm, bias_start, + gpu_buddy_alloc_blocks(&mm, bias_start, bias_end, bias_size + ps, ps, &allocated, - DRM_BUDDY_RANGE_ALLOCATION), + GPU_BUDDY_RANGE_ALLOCATION), "buddy_alloc didn't fail with bias(%x-%x), size=3D%u, ps=3D%u\n", bias_start, bias_end, bias_size + ps, ps); =20 /* bias range too small for size */ KUNIT_ASSERT_TRUE_MSG(test, - drm_buddy_alloc_blocks(&mm, bias_start + ps, + gpu_buddy_alloc_blocks(&mm, bias_start + ps, bias_end, bias_size, ps, &allocated, - DRM_BUDDY_RANGE_ALLOCATION), + GPU_BUDDY_RANGE_ALLOCATION), "buddy_alloc didn't fail with bias(%x-%x), size=3D%u, ps=3D%u\n", bias_start + ps, bias_end, bias_size, ps); =20 /* bias misaligned */ KUNIT_ASSERT_TRUE_MSG(test, - drm_buddy_alloc_blocks(&mm, bias_start + ps, + gpu_buddy_alloc_blocks(&mm, bias_start + ps, bias_end - ps, bias_size >> 1, bias_size >> 1, &allocated, - DRM_BUDDY_RANGE_ALLOCATION), + GPU_BUDDY_RANGE_ALLOCATION), "buddy_alloc h didn't fail with bias(%x-%x), size=3D%u, ps=3D%u\= n", bias_start + ps, bias_end - ps, bias_size >> 1, bias_size >> 1); =20 /* single big page */ KUNIT_ASSERT_FALSE_MSG(test, - drm_buddy_alloc_blocks(&mm, bias_start, + gpu_buddy_alloc_blocks(&mm, bias_start, bias_end, bias_size, bias_size, &tmp, - DRM_BUDDY_RANGE_ALLOCATION), + GPU_BUDDY_RANGE_ALLOCATION), "buddy_alloc i failed with bias(%x-%x), size=3D%u, ps=3D%u\n", bias_start, bias_end, bias_size, bias_size); - drm_buddy_free_list(&mm, &tmp, 0); + gpu_buddy_free_list(&mm, &tmp, 0); =20 /* single page with internal round_up */ KUNIT_ASSERT_FALSE_MSG(test, - drm_buddy_alloc_blocks(&mm, bias_start, + gpu_buddy_alloc_blocks(&mm, bias_start, bias_end, ps, bias_size, &tmp, - DRM_BUDDY_RANGE_ALLOCATION), + GPU_BUDDY_RANGE_ALLOCATION), "buddy_alloc failed with bias(%x-%x), size=3D%u, ps=3D%u\n", bias_start, bias_end, ps, bias_size); - drm_buddy_free_list(&mm, &tmp, 0); + gpu_buddy_free_list(&mm, &tmp, 0); =20 /* random size within */ size =3D max(round_up(prandom_u32_state(&prng) % bias_rem, ps), ps); if (size) KUNIT_ASSERT_FALSE_MSG(test, - drm_buddy_alloc_blocks(&mm, bias_start, + gpu_buddy_alloc_blocks(&mm, bias_start, bias_end, size, ps, &tmp, - DRM_BUDDY_RANGE_ALLOCATION), + GPU_BUDDY_RANGE_ALLOCATION), "buddy_alloc failed with bias(%x-%x), size=3D%u, ps=3D%u\n", bias_start, bias_end, size, ps); =20 bias_rem -=3D size; /* too big for current avail */ KUNIT_ASSERT_TRUE_MSG(test, - drm_buddy_alloc_blocks(&mm, bias_start, + gpu_buddy_alloc_blocks(&mm, bias_start, bias_end, bias_rem + ps, ps, &allocated, - DRM_BUDDY_RANGE_ALLOCATION), + GPU_BUDDY_RANGE_ALLOCATION), "buddy_alloc didn't fail with bias(%x-%x), size=3D%u, ps=3D%u\n", bias_start, bias_end, bias_rem + ps, ps); =20 @@ -248,10 +248,10 @@ static void drm_test_buddy_alloc_range_bias(struct ku= nit *test) size =3D max(size, ps); =20 KUNIT_ASSERT_FALSE_MSG(test, - drm_buddy_alloc_blocks(&mm, bias_start, + gpu_buddy_alloc_blocks(&mm, bias_start, bias_end, size, ps, &allocated, - DRM_BUDDY_RANGE_ALLOCATION), + GPU_BUDDY_RANGE_ALLOCATION), "buddy_alloc failed with bias(%x-%x), size=3D%u, ps=3D%u\n", bias_start, bias_end, size, ps); /* @@ -259,15 +259,15 @@ static void drm_test_buddy_alloc_range_bias(struct ku= nit *test) * unallocated, and ideally not always on the bias * boundaries. */ - drm_buddy_free_list(&mm, &tmp, 0); + gpu_buddy_free_list(&mm, &tmp, 0); } else { list_splice_tail(&tmp, &allocated); } } =20 kfree(order); - drm_buddy_free_list(&mm, &allocated, 0); - drm_buddy_fini(&mm); + gpu_buddy_free_list(&mm, &allocated, 0); + gpu_buddy_fini(&mm); =20 /* * Something more free-form. Idea is to pick a random starting bias @@ -278,7 +278,7 @@ static void drm_test_buddy_alloc_range_bias(struct kuni= t *test) * allocated nodes in the middle of the address space. */ =20 - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_init(&mm, mm_size, ps), + KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_init(&mm, mm_size, ps), "buddy_init failed\n"); =20 bias_start =3D round_up(prandom_u32_state(&prng) % (mm_size - ps), ps); @@ -290,10 +290,10 @@ static void drm_test_buddy_alloc_range_bias(struct ku= nit *test) u32 size =3D max(round_up(prandom_u32_state(&prng) % bias_rem, ps), ps); =20 KUNIT_ASSERT_FALSE_MSG(test, - drm_buddy_alloc_blocks(&mm, bias_start, + gpu_buddy_alloc_blocks(&mm, bias_start, bias_end, size, ps, &allocated, - DRM_BUDDY_RANGE_ALLOCATION), + GPU_BUDDY_RANGE_ALLOCATION), "buddy_alloc failed with bias(%x-%x), size=3D%u, ps=3D%u\n", bias_start, bias_end, size, ps); bias_rem -=3D size; @@ -319,24 +319,24 @@ static void drm_test_buddy_alloc_range_bias(struct ku= nit *test) KUNIT_ASSERT_EQ(test, bias_start, 0); KUNIT_ASSERT_EQ(test, bias_end, mm_size); KUNIT_ASSERT_TRUE_MSG(test, - drm_buddy_alloc_blocks(&mm, bias_start, bias_end, + gpu_buddy_alloc_blocks(&mm, bias_start, bias_end, ps, ps, &allocated, - DRM_BUDDY_RANGE_ALLOCATION), + GPU_BUDDY_RANGE_ALLOCATION), "buddy_alloc passed with bias(%x-%x), size=3D%u\n", bias_start, bias_end, ps); =20 - drm_buddy_free_list(&mm, &allocated, 0); - drm_buddy_fini(&mm); + gpu_buddy_free_list(&mm, &allocated, 0); + gpu_buddy_fini(&mm); =20 /* - * Allocate cleared blocks in the bias range when the DRM buddy's clear a= vail is + * Allocate cleared blocks in the bias range when the GPU buddy's clear a= vail is * zero. This will validate the bias range allocation in scenarios like s= ystem boot * when no cleared blocks are available and exercise the fallback path to= o. The resulting * blocks should always be dirty. */ =20 - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_init(&mm, mm_size, ps), + KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_init(&mm, mm_size, ps), "buddy_init failed\n"); =20 bias_start =3D round_up(prandom_u32_state(&prng) % (mm_size - ps), ps); @@ -344,11 +344,11 @@ static void drm_test_buddy_alloc_range_bias(struct ku= nit *test) bias_end =3D max(bias_end, bias_start + ps); bias_rem =3D bias_end - bias_start; =20 - flags =3D DRM_BUDDY_CLEAR_ALLOCATION | DRM_BUDDY_RANGE_ALLOCATION; + flags =3D GPU_BUDDY_CLEAR_ALLOCATION | GPU_BUDDY_RANGE_ALLOCATION; size =3D max(round_up(prandom_u32_state(&prng) % bias_rem, ps), ps); =20 KUNIT_ASSERT_FALSE_MSG(test, - drm_buddy_alloc_blocks(&mm, bias_start, + gpu_buddy_alloc_blocks(&mm, bias_start, bias_end, size, ps, &allocated, flags), @@ -356,27 +356,27 @@ static void drm_test_buddy_alloc_range_bias(struct ku= nit *test) bias_start, bias_end, size, ps); =20 list_for_each_entry(block, &allocated, link) - KUNIT_EXPECT_EQ(test, drm_buddy_block_is_clear(block), false); + KUNIT_EXPECT_EQ(test, gpu_buddy_block_is_clear(block), false); =20 - drm_buddy_free_list(&mm, &allocated, 0); - drm_buddy_fini(&mm); + gpu_buddy_free_list(&mm, &allocated, 0); + gpu_buddy_fini(&mm); } =20 -static void drm_test_buddy_alloc_clear(struct kunit *test) +static void gpu_test_buddy_alloc_clear(struct kunit *test) { unsigned long n_pages, total, i =3D 0; const unsigned long ps =3D SZ_4K; - struct drm_buddy_block *block; + struct gpu_buddy_block *block; const int max_order =3D 12; LIST_HEAD(allocated); - struct drm_buddy mm; + struct gpu_buddy mm; unsigned int order; u32 mm_size, size; LIST_HEAD(dirty); LIST_HEAD(clean); =20 mm_size =3D SZ_4K << max_order; - KUNIT_EXPECT_FALSE(test, drm_buddy_init(&mm, mm_size, ps)); + KUNIT_EXPECT_FALSE(test, gpu_buddy_init(&mm, mm_size, ps)); =20 KUNIT_EXPECT_EQ(test, mm.max_order, max_order); =20 @@ -389,11 +389,11 @@ static void drm_test_buddy_alloc_clear(struct kunit *= test) * is indeed all dirty pages and vice versa. Free it all again, * keeping the dirty/clear status. */ - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, 0, mm_size, + KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_alloc_blocks(&mm, 0, mm_size, 5 * ps, ps, &allocated, - DRM_BUDDY_TOPDOWN_ALLOCATION), + GPU_BUDDY_TOPDOWN_ALLOCATION), "buddy_alloc hit an error size=3D%lu\n", 5 * ps); - drm_buddy_free_list(&mm, &allocated, DRM_BUDDY_CLEARED); + gpu_buddy_free_list(&mm, &allocated, GPU_BUDDY_CLEARED); =20 n_pages =3D 10; do { @@ -406,37 +406,37 @@ static void drm_test_buddy_alloc_clear(struct kunit *= test) flags =3D 0; } else { list =3D &clean; - flags =3D DRM_BUDDY_CLEAR_ALLOCATION; + flags =3D GPU_BUDDY_CLEAR_ALLOCATION; } =20 - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, 0, mm_size, + KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_alloc_blocks(&mm, 0, mm_size, ps, ps, list, flags), "buddy_alloc hit an error size=3D%lu\n", ps); } while (++i < n_pages); =20 list_for_each_entry(block, &clean, link) - KUNIT_EXPECT_EQ(test, drm_buddy_block_is_clear(block), true); + KUNIT_EXPECT_EQ(test, gpu_buddy_block_is_clear(block), true); =20 list_for_each_entry(block, &dirty, link) - KUNIT_EXPECT_EQ(test, drm_buddy_block_is_clear(block), false); + KUNIT_EXPECT_EQ(test, gpu_buddy_block_is_clear(block), false); =20 - drm_buddy_free_list(&mm, &clean, DRM_BUDDY_CLEARED); + gpu_buddy_free_list(&mm, &clean, GPU_BUDDY_CLEARED); =20 /* * Trying to go over the clear limit for some allocation. * The allocation should never fail with reasonable page-size. */ - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, 0, mm_size, + KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_alloc_blocks(&mm, 0, mm_size, 10 * ps, ps, &clean, - DRM_BUDDY_CLEAR_ALLOCATION), + GPU_BUDDY_CLEAR_ALLOCATION), "buddy_alloc hit an error size=3D%lu\n", 10 * ps); =20 - drm_buddy_free_list(&mm, &clean, DRM_BUDDY_CLEARED); - drm_buddy_free_list(&mm, &dirty, 0); - drm_buddy_fini(&mm); + gpu_buddy_free_list(&mm, &clean, GPU_BUDDY_CLEARED); + gpu_buddy_free_list(&mm, &dirty, 0); + gpu_buddy_fini(&mm); =20 - KUNIT_EXPECT_FALSE(test, drm_buddy_init(&mm, mm_size, ps)); + KUNIT_EXPECT_FALSE(test, gpu_buddy_init(&mm, mm_size, ps)); =20 /* * Create a new mm. Intentionally fragment the address space by creating @@ -458,34 +458,34 @@ static void drm_test_buddy_alloc_clear(struct kunit *= test) else list =3D &clean; =20 - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, 0, mm_size, + KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_alloc_blocks(&mm, 0, mm_size, ps, ps, list, 0), "buddy_alloc hit an error size=3D%lu\n", ps); } while (++i < n_pages); =20 - drm_buddy_free_list(&mm, &clean, DRM_BUDDY_CLEARED); - drm_buddy_free_list(&mm, &dirty, 0); + gpu_buddy_free_list(&mm, &clean, GPU_BUDDY_CLEARED); + gpu_buddy_free_list(&mm, &dirty, 0); =20 order =3D 1; do { size =3D SZ_4K << order; =20 - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, 0, mm_size, + KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_alloc_blocks(&mm, 0, mm_size, size, size, &allocated, - DRM_BUDDY_CLEAR_ALLOCATION), + GPU_BUDDY_CLEAR_ALLOCATION), "buddy_alloc hit an error size=3D%u\n", size); total =3D 0; list_for_each_entry(block, &allocated, link) { if (size !=3D mm_size) - KUNIT_EXPECT_EQ(test, drm_buddy_block_is_clear(block), false); - total +=3D drm_buddy_block_size(&mm, block); + KUNIT_EXPECT_EQ(test, gpu_buddy_block_is_clear(block), false); + total +=3D gpu_buddy_block_size(&mm, block); } KUNIT_EXPECT_EQ(test, total, size); =20 - drm_buddy_free_list(&mm, &allocated, 0); + gpu_buddy_free_list(&mm, &allocated, 0); } while (++order <=3D max_order); =20 - drm_buddy_fini(&mm); + gpu_buddy_fini(&mm); =20 /* * Create a new mm with a non power-of-two size. Allocate a random size f= rom each @@ -494,44 +494,44 @@ static void drm_test_buddy_alloc_clear(struct kunit *= test) */ mm_size =3D (SZ_4K << max_order) + (SZ_4K << (max_order - 2)); =20 - KUNIT_EXPECT_FALSE(test, drm_buddy_init(&mm, mm_size, ps)); + KUNIT_EXPECT_FALSE(test, gpu_buddy_init(&mm, mm_size, ps)); KUNIT_EXPECT_EQ(test, mm.max_order, max_order); - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, 0, SZ_4K << max_= order, + KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_alloc_blocks(&mm, 0, SZ_4K << max_= order, 4 * ps, ps, &allocated, - DRM_BUDDY_RANGE_ALLOCATION), + GPU_BUDDY_RANGE_ALLOCATION), "buddy_alloc hit an error size=3D%lu\n", 4 * ps); - drm_buddy_free_list(&mm, &allocated, DRM_BUDDY_CLEARED); - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, 0, SZ_4K << max_= order, + gpu_buddy_free_list(&mm, &allocated, GPU_BUDDY_CLEARED); + KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_alloc_blocks(&mm, 0, SZ_4K << max_= order, 2 * ps, ps, &allocated, - DRM_BUDDY_CLEAR_ALLOCATION), + GPU_BUDDY_CLEAR_ALLOCATION), "buddy_alloc hit an error size=3D%lu\n", 2 * ps); - drm_buddy_free_list(&mm, &allocated, DRM_BUDDY_CLEARED); - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, SZ_4K << max_ord= er, mm_size, + gpu_buddy_free_list(&mm, &allocated, GPU_BUDDY_CLEARED); + KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_alloc_blocks(&mm, SZ_4K << max_ord= er, mm_size, ps, ps, &allocated, - DRM_BUDDY_RANGE_ALLOCATION), + GPU_BUDDY_RANGE_ALLOCATION), "buddy_alloc hit an error size=3D%lu\n", ps); - drm_buddy_free_list(&mm, &allocated, DRM_BUDDY_CLEARED); - drm_buddy_fini(&mm); + gpu_buddy_free_list(&mm, &allocated, GPU_BUDDY_CLEARED); + gpu_buddy_fini(&mm); } =20 -static void drm_test_buddy_alloc_contiguous(struct kunit *test) +static void gpu_test_buddy_alloc_contiguous(struct kunit *test) { const unsigned long ps =3D SZ_4K, mm_size =3D 16 * 3 * SZ_4K; unsigned long i, n_pages, total; - struct drm_buddy_block *block; - struct drm_buddy mm; + struct gpu_buddy_block *block; + struct gpu_buddy mm; LIST_HEAD(left); LIST_HEAD(middle); LIST_HEAD(right); LIST_HEAD(allocated); =20 - KUNIT_EXPECT_FALSE(test, drm_buddy_init(&mm, mm_size, ps)); + KUNIT_EXPECT_FALSE(test, gpu_buddy_init(&mm, mm_size, ps)); =20 /* * Idea is to fragment the address space by alternating block * allocations between three different lists; one for left, middle and * right. We can then free a list to simulate fragmentation. In - * particular we want to exercise the DRM_BUDDY_CONTIGUOUS_ALLOCATION, + * particular we want to exercise the GPU_BUDDY_CONTIGUOUS_ALLOCATION, * including the try_harder path. */ =20 @@ -548,66 +548,66 @@ static void drm_test_buddy_alloc_contiguous(struct ku= nit *test) else list =3D &right; KUNIT_ASSERT_FALSE_MSG(test, - drm_buddy_alloc_blocks(&mm, 0, mm_size, + gpu_buddy_alloc_blocks(&mm, 0, mm_size, ps, ps, list, 0), "buddy_alloc hit an error size=3D%lu\n", ps); } while (++i < n_pages); =20 - KUNIT_ASSERT_TRUE_MSG(test, drm_buddy_alloc_blocks(&mm, 0, mm_size, + KUNIT_ASSERT_TRUE_MSG(test, gpu_buddy_alloc_blocks(&mm, 0, mm_size, 3 * ps, ps, &allocated, - DRM_BUDDY_CONTIGUOUS_ALLOCATION), + GPU_BUDDY_CONTIGUOUS_ALLOCATION), "buddy_alloc didn't error size=3D%lu\n", 3 * ps); =20 - drm_buddy_free_list(&mm, &middle, 0); - KUNIT_ASSERT_TRUE_MSG(test, drm_buddy_alloc_blocks(&mm, 0, mm_size, + gpu_buddy_free_list(&mm, &middle, 0); + KUNIT_ASSERT_TRUE_MSG(test, gpu_buddy_alloc_blocks(&mm, 0, mm_size, 3 * ps, ps, &allocated, - DRM_BUDDY_CONTIGUOUS_ALLOCATION), + GPU_BUDDY_CONTIGUOUS_ALLOCATION), "buddy_alloc didn't error size=3D%lu\n", 3 * ps); - KUNIT_ASSERT_TRUE_MSG(test, drm_buddy_alloc_blocks(&mm, 0, mm_size, + KUNIT_ASSERT_TRUE_MSG(test, gpu_buddy_alloc_blocks(&mm, 0, mm_size, 2 * ps, ps, &allocated, - DRM_BUDDY_CONTIGUOUS_ALLOCATION), + GPU_BUDDY_CONTIGUOUS_ALLOCATION), "buddy_alloc didn't error size=3D%lu\n", 2 * ps); =20 - drm_buddy_free_list(&mm, &right, 0); - KUNIT_ASSERT_TRUE_MSG(test, drm_buddy_alloc_blocks(&mm, 0, mm_size, + gpu_buddy_free_list(&mm, &right, 0); + KUNIT_ASSERT_TRUE_MSG(test, gpu_buddy_alloc_blocks(&mm, 0, mm_size, 3 * ps, ps, &allocated, - DRM_BUDDY_CONTIGUOUS_ALLOCATION), + GPU_BUDDY_CONTIGUOUS_ALLOCATION), "buddy_alloc didn't error size=3D%lu\n", 3 * ps); /* * At this point we should have enough contiguous space for 2 blocks, * however they are never buddies (since we freed middle and right) so * will require the try_harder logic to find them. */ - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, 0, mm_size, + KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_alloc_blocks(&mm, 0, mm_size, 2 * ps, ps, &allocated, - DRM_BUDDY_CONTIGUOUS_ALLOCATION), + GPU_BUDDY_CONTIGUOUS_ALLOCATION), "buddy_alloc hit an error size=3D%lu\n", 2 * ps); =20 - drm_buddy_free_list(&mm, &left, 0); - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, 0, mm_size, + gpu_buddy_free_list(&mm, &left, 0); + KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_alloc_blocks(&mm, 0, mm_size, 3 * ps, ps, &allocated, - DRM_BUDDY_CONTIGUOUS_ALLOCATION), + GPU_BUDDY_CONTIGUOUS_ALLOCATION), "buddy_alloc hit an error size=3D%lu\n", 3 * ps); =20 total =3D 0; list_for_each_entry(block, &allocated, link) - total +=3D drm_buddy_block_size(&mm, block); + total +=3D gpu_buddy_block_size(&mm, block); =20 KUNIT_ASSERT_EQ(test, total, ps * 2 + ps * 3); =20 - drm_buddy_free_list(&mm, &allocated, 0); - drm_buddy_fini(&mm); + gpu_buddy_free_list(&mm, &allocated, 0); + gpu_buddy_fini(&mm); } =20 -static void drm_test_buddy_alloc_pathological(struct kunit *test) +static void gpu_test_buddy_alloc_pathological(struct kunit *test) { u64 mm_size, size, start =3D 0; - struct drm_buddy_block *block; + struct gpu_buddy_block *block; const int max_order =3D 3; unsigned long flags =3D 0; int order, top; - struct drm_buddy mm; + struct gpu_buddy mm; LIST_HEAD(blocks); LIST_HEAD(holes); LIST_HEAD(tmp); @@ -620,7 +620,7 @@ static void drm_test_buddy_alloc_pathological(struct ku= nit *test) */ =20 mm_size =3D SZ_4K << max_order; - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_init(&mm, mm_size, SZ_4K), + KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_init(&mm, mm_size, SZ_4K), "buddy_init failed\n"); =20 KUNIT_EXPECT_EQ(test, mm.max_order, max_order); @@ -630,18 +630,18 @@ static void drm_test_buddy_alloc_pathological(struct = kunit *test) block =3D list_first_entry_or_null(&blocks, typeof(*block), link); if (block) { list_del(&block->link); - drm_buddy_free_block(&mm, block); + gpu_buddy_free_block(&mm, block); } =20 for (order =3D top; order--;) { size =3D get_size(order, mm.chunk_size); - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, start, + KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_alloc_blocks(&mm, start, mm_size, size, size, &tmp, flags), "buddy_alloc hit -ENOMEM with order=3D%d, top=3D%d\n", order, top); =20 - block =3D list_first_entry_or_null(&tmp, struct drm_buddy_block, link); + block =3D list_first_entry_or_null(&tmp, struct gpu_buddy_block, link); KUNIT_ASSERT_TRUE_MSG(test, block, "alloc_blocks has no blocks\n"); =20 list_move_tail(&block->link, &blocks); @@ -649,45 +649,45 @@ static void drm_test_buddy_alloc_pathological(struct = kunit *test) =20 /* There should be one final page for this sub-allocation */ size =3D get_size(0, mm.chunk_size); - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, start, mm_size, + KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_alloc_blocks(&mm, start, mm_size, size, size, &tmp, flags), "buddy_alloc hit -ENOMEM for hole\n"); =20 - block =3D list_first_entry_or_null(&tmp, struct drm_buddy_block, link); + block =3D list_first_entry_or_null(&tmp, struct gpu_buddy_block, link); KUNIT_ASSERT_TRUE_MSG(test, block, "alloc_blocks has no blocks\n"); =20 list_move_tail(&block->link, &holes); =20 size =3D get_size(top, mm.chunk_size); - KUNIT_ASSERT_TRUE_MSG(test, drm_buddy_alloc_blocks(&mm, start, mm_size, + KUNIT_ASSERT_TRUE_MSG(test, gpu_buddy_alloc_blocks(&mm, start, mm_size, size, size, &tmp, flags), "buddy_alloc unexpectedly succeeded at top-order %d/%d, it should= be full!", top, max_order); } =20 - drm_buddy_free_list(&mm, &holes, 0); + gpu_buddy_free_list(&mm, &holes, 0); =20 /* Nothing larger than blocks of chunk_size now available */ for (order =3D 1; order <=3D max_order; order++) { size =3D get_size(order, mm.chunk_size); - KUNIT_ASSERT_TRUE_MSG(test, drm_buddy_alloc_blocks(&mm, start, mm_size, + KUNIT_ASSERT_TRUE_MSG(test, gpu_buddy_alloc_blocks(&mm, start, mm_size, size, size, &tmp, flags), "buddy_alloc unexpectedly succeeded at order %d, it should be ful= l!", order); } =20 list_splice_tail(&holes, &blocks); - drm_buddy_free_list(&mm, &blocks, 0); - drm_buddy_fini(&mm); + gpu_buddy_free_list(&mm, &blocks, 0); + gpu_buddy_fini(&mm); } =20 -static void drm_test_buddy_alloc_pessimistic(struct kunit *test) +static void gpu_test_buddy_alloc_pessimistic(struct kunit *test) { u64 mm_size, size, start =3D 0; - struct drm_buddy_block *block, *bn; + struct gpu_buddy_block *block, *bn; const unsigned int max_order =3D 16; unsigned long flags =3D 0; - struct drm_buddy mm; + struct gpu_buddy mm; unsigned int order; LIST_HEAD(blocks); LIST_HEAD(tmp); @@ -699,19 +699,19 @@ static void drm_test_buddy_alloc_pessimistic(struct k= unit *test) */ =20 mm_size =3D SZ_4K << max_order; - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_init(&mm, mm_size, SZ_4K), + KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_init(&mm, mm_size, SZ_4K), "buddy_init failed\n"); =20 KUNIT_EXPECT_EQ(test, mm.max_order, max_order); =20 for (order =3D 0; order < max_order; order++) { size =3D get_size(order, mm.chunk_size); - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, start, mm_size, + KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_alloc_blocks(&mm, start, mm_size, size, size, &tmp, flags), "buddy_alloc hit -ENOMEM with order=3D%d\n", order); =20 - block =3D list_first_entry_or_null(&tmp, struct drm_buddy_block, link); + block =3D list_first_entry_or_null(&tmp, struct gpu_buddy_block, link); KUNIT_ASSERT_TRUE_MSG(test, block, "alloc_blocks has no blocks\n"); =20 list_move_tail(&block->link, &blocks); @@ -719,11 +719,11 @@ static void drm_test_buddy_alloc_pessimistic(struct k= unit *test) =20 /* And now the last remaining block available */ size =3D get_size(0, mm.chunk_size); - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, start, mm_size, + KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_alloc_blocks(&mm, start, mm_size, size, size, &tmp, flags), "buddy_alloc hit -ENOMEM on final alloc\n"); =20 - block =3D list_first_entry_or_null(&tmp, struct drm_buddy_block, link); + block =3D list_first_entry_or_null(&tmp, struct gpu_buddy_block, link); KUNIT_ASSERT_TRUE_MSG(test, block, "alloc_blocks has no blocks\n"); =20 list_move_tail(&block->link, &blocks); @@ -731,58 +731,58 @@ static void drm_test_buddy_alloc_pessimistic(struct k= unit *test) /* Should be completely full! */ for (order =3D max_order; order--;) { size =3D get_size(order, mm.chunk_size); - KUNIT_ASSERT_TRUE_MSG(test, drm_buddy_alloc_blocks(&mm, start, mm_size, + KUNIT_ASSERT_TRUE_MSG(test, gpu_buddy_alloc_blocks(&mm, start, mm_size, size, size, &tmp, flags), "buddy_alloc unexpectedly succeeded, it should be full!"); } =20 block =3D list_last_entry(&blocks, typeof(*block), link); list_del(&block->link); - drm_buddy_free_block(&mm, block); + gpu_buddy_free_block(&mm, block); =20 /* As we free in increasing size, we make available larger blocks */ order =3D 1; list_for_each_entry_safe(block, bn, &blocks, link) { list_del(&block->link); - drm_buddy_free_block(&mm, block); + gpu_buddy_free_block(&mm, block); =20 size =3D get_size(order, mm.chunk_size); - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, start, mm_size, + KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_alloc_blocks(&mm, start, mm_size, size, size, &tmp, flags), "buddy_alloc hit -ENOMEM with order=3D%d\n", order); =20 - block =3D list_first_entry_or_null(&tmp, struct drm_buddy_block, link); + block =3D list_first_entry_or_null(&tmp, struct gpu_buddy_block, link); KUNIT_ASSERT_TRUE_MSG(test, block, "alloc_blocks has no blocks\n"); =20 list_del(&block->link); - drm_buddy_free_block(&mm, block); + gpu_buddy_free_block(&mm, block); order++; } =20 /* To confirm, now the whole mm should be available */ size =3D get_size(max_order, mm.chunk_size); - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, start, mm_size, + KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_alloc_blocks(&mm, start, mm_size, size, size, &tmp, flags), "buddy_alloc (realloc) hit -ENOMEM with order=3D%d\n", max_order); =20 - block =3D list_first_entry_or_null(&tmp, struct drm_buddy_block, link); + block =3D list_first_entry_or_null(&tmp, struct gpu_buddy_block, link); KUNIT_ASSERT_TRUE_MSG(test, block, "alloc_blocks has no blocks\n"); =20 list_del(&block->link); - drm_buddy_free_block(&mm, block); - drm_buddy_free_list(&mm, &blocks, 0); - drm_buddy_fini(&mm); + gpu_buddy_free_block(&mm, block); + gpu_buddy_free_list(&mm, &blocks, 0); + gpu_buddy_fini(&mm); } =20 -static void drm_test_buddy_alloc_optimistic(struct kunit *test) +static void gpu_test_buddy_alloc_optimistic(struct kunit *test) { u64 mm_size, size, start =3D 0; - struct drm_buddy_block *block; + struct gpu_buddy_block *block; unsigned long flags =3D 0; const int max_order =3D 16; - struct drm_buddy mm; + struct gpu_buddy mm; LIST_HEAD(blocks); LIST_HEAD(tmp); int order; @@ -794,19 +794,19 @@ static void drm_test_buddy_alloc_optimistic(struct ku= nit *test) =20 mm_size =3D SZ_4K * ((1 << (max_order + 1)) - 1); =20 - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_init(&mm, mm_size, SZ_4K), + KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_init(&mm, mm_size, SZ_4K), "buddy_init failed\n"); =20 KUNIT_EXPECT_EQ(test, mm.max_order, max_order); =20 for (order =3D 0; order <=3D max_order; order++) { size =3D get_size(order, mm.chunk_size); - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, start, mm_size, + KUNIT_ASSERT_FALSE_MSG(test, gpu_buddy_alloc_blocks(&mm, start, mm_size, size, size, &tmp, flags), "buddy_alloc hit -ENOMEM with order=3D%d\n", order); =20 - block =3D list_first_entry_or_null(&tmp, struct drm_buddy_block, link); + block =3D list_first_entry_or_null(&tmp, struct gpu_buddy_block, link); KUNIT_ASSERT_TRUE_MSG(test, block, "alloc_blocks has no blocks\n"); =20 list_move_tail(&block->link, &blocks); @@ -814,80 +814,80 @@ static void drm_test_buddy_alloc_optimistic(struct ku= nit *test) =20 /* Should be completely full! */ size =3D get_size(0, mm.chunk_size); - KUNIT_ASSERT_TRUE_MSG(test, drm_buddy_alloc_blocks(&mm, start, mm_size, + KUNIT_ASSERT_TRUE_MSG(test, gpu_buddy_alloc_blocks(&mm, start, mm_size, size, size, &tmp, flags), "buddy_alloc unexpectedly succeeded, it should be full!"); =20 - drm_buddy_free_list(&mm, &blocks, 0); - drm_buddy_fini(&mm); + gpu_buddy_free_list(&mm, &blocks, 0); + gpu_buddy_fini(&mm); } =20 -static void drm_test_buddy_alloc_limit(struct kunit *test) +static void gpu_test_buddy_alloc_limit(struct kunit *test) { u64 size =3D U64_MAX, start =3D 0; - struct drm_buddy_block *block; + struct gpu_buddy_block *block; unsigned long flags =3D 0; LIST_HEAD(allocated); - struct drm_buddy mm; + struct gpu_buddy mm; =20 - KUNIT_EXPECT_FALSE(test, drm_buddy_init(&mm, size, SZ_4K)); + KUNIT_EXPECT_FALSE(test, gpu_buddy_init(&mm, size, SZ_4K)); =20 - KUNIT_EXPECT_EQ_MSG(test, mm.max_order, DRM_BUDDY_MAX_ORDER, + KUNIT_EXPECT_EQ_MSG(test, mm.max_order, GPU_BUDDY_MAX_ORDER, "mm.max_order(%d) !=3D %d\n", mm.max_order, - DRM_BUDDY_MAX_ORDER); + GPU_BUDDY_MAX_ORDER); =20 size =3D mm.chunk_size << mm.max_order; - KUNIT_EXPECT_FALSE(test, drm_buddy_alloc_blocks(&mm, start, size, size, + KUNIT_EXPECT_FALSE(test, gpu_buddy_alloc_blocks(&mm, start, size, size, mm.chunk_size, &allocated, flags)); =20 - block =3D list_first_entry_or_null(&allocated, struct drm_buddy_block, li= nk); + block =3D list_first_entry_or_null(&allocated, struct gpu_buddy_block, li= nk); KUNIT_EXPECT_TRUE(test, block); =20 - KUNIT_EXPECT_EQ_MSG(test, drm_buddy_block_order(block), mm.max_order, + KUNIT_EXPECT_EQ_MSG(test, gpu_buddy_block_order(block), mm.max_order, "block order(%d) !=3D %d\n", - drm_buddy_block_order(block), mm.max_order); + gpu_buddy_block_order(block), mm.max_order); =20 - KUNIT_EXPECT_EQ_MSG(test, drm_buddy_block_size(&mm, block), + KUNIT_EXPECT_EQ_MSG(test, gpu_buddy_block_size(&mm, block), BIT_ULL(mm.max_order) * mm.chunk_size, "block size(%llu) !=3D %llu\n", - drm_buddy_block_size(&mm, block), + gpu_buddy_block_size(&mm, block), BIT_ULL(mm.max_order) * mm.chunk_size); =20 - drm_buddy_free_list(&mm, &allocated, 0); - drm_buddy_fini(&mm); + gpu_buddy_free_list(&mm, &allocated, 0); + gpu_buddy_fini(&mm); } =20 -static int drm_buddy_suite_init(struct kunit_suite *suite) +static int gpu_buddy_suite_init(struct kunit_suite *suite) { while (!random_seed) random_seed =3D get_random_u32(); =20 - kunit_info(suite, "Testing DRM buddy manager, with random_seed=3D0x%x\n", + kunit_info(suite, "Testing GPU buddy manager, with random_seed=3D0x%x\n", random_seed); =20 return 0; } =20 -static struct kunit_case drm_buddy_tests[] =3D { - KUNIT_CASE(drm_test_buddy_alloc_limit), - KUNIT_CASE(drm_test_buddy_alloc_optimistic), - KUNIT_CASE(drm_test_buddy_alloc_pessimistic), - KUNIT_CASE(drm_test_buddy_alloc_pathological), - KUNIT_CASE(drm_test_buddy_alloc_contiguous), - KUNIT_CASE(drm_test_buddy_alloc_clear), - KUNIT_CASE(drm_test_buddy_alloc_range_bias), - KUNIT_CASE(drm_test_buddy_fragmentation_performance), +static struct kunit_case gpu_buddy_tests[] =3D { + KUNIT_CASE(gpu_test_buddy_alloc_limit), + KUNIT_CASE(gpu_test_buddy_alloc_optimistic), + KUNIT_CASE(gpu_test_buddy_alloc_pessimistic), + KUNIT_CASE(gpu_test_buddy_alloc_pathological), + KUNIT_CASE(gpu_test_buddy_alloc_contiguous), + KUNIT_CASE(gpu_test_buddy_alloc_clear), + KUNIT_CASE(gpu_test_buddy_alloc_range_bias), + KUNIT_CASE(gpu_test_buddy_fragmentation_performance), {} }; =20 -static struct kunit_suite drm_buddy_test_suite =3D { - .name =3D "drm_buddy", - .suite_init =3D drm_buddy_suite_init, - .test_cases =3D drm_buddy_tests, +static struct kunit_suite gpu_buddy_test_suite =3D { + .name =3D "gpu_buddy", + .suite_init =3D gpu_buddy_suite_init, + .test_cases =3D gpu_buddy_tests, }; =20 -kunit_test_suite(drm_buddy_test_suite); +kunit_test_suite(gpu_buddy_test_suite); =20 MODULE_AUTHOR("Intel Corporation"); -MODULE_DESCRIPTION("Kunit test for drm_buddy functions"); +MODULE_DESCRIPTION("Kunit test for gpu_buddy functions"); MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/tests/gpu_random.c b/drivers/gpu/tests/gpu_random.c new file mode 100644 index 000000000000..54f1f6a3a6c1 --- /dev/null +++ b/drivers/gpu/tests/gpu_random.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include +#include +#include +#include +#include + +#include "gpu_random.h" + +u32 gpu_prandom_u32_max_state(u32 ep_ro, struct rnd_state *state) +{ + return upper_32_bits((u64)prandom_u32_state(state) * ep_ro); +} +EXPORT_SYMBOL(gpu_prandom_u32_max_state); + +void gpu_random_reorder(unsigned int *order, unsigned int count, + struct rnd_state *state) +{ + unsigned int i, j; + + for (i =3D 0; i < count; ++i) { + BUILD_BUG_ON(sizeof(unsigned int) > sizeof(u32)); + j =3D gpu_prandom_u32_max_state(count, state); + swap(order[i], order[j]); + } +} +EXPORT_SYMBOL(gpu_random_reorder); + +unsigned int *gpu_random_order(unsigned int count, struct rnd_state *state) +{ + unsigned int *order, i; + + order =3D kmalloc_array(count, sizeof(*order), GFP_KERNEL); + if (!order) + return order; + + for (i =3D 0; i < count; i++) + order[i] =3D i; + + gpu_random_reorder(order, count, state); + return order; +} +EXPORT_SYMBOL(gpu_random_order); + +MODULE_DESCRIPTION("GPU Randomization Utilities"); +MODULE_LICENSE("Dual MIT/GPL"); diff --git a/drivers/gpu/tests/gpu_random.h b/drivers/gpu/tests/gpu_random.h new file mode 100644 index 000000000000..b68cf3448264 --- /dev/null +++ b/drivers/gpu/tests/gpu_random.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __GPU_RANDOM_H__ +#define __GPU_RANDOM_H__ + +/* This is a temporary home for a couple of utility functions that should + * be transposed to lib/ at the earliest convenience. + */ + +#include + +#define GPU_RND_STATE_INITIALIZER(seed__) ({ \ + struct rnd_state state__; \ + prandom_seed_state(&state__, (seed__)); \ + state__; \ +}) + +#define GPU_RND_STATE(name__, seed__) \ + struct rnd_state name__ =3D GPU_RND_STATE_INITIALIZER(seed__) + +unsigned int *gpu_random_order(unsigned int count, + struct rnd_state *state); +void gpu_random_reorder(unsigned int *order, + unsigned int count, + struct rnd_state *state); +u32 gpu_prandom_u32_max_state(u32 ep_ro, + struct rnd_state *state); + +#endif /* !__GPU_RANDOM_H__ */ diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index d51777df12d1..6ae1383b0e2e 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -37,6 +37,8 @@ source "drivers/char/agp/Kconfig" =20 source "drivers/gpu/vga/Kconfig" =20 +source "drivers/gpu/Kconfig" + source "drivers/gpu/host1x/Kconfig" source "drivers/gpu/ipu-v3/Kconfig" source "drivers/gpu/nova-core/Kconfig" diff --git a/include/drm/drm_buddy.h b/include/drm/drm_buddy.h index b909fa8f810a..3054369bebff 100644 --- a/include/drm/drm_buddy.h +++ b/include/drm/drm_buddy.h @@ -6,166 +6,13 @@ #ifndef __DRM_BUDDY_H__ #define __DRM_BUDDY_H__ =20 -#include -#include -#include -#include -#include +#include =20 struct drm_printer; =20 -#define DRM_BUDDY_RANGE_ALLOCATION BIT(0) -#define DRM_BUDDY_TOPDOWN_ALLOCATION BIT(1) -#define DRM_BUDDY_CONTIGUOUS_ALLOCATION BIT(2) -#define DRM_BUDDY_CLEAR_ALLOCATION BIT(3) -#define DRM_BUDDY_CLEARED BIT(4) -#define DRM_BUDDY_TRIM_DISABLE BIT(5) - -struct drm_buddy_block { -#define DRM_BUDDY_HEADER_OFFSET GENMASK_ULL(63, 12) -#define DRM_BUDDY_HEADER_STATE GENMASK_ULL(11, 10) -#define DRM_BUDDY_ALLOCATED (1 << 10) -#define DRM_BUDDY_FREE (2 << 10) -#define DRM_BUDDY_SPLIT (3 << 10) -#define DRM_BUDDY_HEADER_CLEAR GENMASK_ULL(9, 9) -/* Free to be used, if needed in the future */ -#define DRM_BUDDY_HEADER_UNUSED GENMASK_ULL(8, 6) -#define DRM_BUDDY_HEADER_ORDER GENMASK_ULL(5, 0) - u64 header; - - struct drm_buddy_block *left; - struct drm_buddy_block *right; - struct drm_buddy_block *parent; - - void *private; /* owned by creator */ - - /* - * While the block is allocated by the user through drm_buddy_alloc*, - * the user has ownership of the link, for example to maintain within - * a list, if so desired. As soon as the block is freed with - * drm_buddy_free* ownership is given back to the mm. - */ - union { - struct rb_node rb; - struct list_head link; - }; - - struct list_head tmp_link; -}; - -/* Order-zero must be at least SZ_4K */ -#define DRM_BUDDY_MAX_ORDER (63 - 12) - -/* - * Binary Buddy System. - * - * Locking should be handled by the user, a simple mutex around - * drm_buddy_alloc* and drm_buddy_free* should suffice. - */ -struct drm_buddy { - /* Maintain a free list for each order. */ - struct rb_root **free_trees; - - /* - * Maintain explicit binary tree(s) to track the allocation of the - * address space. This gives us a simple way of finding a buddy block - * and performing the potentially recursive merge step when freeing a - * block. Nodes are either allocated or free, in which case they will - * also exist on the respective free list. - */ - struct drm_buddy_block **roots; - - /* - * Anything from here is public, and remains static for the lifetime of - * the mm. Everything above is considered do-not-touch. - */ - unsigned int n_roots; - unsigned int max_order; - - /* Must be at least SZ_4K */ - u64 chunk_size; - u64 size; - u64 avail; - u64 clear_avail; -}; - -static inline u64 -drm_buddy_block_offset(const struct drm_buddy_block *block) -{ - return block->header & DRM_BUDDY_HEADER_OFFSET; -} - -static inline unsigned int -drm_buddy_block_order(struct drm_buddy_block *block) -{ - return block->header & DRM_BUDDY_HEADER_ORDER; -} - -static inline unsigned int -drm_buddy_block_state(struct drm_buddy_block *block) -{ - return block->header & DRM_BUDDY_HEADER_STATE; -} - -static inline bool -drm_buddy_block_is_allocated(struct drm_buddy_block *block) -{ - return drm_buddy_block_state(block) =3D=3D DRM_BUDDY_ALLOCATED; -} - -static inline bool -drm_buddy_block_is_clear(struct drm_buddy_block *block) -{ - return block->header & DRM_BUDDY_HEADER_CLEAR; -} - -static inline bool -drm_buddy_block_is_free(struct drm_buddy_block *block) -{ - return drm_buddy_block_state(block) =3D=3D DRM_BUDDY_FREE; -} - -static inline bool -drm_buddy_block_is_split(struct drm_buddy_block *block) -{ - return drm_buddy_block_state(block) =3D=3D DRM_BUDDY_SPLIT; -} - -static inline u64 -drm_buddy_block_size(struct drm_buddy *mm, - struct drm_buddy_block *block) -{ - return mm->chunk_size << drm_buddy_block_order(block); -} - -int drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size); - -void drm_buddy_fini(struct drm_buddy *mm); - -struct drm_buddy_block * -drm_get_buddy(struct drm_buddy_block *block); - -int drm_buddy_alloc_blocks(struct drm_buddy *mm, - u64 start, u64 end, u64 size, - u64 min_page_size, - struct list_head *blocks, - unsigned long flags); - -int drm_buddy_block_trim(struct drm_buddy *mm, - u64 *start, - u64 new_size, - struct list_head *blocks); - -void drm_buddy_reset_clear(struct drm_buddy *mm, bool is_clear); - -void drm_buddy_free_block(struct drm_buddy *mm, struct drm_buddy_block *bl= ock); - -void drm_buddy_free_list(struct drm_buddy *mm, - struct list_head *objects, - unsigned int flags); - -void drm_buddy_print(struct drm_buddy *mm, struct drm_printer *p); -void drm_buddy_block_print(struct drm_buddy *mm, - struct drm_buddy_block *block, +/* DRM-specific GPU Buddy Allocator print helpers */ +void drm_buddy_print(struct gpu_buddy *mm, struct drm_printer *p); +void drm_buddy_block_print(struct gpu_buddy *mm, + struct gpu_buddy_block *block, struct drm_printer *p); #endif diff --git a/include/linux/gpu_buddy.h b/include/linux/gpu_buddy.h new file mode 100644 index 000000000000..3e4bd11ccb71 --- /dev/null +++ b/include/linux/gpu_buddy.h @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright =C2=A9 2021 Intel Corporation + */ + +#ifndef __GPU_BUDDY_H__ +#define __GPU_BUDDY_H__ + +#include +#include +#include +#include +#include + +#define GPU_BUDDY_RANGE_ALLOCATION BIT(0) +#define GPU_BUDDY_TOPDOWN_ALLOCATION BIT(1) +#define GPU_BUDDY_CONTIGUOUS_ALLOCATION BIT(2) +#define GPU_BUDDY_CLEAR_ALLOCATION BIT(3) +#define GPU_BUDDY_CLEARED BIT(4) +#define GPU_BUDDY_TRIM_DISABLE BIT(5) + +enum gpu_buddy_free_tree { + GPU_BUDDY_CLEAR_TREE =3D 0, + GPU_BUDDY_DIRTY_TREE, + GPU_BUDDY_MAX_FREE_TREES, +}; + +#define for_each_free_tree(tree) \ + for ((tree) =3D 0; (tree) < GPU_BUDDY_MAX_FREE_TREES; (tree)++) + +struct gpu_buddy_block { +#define GPU_BUDDY_HEADER_OFFSET GENMASK_ULL(63, 12) +#define GPU_BUDDY_HEADER_STATE GENMASK_ULL(11, 10) +#define GPU_BUDDY_ALLOCATED (1 << 10) +#define GPU_BUDDY_FREE (2 << 10) +#define GPU_BUDDY_SPLIT (3 << 10) +#define GPU_BUDDY_HEADER_CLEAR GENMASK_ULL(9, 9) +/* Free to be used, if needed in the future */ +#define GPU_BUDDY_HEADER_UNUSED GENMASK_ULL(8, 6) +#define GPU_BUDDY_HEADER_ORDER GENMASK_ULL(5, 0) + u64 header; + + struct gpu_buddy_block *left; + struct gpu_buddy_block *right; + struct gpu_buddy_block *parent; + + void *private; /* owned by creator */ + + /* + * While the block is allocated by the user through gpu_buddy_alloc*, + * the user has ownership of the link, for example to maintain within + * a list, if so desired. As soon as the block is freed with + * gpu_buddy_free* ownership is given back to the mm. + */ + union { + struct rb_node rb; + struct list_head link; + }; + + struct list_head tmp_link; +}; + +/* Order-zero must be at least SZ_4K */ +#define GPU_BUDDY_MAX_ORDER (63 - 12) + +/* + * Binary Buddy System. + * + * Locking should be handled by the user, a simple mutex around + * gpu_buddy_alloc* and gpu_buddy_free* should suffice. + */ +struct gpu_buddy { + /* Maintain a free list for each order. */ + struct rb_root **free_trees; + + /* + * Maintain explicit binary tree(s) to track the allocation of the + * address space. This gives us a simple way of finding a buddy block + * and performing the potentially recursive merge step when freeing a + * block. Nodes are either allocated or free, in which case they will + * also exist on the respective free list. + */ + struct gpu_buddy_block **roots; + + /* + * Anything from here is public, and remains static for the lifetime of + * the mm. Everything above is considered do-not-touch. + */ + unsigned int n_roots; + unsigned int max_order; + + /* Must be at least SZ_4K */ + u64 chunk_size; + u64 size; + u64 avail; + u64 clear_avail; +}; + +static inline u64 +gpu_buddy_block_offset(const struct gpu_buddy_block *block) +{ + return block->header & GPU_BUDDY_HEADER_OFFSET; +} + +static inline unsigned int +gpu_buddy_block_order(struct gpu_buddy_block *block) +{ + return block->header & GPU_BUDDY_HEADER_ORDER; +} + +static inline unsigned int +gpu_buddy_block_state(struct gpu_buddy_block *block) +{ + return block->header & GPU_BUDDY_HEADER_STATE; +} + +static inline bool +gpu_buddy_block_is_allocated(struct gpu_buddy_block *block) +{ + return gpu_buddy_block_state(block) =3D=3D GPU_BUDDY_ALLOCATED; +} + +static inline bool +gpu_buddy_block_is_clear(struct gpu_buddy_block *block) +{ + return block->header & GPU_BUDDY_HEADER_CLEAR; +} + +static inline bool +gpu_buddy_block_is_free(struct gpu_buddy_block *block) +{ + return gpu_buddy_block_state(block) =3D=3D GPU_BUDDY_FREE; +} + +static inline bool +gpu_buddy_block_is_split(struct gpu_buddy_block *block) +{ + return gpu_buddy_block_state(block) =3D=3D GPU_BUDDY_SPLIT; +} + +static inline u64 +gpu_buddy_block_size(struct gpu_buddy *mm, + struct gpu_buddy_block *block) +{ + return mm->chunk_size << gpu_buddy_block_order(block); +} + +int gpu_buddy_init(struct gpu_buddy *mm, u64 size, u64 chunk_size); + +void gpu_buddy_fini(struct gpu_buddy *mm); + +struct gpu_buddy_block * +gpu_get_buddy(struct gpu_buddy_block *block); + +int gpu_buddy_alloc_blocks(struct gpu_buddy *mm, + u64 start, u64 end, u64 size, + u64 min_page_size, + struct list_head *blocks, + unsigned long flags); + +int gpu_buddy_block_trim(struct gpu_buddy *mm, + u64 *start, + u64 new_size, + struct list_head *blocks); + +void gpu_buddy_reset_clear(struct gpu_buddy *mm, bool is_clear); + +void gpu_buddy_free_block(struct gpu_buddy *mm, struct gpu_buddy_block *bl= ock); + +void gpu_buddy_free_list(struct gpu_buddy *mm, + struct list_head *objects, + unsigned int flags); + +void gpu_buddy_print(struct gpu_buddy *mm); +void gpu_buddy_block_print(struct gpu_buddy *mm, + struct gpu_buddy_block *block); +#endif --=20 2.34.1 From nobody Sun Feb 8 09:32:51 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013025.outbound.protection.outlook.com [40.93.201.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 501493C1FF7; Tue, 20 Jan 2026 20:43:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.201.25 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941830; cv=fail; b=D1Z9UpD6BkOi2B7H4wRtt2LUsMv2UqBcmSNV+N+L/nI9cex3k9w/ST+dbyb9n1HvwqSQKVrL4SXQ8V49nLRxP0pcHNVbqhQpSFtAf3vtRWZXC08VEZIWtU2XazASXJNraEtJnC8W+YsN5fWabngdLBwQMT5PeHH3qSr15WY+JQ0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941830; c=relaxed/simple; bh=5AbQNtFgFg5hut6XyuDw/4x2Y312e7ZHM84oY5PVGXI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=hBOnucbXwbsZNeXPe031ZPJwOfsMVqw+Ep5NgsBfPzQIfrXfHVlRMBD3EDEEyQBSqaT7R80eVUCdP0JpT8yncf39BxhlmDOvPbekdf+i0+1o9Z+mQJB39c0+e3yCwpBmckY9cqCz/jgy+GFtjJF4XtOq7OOannw898tJfQQzNq8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=pcjqvZ0m; arc=fail smtp.client-ip=40.93.201.25 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="pcjqvZ0m" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=LUc8qOkZEO2aHTb8Xje6xS1n0qrZXlzLybjONTgpYCQXhw8zBZuJCBome9IZaTWOmq7NO4qosojrlgT61bFYKm1H79aLZHNnYxa2BVHdI5V0T0PqiqGa/lqTYUZTXCigNiexIplZZ6qfqFVUAu6qr5v6YmTfmCAeUI5C4DUNPh6w90Yi87qwCt2O1SoD62pVmfgdPN6Hp+OXAO8HHIdjJmEwPQ/3NUx0MjkngpohxAgwp7pBcdyEsT/uirTzDgZjk3kK+u7YygfH8kDTN1Ffq0HIn7azIsOhtfgDOb2yGqXBtHIcYaqQDzCcDhFOKMWy9Z0ukB3Utw6c+novNdo58A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=nhJEbm334Y4mYLDLMaEKkpHpnXKWUl+ulNe7MV5HAkk=; b=nwoUDggYsnRLYBtiJRPrWrywxq28AaQC5RwOXyY4B6yNMS5SbAB+7SoUB/ZLDRsSV5ldB4imF1fSrkjrem6Hx/P6Scv06O4RcANGS/omDL23oFObxK0n+B6TZlTMWCQ2JefeIvfGdOAD5FX3/rcVnFMbLAuwSTukhkPDorHBySZegl5FnVBGowGg8l2/UYGV+iCT/+GY07ASyqUKDqRAoeD9ku9nXpoKAGMjiFtP8eDa9UrkFPj1vOKBaDlPDJejNndJZRAnVwXIlsVZVtJ9H2JVthR0iOaJbXYtHe3kXpOcls8JVfATBjx+1IZ2/8Vilr0SX/yjIr9GfjVoirOywg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=nhJEbm334Y4mYLDLMaEKkpHpnXKWUl+ulNe7MV5HAkk=; b=pcjqvZ0mc/YWE+xlCFnH2tMvChftx4xH+oLYEo2hCBi0lVRePix6RE2TqbERl1fZ3WjL35qALytgenHKuB4Ru6eLM+vorL6uv61HGoZUjVkxKsFssFXUMSuUpGy6MqTd8U038gWBc7gKvXrG6EA5nQN8VmrbomGBS00BVDHU/4AonRhb2hf5qmpatNnWAVH1ZbrpPWRi3EpZnmr2etn/DwoEv7Ia3L7bhL28oONMzN/sonspssCyCLOqTXjGxCiVqv82q2S7/hVaonk+djnWnqmNSCgwRZcueAhialHhYO+Orprc0n5cGJxZ5HMmT08/+85/lpvqMNJ/ec4mIL4NXg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by PH7PR12MB6809.namprd12.prod.outlook.com (2603:10b6:510:1af::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.12; Tue, 20 Jan 2026 20:43:36 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9542.008; Tue, 20 Jan 2026 20:43:36 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jonathan Corbet , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Huang Rui , Matthew Auld , Matthew Brost , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Helge Deller , Danilo Krummrich , Alice Ryhl , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Alexey Ivanov , Balbir Singh , Philipp Stanner , Elle Rhumsaa , Daniel Almeida , joel@joelfernandes.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, linux-doc@vger.kernel.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-fbdev@vger.kernel.org, Joel Fernandes Subject: [PATCH RFC v6 03/26] rust: gpu: Add GPU buddy allocator bindings Date: Tue, 20 Jan 2026 15:42:40 -0500 Message-Id: <20260120204303.3229303-4-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120204303.3229303-1-joelagnelf@nvidia.com> References: <20260120204303.3229303-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MN2PR05CA0058.namprd05.prod.outlook.com (2603:10b6:208:236::27) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|PH7PR12MB6809:EE_ X-MS-Office365-Filtering-Correlation-Id: 99bf8f45-c2b3-4d97-57b9-08de58649570 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|7416014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?muEdQROPK5EArplyVoWiZHTb8TtDET0mRzVd4VqaK/4gdDEm7DqYlLH+iz0f?= =?us-ascii?Q?+4Zatp1AfIYXwpBRjSYRUPyxH+Kwdx9VA1yziXYePyj2vRYSQV7VyE/dhbXk?= =?us-ascii?Q?kdPyE6JSsnKDaGCP4aIdm5KYY6wA1FF/mJahJcoBQg1+BzC4+1Lfi7JbS4YY?= =?us-ascii?Q?VilCV74wECXrK7jfDoKA+YLVE0BaEpfR8nxelzrY3ojFgOm/Swjj+KacRh2+?= =?us-ascii?Q?fK+ZH4FeimOYRSOgOzFLH/meDd20nLK5OHVp5B8uWS5Pqd3oLipc4rh2cX7l?= =?us-ascii?Q?xwh/KWjKrV03cN3RmWpp0+mklDV68OT5grX1uQm6y1KLOhcOFzM1KSLjk+ZC?= =?us-ascii?Q?/9A5lcuiAir+fx8bJ0Pf3jYcTWpiVqRbKx5Lv8MiflbDNjTJpYaAR6H3u9Gf?= =?us-ascii?Q?ppuxgjFTLuWyZJiDGHPgTkbL3/gdC6H6U0oSvse4RGcG1fkJZdTjburw3yKS?= =?us-ascii?Q?ScdHTck8XGWaJOXkp7V8G3BCUTdUNJKc6Ql/NOOte9y2B6wYUqUWtNUOyBHA?= =?us-ascii?Q?SwaWUouZukiNwuEmxuRfoF3CT5Xt/E9S260ohpo6lZcReoKjrOD+u+2slZTU?= =?us-ascii?Q?hu3jU+eE8xHlVxnlyFvS4Ok6Mhf/GU0X4vvFRKfpNQF6EssAJlCX1hu/vKHe?= =?us-ascii?Q?DlsVjZEDAFXxLaz39hISDw31QpGf1AQxlVH650x6hNkOpmcy87XyDMb8I2PH?= =?us-ascii?Q?qSk8auHK+hYYKWhdhmrsWAYfOxQ1NR3Dzh6jFGaAhNScFk9uwr2GWx3chyhC?= =?us-ascii?Q?vu0B2DjYKWKKCKSTme9fx38CP41slxOkdr2sKMvfai6hRyTvucMzGtjK+m3O?= =?us-ascii?Q?yHDcnfRbWy3IX3/fGjnM799eAxHoJxfo9etgAiYqMxt21d6JCSP3s8GCdmzV?= =?us-ascii?Q?u0LpMwG53FkgMyKpJ0dimJI2RUxtQVirOdvZy/KUokmN8H3Yxreo1xO6xrL7?= =?us-ascii?Q?t20ZiJHM6B0hf5z8YEVGCQjhGt7bb+NYWnPvDP8NDKiguYRaYA3yqbLA0F39?= =?us-ascii?Q?luKWTp12NqZttqYFtfzgR42BkWf+jX2Q7SME31kbFhC6JaWFniuzVtFahPze?= =?us-ascii?Q?d4V1tTCeIAwflJvPoct2+7eVYMJtLcl3/eBXGaCwKTC2x/Cvprwtg/pClkL5?= =?us-ascii?Q?cJrCDG91cgx+huJD17h6TcqceatkgNAKzq9eJUwyUJibSaBRPM5gVS/b24i4?= =?us-ascii?Q?lIhRNYw9g2riWloeT6orBWhDvFtbJUSFU9U0uUQ6sxSScr3IX+UdbNRk+F2m?= =?us-ascii?Q?o3MoFBxTBUg2ijjPPc9q+FyGFikvk76W8TAdlAVFUnvo2F8D1NrZPu9uieUX?= =?us-ascii?Q?2zptcWFaOpOs4nTjYWGIAdDZviv6v9T3iHDweNAQiZdz1gbDvoquJLcijxju?= =?us-ascii?Q?47cwvxXki/N8XiIG26GNl1FzV12PWk/rIcR0lBaLZP/75A1Ipy+rFpoxFx00?= =?us-ascii?Q?XSnT1tN8AY2lDs3Bnrq8xRpU68HNsd8zrL4fh6C4YNwaUphvylqi/BD/lTyj?= =?us-ascii?Q?t13PYngW8suzEu4csAYsEOivSjP3IDCnLuqDZVr101kfXB7dmPueJoJ524H3?= =?us-ascii?Q?ZjEIW8QzIF8endsdUMg=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR12MB6486.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(376014)(7416014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?Y6rO84NO4Y+ycmIWLKe8nBV8mUkKUjucgWPZ/0DHbDKMLn6EgFLMkFT9eq6V?= =?us-ascii?Q?1OHwLYW19YQN/w/Fz/7hM7HD4ygZjRja9UmtO0gTOqoBTjZn9AVhzmizcJKE?= =?us-ascii?Q?2w5kh6ywHNfIzaMp/yuSYVbF43lT9JvWZ12m0KY8+20/18d7sIcGBM3nGocY?= =?us-ascii?Q?M2u+LXI51UQwRVbqGJuQCMIDD+mBYrg0AFWg0kVrJwHNCwINmic1hmI9d/RI?= =?us-ascii?Q?z+MC/U3AdojlySv/Izr89hAdKC+MlJwuR9Rt0ekhiDlssQOCb+ErvHRAJ0YE?= =?us-ascii?Q?ZZ1NpyE1lycUcmecQr2JoO4x5d0MQVSNdOLJqPvw/fxb8JQjz9fR1IfuLCHc?= =?us-ascii?Q?pA4IPjBdA3J325/MDApWulH/Eyn3L6KKPYwTCV07SQ2UdwixAI/wrBYcQJXn?= =?us-ascii?Q?1SdMGvxtUKnbdH4o2L5OcYR6MjAYatmtihkkZ1h2oYQStRq963PkhtAvLJ0n?= =?us-ascii?Q?LXr4WtNa7UtfHOZibOO2ox1mQRwgOtWfwxSUFcGp05qDBRZidj3mUPeMWkLr?= =?us-ascii?Q?ssi2kGuCDPlrhOkvgnASbXHn69xvSwrDdrfmXbi8S3H7bDpbjQv1wUvdvvxX?= =?us-ascii?Q?l55d69d44F3VqwBodcI9DCfFd19AiOjwTJ9qU6k6edT6LpBwK2zp4KtiONAV?= =?us-ascii?Q?sGf1HJD5fUXwzbMruJT+sy2+5Je0AxEOfmQzHjN6jCj8Czuk8PhebI2Tl8TY?= =?us-ascii?Q?J4IlnNhB0o2/EheaI3GHtrkpEdZk1K520pdKQAZMH0STfcupr/MxYJp6XT1X?= =?us-ascii?Q?922W256pCQJbRHq7e/VuaQInI506O4SfStFIoZsAepW09GCmWJL47dbFxM3h?= =?us-ascii?Q?LvyKj+JLdk0QYS4YiGQcW8Kv2zSyEqCVvmpyLqkNwcoK0jptkJIl3pi01l/d?= =?us-ascii?Q?Y2VqWv5qyObVZFQS2G6G6h4mhXoX74JfyHlPRCmziMctb0qJyQ9p1HBInk0v?= =?us-ascii?Q?4EkoRSqWIeRWz2w8N3vN2ekqsiM+fzShTjZT7j9vsQhHoGvVa/JoA7G8inni?= =?us-ascii?Q?unuE1mhkFJ/+uftLZTBv7vNhjuZqf9w+Qir16GaI2t+nbEtl3xoY4tpRcxzo?= =?us-ascii?Q?3TAOzzYcjXqDMQuAhUlA1YTyzqLXP14c3LotyLzyAslYTYiLPDi2WTo1j4Ia?= =?us-ascii?Q?TgUEFJ10hktceUD32e8TnwFDfuy62S/FhsvS7JSNRE/fvmXIdAQYljCZuKa9?= =?us-ascii?Q?wHI1TwiDDH3Q9bHaJsw5gn9xvkZ+UZJxZWpeAN6ypvK/DXDgFsakVPK7oZa5?= =?us-ascii?Q?+7/UFsNe/RB6fk71++tC/T3c7OXjQ0oupS8Kd6XFd/vnAeAGoOHHeVkCucWZ?= =?us-ascii?Q?5AP/APmo9xT06loeHE108AqQuo+QkGD1mzckOewzE3M2Y2ek1MK/qQ8dKleS?= =?us-ascii?Q?5iQ+04d8PoT35jTiswgf8tvhQb0MKvq6fnQHx1usGdegHNMhJKmVBzktTJsU?= =?us-ascii?Q?TH3b74gpeTBH2rY2wX94WcwEJp6dTSp2qioHL2Zpa7KDHSmXbAcok8Z/kvUg?= =?us-ascii?Q?f9//FT9jA+pScIuOu1bDUgBcuj5oAx0XzWmzy6DrebVcUVDZFy5x4+51Bdgw?= =?us-ascii?Q?wnItfbmkLdqQmwoG5r/5ey5yh86NAg/mbH/r4pusVmobu/AdbDQ2C+fwz8Sq?= =?us-ascii?Q?pj6mgXcM3k/MN+TUzjyLZiX2lWwWHjpda95x/s7He2m6+dtxWmwmS2m+eNiC?= =?us-ascii?Q?bv89cqOUOoGcmCGPn/F36qr0aoiwfUUT0i8NKzRhDMn8V85QiEUlz+VFHdBV?= =?us-ascii?Q?FPqhiMsbzg=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 99bf8f45-c2b3-4d97-57b9-08de58649570 X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB6486.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 20:43:36.5025 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: EmGYFkBv7ILBTjFjVnMGEtYlN4KgkwC52DcvC3QhQgF2uhYIjcELjlZFH+snBpi0GBh6sMeCZut77s3xo+HHXw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6809 Content-Type: text/plain; charset="utf-8" Add safe Rust abstractions over the Linux kernel's GPU buddy allocator for physical memory management. The GPU buddy allocator implements a binary buddy system useful for GPU physical memory allocation. nova-core will use it for physical memory allocation. Signed-off-by: Joel Fernandes --- rust/bindings/bindings_helper.h | 11 + rust/helpers/gpu.c | 23 ++ rust/helpers/helpers.c | 1 + rust/kernel/gpu/buddy.rs | 538 ++++++++++++++++++++++++++++++++ rust/kernel/gpu/mod.rs | 5 + rust/kernel/lib.rs | 2 + 6 files changed, 580 insertions(+) create mode 100644 rust/helpers/gpu.c create mode 100644 rust/kernel/gpu/buddy.rs create mode 100644 rust/kernel/gpu/mod.rs diff --git a/rust/bindings/bindings_helper.h b/rust/bindings/bindings_helpe= r.h index a067038b4b42..940b854a1f93 100644 --- a/rust/bindings/bindings_helper.h +++ b/rust/bindings/bindings_helper.h @@ -29,6 +29,7 @@ #include =20 #include +#include #include #include #include @@ -144,6 +145,16 @@ const vm_flags_t RUST_CONST_HELPER_VM_MIXEDMAP =3D VM_= MIXEDMAP; const vm_flags_t RUST_CONST_HELPER_VM_HUGEPAGE =3D VM_HUGEPAGE; const vm_flags_t RUST_CONST_HELPER_VM_NOHUGEPAGE =3D VM_NOHUGEPAGE; =20 +#if IS_ENABLED(CONFIG_GPU_BUDDY) +const unsigned long RUST_CONST_HELPER_GPU_BUDDY_RANGE_ALLOCATION =3D GPU_B= UDDY_RANGE_ALLOCATION; +const unsigned long RUST_CONST_HELPER_GPU_BUDDY_TOPDOWN_ALLOCATION =3D GPU= _BUDDY_TOPDOWN_ALLOCATION; +const unsigned long RUST_CONST_HELPER_GPU_BUDDY_CONTIGUOUS_ALLOCATION =3D + GPU_BUDDY_CONTIGUOUS_ALLOCATION; +const unsigned long RUST_CONST_HELPER_GPU_BUDDY_CLEAR_ALLOCATION =3D GPU_B= UDDY_CLEAR_ALLOCATION; +const unsigned long RUST_CONST_HELPER_GPU_BUDDY_CLEARED =3D GPU_BUDDY_CLEA= RED; +const unsigned long RUST_CONST_HELPER_GPU_BUDDY_TRIM_DISABLE =3D GPU_BUDDY= _TRIM_DISABLE; +#endif + #if IS_ENABLED(CONFIG_ANDROID_BINDER_IPC_RUST) #include "../../drivers/android/binder/rust_binder.h" #include "../../drivers/android/binder/rust_binder_events.h" diff --git a/rust/helpers/gpu.c b/rust/helpers/gpu.c new file mode 100644 index 000000000000..38b1a4e6bef8 --- /dev/null +++ b/rust/helpers/gpu.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +#ifdef CONFIG_GPU_BUDDY + +__rust_helper u64 rust_helper_gpu_buddy_block_offset(const struct gpu_budd= y_block *block) +{ + return gpu_buddy_block_offset(block); +} + +__rust_helper unsigned int rust_helper_gpu_buddy_block_order(struct gpu_bu= ddy_block *block) +{ + return gpu_buddy_block_order(block); +} + +__rust_helper u64 rust_helper_gpu_buddy_block_size(struct gpu_buddy *mm, + struct gpu_buddy_block *block) +{ + return gpu_buddy_block_size(mm, block); +} + +#endif /* CONFIG_GPU_BUDDY */ diff --git a/rust/helpers/helpers.c b/rust/helpers/helpers.c index 634fa2386bbb..6db7c4c25afa 100644 --- a/rust/helpers/helpers.c +++ b/rust/helpers/helpers.c @@ -29,6 +29,7 @@ #include "err.c" #include "irq.c" #include "fs.c" +#include "gpu.c" #include "io.c" #include "jump_label.c" #include "kunit.c" diff --git a/rust/kernel/gpu/buddy.rs b/rust/kernel/gpu/buddy.rs new file mode 100644 index 000000000000..7fb8e505ff9f --- /dev/null +++ b/rust/kernel/gpu/buddy.rs @@ -0,0 +1,538 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! GPU buddy allocator bindings. +//! +//! C header: [`include/linux/gpu_buddy.h`](srctree/include/linux/gpu_budd= y.h) +//! +//! This module provides Rust abstractions over the Linux kernel's GPU bud= dy +//! allocator, which implements a binary buddy memory allocator. +//! +//! The buddy allocator manages a contiguous address space and allocates b= locks +//! in power-of-two sizes, useful for GPU physical memory management. +//! +//! # Examples +//! +//! ``` +//! use kernel::{ +//! gpu::buddy::{BuddyFlags, GpuBuddy, GpuBuddyAllocParams, GpuBuddyPa= rams}, +//! prelude::*, +//! sizes::*, // +//! }; +//! +//! // Create a 1GB buddy allocator with 4KB minimum chunk size. +//! let mut buddy =3D GpuBuddy::new(GpuBuddyParams { +//! base_offset_bytes: 0, +//! physical_memory_size_bytes: SZ_1G as u64, +//! chunk_size_bytes: SZ_4K as u64, +//! })?; +//! +//! // Verify initial state. +//! assert_eq!(buddy.size(), SZ_1G as u64); +//! assert_eq!(buddy.chunk_size(), SZ_4K as u64); +//! let initial_free =3D buddy.free_memory_bytes(); +//! +//! // Base allocation params - reused across tests with field overrides. +//! let params =3D GpuBuddyAllocParams { +//! start_range_address: 0, +//! end_range_address: 0, // Entire range. +//! size_bytes: SZ_16M as u64, +//! min_block_size_bytes: SZ_16M as u64, +//! buddy_flags: BuddyFlags::try_new(BuddyFlags::RANGE_ALLOCATION)?, +//! }; +//! +//! // Test top-down allocation (allocates from highest addresses). +//! let topdown =3D buddy.alloc_blocks(GpuBuddyAllocParams { +//! buddy_flags: BuddyFlags::try_new(BuddyFlags::TOPDOWN_ALLOCATION)?, +//! ..params +//! })?; +//! assert_eq!(buddy.free_memory_bytes(), initial_free - SZ_16M as u64); +//! +//! for block in topdown.iter() { +//! assert_eq!(block.offset(), (SZ_1G - SZ_16M) as u64); +//! assert_eq!(block.order(), 12); // 2^12 pages +//! assert_eq!(block.size(), SZ_16M as u64); +//! } +//! drop(topdown); +//! assert_eq!(buddy.free_memory_bytes(), initial_free); +//! +//! // Allocate 16MB - should result in a single 16MB block at offset 0. +//! let allocated =3D buddy.alloc_blocks(params)?; +//! assert_eq!(buddy.free_memory_bytes(), initial_free - SZ_16M as u64); +//! +//! for block in allocated.iter() { +//! assert_eq!(block.offset(), 0); +//! assert_eq!(block.order(), 12); // 2^12 pages +//! assert_eq!(block.size(), SZ_16M as u64); +//! } +//! drop(allocated); +//! assert_eq!(buddy.free_memory_bytes(), initial_free); +//! +//! // Test non-contiguous allocation with fragmented memory. +//! // Create fragmentation by allocating 4MB blocks at [0,4M) and [8M,12M= ). +//! let params_4m =3D GpuBuddyAllocParams { +//! end_range_address: SZ_4M as u64, +//! size_bytes: SZ_4M as u64, +//! min_block_size_bytes: SZ_4M as u64, +//! ..params +//! }; +//! let frag1 =3D buddy.alloc_blocks(params_4m)?; +//! assert_eq!(buddy.free_memory_bytes(), initial_free - SZ_4M as u64); +//! +//! let frag2 =3D buddy.alloc_blocks(GpuBuddyAllocParams { +//! start_range_address: SZ_8M as u64, +//! end_range_address: (SZ_8M + SZ_4M) as u64, +//! ..params_4m +//! })?; +//! assert_eq!(buddy.free_memory_bytes(), initial_free - SZ_8M as u64); +//! +//! // Allocate 8MB without CONTIGUOUS - should return 2 blocks from the h= oles. +//! let fragmented =3D buddy.alloc_blocks(GpuBuddyAllocParams { +//! end_range_address: SZ_16M as u64, +//! size_bytes: SZ_8M as u64, +//! min_block_size_bytes: SZ_4M as u64, +//! ..params +//! })?; +//! assert_eq!(buddy.free_memory_bytes(), initial_free - (SZ_16M) as u64); +//! +//! let (mut count, mut total) =3D (0u32, 0u64); +//! for block in fragmented.iter() { +//! // The 8MB allocation should return 2 blocks, each 4MB. +//! assert_eq!(block.size(), SZ_4M as u64); +//! total +=3D block.size(); +//! count +=3D 1; +//! } +//! assert_eq!(total, SZ_8M as u64); +//! assert_eq!(count, 2); +//! drop(fragmented); +//! drop(frag2); +//! drop(frag1); +//! assert_eq!(buddy.free_memory_bytes(), initial_free); +//! +//! // Test CONTIGUOUS failure when only fragmented space available. +//! // Create a small buddy allocator with only 16MB of memory. +//! let mut small =3D GpuBuddy::new(GpuBuddyParams { +//! base_offset_bytes: 0, +//! physical_memory_size_bytes: SZ_16M as u64, +//! chunk_size_bytes: SZ_4K as u64, +//! })?; +//! +//! // Allocate 4MB blocks at [0,4M) and [8M,12M) to create fragmented mem= ory. +//! let hole1 =3D small.alloc_blocks(params_4m)?; +//! let hole2 =3D small.alloc_blocks(GpuBuddyAllocParams { +//! start_range_address: SZ_8M as u64, +//! end_range_address: (SZ_8M + SZ_4M) as u64, +//! ..params_4m +//! })?; +//! +//! // 8MB contiguous should fail - only two non-contiguous 4MB holes exis= t. +//! let result =3D small.alloc_blocks(GpuBuddyAllocParams { +//! size_bytes: SZ_8M as u64, +//! min_block_size_bytes: SZ_4M as u64, +//! buddy_flags: BuddyFlags::try_new(BuddyFlags::CONTIGUOUS_ALLOCATION= )?, +//! ..params +//! }); +//! assert!(result.is_err()); +//! drop(hole2); +//! drop(hole1); +//! +//! # Ok::<(), Error>(()) +//! ``` + +use crate::{ + bindings, + clist::CListHead, + clist_create, + error::to_result, + new_mutex, + prelude::*, + sync::{ + lock::mutex::MutexGuard, + Arc, + Mutex, // + }, + types::Opaque, +}; + +/// Flags for GPU buddy allocator operations. +/// +/// These flags control the allocation behavior of the buddy allocator. +#[derive(Clone, Copy, Default, PartialEq, Eq)] +pub struct BuddyFlags(usize); + +impl BuddyFlags { + /// Range-based allocation from start to end addresses. + pub const RANGE_ALLOCATION: usize =3D bindings::GPU_BUDDY_RANGE_ALLOCA= TION; + + /// Allocate from top of address space downward. + pub const TOPDOWN_ALLOCATION: usize =3D bindings::GPU_BUDDY_TOPDOWN_AL= LOCATION; + + /// Allocate physically contiguous blocks. + pub const CONTIGUOUS_ALLOCATION: usize =3D bindings::GPU_BUDDY_CONTIGU= OUS_ALLOCATION; + + /// Request allocation from the cleared (zeroed) memory. The zero'ing = is not + /// done by the allocator, but by the caller before freeing old blocks. + pub const CLEAR_ALLOCATION: usize =3D bindings::GPU_BUDDY_CLEAR_ALLOCA= TION; + + /// Disable trimming of partially used blocks. + pub const TRIM_DISABLE: usize =3D bindings::GPU_BUDDY_TRIM_DISABLE; + + /// Mark blocks as cleared (zeroed) when freeing. When set during free, + /// indicates that the caller has already zeroed the memory. + pub const CLEARED: usize =3D bindings::GPU_BUDDY_CLEARED; + + /// Create [`BuddyFlags`] from a raw value with validation. + /// + /// Use `|` operator to combine flags if needed, before calling this m= ethod. + pub fn try_new(flags: usize) -> Result { + // Flags must not exceed u32::MAX to satisfy the GPU buddy allocat= or C API. + if flags > u32::MAX as usize { + return Err(EINVAL); + } + + // `TOPDOWN_ALLOCATION` only works without `RANGE_ALLOCATION`. Whe= n both are + // set, `TOPDOWN_ALLOCATION` is silently ignored by the allocator.= Reject this. + if (flags & Self::RANGE_ALLOCATION) !=3D 0 && (flags & Self::TOPDO= WN_ALLOCATION) !=3D 0 { + return Err(EINVAL); + } + + Ok(Self(flags)) + } + + /// Get raw value of the flags. + pub(crate) fn as_raw(self) -> usize { + self.0 + } +} + +/// Parameters for creating a GPU buddy allocator. +#[derive(Clone, Copy)] +pub struct GpuBuddyParams { + /// Base offset in bytes where the managed memory region starts. + /// Allocations will be offset by this value. + pub base_offset_bytes: u64, + /// Total physical memory size managed by the allocator in bytes. + pub physical_memory_size_bytes: u64, + /// Minimum allocation unit / chunk size in bytes, must be >=3D 4KB. + pub chunk_size_bytes: u64, +} + +/// Parameters for allocating blocks from a GPU buddy allocator. +#[derive(Clone, Copy)] +pub struct GpuBuddyAllocParams { + /// Start of allocation range in bytes. Use 0 for beginning. + pub start_range_address: u64, + /// End of allocation range in bytes. Use 0 for entire range. + pub end_range_address: u64, + /// Total size to allocate in bytes. + pub size_bytes: u64, + /// Minimum block size for fragmented allocations in bytes. + pub min_block_size_bytes: u64, + /// Buddy allocator behavior flags. + pub buddy_flags: BuddyFlags, +} + +/// Inner structure holding the actual buddy allocator. +/// +/// # Synchronization +/// +/// The C `gpu_buddy` API requires synchronization (see `include/linux/gpu= _buddy.h`). +/// The internal [`GpuBuddyGuard`] ensures that the lock is held for all +/// allocator and free operations, preventing races between concurrent all= ocations +/// and the freeing that occurs when [`AllocatedBlocks`] is dropped. +/// +/// # Invariants +/// +/// The inner [`Opaque`] contains a valid, initialized buddy allocator. +#[pin_data(PinnedDrop)] +struct GpuBuddyInner { + #[pin] + inner: Opaque, + #[pin] + lock: Mutex<()>, + /// Base offset for all allocations (does not change after init). + base_offset: u64, + /// Cached chunk size (does not change after init). + chunk_size: u64, + /// Cached total size (does not change after init). + size: u64, +} + +impl GpuBuddyInner { + /// Create a pin-initializer for the buddy allocator. + fn new(params: &GpuBuddyParams) -> impl PinInit { + let base_offset =3D params.base_offset_bytes; + let size =3D params.physical_memory_size_bytes; + let chunk_size =3D params.chunk_size_bytes; + + try_pin_init!(Self { + inner <- Opaque::try_ffi_init(|ptr| { + // SAFETY: ptr points to valid uninitialized memory from t= he pin-init + // infrastructure. gpu_buddy_init will initialize the stru= cture. + to_result(unsafe { bindings::gpu_buddy_init(ptr, size, chu= nk_size) }) + }), + lock <- new_mutex!(()), + base_offset: base_offset, + chunk_size: chunk_size, + size: size, + }) + } + + /// Lock the mutex and return a guard for accessing the allocator. + fn lock(&self) -> GpuBuddyGuard<'_> { + GpuBuddyGuard { + inner: self, + _guard: self.lock.lock(), + } + } +} + +#[pinned_drop] +impl PinnedDrop for GpuBuddyInner { + fn drop(self: Pin<&mut Self>) { + let guard =3D self.lock(); + + // SAFETY: guard provides exclusive access to the allocator. + unsafe { + bindings::gpu_buddy_fini(guard.as_raw()); + } + } +} + +// SAFETY: [`GpuBuddyInner`] can be sent between threads. +unsafe impl Send for GpuBuddyInner {} + +// SAFETY: [`GpuBuddyInner`] is `Sync` because the internal [`GpuBuddyGuar= d`] +// serializes all access to the C allocator, preventing data races. +unsafe impl Sync for GpuBuddyInner {} + +/// Guard that proves the lock is held, enabling access to the allocator. +/// +/// # Invariants +/// +/// The inner `_guard` holds the lock for the duration of this guard's lif= etime. +pub(crate) struct GpuBuddyGuard<'a> { + inner: &'a GpuBuddyInner, + _guard: MutexGuard<'a, ()>, +} + +impl GpuBuddyGuard<'_> { + /// Get a raw pointer to the underlying C `gpu_buddy` structure. + fn as_raw(&self) -> *mut bindings::gpu_buddy { + self.inner.inner.get() + } +} + +/// GPU buddy allocator instance. +/// +/// This structure wraps the C `gpu_buddy` allocator using reference count= ing. +/// The allocator is automatically cleaned up when all references are drop= ped. +/// +/// # Invariants +/// +/// The inner [`Arc`] points to a valid, initialized GPU buddy allocator. +pub struct GpuBuddy(Arc); + +impl GpuBuddy { + /// Create a new buddy allocator. + /// + /// Creates a buddy allocator that manages a contiguous address space = of the given + /// size, with the specified minimum allocation unit (chunk_size must = be at least 4KB). + pub fn new(params: GpuBuddyParams) -> Result { + Ok(Self(Arc::pin_init( + GpuBuddyInner::new(¶ms), + GFP_KERNEL, + )?)) + } + + /// Get the base offset for allocations. + pub fn base_offset(&self) -> u64 { + self.0.base_offset + } + + /// Get the chunk size (minimum allocation unit). + pub fn chunk_size(&self) -> u64 { + self.0.chunk_size + } + + /// Get the total managed size. + pub fn size(&self) -> u64 { + self.0.size + } + + /// Get the available (free) memory in bytes. + pub fn free_memory_bytes(&self) -> u64 { + let guard =3D self.0.lock(); + // SAFETY: guard provides exclusive access to the allocator. + unsafe { (*guard.as_raw()).avail } + } + + /// Allocate blocks from the buddy allocator. + /// + /// Returns an [`Arc`] structure that owns the alloca= ted blocks + /// and automatically frees them when all references are dropped. + /// + /// Takes `&self` instead of `&mut self` because the internal [`Mutex`= ] provides + /// synchronization - no external `&mut` exclusivity needed. + pub fn alloc_blocks(&self, params: GpuBuddyAllocParams) -> Result> { + let buddy_arc =3D Arc::clone(&self.0); + + // Create pin-initializer that initializes list and allocates bloc= ks. + let init =3D try_pin_init!(AllocatedBlocks { + list <- CListHead::try_init(|list| { + // Lock while allocating to serialize with concurrent free= s. + let guard =3D buddy_arc.lock(); + + // SAFETY: guard provides exclusive access, list is initia= lized. + to_result(unsafe { + bindings::gpu_buddy_alloc_blocks( + guard.as_raw(), + params.start_range_address, + params.end_range_address, + params.size_bytes, + params.min_block_size_bytes, + list.as_raw(), + params.buddy_flags.as_raw(), + ) + }) + }), + buddy: Arc::clone(&buddy_arc), + flags: params.buddy_flags, + }); + + Arc::pin_init(init, GFP_KERNEL) + } +} + +/// Allocated blocks from the buddy allocator with automatic cleanup. +/// +/// This structure owns a list of allocated blocks and ensures they are +/// automatically freed when dropped. Use `iter()` to iterate over all +/// allocated [`Block`] structures. +/// +/// # Invariants +/// +/// - `list` is an initialized, valid list head containing allocated block= s. +/// - `buddy` references a valid [`GpuBuddyInner`]. +#[pin_data(PinnedDrop)] +pub struct AllocatedBlocks { + #[pin] + list: CListHead, + buddy: Arc, + flags: BuddyFlags, +} + +impl AllocatedBlocks { + /// Check if the block list is empty. + pub fn is_empty(&self) -> bool { + // An empty list head points to itself. + !self.list.is_linked() + } + + /// Iterate over allocated blocks. + /// + /// Returns an iterator yielding [`AllocatedBlock`] references. The bl= ocks + /// are only valid for the duration of the borrow of `self`. + pub fn iter(&self) -> impl Iterator> + '_ { + // SAFETY: list contains gpu_buddy_block items linked via __bindge= n_anon_1.link. + let clist =3D unsafe { + clist_create!( + self.list.as_raw(), + Block, + bindings::gpu_buddy_block, + __bindgen_anon_1.link + ) + }; + + clist + .iter() + .map(|block| AllocatedBlock { block, alloc: self }) + } +} + +#[pinned_drop] +impl PinnedDrop for AllocatedBlocks { + fn drop(self: Pin<&mut Self>) { + let guard =3D self.buddy.lock(); + + // SAFETY: + // - list is valid per the type's invariants. + // - guard provides exclusive access to the allocator. + // CAST: BuddyFlags were validated to fit in u32 at construction. + unsafe { + bindings::gpu_buddy_free_list( + guard.as_raw(), + self.list.as_raw(), + self.flags.as_raw() as u32, + ); + } + } +} + +/// A GPU buddy block. +/// +/// Transparent wrapper over C `gpu_buddy_block` structure. This type is r= eturned +/// as references from [`CListIter`] during iteration over [`AllocatedBloc= ks`]. +/// +/// # Invariants +/// +/// The inner [`Opaque`] contains a valid, allocated `gpu_buddy_block`. +#[repr(transparent)] +pub struct Block(Opaque); + +impl Block { + /// Get a raw pointer to the underlying C block. + fn as_raw(&self) -> *mut bindings::gpu_buddy_block { + self.0.get() + } + + /// Get the block's offset in the address space. + pub(crate) fn offset(&self) -> u64 { + // SAFETY: self.as_raw() is valid per the type's invariants. + unsafe { bindings::gpu_buddy_block_offset(self.as_raw()) } + } + + /// Get the block order. + pub(crate) fn order(&self) -> u32 { + // SAFETY: self.as_raw() is valid per the type's invariants. + unsafe { bindings::gpu_buddy_block_order(self.as_raw()) } + } +} + +// SAFETY: `Block` is a transparent wrapper over `gpu_buddy_block` which i= s not +// modified after allocation. It can be safely sent between threads. +unsafe impl Send for Block {} + +// SAFETY: `Block` is a transparent wrapper over `gpu_buddy_block` which i= s not +// modified after allocation. It can be safely shared among threads. +unsafe impl Sync for Block {} + +/// An allocated block with access to the allocation list. +/// +/// # Invariants +/// +/// - `block` is a valid reference to an allocated [`Block`]. +/// - `alloc` is a valid reference to the [`AllocatedBlocks`] that owns th= is block. +pub struct AllocatedBlock<'a> { + block: &'a Block, + alloc: &'a AllocatedBlocks, +} + +impl AllocatedBlock<'_> { + /// Get the block's offset in the address space. + /// + /// Returns the absolute offset including the allocator's base offset. + /// This is the actual address to use for accessing the allocated memo= ry. + pub fn offset(&self) -> u64 { + self.alloc.buddy.base_offset + self.block.offset() + } + + /// Get the block order (size =3D chunk_size << order). + pub fn order(&self) -> u32 { + self.block.order() + } + + /// Get the block's size in bytes. + pub fn size(&self) -> u64 { + self.alloc.buddy.chunk_size << self.block.order() + } +} diff --git a/rust/kernel/gpu/mod.rs b/rust/kernel/gpu/mod.rs new file mode 100644 index 000000000000..8f25e6367edc --- /dev/null +++ b/rust/kernel/gpu/mod.rs @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! GPU subsystem abstractions. + +pub mod buddy; diff --git a/rust/kernel/lib.rs b/rust/kernel/lib.rs index cd7e6a1055b0..d754d777f8ff 100644 --- a/rust/kernel/lib.rs +++ b/rust/kernel/lib.rs @@ -98,6 +98,8 @@ pub mod firmware; pub mod fmt; pub mod fs; +#[cfg(CONFIG_GPU_BUDDY)] +pub mod gpu; #[cfg(CONFIG_I2C =3D "y")] pub mod i2c; pub mod id_pool; --=20 2.34.1 From nobody Sun Feb 8 09:32:51 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013025.outbound.protection.outlook.com [40.93.201.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9B283B9612; Tue, 20 Jan 2026 20:43:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.201.25 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941826; cv=fail; b=VSyCNByeDwPTwizirT4pKEMipIgN1fDVuO40+0v0t387i9xi+jaSrZYgrMr4jf2feUqloRNKLePlJ4R41MeCNVo+cDyTJ6bN7xmtm4rtfkmT1M/d5tCrxKkH4K1b+khd9T2tp0QZ3BSvrXziakfqRccn13hgEW7+ghJSnrXE6F4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941826; c=relaxed/simple; bh=FhytbWkFHvyWRG4Rt5UCeV6FajI2XyelHfcIfUQtYhk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=rp+7uRMvTp4tznr4FkVzDNJGFkhs2zVcXrnO9Pq1kjNdpwepUZz3COoa13TI0+I/n0igTkYu9i1dB7yHVaFavDpG7GktdWshRHht7N42wl4mcqm6iLMU4GEFr+NHEM5NwmreF+z7zN5NyXrZbmPXuf0mwIZGZ6Pf1KiiiP3ShjA= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=CgLmY+8c; arc=fail smtp.client-ip=40.93.201.25 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="CgLmY+8c" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=pRGZX5wmH/nve4X/HnuO8Y/Xfr+X8drG91wnt25jXKPzn6p5c/gZMl6/nibzFx7q2RUgAnEyH+0U8qVgDyU9rYYzlLwOiTpVA7ADURlOAWeJyCbYj1qJ73Ej8YVAkq7emKOY816ldOfdoxx+4CUvIYcv3k2dOav9PgdU/zYIoQWxlu8w0RNmOdaQZRJTbAzIdaSczWKRjoNj8b6l1RNU+VoHyOOzqNGkxSwiohU0qBnCxJiTk04FIFO0jXYpBb0fL1mxB7Q62BjLblf7jk7fBi82q13iIwDUkkl6nRsjCjF09WtvWpCW1c5B5BshHwa9OAgiVHtcTzvsLJ6fmKvpYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=n+x0ei/AWu/7WupWw4pDblQ/NkgXVbipSpkrLiLj1wU=; b=uw0NM6weGDZgRuEoiX+GCK5f1QN0pY0/GE/AMTJvjBsc0U4FWDPvLQfKGTdPEdbPgRai3RqyzwFrtoQBhlcFuTRzOYLWQef6DEZsOz5Iq+MWnceXK361x5e5XfsUHS7+2zCl+0ZWPleRlsCi6F7z2ihZ2T7eKByRwH//BX/hnoRS8agfaPPr1kbhdKOahjECByOH1Rino7lS7UmMXHnfd58CVzgW70zmKf/RIJZ2uFavvS7SXOWeAXwGJXJ6hJnoDX885wTwmwbHoP3k/3xEGCKUWDmPToPurjszxA7rfDF77WxfOiHi+KO956OpQh6BEkTopsW62WqheR6gmNcpQA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=n+x0ei/AWu/7WupWw4pDblQ/NkgXVbipSpkrLiLj1wU=; b=CgLmY+8cpJXlHLh1DwwcCtgPjDs1vDeUfdi1ieLuM+49JNh3MP9BpeZH61DLbVIsnRuoJNTbFy0jjpWkgCXnR+WTtW4G3ni9AF1D2ook/rl+LIsnXskFKo0QL4xbbSChh3NSMrj8Z5Buugj9uyB5fOLLy3/J3ntbT25dMiQ3CSSOcsBDEl8Kea/ArXAob39hN8uRL9s3pBtAR7zzeXPqfGr7sImMi5KPhaz51e207biJA22OwHuYRei9d8qNn+kIsYAcCQ3TbkZW1Ny3ndUGLktFiM9CwRy4944pfs5kCDZ10DvvSd59zMImLMGy01bo8FcfAAohyLdMjHSWB5ZPqw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by PH7PR12MB6809.namprd12.prod.outlook.com (2603:10b6:510:1af::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.12; Tue, 20 Jan 2026 20:43:39 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9542.008; Tue, 20 Jan 2026 20:43:38 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jonathan Corbet , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Huang Rui , Matthew Auld , Matthew Brost , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Helge Deller , Danilo Krummrich , Alice Ryhl , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Alexey Ivanov , Balbir Singh , Philipp Stanner , Elle Rhumsaa , Daniel Almeida , joel@joelfernandes.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, linux-doc@vger.kernel.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-fbdev@vger.kernel.org, Joel Fernandes Subject: [PATCH RFC v6 04/26] nova-core: mm: Select GPU_BUDDY for VRAM allocation Date: Tue, 20 Jan 2026 15:42:41 -0500 Message-Id: <20260120204303.3229303-5-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120204303.3229303-1-joelagnelf@nvidia.com> References: <20260120204303.3229303-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BL0PR0102CA0018.prod.exchangelabs.com (2603:10b6:207:18::31) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|PH7PR12MB6809:EE_ X-MS-Office365-Filtering-Correlation-Id: c32edea7-fc6a-4e6f-db3b-08de5864967a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|7416014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?/MgQc5bwZ6UpJmOQOu2NqWVJ2CSfwyQnHrZVx5D4Xg5SDftzlCpubCNpkr2+?= =?us-ascii?Q?Hb9RPcqwcmdfCoJbJiEiKWrIZ9vN31fOw4kaa5jT9ZkaoX0w0Dne6kYbxnOx?= =?us-ascii?Q?XCy0l8nop+bGFaEhGEHcU/6oaUVPnDdZ7M0YFcaGudyVI9eI/iyxMOGBadYn?= =?us-ascii?Q?as2gE0hKVIRzYrs8yVJeP+2qsOULbzoTkoO5zJDKYRliGV8UJ82QyhEVqYuZ?= =?us-ascii?Q?DEwQx8o2oVt7w+wSdYFB6Ve7quKpluAb8Prya7p17jooWOGe8jazNwy34ANc?= =?us-ascii?Q?5qGrQB/+G44WemDgymNLTgfp+J4KXlbdeBYtABwhHuPmXeLbNGEGNAH759g3?= =?us-ascii?Q?bYNX3usN1EiCWPu5dMZtBTb+tk9y2S3OBjc2ZWkyodwJqBvpRaiP0eoAUcvY?= =?us-ascii?Q?9qG3SJPHcR15kXjOrDFf73IK7YADNgO3u0snxxOJ7WT4+psx8dZHvJVZ0bLp?= =?us-ascii?Q?K/SleUWAHu2iqj+6xCdhyO9aOICsiq8BUNvTQckluNpw3640BqKbKKNeFdyz?= =?us-ascii?Q?H1iFFrPYDfkJkcpuIh7CVBismbchRPv5ir+ABGwwz08hLoZAm9JSMW2iUmOw?= =?us-ascii?Q?ksWWciqiLf2SxecRjxUGXewYFF/J0Pk1eKr/hLbMlQgulpJHFf5qxNrDvDFO?= =?us-ascii?Q?iu27un1D4gbjnfcdBq1cqug7YJyo3gsCHIAGlD+10nFA5GqKa9zWXAvCC3M2?= =?us-ascii?Q?JjbxA6wXChsUYD31KJurN4C4zsHM4lLmpQ5jskuE7YpHQUdNMRVxXAQ9RU0r?= =?us-ascii?Q?LvTz+PbFvcHvLmN4h06Wbb96UYN/Q29FWcpMikGQgAEesfOThqoTwEYpq9V6?= =?us-ascii?Q?YMVcRLRO6ILZXxKw9ocujJd28Ye5B3eKVYDxX4BaiDxBM0uKcH/8zUiI+iOb?= =?us-ascii?Q?Lyw4CAGjC9jXZWaqFAGuaFWfuSasyyDkLtG0D6T+Z1erX3Enp2b+LIYvLRxf?= =?us-ascii?Q?A8NT5WGj6izmrsiaLii1zy7TrvkFe597lNcfG6C/oHfCzjFnTtg3VoW/EdlV?= =?us-ascii?Q?hZ3FlOempQrYqzBwpTZlsOu44cjqkDtD1Fv2e5u4TAnVLlkFC3E9YZ49fIRc?= =?us-ascii?Q?BlF+ljHrOHE1H+hLTa/qVKgYGIHVm9rgpnQGVYkIOXHLIiJbNlUfm3nqhFwb?= =?us-ascii?Q?R+uHsGliYrtLphVeBHkDEnI+BBiahza/gWw9OWiSueQxKdePwSQBB3X/Krju?= =?us-ascii?Q?Y43pbDjzBBVZb3QsTm9/d4tqB4Z1Yp68X14Cpyptqnc1oclwngKEBRAfbhDM?= =?us-ascii?Q?4futi9QdTuDGIimsxUIB5z98iHsZPbe8Hs2gTjojPo29kv+clDotZEGj7iwN?= =?us-ascii?Q?l+zy+qP9CFNyCMk2AfDXbzcWUJPUVSIcpHrVcFhUpkYNZwizAOCRM6SSuZF1?= =?us-ascii?Q?V1Mg6oykanILaVpB5Hfdu7oi9S9MfEyOOhcn2R+P3RPjFxu4gIwpQu4YnX1n?= =?us-ascii?Q?G+EfhNapIr1BEJftBdGfbxdJo0c8zxT2FsfSSODJMTTPFCChsVXpayYEb3xv?= =?us-ascii?Q?bC+nOyBJxRIpP55vpTfExGjBPuaPWphMadeCAOCxiuC6HnOjWVpf646/iPid?= =?us-ascii?Q?UuUmLPDX8Q9QWMPnHkI=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR12MB6486.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(376014)(7416014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?N9s2KYgkuvuvtNdO01soKnsiY8DVEnjJK2sPZp3EKTJEf3KryHdntbjAnSUS?= =?us-ascii?Q?rkl9OFxDo13gD1X7ZOh7VSiBuhAxsmkueF1De1COVObGGGQ/IadHPw2Of3fu?= =?us-ascii?Q?xj6dVabkgzWboue+fvpEMvcqhHQ01s/EJSm7M6HDXhCRqDlm9SYBvDNPyAN9?= =?us-ascii?Q?eCujEZUiGA8OXIJEklU2BwK02+g/0kMaKpLDBQMuw5iA+aL6z+2vnKOaRK87?= =?us-ascii?Q?PEAT6hsaEXbDxbOVtYlrXuhjrs2XqWKKWyCR6wGF+M6GA+PJ4/1F3A9XTt8p?= =?us-ascii?Q?9UP5XqOsiOfWM0a1FTVCx7TPxOLd9mobRUOAE6vrQZf+xKtFaA5OZJkkILz4?= =?us-ascii?Q?VdqOJ6sUCoYXaC5KJt/G7qUj1P8s0DWNYfYogVDeULUM2ItD4jL5JB3q1tYP?= =?us-ascii?Q?vAjI/wLJbAolDy5PZ3v6PS/L7mjgMLsUAylBG3OOS9ACaT9aaTlOvpfu0mPa?= =?us-ascii?Q?/AYJ2PJlDJXyTCRpzncHctfHHebijnKU9CZSO1ksfECGuBJ+vKG1aZCP0SJm?= =?us-ascii?Q?YU12Yms0I6yq+qeVwcEQQymXj687hFhCpNgUVTMr9Go26mQy3nknWyRyJh/7?= =?us-ascii?Q?h7EUc9PGLdnQTH8uZZsPoKsm0KdeXCmrWOwixf5TXE4YfQDwEbhquOsV/Hs7?= =?us-ascii?Q?93ramke6j0r7VlLadEJRw6nptTX/fJUBPUzVWGtypN3JAFB6vJah3lGWTqNY?= =?us-ascii?Q?vka7lAnlsrZuC3LS5y0HaXcBumY57cesSsEO6ozTWz97KjUVI+EyxVnvfgoE?= =?us-ascii?Q?DGqKjRslD07pcVRPdIX6TfsihK46wO1RQ192R8JTcqAa3oVE9PbdQOP4U0PE?= =?us-ascii?Q?AOJfquRMLcIdfCngCepng9dzIlfI5sslMgwCREgv0WG1A5KVrrhqG/Stu1Hw?= =?us-ascii?Q?07aJvCAjuzRYE4H4H7/2dU9KsqbX3kOTqSfsPncKeqxdONTEtl+yXiJOlOzu?= =?us-ascii?Q?dcEQx+hL3VRK2X1mGf2v8LP7UU9umUPkcue7pKKG3WFltNZXTQ1DEFw2teoi?= =?us-ascii?Q?KhB/dxOchh8nWj5bETIUiaELjc4VvUN4paW6i87ESFPn0VAu4R4IgXHVw6TL?= =?us-ascii?Q?/TW1MsNQJ1G0MwJjGOo0AekDFyXcJI3mU3/zCejOpSiM2SBC8yr0XrCFH0mQ?= =?us-ascii?Q?QuN2WDVWCYkeegBlcTzPSRnY8FeIMTT2Rou36ye3H4KRer+XndvaYwTLCb3B?= =?us-ascii?Q?gesYcyG5EiyLXGAyMs0eKdV8/fBKMezdvMr44qX7MxJ6pvlp6iH124T+x5VC?= =?us-ascii?Q?DLgaT5aQ3x+dlKT288nJasD6zhBpcwmPpKTyKu7VjCtBrV48iT1diESGjC7v?= =?us-ascii?Q?q3fIWsjZw2qK8xlzwJl4O2B9vu7nbjx+pHDTDG4UyyshuO2K8TrK+ynch2UH?= =?us-ascii?Q?ifDsiXH03E/64vQz5LTfNZvHKbNjN6I5LuNmF3YEHaHy6tntnIzZgCkrrwlC?= =?us-ascii?Q?V0jClS/cNK+mMZEnmSqHsZqTpO207nCLeDZus/4NT3uCnrLhLniNfFt5A4gi?= =?us-ascii?Q?u3QqakOk9nce/KXGpy2eeG0I89azkN9ugtQUlrZnvv6/mGzPLdvdVQdOxxMI?= =?us-ascii?Q?rfhfIBiHpDFB6wtXl0dS1DCRucSda/tyXc/UITmS3Jiq9VcVb0flqcFc5m4T?= =?us-ascii?Q?Z4uBaVB97aRibsldPY8XCRLsQtCFwMoIDA1cHvuiwBAQCnTN1B3XvyazSLky?= =?us-ascii?Q?4exIhK/KoXFPAHtNSBbi6bgmPUoEmd/YJqsQRKYUFxosyaIiWdbxdu/wt0hF?= =?us-ascii?Q?OIBn4488cQ=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: c32edea7-fc6a-4e6f-db3b-08de5864967a X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB6486.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 20:43:37.9878 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: sto/BtlBzKE8ZAYCVd/M/NufiTSxi4o0+K9BgN7loOsEioNT4zNI5kzF5C6WPJgK3Ie34C68ki3bmn2Uf1+xtg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6809 Content-Type: text/plain; charset="utf-8" Select the GPU_BUDDY allocator config option, which provides the buddy allocator bindings needed for VRAM page allocation in nova-core's memory management subsystem. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/nova-core/Kconfig b/drivers/gpu/nova-core/Kconfig index 527920f9c4d3..809485167aff 100644 --- a/drivers/gpu/nova-core/Kconfig +++ b/drivers/gpu/nova-core/Kconfig @@ -5,6 +5,7 @@ config NOVA_CORE depends on RUST select RUST_FW_LOADER_ABSTRACTIONS select AUXILIARY_BUS + select GPU_BUDDY default n help Choose this if you want to build the Nova Core driver for Nvidia --=20 2.34.1 From nobody Sun Feb 8 09:32:51 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013025.outbound.protection.outlook.com [40.93.201.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31F413D34B8; Tue, 20 Jan 2026 20:43:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.201.25 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941833; cv=fail; b=DKsr0zmarV+ubDe1zPRWEgT3PN+weou+ZqckUiPBJrXEmBkw6TQqVkrQyi3HqRncTGQo9anqCyHzW2fR/ewHUqRuuNh3NLTT4yQ9WlzfDbt432uq1Ml+A9Yl/xRBoU/tB1HRQWDHND1P5gasw25nxFuvy9tPZIPzm7hvJEOZH7A= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941833; c=relaxed/simple; bh=mGD78hzfM1uhW1v3Z9XeNpMNbxYSE2UiDzdP6LQz7PM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=XqlJxav8fWiQJOi4uCm/JsrAGbXJF07NV5JirLzvBRDXfejQmSQw+QoZp10bzIyVaX0Dl2U2oe+lJpWisN696SvVDQPc0p1SokKUV0AhGOUKN9Pivy3ElvPRrQETxEMzf6NkIatRNQtZlYOKnuHmy+xs4lhvln4rRU3a6CYQG9E= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=IiIeYSsE; arc=fail smtp.client-ip=40.93.201.25 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="IiIeYSsE" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=XwxrqWnGM02P4gXmWTLZH1Su62m+JaFkCRQLdJpI4MOeigLkcAWFshd9ZCS9mzPzM2CWVpxsCP/bL6NWiWRhorDmc+yD2F3Y6224FdyntpFxI2zZRdaYleoMZ3swWaK0eG/66EL8hIMJpXAv2uE8wIxPlYMUApDiKOAXbBTTi00gJ4L4Zfz2DEONmw1DOFBSTWsdpzymRRcLykPmEGtwSCoEfGQFRUJBGKt7dbif0HKqfV2rvZN8ba7ux0672BgROnH4MCEz/v+esOE5F7BBuxCB0FXH/J8iA0XghdXhi39jVZWBg+XEkfIgOczeqwzVbQnTS8kMNKVp3CBfFEi7Ag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=6ScqGeltuG1c0AbwJXdXDI8rVe3fvbpxPInfotw6cTc=; b=n+0KqJ3VQ0yBlBVZhUAFhc8DHBorVEZv6bZk1Y2mTZsEm7cX4qbR501cUNnJpCOesqFdEKR2OwSw9/5/OjgdWk1AXcmXapco5JulpAdtQgAVTEUfkTvl2hIfhaksVMoPAoqGWqv7z9bGZwhfGaVmH9XitmM+jl/Q7twHuPKCzCKYquvC6S7lbZw+CU/vTf9UmQkgJ0TfbFeG+Nf+F66rXO7SMZumTbqruMKhvzxowW25IlnYq83yt/G+AyOAwO+ssSB69FtuXxRESE6Ou6nkITZQfrg0arFOBCPvLYiv8qC1T93zualElZ56jvHU0oAsfswXT99LyxBNFFL6xjJbKQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6ScqGeltuG1c0AbwJXdXDI8rVe3fvbpxPInfotw6cTc=; b=IiIeYSsEFTrr7gyuh0g9E4WstWTemK7RQmqdsEReTUK6b5u5o92saReMVcpJDp/3hV6XO9vI0iabr/GIJKA5Y7l5SvwpEvRtaO4nbYeftJUWdKZ/tLhBl2ID0HakYYoEtriNimrm+b3ZTUalrZP+unuSKElhVzxHh9krIdUB/Ls+bQC98weL5dqEz92VOVfY9aBQ1AQ4t7mZ3zA4UXMLtSLqhGmnEwZ+0iweNMUnbgryhkQngZsTV1NMS67LzlbjZK3f5/bQlweLEIt5QNAvzDyVyH1MMNGK2y5oxfgF+r8/kBNqFKngzxNQsgTHfdJEutlmxYKi4HLO3bhqXixu9Q== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by PH7PR12MB6809.namprd12.prod.outlook.com (2603:10b6:510:1af::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.12; Tue, 20 Jan 2026 20:43:40 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9542.008; Tue, 20 Jan 2026 20:43:40 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jonathan Corbet , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Huang Rui , Matthew Auld , Matthew Brost , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Helge Deller , Danilo Krummrich , Alice Ryhl , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Alexey Ivanov , Balbir Singh , Philipp Stanner , Elle Rhumsaa , Daniel Almeida , joel@joelfernandes.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, linux-doc@vger.kernel.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-fbdev@vger.kernel.org, Joel Fernandes Subject: [PATCH RFC v6 05/26] nova-core: mm: Add support to use PRAMIN windows to write to VRAM Date: Tue, 20 Jan 2026 15:42:42 -0500 Message-Id: <20260120204303.3229303-6-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120204303.3229303-1-joelagnelf@nvidia.com> References: <20260120204303.3229303-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BL0PR0102CA0020.prod.exchangelabs.com (2603:10b6:207:18::33) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|PH7PR12MB6809:EE_ X-MS-Office365-Filtering-Correlation-Id: 9e856023-86c1-432a-5200-08de58649787 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|7416014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?lm4K6DUwAbMvzRumw9gaRmVjOxSC/vvwlafgg3SdY+QQs1Ux8j4KCMz2Y6n0?= =?us-ascii?Q?qzBgsl9jm9ji8UZ9U5dy56YFlsr9Kuo4BvE6Ckg7dk13z16D0Qmc83mXzb9W?= =?us-ascii?Q?gdiQu2mYvnr3NXCLigjXa/PpJoHbp74KWaIuSgXLwqZitvrYSmIZmDDxlO9l?= =?us-ascii?Q?2fHpX9HIKuXG7kC3YkKnNg/gIuC0lAjCU4ZUv7g3WLgy7lQ/rSb5OsOcUOuU?= =?us-ascii?Q?XN3H2+BdQxX1lmNdprqxVHO1GwQojRmU/wNbCvCMDZswgrbLWQtck4itIFLD?= =?us-ascii?Q?HdSn4fqR/sbhi2FTRGCIS6Wz1QwQfVtqJy9DAX/qGZ6UupKrg3TYqsyPQ3rq?= =?us-ascii?Q?/+UwVgnyXVRkS074N0/S9FeQ7reA7ywM0QdRHPQztHTF4+K/AqnDzlrFsF07?= =?us-ascii?Q?UoMY+Uf6gW4yPB+GGkP4gp1AHC1uoMMWPUZxYmsR79xJMFdAetYJWxySJQWZ?= =?us-ascii?Q?cvDw6iYPABeN2AOg0EBl9YYjL56XjRvo1Rh1BbVvAGog5sXsWxjOfC78s7zI?= =?us-ascii?Q?O38c55wlMjJPP8wwA4nu6GZaax7XE5OUEOOQ9KR5I3jgs38OxEsSBmzQuF/J?= =?us-ascii?Q?7OOEa5WOujLBP4d5nDwnxXsvZuhN1mFWAxtX0AW5mQygbBD7ll83pFxkohr6?= =?us-ascii?Q?0GAaXEaRON1N6QF4kSizGSbWlS0dGRx0hp2qeopICNydlRHghLSywGMARUNP?= =?us-ascii?Q?bN3aSJ/dloKQ0hhTN3UhRTDyIy/dwO4BLm2SzVmBrnXOOqP6XgBZnm98BpR0?= =?us-ascii?Q?EXBIklmONq48WDra3quCmAG+NcbQTZ9/KoVyrX0aDa7qK40qf6n01p82w8dI?= =?us-ascii?Q?AkW/4EZzhmfULQlU+u2YzR4E9E8E0hifihrUfGFw/3UykAEFM/JEk55ol2mD?= =?us-ascii?Q?AATv3yN45by6npnJBHrAm+olbCjxX84idpD+hivTEqvzQb95F2E/nrpUhInc?= =?us-ascii?Q?3OYkPq3Fcx9sJzZxwQ8K5Qxbp9JzmxUcSwH6GFedias/c1H1+ZtYXE0xVDPh?= =?us-ascii?Q?CkmoCIxzz+J39YfIi7PzDMv7QAODZ8or6ZyfNDt84YA+df/nk3EhYT+nXNt2?= =?us-ascii?Q?BOvcnhp0hzNWo+Sl2W7FejTOo42OaC/5C4C2Kzg3R7gu7NLuHdLWYKJ1DEmJ?= =?us-ascii?Q?jJ/5FxKo4wzmN5KLZ/6lgEin+LsRe6Ax7yUGJhqxXjZDeeddDCSWRJNeGTDA?= =?us-ascii?Q?vp2pFgHk9t4lAzExbdib7Umu/7r53N29UVI3Pbv4RrLrhLLKx2ns91KFYAAi?= =?us-ascii?Q?xo7X2vCw1mNt5fGQRbS0zpEQ34tz9jtEXegIorfKVGRpFF0FMWBEbqY01cQb?= =?us-ascii?Q?dQR/TJMpmtKbi8mGHYF5D7JFUQzLw3PLPZ4hAYsltUebgHxkgQow2DgD1mHg?= =?us-ascii?Q?rNUz/gTmquRe5XQ1nvty5UGF7fPWOR1yl0RmwOjuNF/ep3/ZK6NIelncNSFB?= =?us-ascii?Q?NfyL6L8aOWrM9Kiuq1dPEf6VK4C7O2588C6Ztpacz0cW1yhnMKD++AKMbBHP?= =?us-ascii?Q?yGZYZVj+IuWQFWQVXjijc3jw+llruGb9UYNsv88hgVbiGgPw4XnrMWIQFQib?= =?us-ascii?Q?1tlJkk3qUMYjAO8ZswY=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR12MB6486.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(376014)(7416014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?8mSDmDOLL9uTHSldXQToVyMdpESTYzyo9Gt7a3ngQgG1uNfq9R+uV8FPeUZS?= =?us-ascii?Q?bFvYBFDimxn0Z7caQfb9ZtA2YD7Vv1pUz3rjkSzpT1eGpGsSTqC6QZZTBute?= =?us-ascii?Q?d/oMwG+iLI+tJQTFzM6LrlfZ9LT54DSfmgQFBYJmO0sNMIJmMTZFeII/I+ES?= =?us-ascii?Q?QiAoUB2W5nb0EnQc/yGmiE4Gs8aPCYvNHulghsx+i9hJfoIaM85hQ48SUPbc?= =?us-ascii?Q?n8bWKSsPOXKM6U3jRg6p8MIvONmoRNA42dItWx7zBRaRD5vqW1nFKeT9MwPI?= =?us-ascii?Q?esps8cs2hm5bDI2b4jALFhEvW4HDYEkMxtlTsJmKCTUHd2KRZIMySZt6MQFZ?= =?us-ascii?Q?N0VDrXNmTNlw00YE6OuL8ys5bNrOxxIeHipou265U6CXFKi496bug2Hu1sjT?= =?us-ascii?Q?fDocDOM+1m9DQpFNGMTC7S3lrBuR/39LzXvKQ8tarWPgBm4V7sIco5gV1WgU?= =?us-ascii?Q?BUjDn5AUQ3S+yWhxnFx/is0g/asCZOT8aw7yiDh++yAJBsWMX3tF92qcOj1k?= =?us-ascii?Q?pk7d5brtN+JsJ4E5I3bDPhOOKXPpvZ+j82ozg7/jhxWAvMmwp5HZAbhggtcp?= =?us-ascii?Q?xfNWhba38tH8RyUac6QvZbGhkisDyYMl+HnbzVQBqKYNv+foqMAfjWQXBImu?= =?us-ascii?Q?zX9gxm5v00A+oUtMhqxwj0YQbewe2B0TX7KnsIn5mQoc7Pw9NJVekHh4FtJX?= =?us-ascii?Q?m4Z7MpXE0sNyCi9AzGV/ax2szfG2gi8DGpRm7Kn20ComJwufyKZX5JjVid8k?= =?us-ascii?Q?cQgpgQTASlqWRZklHjSIptyqvpbwD41qJQGrHurz4togBbaBaQNe2s+nfQxI?= =?us-ascii?Q?2A+4jW6St3+hfYly03oTSWiHgVYLIVkNXEJyzH9m51JRaihgmMusFfqix59z?= =?us-ascii?Q?5jrL4A2qyxkEWnk5wiWqBRUaveHaTfwZwwi9qWcc1QW8kG9KiCmb5zX234co?= =?us-ascii?Q?D0UGe1pO8Irs1RoaeBybwHdr83I4FYbmAhV7yw9bwmH0C4QwONpS59vUYsr6?= =?us-ascii?Q?3IgEL4d8uT5HSxvIv2ivcQH0qYrIMZugo8RWhSU/9rYLVOXxiooW6x1Xua1D?= =?us-ascii?Q?OjwEUjqPl+T3tvBYzRPakgo+QfvAlRUkqVtrREX83bnwUzNKVtV4V3JSgyUk?= =?us-ascii?Q?OqwgfvbzccliAy/5x7LLd/WH4XLm5tmwVBoviVllSuBW/zHY56d0DDNvB5pj?= =?us-ascii?Q?5hFlDRNri8mxAjb/9XbM+E3vWqum/tbFf8F55QFbPJRBgnFN5UoW7FA5t3qF?= =?us-ascii?Q?7jVXhOcDp94PS45TuOB0SejRuPcTvmGzc9nFobELGI2JN8Rl6vQ4zOGvh/nx?= =?us-ascii?Q?CxFWs9eTyK/je+8fC2Auf1efiRbczphEIsUKynM4g2GTKtcS9lcBzjPDKf0R?= =?us-ascii?Q?JFWcQs3mBnCOzRsjKtW8uUxcz6BM3zIwJrjKOmStKZcrNvqnDaT2RRs6F4vL?= =?us-ascii?Q?XTK0NDGfwuOJYo2FjLvBNqSALxxOQPGKUEF1SsXinDDJSdh/08DKvVmYnHSO?= =?us-ascii?Q?EyAtnYWz/e0+b8SCEgvK5KGVKxXGUmJYfUpaYJNeuVaPGzQfw8sJpZ8af3pS?= =?us-ascii?Q?IBOT4gbvxc0F+tjRw3nXsk3EBPAmHB91fvpFU4HliGcM4Pk8iOMV8PGeyA9S?= =?us-ascii?Q?e+l8buwm/Klf0Z/m3u3HTMsJ9GH4ZEY8bhhl+0iAeSKLZr4QWQhP61aasvpM?= =?us-ascii?Q?iWSSahZ1L6DHmUKkZDadBDC4y9/e6XHD4Ks7M1FbRQNZfI4a4NPCdDXiuh0N?= =?us-ascii?Q?rSsuGiindw=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9e856023-86c1-432a-5200-08de58649787 X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB6486.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 20:43:39.8648 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: HRuW37qBhFI0y/W/F2Zn4Omj33hrsjBoZHAnkBvaJlGoc8Zdmb5h8SG/NeUNF7t6Z8xJMeIeRhElqpQaTCZjtg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6809 Content-Type: text/plain; charset="utf-8" PRAMIN apertures are a crucial mechanism to direct read/write to VRAM. Add support for the same. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/mm/mod.rs | 5 + drivers/gpu/nova-core/mm/pramin.rs | 244 +++++++++++++++++++++++++++++ drivers/gpu/nova-core/nova_core.rs | 1 + drivers/gpu/nova-core/regs.rs | 5 + 4 files changed, 255 insertions(+) create mode 100644 drivers/gpu/nova-core/mm/mod.rs create mode 100644 drivers/gpu/nova-core/mm/pramin.rs diff --git a/drivers/gpu/nova-core/mm/mod.rs b/drivers/gpu/nova-core/mm/mod= .rs new file mode 100644 index 000000000000..7a5dd4220c67 --- /dev/null +++ b/drivers/gpu/nova-core/mm/mod.rs @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Memory management subsystems for nova-core. + +pub(crate) mod pramin; diff --git a/drivers/gpu/nova-core/mm/pramin.rs b/drivers/gpu/nova-core/mm/= pramin.rs new file mode 100644 index 000000000000..6a7ea2dc7d77 --- /dev/null +++ b/drivers/gpu/nova-core/mm/pramin.rs @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Direct VRAM access through the PRAMIN aperture. +//! +//! PRAMIN provides a 1MB sliding window into VRAM through BAR0, allowing = the CPU to access +//! video memory directly. The [`Window`] type automatically repositions t= he window when +//! accessing different VRAM regions and restores the original position on= drop. This allows +//! to reuse the same window for multiple accesses in the same window. +//! +//! The PRAMIN aperture is a 1MB region at BAR0 + 0x700000 for all GPUs. T= he window base is +//! controlled by the `NV_PBUS_BAR0_WINDOW` register and must be 64KB alig= ned. +//! +//! # Examples +//! +//! ## Basic read/write +//! +//! ```no_run +//! use crate::driver::Bar0; +//! use crate::mm::pramin; +//! use kernel::devres::Devres; +//! use kernel::sync::Arc; +//! +//! fn example(devres_bar: Arc>) -> Result<()> { +//! let mut pram_win =3D pramin::Window::new(devres_bar)?; +//! +//! // Write and read back. +//! pram_win.try_write32(0x100, 0xDEADBEEF)?; +//! let val =3D pram_win.try_read32(0x100)?; +//! assert_eq!(val, 0xDEADBEEF); +//! +//! Ok(()) +//! // Original window position restored on drop. +//! } +//! ``` +//! +//! ## Auto-repositioning across VRAM regions +//! +//! ```no_run +//! use crate::driver::Bar0; +//! use crate::mm::pramin; +//! use kernel::devres::Devres; +//! use kernel::sync::Arc; +//! +//! fn example(devres_bar: Arc>) -> Result<()> { +//! let mut pram_win =3D pramin::Window::new(devres_bar)?; +//! +//! // Access first 1MB region. +//! pram_win.try_write32(0x100, 0x11111111)?; +//! +//! // Access at 2MB - window auto-repositions. +//! pram_win.try_write32(0x200000, 0x22222222)?; +//! +//! // Back to first region - window repositions again. +//! let val =3D pram_win.try_read32(0x100)?; +//! assert_eq!(val, 0x11111111); +//! +//! Ok(()) +//! } +//! ``` + +#![allow(unused)] + +use crate::{ + driver::Bar0, + regs, // +}; + +use kernel::bits::genmask_u64; +use kernel::devres::Devres; +use kernel::prelude::*; +use kernel::ptr::{ + Alignable, + Alignment, // +}; +use kernel::sizes::{ + SZ_1M, + SZ_64K, // +}; +use kernel::sync::Arc; + +/// PRAMIN aperture base offset in BAR0. +const PRAMIN_BASE: usize =3D 0x700000; + +/// PRAMIN aperture size (1MB). +const PRAMIN_SIZE: usize =3D SZ_1M; + +/// 64KB alignment for window base. +const WINDOW_ALIGN: Alignment =3D Alignment::new::(); + +/// Maximum addressable VRAM offset (40-bit address space). +/// +/// The `NV_PBUS_BAR0_WINDOW` register has a 24-bit `window_base` field (b= its 23:0) that stores +/// bits [39:16] of the target VRAM address. This limits the addressable s= pace to 2^40 bytes. +/// +/// CAST: On 64-bit systems, this fits in usize. +const MAX_VRAM_OFFSET: usize =3D genmask_u64(0..=3D39) as usize; + +/// Generate a PRAMIN read accessor. +macro_rules! define_pramin_read { + ($name:ident, $ty:ty) =3D> { + #[doc =3D concat!("Read a `", stringify!($ty), "` from VRAM at the= given offset.")] + pub(crate) fn $name(&mut self, vram_offset: usize) -> Result<$ty> { + // Compute window parameters without bar reference. + let (bar_offset, new_base) =3D + self.compute_window(vram_offset, ::core::mem::size_of::<$t= y>())?; + + // Update window base if needed and perform read. + let bar =3D self.bar.try_access().ok_or(ENODEV)?; + if let Some(base) =3D new_base { + Self::write_window_base(&bar, base); + self.current_base =3D base; + } + bar.$name(bar_offset) + } + }; +} + +/// Generate a PRAMIN write accessor. +macro_rules! define_pramin_write { + ($name:ident, $ty:ty) =3D> { + #[doc =3D concat!("Write a `", stringify!($ty), "` to VRAM at the = given offset.")] + pub(crate) fn $name(&mut self, vram_offset: usize, value: $ty) -> = Result { + // Compute window parameters without bar reference. + let (bar_offset, new_base) =3D + self.compute_window(vram_offset, ::core::mem::size_of::<$t= y>())?; + + // Update window base if needed and perform write. + let bar =3D self.bar.try_access().ok_or(ENODEV)?; + if let Some(base) =3D new_base { + Self::write_window_base(&bar, base); + self.current_base =3D base; + } + bar.$name(value, bar_offset) + } + }; +} + +/// PRAMIN window for direct VRAM access. +/// +/// The window auto-repositions when accessing VRAM offsets outside the cu= rrent 1MB range. +/// Original window position is saved on creation and restored on drop. +pub(crate) struct Window { + bar: Arc>, + saved_base: usize, + current_base: usize, +} + +impl Window { + /// Create a new PRAMIN window accessor. + /// + /// Saves the current window position for restoration on drop. + pub(crate) fn new(bar: Arc>) -> Result { + let bar_access =3D bar.try_access().ok_or(ENODEV)?; + let saved_base =3D Self::try_read_window_base(&bar_access)?; + + Ok(Self { + bar, + saved_base, + current_base: saved_base, + }) + } + + /// Read the current window base from the BAR0_WINDOW register. + fn try_read_window_base(bar: &Bar0) -> Result { + let reg =3D regs::NV_PBUS_BAR0_WINDOW::read(bar); + let base =3D u64::from(reg.window_base()); + let shifted =3D base.checked_shl(16).ok_or(EOVERFLOW)?; + shifted.try_into().map_err(|_| EOVERFLOW) + } + + /// Write a new window base to the BAR0_WINDOW register. + fn write_window_base(bar: &Bar0, base: usize) { + // CAST: + // - We have guaranteed that the base is within the addressable ra= nge (40-bits). + // - After >> 16, a 40-bit aligned base becomes 24 bits, which fit= s in u32. + regs::NV_PBUS_BAR0_WINDOW::default() + .set_window_base((base >> 16) as u32) + .write(bar); + } + + /// Compute window parameters for a VRAM access. + /// + /// Returns (bar_offset, new_base) where: + /// - bar_offset: The BAR0 offset to use for the access + /// - new_base: Some(base) if window needs repositioning, None otherwi= se + fn compute_window( + &self, + vram_offset: usize, + access_size: usize, + ) -> Result<(usize, Option)> { + // Validate VRAM offset is within addressable range (40-bit addres= s space). + let end_offset =3D vram_offset.checked_add(access_size).ok_or(EINV= AL)?; + if end_offset > MAX_VRAM_OFFSET + 1 { + return Err(EINVAL); + } + + // Calculate which 64KB-aligned base we need. + let needed_base =3D vram_offset.align_down(WINDOW_ALIGN); + + // Calculate offset within the window. + let offset_in_window =3D vram_offset - needed_base; + + // Check if access fits in 1MB window from this base. + if offset_in_window + access_size > PRAMIN_SIZE { + return Err(EINVAL); + } + + // Return bar offset and whether window needs repositioning. + let new_base =3D if self.current_base !=3D needed_base { + Some(needed_base) + } else { + None + }; + + Ok((PRAMIN_BASE + offset_in_window, new_base)) + } + + define_pramin_read!(try_read8, u8); + define_pramin_read!(try_read16, u16); + define_pramin_read!(try_read32, u32); + define_pramin_read!(try_read64, u64); + + define_pramin_write!(try_write8, u8); + define_pramin_write!(try_write16, u16); + define_pramin_write!(try_write32, u32); + define_pramin_write!(try_write64, u64); +} + +impl Drop for Window { + fn drop(&mut self) { + // Restore the original window base if it changed. + if self.current_base !=3D self.saved_base { + if let Some(bar) =3D self.bar.try_access() { + Self::write_window_base(&bar, self.saved_base); + } + } + } +} + +// SAFETY: `Window` requires `&mut self` for all accessors. +unsafe impl Send for Window {} + +// SAFETY: `Window` requires `&mut self` for all accessors. +unsafe impl Sync for Window {} diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nov= a_core.rs index c1121e7c64c5..3de00db3279e 100644 --- a/drivers/gpu/nova-core/nova_core.rs +++ b/drivers/gpu/nova-core/nova_core.rs @@ -13,6 +13,7 @@ mod gfw; mod gpu; mod gsp; +mod mm; mod num; mod regs; mod sbuffer; diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 82cc6c0790e5..c8b8fbdcf608 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -96,6 +96,11 @@ fn fmt(&self, f: &mut kernel::fmt::Formatter<'_>) -> ker= nel::fmt::Result { 31:16 frts_err_code as u16; }); =20 +register!(NV_PBUS_BAR0_WINDOW @ 0x00001700, "BAR0 window control for PRAMI= N access" { + 25:24 target as u8, "Target memory (0=3DVRAM, 1=3DSYS_MEM_COH, 2=3DS= YS_MEM_NONCOH)"; + 23:0 window_base as u32, "Window base address (bits 39:16 of FB add= r)"; +}); + // PFB =20 // The following two registers together hold the physical system memory ad= dress that is used by the --=20 2.34.1 From nobody Sun Feb 8 09:32:51 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013025.outbound.protection.outlook.com [40.93.201.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF8953D410F; Tue, 20 Jan 2026 20:43:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.201.25 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941836; cv=fail; b=BXZjNa7yNQFtGkfku+qGSlcgCar2SkYxlBAUibWIB143T9ojpSAOCGUZsakzbV4qLwf83FlJ6I9T3iMhhGRS/Ii6AE7oUssIkEk5HWRj6OfhabqERMSi0oSy9UmR9cYz2efzQE33tkEN36s3TGBLbrL5/eTlbDGI49NqQpt0+3E= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941836; c=relaxed/simple; bh=e+PTyV9dTIwzBd51miBl2hLZ9CDRkwc8t1veWtGTpKY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=uEHef9TIOPzTHwn38Rh/OAwftG/ZSdTl/aF0MpHjYndPfZObkNsiWqLVFUk48Dqbb1DPEAQf1AOiRXbOQ/jGVYYQESom9O7H43wPbghxYcLlqW4HhOQuJDRmL+pq0Y/7PDboXMr8zDBBOO3hPVscwlT4zbdnaPJj/77agCRkDj8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=PufFANsg; arc=fail smtp.client-ip=40.93.201.25 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="PufFANsg" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=MqJPLPOs0nfGD60ZwGgFcZZS4cDQYysVJ6f5DUPsQJPhCiJHAjfPL/ssxUav1rBa3V8DPhG6PXMMWf95V2FlCdE+ghr2tGjf2EkEG2I6iUQ0/T5mk5enyshFata/Z6jZUzXS3DM3u2Og87EZMYVewd2eNF3d8BVhirO85M6OGrNVxUz9t7+ZjqjZI6S+/0lQrnE83oHARSjikJsN2IJyd4DfUU79NqJLYs3dGqGjFGwM0CBo05PKSylKEP8N2FDJW2yJu7dk2CZ6fC3254kkeYVFKPMf4qEfcAMJVNpoZIFnEP0hlQ7NU8ZrDAkpUpcPMqdOl8tPlFbg27tjSf9KjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=0lLiZUeYPn/js39AiTKJRSj8gMeB3+hvMowM+2efJOA=; b=OPAuVUNbpenPvHKoaCj2hAMNvwegsCpld5eOZ4BgHe6gFOmgQ4G2fgbH18pSs7FiJxS3TszywKS348bR55a0+/fBf0PD074GcGs0w6NnNPX5YQHyVMpcrhpZJHcd/sWbASO8XRBzl7kNQnn35sJIQ6xzKUZKadLGeA1byE8wbQTTwfNStNXH1BrcOJlWgVel6ON/PtWXxe8CfTjiUJObnsgQ8lFJZK5Eu1MumT6IX63rQmei2AZmxofMNI/s8k8uE2Xy4KW5DSW0ELQ/2o4hT7Zbke/w9KCBrtayIgm4oChjfE8oMibgxeQPmdHsgebDd9JheXn/Wzz+esborhnwOg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0lLiZUeYPn/js39AiTKJRSj8gMeB3+hvMowM+2efJOA=; b=PufFANsg7piKmHFqsdAJRBcjKVUgdxPO//3iCqzm2aOmoSI3O44C+xtYyd+QrjVfszSJCss3donE1d5jRWzVgqZa98Jim7HJxYyq6K6RX7ZzIqedy7rJAmGbBJG0kmpdw1SGccapyspbUinxG8WLtjoIrMa/P2/WV2uLFN6tRNZS5ahaeCMKjDNuB4SkO77tbMzbxQeacuk4VanuOoL3OOt7V/z9x7yzC9rXpdiaaWNrwDnZAf0iNwGKNWSXVQOKxxj/WpWWs1+IbQ1EqDOjMdSNmcE4/XT08J4x3rVsImIOeuvIgp6WXwjL5c+JaiZld60SuABijNX55VP/UjZpKA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by PH7PR12MB6809.namprd12.prod.outlook.com (2603:10b6:510:1af::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.12; Tue, 20 Jan 2026 20:43:42 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9542.008; Tue, 20 Jan 2026 20:43:42 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jonathan Corbet , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Huang Rui , Matthew Auld , Matthew Brost , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Helge Deller , Danilo Krummrich , Alice Ryhl , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Alexey Ivanov , Balbir Singh , Philipp Stanner , Elle Rhumsaa , Daniel Almeida , joel@joelfernandes.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, linux-doc@vger.kernel.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-fbdev@vger.kernel.org, Joel Fernandes Subject: [PATCH RFC v6 06/26] docs: gpu: nova-core: Document the PRAMIN aperture mechanism Date: Tue, 20 Jan 2026 15:42:43 -0500 Message-Id: <20260120204303.3229303-7-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120204303.3229303-1-joelagnelf@nvidia.com> References: <20260120204303.3229303-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MN2PR08CA0011.namprd08.prod.outlook.com (2603:10b6:208:239::16) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|PH7PR12MB6809:EE_ X-MS-Office365-Filtering-Correlation-Id: aa3b5eb0-2868-410f-291d-08de586498a5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|7416014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?nNpBb9VP+po/HsvCXt975RayLU4aKnNkHp9Zq1e7d5A0Hl7idvR6SaD3TFpx?= =?us-ascii?Q?0YEaAenhj+1b9Te0ERU0opIfYYvSLAqoQiAGYtlcgx4e8IzYvtYpVBEGSmwW?= =?us-ascii?Q?/GGwc0tutAYHU5MiEhdvKwnK11/skBHwI27+m3rEdC3pHuE0Q2YxIb8AiVDi?= =?us-ascii?Q?+rdh8Lq8qwKun/EgKt/YkblRBxul//XT/6ByUMyais7AGT1eAyXMTaQ3ErgT?= =?us-ascii?Q?Q9JteP8it761qGyJOxh7WF/2rsx1jEctdPnX54pY+Ejx/QvTKATo7zzVR5HQ?= =?us-ascii?Q?ir3oAdPXVFIWMBCBuqbpidkMVdDDg1bRmhpbNtw1go2NSDP2SQjR+p1ovtaM?= =?us-ascii?Q?LWC5Yslpgu1JA1dWGqRFLMJNvEvpf+LKtnEFpFJH/uJpevmFV3+xhN/cCU52?= =?us-ascii?Q?czgZ/3c5gYzU+VIOG7HWFlJ1oYPyDPh1yQW3wNUpA6jWPlkjQ141GrUAyj7V?= =?us-ascii?Q?8q4bSyujJ4FDckmjbe/X+JuhhuCI8aTKpPA2AlN79dYY5d8cRaJYhKRoSsMO?= =?us-ascii?Q?RJ4KBCQm5Naxfx9JoiRqKI/1IkoVze0fDswuRbMpU1Ji8SUNCLbqnmc/ga/0?= =?us-ascii?Q?1vCjK27nkfM3WgjpqFm7FBzZJa/gpKXMT6cl3XZRgL7CSV8Q9Nk2JEqkuwcV?= =?us-ascii?Q?TtVt4vGVHbJa5n/8FIKr5o6uegTbx+FxkyNJ6P60/UgY/0S0fv66YZNTRZwq?= =?us-ascii?Q?7cqhaoyenA6oqHUEDDvVXAHZVuvbb5TP02u5W0drPXp7syvZE01KT5HOhnw2?= =?us-ascii?Q?Xcwvv0ATDuciFnVcOr0E8ZLLgRUbDDBcrpU9qtw/q1e71lGHFEIY1u4e7Ywm?= =?us-ascii?Q?sIYiFSmycnv7hedLu3SspnHXAys1YiFis6XB3Ss4ne4IDrREpDexaalWLnKB?= =?us-ascii?Q?YdPpbXxdLc8zDNv9p5gnrien3t6Z5J+DNW4q6A01hdvRV+SKAK0r/g1JwVH5?= =?us-ascii?Q?0yoSlHxnd8rSuLnozAe9h8lLETAmw2UXGWcjeYAF8dyKAKqjhsRy+t6i67xr?= =?us-ascii?Q?TQqOx8u/9DwzEX8HrVvn8FvgnW5Z74DdKj+K8ii8r1Q3YFjiY96Xv/P8fvAl?= =?us-ascii?Q?j79IWvLbJPTaIv2YIpQwBkJwcUzQ9p7O4hsdsxRq2xyn8OHQPOISI4c46so4?= =?us-ascii?Q?PAGLHHzzswbOGGI6OXzx8ho0NCYegv8OsynGBKnTzkvNwrzM+23x1KlpSCCf?= =?us-ascii?Q?TjMHc3yVNmf9XyAKTwXQ669fhKPO1BMsPncD8KD49dEItjuEJZwz2OK+ZJn9?= =?us-ascii?Q?Y9LnYj17hlqJTzUThD8xlGnOA2Li93x0On3HqsLTDCTOOrrz1j2j536ovUIT?= =?us-ascii?Q?EM1M0BKgJ16KqzcRE0j9ycBcAmVLUudBxbssuOc8B/d4ph9jBH7mkqv6E02v?= =?us-ascii?Q?TVjxlla7Od835BcCpMfxW1TW16G70eCOS+3yFx+SXj00jEJ4FgHCJ5nofdD8?= =?us-ascii?Q?Q6Kw+qLSlPBaqJOrgI1ZzRDRiuAPlQL3XC8FEZcq1XcNlaXWmrvHWI9mvd5T?= =?us-ascii?Q?CpLsS291EPacKIEaPELXwZjjhJINb/GU4j6y8Bo6a9t8HhFITIYCvV7aoBus?= =?us-ascii?Q?DJAzVR//YN+HI95Uyzg=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR12MB6486.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(376014)(7416014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?U+Z7GRhN2w5lYsW7IbDji+TLj2LujdlAvyCgN/3hPEaiuCU1l3+C5UfCqie0?= =?us-ascii?Q?lFpi3TfdLL+uaFmRHdlKzuZ9mcSXIXqW78JAyMVtnln9xnjTvcAxmgHyd5Iv?= =?us-ascii?Q?71CK+o24mRT9HZUMVmRVatK2SB1oYSK1BTrMVTpepTfy6ikBjLmtTV9F+gq6?= =?us-ascii?Q?Ng+JWymPBtu0L+cmKyAKEl0hE9IylvHp5jXjcAWmuPhnT3G8fe9vYRculqHb?= =?us-ascii?Q?zCthqynah7npT1igrzKZk35h4KmxoqLg9UgHreFC0vTZbZX0NsMD8tfZpbBU?= =?us-ascii?Q?v6syaLt/qweyxThF8goT4t8KdsIM4oX32cKxSEw0E1+PyDPavejv/CTkt69F?= =?us-ascii?Q?80+f5Cv2Jo+0LFPg7wXw6P9WLjDqmiG48nYbGnXIYr+pwWagWL9xKZt0Epxj?= =?us-ascii?Q?kKKEqHUpwHXaCCEorKDZAWI/tZuRDkZDKSmV7g124dhASC8yKQfVJHvrCBQv?= =?us-ascii?Q?BGb4H3YmlwMWU9e3WwbmgzhNl+4z3G6GfKA85w+oOhNfoG7e2OTxBASiJJY1?= =?us-ascii?Q?q69XFpqPYt9p8zI1jot3Fe4EOw1WZqM9pXTLL0BGFEe1wGEIkwLIxanpCo/O?= =?us-ascii?Q?gji3qV0rk9D+N14HJiDTEwx/EazK2+XPJcW5KXs7WlGdhe/yN0btXijjJRwF?= =?us-ascii?Q?iJPIO8yYFs3lCekvXazbpT7m59mlp50iydC5aLP65RHCTcpB1y4wKXtN+SN5?= =?us-ascii?Q?DOXrqBf94DDga0F3zL4HLyIenpaEaRflTmEh+Tdv9o8jOkvuo9N3uoCFlI8y?= =?us-ascii?Q?JkGAMsKO36/ntFCyqDTLVk5ovSJJV/bigKN7bwwwUHYYuN4vhaIxMck78gHg?= =?us-ascii?Q?ngFri8Tb1P0yojk4HSZwSVTPw/iLdmyzvECtIgaTp4hyXfN+5us+mWSmgzqB?= =?us-ascii?Q?StZfKBgGcY4Ic/s/SXufHjbLjS/xrA6D6bwHJJ4VuqfJpxcuutJu9pzH4rgS?= =?us-ascii?Q?MY/2v3cnLeHMiVSnaVrbUh5qbo2/0yMPaU8M0nHZKOK5BrZP0rN1GPl3gbb4?= =?us-ascii?Q?DY0FW6xuMiNi1gJu1KnBUepdy68onjySP7DiyUo0+5l9SoADs4PyXOaw58a7?= =?us-ascii?Q?qQbdtgffZaIB6j8e3xuWWhHpCOY776aQLmLADJVOHjLEmTiDU4RKGRvlIbMp?= =?us-ascii?Q?NrN3yGOtYZ9n6AEjm1buCBwSdwwh21EP6gJtbRWAurvcWZ76dbMUjmFgyJaW?= =?us-ascii?Q?YigL8cKyFtZ/MG/w6mYDPgJ66eACeNg2ykVf4R/BHApWgBuAg07LVaDhuSBg?= =?us-ascii?Q?oH3s5KRfo5pj6Ret5ExLYA0n/Zgpb+0tzh3DLylvJnWDcYTcuwRPCFyzkajX?= =?us-ascii?Q?Puy5IRywzqFndrEB3zcj02OOE2EJCIsOL3dTUgCla0J2rYCkKzXW+/BwLLvN?= =?us-ascii?Q?ndiQ6KaMlaWZH8U2SFZ00LyNCygEqX608acwejAb16pgU2eK850fsHsi3857?= =?us-ascii?Q?DxDtG98pV3ftEgur5gbsLLrMMYn6cQyh7rz1kRoyPZcTNEdqu7R7RvMv3UY7?= =?us-ascii?Q?vGC9qwDD/181ZlObW5nh8+5KVuJt3n7x1fBI3foAe+D8OWtKdtM+sdoAYqnk?= =?us-ascii?Q?ssxNGg2OrqQGKVsTNtEa0FRAowgjCP1yXqX5mTCSUUtLJajLJO13kQx8RLen?= =?us-ascii?Q?Aow2R55LjCD7AK8alLP/4CkerWJhYFpbfQUvacbUpspW73YH+kofYZbqlfWh?= =?us-ascii?Q?avAIgmZ8sANNTDa9PwVGwmtO6KqptZkosHNAaNLfhiiTEVV0qDIJ130aJjnD?= =?us-ascii?Q?XKEwZl+6jQ=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: aa3b5eb0-2868-410f-291d-08de586498a5 X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB6486.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 20:43:41.6569 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 4VeJnXxF0Ev8BAY88aiL3NLBXSy0s+7yNbpwAZPXf4UBgaZ7jLs9aj3xtUROlnwkcCY59+3CNjLXud5GyEKsvw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6809 Content-Type: text/plain; charset="utf-8" Add documentation for the PRAMIN aperture mechanism used by nova-core for direct VRAM access. Nova only uses TARGET=3DVID_MEM for VRAM access. The SYS_MEM target values are documented for completeness but not used by the driver. Signed-off-by: Joel Fernandes --- Documentation/gpu/nova/core/pramin.rst | 125 +++++++++++++++++++++++++ Documentation/gpu/nova/index.rst | 1 + 2 files changed, 126 insertions(+) create mode 100644 Documentation/gpu/nova/core/pramin.rst diff --git a/Documentation/gpu/nova/core/pramin.rst b/Documentation/gpu/nov= a/core/pramin.rst new file mode 100644 index 000000000000..55ec9d920629 --- /dev/null +++ b/Documentation/gpu/nova/core/pramin.rst @@ -0,0 +1,125 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D +PRAMIN aperture mechanism +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + +.. note:: + The following description is approximate and current as of the Ampere f= amily. + It may change for future generations and is intended to assist in under= standing + the driver code. + +Introduction +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +PRAMIN is a hardware aperture mechanism that provides CPU access to GPU Vi= deo RAM (VRAM) before +the GPU's Memory Management Unit (MMU) and page tables are initialized. Th= is 1MB sliding window, +located at a fixed offset within BAR0, is essential for setting up page ta= bles and other critical +GPU data structures without relying on the GPU's MMU. + +Architecture Overview +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The PRAMIN aperture mechanism is logically implemented by the GPU's PBUS (= PCIe Bus Controller Unit) +and provides a CPU-accessible window into VRAM through the PCIe interface:: + + +-----------------+ PCIe +------------------------------+ + | CPU |<----------->| GPU | + +-----------------+ | | + | +----------------------+ | + | | PBUS | | + | | (Bus Controller) | | + | | | | + | | +--------------+<------------ (w= indow starts at + | | | PRAMIN | | | B= AR0 + 0x700000) + | | | Window | | | + | | | (1MB) | | | + | | +--------------+ | | + | | | | | + | +---------|------------+ | + | | | + | v | + | +----------------------+<----------= -- (Program PRAMIN to any + | | VRAM | | 64= KB-aligned VRAM boundary) + | | (Several GBs) | | + | | | | + | | FB[0x000000000000] | | + | | ... | | + | | FB[0x7FFFFFFFFFF] | | + | +----------------------+ | + +------------------------------+ + +PBUS (PCIe Bus Controller) is responsible for, among other things, handlin= g MMIO +accesses to the BAR registers. + +PRAMIN Window Operation +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The PRAMIN window provides a 1MB sliding aperture that can be repositioned= over +the entire VRAM address space using the ``NV_PBUS_BAR0_WINDOW`` register. + +Window Control Mechanism +------------------------- + +The window position is controlled via the PBUS ``BAR0_WINDOW`` register:: + + NV_PBUS_BAR0_WINDOW Register (0x1700): + +-------+--------+--------------------------------------+ + | 31:26 | 25:24 | 23:0 | + | RSVD | TARGET | BASE_ADDR | + | | | (bits 39:16 of VRAM address) | + +-------+--------+--------------------------------------+ + + BASE_ADDR field (bits 23:0): + - Contains bits [39:16] of the target VRAM address + - Provides 40-bit (1TB) address space coverage + - Must be programmed with 64KB-aligned addresses + + TARGET field (bits 25:24): + - 0x0: VRAM (Video Memory) + - 0x1: SYS_MEM_COH (Coherent System Memory) + - 0x2: SYS_MEM_NONCOH (Non-coherent System Memory) + - 0x3: Reserved + + .. note:: + Nova only uses TARGET=3DVRAM (0x0) for video memory access. The SYS= _MEM + target values are documented here for hardware completeness but are + not used by the driver. + +64KB Alignment Requirement +--------------------------- + +The PRAMIN window must be aligned to 64KB boundaries in VRAM. This is enfo= rced +by the ``BASE_ADDR`` field representing bits [39:16] of the target address= :: + + VRAM Address Calculation: + actual_vram_addr =3D (BASE_ADDR << 16) + pramin_offset + Where: + - BASE_ADDR: 24-bit value from NV_PBUS_BAR0_WINDOW[23:0] + - pramin_offset: 20-bit offset within the PRAMIN window [0x00000-0xFFF= FF] + + Example Window Positioning: + +---------------------------------------------------------+ + | VRAM Space | + | | + | 0x000000000 +-----------------+ <-- 64KB aligned | + | | PRAMIN Window | | + | | (1MB) | | + | 0x0000FFFFF +-----------------+ | + | | + | | ^ | + | | | Window can slide | + | v | to any 64KB-aligned boundary | + | | + | 0x123400000 +-----------------+ <-- 64KB aligned | + | | PRAMIN Window | | + | | (1MB) | | + | 0x1234FFFFF +-----------------+ | + | | + | ... | + | | + | 0x7FFFF0000 +-----------------+ <-- 64KB aligned | + | | PRAMIN Window | | + | | (1MB) | | + | 0x7FFFFFFFF +-----------------+ | + +---------------------------------------------------------+ diff --git a/Documentation/gpu/nova/index.rst b/Documentation/gpu/nova/inde= x.rst index e39cb3163581..b8254b1ffe2a 100644 --- a/Documentation/gpu/nova/index.rst +++ b/Documentation/gpu/nova/index.rst @@ -32,3 +32,4 @@ vGPU manager VFIO driver and the nova-drm driver. core/devinit core/fwsec core/falcon + core/pramin --=20 2.34.1 From nobody Sun Feb 8 09:32:51 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013025.outbound.protection.outlook.com [40.93.201.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9725C3B5306; Tue, 20 Jan 2026 20:43:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.201.25 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941838; cv=fail; b=cM3dR6nFdeLc8qSWJwOJ52oZn3IqKlrTUnsjhMNYCc2ksyObYrPLCi8OWnC5m2vzQdQRJVxz8Q08zGugDInCRZv/2CqKlcRYtCGYhlxI/JDe1amgkfsxdfrbB8qk7nXbcB55bbqM6kqL9tMqVunZnVfeECn3rNRMw72NYo4H9yU= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941838; c=relaxed/simple; bh=WYt9pD5dYgvfcPNjHUhOXgr+9ePGsRGEmzu+YCdif/A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=Kc2Y/WeusLU/THyC8SXwS1xAy/g8x/Z5YDwExN+6hrxzWhCSgQDGNNees58ZTCTOSW+TCH8AJf/r8Bb7bPVkSBD/ZCaMtg7wVg5WRZshasbt2uefwDRIIeOuMJMCAknf11erUsoxGY4UyT67gE3fv8y1OmzDgy+Xymoo6uvxcIs= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=Cw4K4NOt; arc=fail smtp.client-ip=40.93.201.25 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Cw4K4NOt" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=yaN8hcUbY1Ux3AFWZwOLGzD5aaJij5R9V6qMvcWOS93G7sIiZ1PcXeKeCV3kS6weN2W3YcnFBko5qx+AW/+eQ1361tEQmM/1iZR3MaXqEAgjnXzU0SSHT6gkD019Oc4GLzg2Ca2ORrj6RtMuVihsRkVa1sVKm6drkcoDjUaTbwsy6J4c6zNVca/jLYexgzskHz82yAAdYpO/m8zDmtB2P4z4yfSPa9+oxraHkARzIaqBN8P41eK5JjfWZreBRVmk/8bWKM4FYsXcD5sTkD+THUSCGXoSh/5aShTmSmMK++A392vELFGMKCa68tlVJSqVLrdbxhOtKOgNs9Wrz8lvrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=q7ly6TgSNWTNlrKlknPvbWXM2Dnn575SqIwcOwuE8hc=; b=aitd8NbCg+eKEKabYg3NjD2ydObfwTgEYhb/g37Mv+S/zdC3HHdwkDcxgqKUDs2M/75Tl8+9j/bkKnzkNRx9kC9FMUt3sqPWTaEThrC+0Dea0iKJU+eX8+ievsqt9p3aVlKLPp+yOcj6gA/eDxRlWp+eu1hof5SMFgrODM60le6JJ0IbFgHuNv9FER4DF42IgkuOGzaHxUIR3CHrvKarUkm8jJ9vPF7xCoFEVVSL6dm/DcuTho+hChXJ/bbfcZm8dY433AOrYdramGXe40rjLGKgerLSm6xIIfN9F88cTh6vqmWWASopse/QpfsKFxd5cCpYt6hRpC9JuEJ6RGSeAQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=q7ly6TgSNWTNlrKlknPvbWXM2Dnn575SqIwcOwuE8hc=; b=Cw4K4NOtD+fqTVWCssbB8Dfn/2LN9j29flZI898eQbC6zu8fju1uE57Ad1inxk+dOMpKpdkHEUhgApOLG8C8OC+KFiRygw2zXVzSXChmT7e3exb0flWmlX8L0S/a7iBcQJxvVgdqphtLPZHX7ITjSeRomOwxhHmOSP2oXPU1N9sLMErjFX/hQIkctDg5LGOhuIf0xWQJartUAEerqty8p84WEcbHvGev2DxjC/Y4qg4UTT/EAgTc2r3RegG/C8o0vamsA63rY8bC6EsAMI7jEgcig8cj1wHxTZJktXdVdTc4VIVrMuOJ4AcIr91W1Mx+AkwJCwvhFjPV+/s/3b9eYQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by PH7PR12MB6809.namprd12.prod.outlook.com (2603:10b6:510:1af::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.12; Tue, 20 Jan 2026 20:43:43 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9542.008; Tue, 20 Jan 2026 20:43:43 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jonathan Corbet , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Huang Rui , Matthew Auld , Matthew Brost , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Helge Deller , Danilo Krummrich , Alice Ryhl , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Alexey Ivanov , Balbir Singh , Philipp Stanner , Elle Rhumsaa , Daniel Almeida , joel@joelfernandes.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, linux-doc@vger.kernel.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-fbdev@vger.kernel.org, Joel Fernandes Subject: [PATCH RFC v6 07/26] nova-core: Add BAR1 aperture type and size constant Date: Tue, 20 Jan 2026 15:42:44 -0500 Message-Id: <20260120204303.3229303-8-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120204303.3229303-1-joelagnelf@nvidia.com> References: <20260120204303.3229303-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MN0PR04CA0003.namprd04.prod.outlook.com (2603:10b6:208:52d::15) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|PH7PR12MB6809:EE_ X-MS-Office365-Filtering-Correlation-Id: cfb68622-fac3-44f1-23fa-08de586499a8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|7416014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?ZB6mw5GDkbFhNIJJdB3p/ED/pH2I7sYRWFGLA1mrX252i4DngHgbolIjddpA?= =?us-ascii?Q?UVfHEGNAptCnyzj0bruXHceixhCtWDdZJ/nL/l9h1qLOfZbyvWieeE1vs05M?= =?us-ascii?Q?n+m5z0U6Li6LJLujOzAhGXFauJE9RqIKp84KBEvdl3LY9zeeDlDmj5aMt0nJ?= =?us-ascii?Q?hKqSlBLkmSh8NXVGGRNJmwC5ze5C9eXXeFz6+HKUez01+zwedO6OzB4lFZr/?= =?us-ascii?Q?fZcE1zhjfBQKwCR0vNcj3QlF/vlLdsPyRzK2YuzWu15ioCVlDY0Tnzo0O6HZ?= =?us-ascii?Q?Y0MMISZGgjpT8nUMohzL5wu6mgPpQl/b6Nv15ZY8/yVwuunyCD4p/rAoJ0Hw?= =?us-ascii?Q?VOQMEkVmH9Vwz2GkLa51ObZ5eOFbXG0UdDPb0ybcIdyYc6APkC8aqfmpGs7U?= =?us-ascii?Q?X/SbschD9In6YX4KnvOBAqfS3t7V/JRQG2HsXCooRLRlVmpmduLonSM44IMd?= =?us-ascii?Q?8G88uDibEaQLUEye4GMlW/bYm2WsJqHZVsJx6A7u3EKC5z9cNpsQshDECjWI?= =?us-ascii?Q?WI1hj264GylguBQqulB1K+V6jheGRdVIe5nReDzeXdhm8vGKFL325byfGw99?= =?us-ascii?Q?Hh2GVBJqWRdl7HT1NlD7fp0OMVKqtf/UqV0QIa30G7KTtalfBCtv3UfS7oqI?= =?us-ascii?Q?OkCishxuYMgh/1858pyxZwkxlIXrKBSywSlIUB/9i0EYR5XFU7jzpW3KDzRa?= =?us-ascii?Q?H0ZweOoO0vBeMvkKsxnkRdkanFmd4BteOr6/d66yIgUUdtWmFfZG6Bm2fvkx?= =?us-ascii?Q?QWcXRV/MHCtS0rY98HedSF6wYqteMZjbtEvq2+daWbPuOq9cgtyN494XNCpy?= =?us-ascii?Q?beN46OZb79NsrxWLzbXQa2Q0dkPDCIO11EVZjriXBt6JAGKkarC48nrOzAJb?= =?us-ascii?Q?ITmFdHQCiLgWGGuyUOWPHyEv+rkKsB/DNEkvaew3KJ6m+7GHd3RaKFyMtS5j?= =?us-ascii?Q?b6USr3DtAkGF7zxURfb3DYfu2bCNW5iUM+TtAvk3zHiHTQTvPhXhaqbDzBzI?= =?us-ascii?Q?8TXOodkpYGy1EuzRruDq5SwfxSIZ9QgvTaKePpj8vEBydemdzOICwaKrHi4n?= =?us-ascii?Q?I113f+Uy+mXSowXjA07vBXfuSB4lGEYkelmIZZCJrehEh9i6uiAFg4Ma97Bb?= =?us-ascii?Q?QI9STB+31p8hm4FzzJoG2e5wfKNIOk4GaQban2u1bEwBxjkSV3ip+kYMP/71?= =?us-ascii?Q?z4XqsDc05VmOqlJwAZuBEo++bY/KmOnnOAlLdQxas4bJhTYPi1Jm5v58wVtk?= =?us-ascii?Q?RFO5jHcf6InxkhRtxzR4kbTihPYuUraQU/GHg9ivxkKVQla26c4NHM4zCv8R?= =?us-ascii?Q?Cz56DhUBgBmjEaGyCyQoRa1hVQBtGWtZoOKHIPD6db/OYD7WUKGi/1R8wMyD?= =?us-ascii?Q?7Na5/IqD9hS/0RAmt2nnRA5T8AQi6GHVx+Bx36H30aidVOipMHrOIW2qCNsv?= =?us-ascii?Q?/E11p4uLCrq+zvDBvspTnK4ZQRT/xsCEyvtn6Fiaj3k5of+MqTbGTVKylEh6?= =?us-ascii?Q?NYQr0GktqHhIEdmutmpTkAu4KFoIrwKXKW+sD8ypEPDMDzm5TRzmaryWGNT3?= =?us-ascii?Q?m2ZcrPMdk96tlGN/cqo=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR12MB6486.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(376014)(7416014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?O8KwpmAYtNNrykupqKw6Xt9t8gARh8252cbl2EyBQVby5TFcGwm3xqVdArR5?= =?us-ascii?Q?6RMkqAv3d0z8aLT+FMsjiRnNxH2O+WptyxLnUd36guD1apue67e6naREz3u+?= =?us-ascii?Q?15e/yLTj93JWYX8cJ64oKPBJhLZs0g69ygeS8Mg5BUxsv2OUwU8BMhfAiHss?= =?us-ascii?Q?sPCgxhkRcDsZ0KqCxrSxu8mnOSn/ntLATwGkOsIwvklvNH/GcX6IS9mpIImI?= =?us-ascii?Q?ga6ozCe/05h2enT6eBPKM8V3TKblVkoG4pSzXlcTV+A86W91kguzyKJEOlBU?= =?us-ascii?Q?euLq9PvT27AsM7TNueLkiMfvxmf14RBZnBGCwjFmxQerDHNtYt0+OBR/MoGQ?= =?us-ascii?Q?oH0c7I9XkHlV1Xuh6WMVLuE/q038zcnFeX3d33UrwMXMhiCaEALPUxJC0fQN?= =?us-ascii?Q?M7LtVtqjz2CM9xoqRutKt++vn9gPP84/cYAytGF4jtKvXyQdVyJzEiYTWBR7?= =?us-ascii?Q?f+P5x8mkzbMm/qmM/lSUD88+dRMQRa4qAjGHF7lVfPhQxgpOT0RPvE0VGnnm?= =?us-ascii?Q?Ukq0176nfcJjgTIJXJEGok2pg6PrwLcZn8T1PDIDj+QtkRLJOCmH1pZnHuTZ?= =?us-ascii?Q?fruKko4WFeRSy05CO+xXP/mucT2tJNggDwCzqgj3L+1KB68Q7lRk8hzYVj9j?= =?us-ascii?Q?KC7AA8KrZxP/3zKE9jo+gAd7jD+TwWfcpT9NUu7p1h+VjmLRf6eaC6fk3fbT?= =?us-ascii?Q?oWOY8+4xV+U7dNB+KxMxG8iwDgHOFAwrK64v1NCXvpvt11O4RUuwamVjPPVG?= =?us-ascii?Q?1hv5jTgAaU3shb/G3JvDTG1+oSmIMr96M48ihieNYZZW/oVyMEWa8sMWZ6dO?= =?us-ascii?Q?93Qa/ws+EDYCXnh1F78hUVyKlI/E+YUZAriLJKb4c0urEZHqWM4wqslU3sQY?= =?us-ascii?Q?nrzwXpL41xxHuhX+eptenl+lYqUI6+GzArBCPbyOSM7k0TJgqAqiOoJ/k62K?= =?us-ascii?Q?08RPAou9yZPuLz3fADtchhTIpFk9VMz61m8Ypw8p4C4G+2tF6AjuUlizFH6p?= =?us-ascii?Q?JVyk+yillo+VWS7AS+t5+t5lKyVnzQCsnBPOC8NPJFuhuUG9MDcY7DIUUU3a?= =?us-ascii?Q?ipl++/W82qwuqowHEyNuLQZ1ck0xBs69JXKG6U3gRfe6DEAcNp28+A2yV2OD?= =?us-ascii?Q?2tvuEJINgu6/jyHSoSF+vpFe+V6PNmj7LaBjtzWMauLsllcZNaEULhxUG8gx?= =?us-ascii?Q?9omlMPgi4TSGpNvQzF20G7v19JBXW0OmdhYt/rSbabu1HUOFXXlGPMNiGSED?= =?us-ascii?Q?yHkz9kXB5CCqNLJWve77SbXqDdreDPINekn4S+sA7UL13hkdTVzJj+ZwyPK9?= =?us-ascii?Q?T+OJ1iwmtP9fj+i+2CnDR/9rm80hYHnq2NrMSElv/HY8FQ3cI9gWlwvNJErD?= =?us-ascii?Q?xn870OVVyIxoJ7ALsWRbqFNPE+Uz71cVNMEhCHQqsoB5O0B9a5ziytvN/cLM?= =?us-ascii?Q?bseHzCtYfhFRpUU22yCxj9Zy8opvhUCuqUB2RbkTSfOQ21nFJsjgRTHulV46?= =?us-ascii?Q?mBQ6Vn93SaWaSJc8ptLMRLsydEZJNKsLcIadS8Cpu3sVaqihiKrTFqOiAgtl?= =?us-ascii?Q?R6FYkMzTYnE5ivqeMO544MsU/rjQGQh88zjNjc5jwrbto77jT4yDytva+wW5?= =?us-ascii?Q?HAWTXbUT2MX9ugTQIKBttQLXXPhrumT+QutEktjPhjStEUZtzzeFKo8Ib/qB?= =?us-ascii?Q?JAicMjfkxAJOAEGGMONeiWypOX6f1d2YPAiUANP4xCEZBbN+Mk7Ce07wF9U1?= =?us-ascii?Q?LElRG0w0jw=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: cfb68622-fac3-44f1-23fa-08de586499a8 X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB6486.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 20:43:43.2688 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: bRlhax3AxS685VFarldKvtN4n95Q5nb+6Fj4nN5P9tgIDbWqvm5BFO+KHP1gpNsK5FF8iEl93GHKN21qP9WueA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6809 Content-Type: text/plain; charset="utf-8" Add BAR1_SIZE constant and Bar1 type alias for the 256MB BAR1 aperture. These are prerequisites for BAR1 memory access functionality. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/driver.rs | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nova-core/driver.rs b/drivers/gpu/nova-core/driver= .rs index 5a4cc047bcfc..d8b2e967ba4c 100644 --- a/drivers/gpu/nova-core/driver.rs +++ b/drivers/gpu/nova-core/driver.rs @@ -13,7 +13,10 @@ Vendor, // }, prelude::*, - sizes::SZ_16M, + sizes::{ + SZ_16M, + SZ_256M, // + }, sync::Arc, // }; =20 @@ -28,6 +31,7 @@ pub(crate) struct NovaCore { } =20 const BAR0_SIZE: usize =3D SZ_16M; +pub(crate) const BAR1_SIZE: usize =3D SZ_256M; =20 // For now we only support Ampere which can use up to 47-bit DMA addresses. // @@ -38,6 +42,7 @@ pub(crate) struct NovaCore { const GPU_DMA_BITS: u32 =3D 47; =20 pub(crate) type Bar0 =3D pci::Bar; +pub(crate) type Bar1 =3D pci::Bar; =20 kernel::pci_device_table!( PCI_TABLE, --=20 2.34.1 From nobody Sun Feb 8 09:32:51 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012052.outbound.protection.outlook.com [52.101.43.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62A053B960D; Tue, 20 Jan 2026 20:44:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.43.52 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941861; cv=fail; b=ghxNWA8FWDn8D12RiHrGdEj23sBDfO2hcsoPRmPN517yipv3p7aegj5CIgZZfBrRMcTP0YpuqJ5qXOvxleBycCrFJuI6mXZCV7PGbhgw/NzySo5Pue0hlCK0yRdwY5Pnuc5+mg7Rv2DLIQRB81yIkG1leyoEzRshAQuMWpD86Ec= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941861; c=relaxed/simple; bh=Xx8zCadKEh9dN64NMxbJgOOV45fTd6tQKfJtq7q/hiM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=ULkbTuRhtZ+6nxDDuGSct/pJwUioQm7dladRPz3TdKxz6+KLTFwHQNt2YjOQoYYd1obNIFWreSp0st+j35xfqKakPE4rd+lqeOq5ztUqfi9kCfbu6d+TdccX8ctW2A3GxUXCJhHPzanhaGTWPoSJYv5qWHMVqZfMgelVajd6W2I= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=RDBEgNZF; arc=fail smtp.client-ip=52.101.43.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="RDBEgNZF" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=egoNIGyTMFmq8Fr7lO3dEOsg8rIxCxlh/tUJkViHke4kWs8bqvHP26kqmW3ioj8bz4AbPHJfpyqtySUFo8ekzu8hDNrh+ZduPon2AkG+SCdZFaSzi8eTJRvaEJ80b7l2LdaWKaYIr9NkF9EOOI/EGeaioNab5pFGIt9yiERNflHvEiZGlHJsIWhgLqbiS8gqc97I4OR8ExFgjg6Tvo/aMMjO2urH7LY3W4SDWyMv6lwfQTFq6frz41/9qmKFagFEFxO+eWi3MGhwGpEovC+J5B47oOFZhMa+g9cz0Y895ORcwuwpD3br+rxkHOr+87XRf+nvXmv2zlOs6N/7PipLyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=N6yduBpRUNj5frgHGs/am9bdgwj9ubygsF/v6jBT90o=; b=MdH60FJRaT1Z8egRsBXcmyc9Y+Rls6ZaAEjezqNnN8ggaRQG7UwdOKOaAeBE6Q8+avZtlmU8vKbjDFysij+mR/3IxOSaub0saE0zJOC5NxY6xxCmKgCr+G0fM0TRFsIV56xMolXqkQi3j9UnSTATj1PdeA5GBmTpKqDnoZMogxw2dxznxxIPcNLsvt+qvkDQ23Dtroxau9VabHmcXqd3o64nI+E6Y7lIAX4Ds57GNh3C4YkstfEJmxN1WYfsY3SWYE/2X8i/sbdjbqyhLI22M19nl+XssPM2BgJ79VnXzWQNxB4s5sfiRvaLn6S0Lnc4RTObJghoQmuVUs+A9LxWLQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=N6yduBpRUNj5frgHGs/am9bdgwj9ubygsF/v6jBT90o=; b=RDBEgNZFWqZowqdEjZw56giYr/v/xDQYnVa0a0c7sEOjnppDyJL5xBGqurXEKfMf/b+UL5hWrijRpR8cgeXZWJJSvR48ClTskaafCLoEAUuwfAYDZi9+8RQ33xH5WgkduTPPbLqpBxFSnUZ14qHRtMbeXq3FhC2+edUXdTR5NA8Wk+K2QQ4PbRabjYDmD9Wus8i2wZsYGlwwiXnlfmNFFND3ThURz03+SV1Dyv8PZnYSq3NUm2reBI6LjzMoteuFChYl3e5aSjMzD4jMRTNo+fuATEnjZQkKZ6Cs9ue6uPKHZNagIdXdqPV5HFTTU3WQtwsmrkG9GWp1J9z3UraV1A== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by PH7PR12MB6809.namprd12.prod.outlook.com (2603:10b6:510:1af::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.12; Tue, 20 Jan 2026 20:44:04 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9542.008; Tue, 20 Jan 2026 20:44:04 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jonathan Corbet , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Huang Rui , Matthew Auld , Matthew Brost , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Helge Deller , Danilo Krummrich , Alice Ryhl , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Alexey Ivanov , Balbir Singh , Philipp Stanner , Elle Rhumsaa , Daniel Almeida , joel@joelfernandes.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, linux-doc@vger.kernel.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-fbdev@vger.kernel.org, Joel Fernandes Subject: [PATCH RFC v6 08/26] nova-core: gsp: Add BAR1 PDE base accessors Date: Tue, 20 Jan 2026 15:42:45 -0500 Message-Id: <20260120204303.3229303-9-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120204303.3229303-1-joelagnelf@nvidia.com> References: <20260120204303.3229303-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BLAPR03CA0064.namprd03.prod.outlook.com (2603:10b6:208:329::9) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|PH7PR12MB6809:EE_ X-MS-Office365-Filtering-Correlation-Id: 03fe6b01-5987-4615-2555-08de5864a628 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|7416014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?DEWiw+ohiMVDIZWX2kd5o+ibSUlSogqe8p3ao53M/c1EXW1SItF7L1bnd8sS?= =?us-ascii?Q?5taAgd/1XqrCf+x8eL2np3cQDAY8v//KVX8IvjZFHst1X+xziwvxSTUcPdG4?= =?us-ascii?Q?tpNaLm47UF+t/IB95PfFWeDkXY8zX9E+pwDVx+TgzNIjchb1DFW4BgQGKfWV?= =?us-ascii?Q?qZBuDmlWAu1zdVc8utOu6JRMZ9jy3kTF6jGM05tXlXTRahW2ttgD4ZEVM4rU?= =?us-ascii?Q?g/iDHEMija/QxLfwlR7vBXrKMycp14v0HmqcxFXdXWOMXtFbMB91pIdVMkLO?= =?us-ascii?Q?jrwtTNS+tnwcnJwsQ8BtmzakkJaIdG7eoQNdD/TJ1V+JrZUX1Ci8O2O+xiJq?= =?us-ascii?Q?Y88H4mTi/WunwtPi0+QGD9WbNNhRV75mWZtHMGXq7tjw+O0+fasqPeb8vt/c?= =?us-ascii?Q?2WyM1ZDgH8LZD8Gbd5yks1Q7GaC2b7w0+DZLKTEl11Gwhj9qir7Cdg8xk7ka?= =?us-ascii?Q?9SxUQTcP1IXfuEBK6GbfGTCQGa6Jl1lx0/z5qv6wlwH1GbF0IGTkkZYzB/42?= =?us-ascii?Q?EsMw21GTlBJ1X8oFVGDdd9PPL9h+Y4BQoG9X2aOLgbKC3I3asHaCzcIoIVsR?= =?us-ascii?Q?KvQ+sXN4l8ZW22ng2Un/ospb4QHjc6rn1YofCMG7sVDNQBFNLNnr2WBqkm+d?= =?us-ascii?Q?Ct9Y8yr1bpG7GOm7mba4PIr0mBe0Ml0tT7R4xs7jrc8BFi1Gr49acrSNkOPM?= =?us-ascii?Q?5e7mD4kjUh/LZjbCRAogkqSDm7J4clXq62rilpY1OSkdkqHYFJJHoIYQdU+K?= =?us-ascii?Q?mG+jI6+vMLkfHP5iObV+aMOwwrOPU4atVu+9k8QWzsmHF1sT+/QHYteq63nQ?= =?us-ascii?Q?50v1kD1qHebwgCXTWCY2o41pdciQeY3R/QnrZZ5NpNe4zr6bkWE3PLbx+Crq?= =?us-ascii?Q?alcRtTFBFpE1GR3q+acLetlraqw8OBMwSFy/1U2gBn7lc3QuhjWyGGy8G91G?= =?us-ascii?Q?LYoKA7tacNKQJmjcfSQ9Wg5M6a5+IDu1vEYTU3ytIDkimnuwcB05SBnsF6ZN?= =?us-ascii?Q?p9aK7ll/HDMXfzJ7nNIRORTVabdlcJZfzw6VM4scfS5jpT63F+PqUirhrPBP?= =?us-ascii?Q?Ce42HLVv2t06cDvWrkoLvfIqPLzcSfyTNsrDazzpvdBRMWpFMrhZ+ghDcemJ?= =?us-ascii?Q?XMCk/AAONz4yEqyqrvLRjAbLoPbOwRew6+fI386ENzpO4f+UNfV4WUnIxygW?= =?us-ascii?Q?bWhQ1/pEkmlbaviWr62BeJSM10Lr3MAQWImkfjoldTyBA0Tn1JW3UAET/JRB?= =?us-ascii?Q?g1L3zs/OrfecVLKFCyT1XQLNfNzivM7MWS0aGLKtz0PSp1gwT/6h8hc2x0eH?= =?us-ascii?Q?e0SdaRaZkV7s58tOcsYMLfKEThQatZRVI7+5d/OcSb0QBVuW8L2ZwdNzybeN?= =?us-ascii?Q?8FGueFR12DGWrE+nTr5l+0b+j0cAb1lqPgBxhKYJT3B4QZk5qtmLoij2ueaE?= =?us-ascii?Q?y6rRGe9CTXxXlgNB2xh4ZuWLdXy5Fr0h6o0DwuL9LAwr1GkQyipqpiqZK+sB?= =?us-ascii?Q?Mw9WlREu1d4z/EPnILovbNkgP39onMrPFpCNT+5lDu7nHyS+fLPo+NM5Gcfx?= =?us-ascii?Q?urVNdrZaMUyw3zIbWzs=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR12MB6486.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(376014)(7416014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?XH3c9j7mKIqhtM7RUFHws9F099xhQbV7pgxWv86grrWo5hwjXJLutylGgApe?= =?us-ascii?Q?jffLDI7CFSIqn4yKvcu0D/CyATHcfUzRw0YoxC9uYEkqNVu3Gtjz9GpisTAK?= =?us-ascii?Q?tNNWwiVz/KwfZehi/TMXYyMjHckzf0D3wWx/4emrdKhMWviXkT07ciCr+Sk9?= =?us-ascii?Q?iCuJRcg0XqTYS99fnHU2El3TmktXdowOXVkNloXpi6gtABKX/mZQSKEwobjA?= =?us-ascii?Q?bA8f1cHNU5WLxV40+6hNwUzxECZCQi5Bj41AbMEHhSfGnqVE7JRnVYApmtdd?= =?us-ascii?Q?G4x0aENYpiDhya5y1XrHAC3XOJswWSD9H1Tt34YrzMgS/JABCxRM+xf0hvp0?= =?us-ascii?Q?xLLJFlx3TYMXfsrf8+RbwuDzdgsYyWT74fyV3VZlHukCxpZdxckGhHRoZNtd?= =?us-ascii?Q?KTWHux9kNv8JOGglFEge9maNrOlNFAy+6n8cfwKbq+xk7XpetH2zIid5+oep?= =?us-ascii?Q?pM3PPtxIls8SWtyfpfYZ+fClh4HV/gPhlhSapbNA3eNXWiOJ8Jj/I0pAS6J2?= =?us-ascii?Q?/O0/sQ948vW5HxZIJdEvJTpVo213TQuGeS2Ek3c9ij7Tg0RI2emJFYhD5qPJ?= =?us-ascii?Q?O4UhTYDlnWQOf9VxdcV2X82AJPg0wg5v2DQQLj5Mwfv/MiEjlWp5q0odBfvY?= =?us-ascii?Q?fWx1EAN3wP2yAdoIQI9R8uVXxvos8wx+c0A+QQFr1cMWiB8c4ftn5W+RD2EV?= =?us-ascii?Q?zBXynQOC/gsXoxE1RgdzdShBlR+X+VSePjifvE3SgB/SIlU0GgO3CKepAPby?= =?us-ascii?Q?LBE8gHEptkFgmAEaG53wMtIcEO9Zy5RTrySdBZiAFXvWbOaVEziYg4JEXSnm?= =?us-ascii?Q?rprXZ0GRARfdoTeqhfV+EOl9xDGXi7RBP7m6tiG15SJqiOrnIdzRGD+0Mmp7?= =?us-ascii?Q?DygAvaIrx7l9ESFE3d+njFySjtoCKeFC94oWzJilcnXUtzN+6I4FVKBN4eEt?= =?us-ascii?Q?d5r9Dahk1bkzhvoPRwEeW38XXy0QGBFb7cPb52qp0bfYLWbz0gFTLCMp7WfX?= =?us-ascii?Q?vcG3UbfQrUe4p+bKM1IJWEszvF7Og42l0LI37HYshnlxMnZQKQqB2vg8KVl3?= =?us-ascii?Q?S8Dp+LO7FlRK6phmJqj/epaDbLYISVUTmUcNQt1b/ZAu08VW9l38kIQBLkWV?= =?us-ascii?Q?LW7ODZ9pCcZwNRZmK53qDY1FRKNpj1wQ46DWhKc1VD0PZIg2dbI4nUnzfaL0?= =?us-ascii?Q?OHzKzil4kaSCPqEd3Fc9VHIzsJIWm4roTSb0+xJyV9Q2ssiVQeazMesB5Irx?= =?us-ascii?Q?Mu3SDIVG7NyJtbbZo9n5lmCnm8yDcw+2tUVHkVzYoDgWHzbqlAuW0rla+Ktd?= =?us-ascii?Q?//z8mDcknU/gTjtIpsUQOWjkTQAU+2KDd2j1phsj/0I8mtSdauVHH3drP/yg?= =?us-ascii?Q?D/CBfPAiV2WpcTKGYDnBjGyoJ2VVcK/NGxPaGliUCjFhwVqWFiXstPutRpFh?= =?us-ascii?Q?ZPy3CzLg+IjO758/szmzMU22nnakw1bkxmgWqlbWj3tA7J5eucpADRsnnIIr?= =?us-ascii?Q?MHPDaIERNywZ+L8GQ3LwpDod2c7VhDzkcGFfAZbBLzWW/H7ll+gb6cTiJRUN?= =?us-ascii?Q?DbqvzZzkM1dwAUAobQh++rL7YjYHZ3y+K9AYH1OrH4cz2FwN62YJcO7btl7y?= =?us-ascii?Q?BaLW81/fLCAJUgRLH7Hy1CuQkNDRjFCYCcyk0uV6sfe4eg1A868MHI+nvpUF?= =?us-ascii?Q?SqHtsVOg1ZejGAI93doAFGoQGdSGRv605dbBbaPbIsGyEvSYUKOzwZr6Ixuc?= =?us-ascii?Q?WbPO43/xrQ=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 03fe6b01-5987-4615-2555-08de5864a628 X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB6486.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 20:44:04.3393 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: mWkNfYQ4TwqmUaQ/8ugLjW/t4DVIKK9O2PraAvToLcXEIHHn1OsIloqTWiDF46eMCXxHLkudAY4aT4PG8ufNJA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6809 Content-Type: text/plain; charset="utf-8" Add accessor methods to GspStaticConfigInfo for retrieving the BAR1 Page Directory Entry base addresses from GSP-RM firmware. These addresses point to the root page tables for BAR1 virtual memory space= s. The page tables are set up by GSP-RM during GPU initialization. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/driver.rs | 1 + drivers/gpu/nova-core/gsp/commands.rs | 8 ++++++++ drivers/gpu/nova-core/gsp/fw/commands.rs | 8 ++++++++ 3 files changed, 17 insertions(+) diff --git a/drivers/gpu/nova-core/driver.rs b/drivers/gpu/nova-core/driver= .rs index d8b2e967ba4c..f30ffa45cf13 100644 --- a/drivers/gpu/nova-core/driver.rs +++ b/drivers/gpu/nova-core/driver.rs @@ -42,6 +42,7 @@ pub(crate) struct NovaCore { const GPU_DMA_BITS: u32 =3D 47; =20 pub(crate) type Bar0 =3D pci::Bar; +#[expect(dead_code)] pub(crate) type Bar1 =3D pci::Bar; =20 kernel::pci_device_table!( diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/= gsp/commands.rs index c8430a076269..7b5025cba106 100644 --- a/drivers/gpu/nova-core/gsp/commands.rs +++ b/drivers/gpu/nova-core/gsp/commands.rs @@ -189,6 +189,7 @@ fn init(&self) -> impl Init { /// The reply from the GSP to the [`GetGspInfo`] command. pub(crate) struct GetGspStaticInfoReply { gpu_name: [u8; 64], + bar1_pde_base: u64, } =20 impl MessageFromGsp for GetGspStaticInfoReply { @@ -202,6 +203,7 @@ fn read( ) -> Result { Ok(GetGspStaticInfoReply { gpu_name: msg.gpu_name_str(), + bar1_pde_base: msg.bar1_pde_base(), }) } } @@ -228,6 +230,12 @@ pub(crate) fn gpu_name(&self) -> core::result::Result<= &str, GpuNameError> { .to_str() .map_err(GpuNameError::InvalidUtf8) } + + /// Returns the BAR1 Page Directory Entry base address. + #[expect(dead_code)] + pub(crate) fn bar1_pde_base(&self) -> u64 { + self.bar1_pde_base + } } =20 /// Send the [`GetGspInfo`] command and awaits for its reply. diff --git a/drivers/gpu/nova-core/gsp/fw/commands.rs b/drivers/gpu/nova-co= re/gsp/fw/commands.rs index 21be44199693..f069f4092911 100644 --- a/drivers/gpu/nova-core/gsp/fw/commands.rs +++ b/drivers/gpu/nova-core/gsp/fw/commands.rs @@ -114,6 +114,14 @@ impl GspStaticConfigInfo { pub(crate) fn gpu_name_str(&self) -> [u8; 64] { self.0.gpuNameString } + + /// Returns the BAR1 Page Directory Entry base address. + /// + /// This is the root page table address for BAR1 virtual memory, + /// set up by GSP-RM firmware. + pub(crate) fn bar1_pde_base(&self) -> u64 { + self.0.bar1PdeBase + } } =20 // SAFETY: Padding is explicit and will not contain uninitialized data. --=20 2.34.1 From nobody Sun Feb 8 09:32:51 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013036.outbound.protection.outlook.com [40.93.201.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF26E407573; Tue, 20 Jan 2026 20:44:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.201.36 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941862; cv=fail; b=p4i/J27RhJbUK4yCev+zQbox+nDJJKe4pFkvkwMrYSeUTg+2crWxNrL63k57FjQBYRr8I6SciT1CiISdeQp4cFWsI1Mv/9RstJX4SWCT/s2KchgUhZgyi8UV64SuifNQlTFyBk5XgEchargBDqRj4717QypbNpSJkDe3vAsIiuE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941862; c=relaxed/simple; bh=yXfnFWm1rG8ZzNTujYBcT12IRNi3gahA90szainudxE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=Rb+hLr2xoOB0VZnEaJfHdbUkjbA44Zf2mtQxYn+XTqYlojEHmfg1RwsB4KMw5+ISsEsASXUYe7KNYBy6LsSSQrl8hPamjWPrxYRozDWJburAs9hl8z1CslOCF1gZUIgGWU0afjSWhGBw0tF2SO6Pqm5r7i9WTNMbciiCtilvvWI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=Xvlz2wRQ; arc=fail smtp.client-ip=40.93.201.36 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Xvlz2wRQ" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=aV5bKx+x6U8EllYwf/hEka8agksGrmaeh92LgOtN/NWyHl2z2jdsfRNRm6ukR7BJL8gtoK8Vx+YrjSvuXrxIoX/MuxBYhBB+QHofliqJE6NHbHoaaBQMEZDqDA0ZdQ4DPL5Ykfz7iEeZFOX5OqlkFvl6iyB8hSy5osStVYFkrr0IlKtN8sirtTGGCqgYHrRfuGKnM1YsCDr6RpHWt7bSUS1OX+WfrlzmOHBPnovVX3MmjXAcApItNcCbkJOd95xMYQQw8r3Wiq9MObIvpD5yNyAxNXE6CvP3CZZCPDruxQEEMJHyXuNDDXg3GoEKwkb4MXwmGLht6cFwGxxU5ewHdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=44qTBUt9Cx8uYWv4QLH+KpMP1qQDvX/8gMFkojo8AJc=; b=k76VQ8Pz7ZxJrH4DD85ZcA82BFgUw6V5VYhUgCBTd/NdDoZnRxQua+Tru1kO0t5L1Axy4cuyc+kYOv/5VaY9IHpmOYQW4nzgRovF8CdSw1gGq13MfQ87h0P3P2zcVkBNxCMy/uALVzxiLhuYNfo+ZZgrzhxCW/v70tUCNFd6VgtYKbEqOMz0MmyarzJDB4vDTDU57Ij6A1/rh4eLBlDD6b5solZwk+3JXrdYdkvCeKGhmpvnzUJSCUq5NUDg9sMOfiIs46YFhd1Z3/AY1NaJdmhW35bAHi/fUn8+A/WGYGS+YUMJM2kR1UgmhRaZkUubJ4UNFz1wVgbbL2beHaiYAg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=44qTBUt9Cx8uYWv4QLH+KpMP1qQDvX/8gMFkojo8AJc=; b=Xvlz2wRQb6ZoGqodTpDYi3N8IMSMW3IWCEEB9txY1MHphnTKjqDCl7aqIQsogLNm4Rwg1Z6uhXMP0HpEHlbGaB3VFOrPI0UCDIuX0dwQbIW6Y4FfVEBkSDXD3eJerRzueGWSu10T2rQC8Nrv7F+9/HRaol8VAnNcM6H5Sru4hvyeCxvbqMOMUF+ElkXF4tdRhtYK2CD4bL+RweNgycVFpcosnJzHV+W+ln50Y8hvCcrrLcBJjrihvX5hFDnqwmWGasUxcr8gEZzTC3vMFSrIeK+0Rc0+kzH6cb3haWeS4emGz6nJShANWNTlvuBAkjus9lgEK1VP7IatnC+Erx/0TA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by PH7PR12MB6809.namprd12.prod.outlook.com (2603:10b6:510:1af::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.12; Tue, 20 Jan 2026 20:44:08 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9542.008; Tue, 20 Jan 2026 20:44:07 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jonathan Corbet , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Huang Rui , Matthew Auld , Matthew Brost , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Helge Deller , Danilo Krummrich , Alice Ryhl , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Alexey Ivanov , Balbir Singh , Philipp Stanner , Elle Rhumsaa , Daniel Almeida , joel@joelfernandes.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, linux-doc@vger.kernel.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-fbdev@vger.kernel.org, Joel Fernandes Subject: [PATCH RFC v6 09/26] nova-core: mm: Add common memory management types Date: Tue, 20 Jan 2026 15:42:46 -0500 Message-Id: <20260120204303.3229303-10-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120204303.3229303-1-joelagnelf@nvidia.com> References: <20260120204303.3229303-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MN2PR14CA0017.namprd14.prod.outlook.com (2603:10b6:208:23e::22) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|PH7PR12MB6809:EE_ X-MS-Office365-Filtering-Correlation-Id: a5a8239d-75da-4005-e4e9-08de5864a7e0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|7416014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?NfOJqJNtTiyvlDrvdaLNsso4lR9cvHtX/ouzgsQjcbZoxeYnxQWxMFCqjIpZ?= =?us-ascii?Q?Y4X7TB0nD6EfjDr3RuzGSHJAcNnZSsvE1eaPEFTw2MFK2S8w8JOwoMz3wU/j?= =?us-ascii?Q?FcIGHpmga7HAwW8gMo5hbXtPXY0lRrnNg/mvEyXU7lf74k9dguxFQ8dSXR0D?= =?us-ascii?Q?YTbsDfORhhUuEjtBR0iFwROXf1zMM60XcG28Iqz2huVb/H55SxceOoEHcyHi?= =?us-ascii?Q?JrFlqYUpdyc6kPILV9YaFayi/J1bcmjONZVXnpH9ZDx6MdOrUfZqUUFQJfEF?= =?us-ascii?Q?SeNlA561RVMINjSHX1hCh6qFecAUQBPXcdKOw3M7ro01qJvqaVofV2u9REIm?= =?us-ascii?Q?c2zKfvO3biwQTGWvRmCW22t6SRr7Z26zzt8suOBCxR8Q1rbImFB+uJe3ZC4c?= =?us-ascii?Q?IpbGuqEHuvb9PSRUNyP9k6Hn7JozUdg7NFJBGBLm04ESiG7aDl4pKJcv/AO5?= =?us-ascii?Q?d0PwfTiRq/n/R21hPix4PoLiI3DC02iN/3qqTZNlGqPaGWSc5OBdLY+aKRre?= =?us-ascii?Q?lsFz0liOtdl6Kf9ykaD+gKAFXZCLRSIRaNnAD5skcgHhUTqyPX938uTNvS2D?= =?us-ascii?Q?rjB15rCCBkumNFwpNnyNAaDLyXBms2gJ7cH2MFPe+z6Felf0/fHVddOLEFiI?= =?us-ascii?Q?3+wLG9fymJXTHohz76JYXqU042HsWH21uOO857slDmNo8GiWzaof2fp84KaP?= =?us-ascii?Q?AQrF7acc6xlTEkVv4Go+hX86cfCES2ihmf3u22zVyoqXfKKUm5dbNsheBFQp?= =?us-ascii?Q?lSjJcunkPJQzChJqE0BefobAnX8VKP94uk0f+4HD9kCRxzWyj4ygE1Gps+vk?= =?us-ascii?Q?8Vbpceu7tUH/tH6bgKeQ/Ikk7hyjR5pLlHfBlAlJyKD6AHmW9n1YTtLiaw5F?= =?us-ascii?Q?psYLagpYOO4vufcj4pMJWnlz9/lxluqm6Lu85gDyESYfFpPPbOnHfd/x2dHy?= =?us-ascii?Q?HliOp51SRSdHqsYJW4VuLXLnJfAw9OT4rUW0aBTOwQYQQmbzZY4D5jxZFAfS?= =?us-ascii?Q?YDCqeG6lVuOY50nNlhvEUuv8T4PnIcs2mhQP0NyaRaBKnOaphJKGJaO9RxbJ?= =?us-ascii?Q?4zC+tTbf8MmValuI5rngEiug7g/q02QTor+vUzKjkxel+dYw4sAKVBXZgSuz?= =?us-ascii?Q?tr5KpwQxvyhOL0litMsXODVTf/GBSa4CmbSKVu7kY4lrj7SSgjoEGpM5csvb?= =?us-ascii?Q?FNBsLxNWKk1Iv/P85b+/VfenQ0JWg9LMMAB+YpznshMcCIVNwTR6badyPGdC?= =?us-ascii?Q?Qs5qDajH/Z58123EafBtEoKRZlzj6xYmGY/jhl2AU5JO3umJd2fd8tlcT7SW?= =?us-ascii?Q?dWkvLUsI7ShRbfrIQSvaUWa5WuwVUUlXksb2dxvGibgEa60EIyQMf+nShve3?= =?us-ascii?Q?r3I0FGJ6nMOF7cHHrspl8wkdazgfu+BoqP2gqNsfuSdfCkuNWDS4oGd0M52x?= =?us-ascii?Q?M4W52M7cxnpFBjRfm4XpsGbXuDYLgJofiDptClB5qJvJRPNUM5/BLUD18NII?= =?us-ascii?Q?VAw4jlRsXRHELm6ahsLbeLr3w4tnTWS4Dn2Vj5rHxf6VWIu5vSXq3+IURUua?= =?us-ascii?Q?FzNQT8VnnnD7simzBN0=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR12MB6486.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(376014)(7416014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?8fwn+V9kaX9F/ObJFvE6WGKFWv2VuYSUtxklaBwlX/HgSfNazz9BVOshCocZ?= =?us-ascii?Q?tWOWmSIfsxj76JCAUJKnzigoK4iP5CAHD4LBNinVqYrmJ7lrldZPmoZ9YdEg?= =?us-ascii?Q?TJAQtcrxC3+OFICMP9H+jhHpJh5Ks/NwwJ+zALeNv7B1pEkPeUzmZMJvmlXU?= =?us-ascii?Q?lOrxhPmpyhkxwkfQqeOfEbVX5VhkjwMLcgcKxhDsyu3rEYYbobVqC6tKvsMM?= =?us-ascii?Q?bIP7FarRgmISbaqugPWn2Vsp3s8crO3VTQEd3rq6NoalIbZqUaS7OQmcrYt2?= =?us-ascii?Q?JafCr+d6Rx6DZezVE7BFLFHaPjYvtEyOzt9K16ONBL92vHeg2QM752lB9XHe?= =?us-ascii?Q?RVj9DY5QJ0KKPUN37fRzbEoJ1ast9APvi/BG/b16x3FJCFpT5z0JQIewTcqi?= =?us-ascii?Q?eQ4xOYsMV5JAkSSPx2+MudSeo+CqqKWobxqyVn93uiR/pWlD4U9S4AB2Y3xZ?= =?us-ascii?Q?p47iqq2QUFv1w1MfWPXs3Pg1ChuwHPyLTDsmzsD0Cu3I305zFKJLn21VjCpc?= =?us-ascii?Q?ybC3S9OTvckzS8LAT9pYi6TcQFdjqkzgo0YjnYmM3RMEK+l9tgC1LgHo2I0v?= =?us-ascii?Q?okoEnJireXmm4F5bO0JSgzX+Mpsj0rujb3Q6wuG2ErZWUUVpD8isVCVEYfJB?= =?us-ascii?Q?ZgB/u9YUMe1mADll4Cs4qAuO/1BngU9aj8fwH6Q8l56Z1cSGmSANp++iLS7l?= =?us-ascii?Q?NYASo3LbebM3hS57RvJRx2Z5s0C8s2ejg7sqGV20qTI7JT64U1PpULGQZZBx?= =?us-ascii?Q?UHsw4g6LkNvIzgSP3JGtiMH15LgoXD/Pm+Q9pMcLEDyrPiFWM7plMKKdIHJ+?= =?us-ascii?Q?riy040KuQmSt75m/4mJuU9fqFdCPS6Ox3OBMb7Ued2A7eAGQRFd76ryWROUS?= =?us-ascii?Q?DsnCFbtMqdwTHbHfhm0Je1OEE3NsvQapG21d107C5xD+e8wvLh+S6Vr8CrkS?= =?us-ascii?Q?NLIJXkvYPKtqZ8Mt1QIAaNWvVxGXpmJOGmihljZPt5gueJkC5Dz4HRn4/c8Y?= =?us-ascii?Q?Zsm9RiA7vjUtaHCEc9oZ2Ueg6h9n0uN3N4/YYxGyNVFmr8GunE482I73kvoM?= =?us-ascii?Q?fKEBfp5bAEqZ50LPNlrBwp48IYDDPmyR7pWbH7jp6ftpVf+wp/PsV/lY8ytk?= =?us-ascii?Q?QOi6kKHdrG1Z7FieOIpaRBNEOhmljsu6kSIx2VEWsGAlZDAyZ7T8DqA30Moq?= =?us-ascii?Q?UEV03MI5mnLmb6ndywFTkQk5mDZkrJENf6DDpYfXmwBw0UauBfTNidfTdqDt?= =?us-ascii?Q?3Gu2tRJvgynoDjclNJqIeMcW2p8pPKRKh52q0IVfdHSotdq8jgPVkXln/wln?= =?us-ascii?Q?FB54hpkmuPcj+VqlKdN8eX6oaSF18HppTPRabumCGfPbx5mZBIrBKqhu2vR4?= =?us-ascii?Q?gbsgXHZtxaL2NKi94O9c8TvKgdE/xW3n9yfhY+SnFTfgJgHvo3lHITjAInRM?= =?us-ascii?Q?0RWAqSWkI22WDai3OI056ZXq4XH5Dk5jBBLUkg46R2kYkFCnjPSR1O8plv9T?= =?us-ascii?Q?7Eje8J/pp0LwGiJsdhqLC6GbovC4Y0HcvEwINCK5jq0ICu9TLNpQXOVTuoJ1?= =?us-ascii?Q?brN2alrZk+S4MSruoDVcLfMNPcdtMhdcWkiAmy4OAbCeY9nVISFUlnRK0M2Z?= =?us-ascii?Q?sYV6kEN4SMhbLUZqO6F8PTYYqfPZSYTI9pF1v+RmYMJ0wDjLDWXZUq0/xraq?= =?us-ascii?Q?rN+dW7FzwoFTuhdpZl5+BC9hfrgkR6t2DI9GmBgPr7qbwRcjkffirwLqsK02?= =?us-ascii?Q?NJ3v9Wwpxw=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: a5a8239d-75da-4005-e4e9-08de5864a7e0 X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB6486.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 20:44:07.1485 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: s5bIZ3UwQTeShk3O1acIcn66p5kkwcb3C1V+yFL1ZjDDW5vm74qWFOkpkuwPO0oZb+Sih1gYu02/TWV5QEzVXg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6809 Content-Type: text/plain; charset="utf-8" Add foundational types for GPU memory management. These types are used throughout the nova memory management subsystem for page table operations, address translation, and memory allocation. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/mm/mod.rs | 147 ++++++++++++++++++++++++++++++++ 1 file changed, 147 insertions(+) diff --git a/drivers/gpu/nova-core/mm/mod.rs b/drivers/gpu/nova-core/mm/mod= .rs index 7a5dd4220c67..b57016d453ce 100644 --- a/drivers/gpu/nova-core/mm/mod.rs +++ b/drivers/gpu/nova-core/mm/mod.rs @@ -2,4 +2,151 @@ =20 //! Memory management subsystems for nova-core. =20 +#![expect(dead_code)] + pub(crate) mod pramin; + +use kernel::sizes::SZ_4K; + +/// Page size in bytes (4 KiB). +pub(crate) const PAGE_SIZE: usize =3D SZ_4K; + +bitfield! { + pub(crate) struct VramAddress(u64), "Physical VRAM address in GPU vide= o memory" { + 11:0 offset as u64, "Offset within 4KB page"; + 63:12 frame_number as u64 =3D> Pfn, "Physical frame number"; + } +} + +impl VramAddress { + /// Create a new VRAM address from a raw value. + pub(crate) const fn new(addr: u64) -> Self { + Self(addr) + } + + /// Get the raw address value as `usize` (useful for MMIO offsets). + pub(crate) const fn raw(&self) -> usize { + self.0 as usize + } + + /// Get the raw address value as `u64`. + pub(crate) const fn raw_u64(&self) -> u64 { + self.0 + } +} + +impl From for VramAddress { + fn from(pfn: Pfn) -> Self { + Self::default().set_frame_number(pfn) + } +} + +bitfield! { + pub(crate) struct VirtualAddress(u64), "Virtual address in GPU address= space" { + 11:0 offset as u64, "Offset within 4KB page"; + 20:12 l4_index as u64, "Level 4 index (PTE)"; + 29:21 l3_index as u64, "Level 3 index (Dual PDE)"; + 38:30 l2_index as u64, "Level 2 index"; + 47:39 l1_index as u64, "Level 1 index"; + 56:48 l0_index as u64, "Level 0 index (PDB)"; + 63:12 frame_number as u64 =3D> Vfn, "Virtual frame number"; + } +} + +impl VirtualAddress { + /// Create a new virtual address from a raw value. + #[expect(dead_code)] + pub(crate) const fn new(addr: u64) -> Self { + Self(addr) + } + + /// Get the page table index for a given level. + pub(crate) fn level_index(&self, level: u64) -> u64 { + match level { + 0 =3D> self.l0_index(), + 1 =3D> self.l1_index(), + 2 =3D> self.l2_index(), + 3 =3D> self.l3_index(), + 4 =3D> self.l4_index(), + _ =3D> 0, + } + } +} + +impl From for VirtualAddress { + fn from(vfn: Vfn) -> Self { + Self::default().set_frame_number(vfn) + } +} + +/// Physical Frame Number. +/// +/// Represents a physical page in VRAM. +#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)] +pub(crate) struct Pfn(u64); + +impl Pfn { + /// Create a new PFN from a frame number. + pub(crate) const fn new(frame_number: u64) -> Self { + Self(frame_number) + } + + /// Get the raw frame number. + pub(crate) const fn raw(self) -> u64 { + self.0 + } +} + +impl From for Pfn { + fn from(addr: VramAddress) -> Self { + addr.frame_number() + } +} + +impl From for Pfn { + fn from(val: u64) -> Self { + Self(val) + } +} + +impl From for u64 { + fn from(pfn: Pfn) -> Self { + pfn.0 + } +} + +/// Virtual Frame Number. +/// +/// Represents a virtual page in GPU address space. +#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)] +pub(crate) struct Vfn(u64); + +impl Vfn { + /// Create a new VFN from a frame number. + pub(crate) const fn new(frame_number: u64) -> Self { + Self(frame_number) + } + + /// Get the raw frame number. + pub(crate) const fn raw(self) -> u64 { + self.0 + } +} + +impl From for Vfn { + fn from(addr: VirtualAddress) -> Self { + addr.frame_number() + } +} + +impl From for Vfn { + fn from(val: u64) -> Self { + Self(val) + } +} + +impl From for u64 { + fn from(vfn: Vfn) -> Self { + vfn.0 + } +} --=20 2.34.1 From nobody Sun Feb 8 09:32:51 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012052.outbound.protection.outlook.com [52.101.43.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BBFBB421EEC; Tue, 20 Jan 2026 20:44:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.43.52 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941864; cv=fail; b=ZzbvFYdqirJjD2dK5f+o7N6dHRMj6V9slZ+8mi9Mr4CPkb03x1uv6qtCn8CMRTq5NFBPxsIuxwrdtX/WratrL8BVUXFUg41l/lsVD8onOx+RNXLp08Xn6V7YColaQmq17FF8mXTdWigNKos2W9Dk9GXS+pAvd0bbEHfIS5qISwI= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941864; c=relaxed/simple; bh=MVaxoRj7lfLSBm4ITDE8nXNiKSVswdvvS/vb8ikXaEQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=LpjIjwyxloUF5sr1gUKMu+KH2s+lgMdv+TvQUfl5RdZkjFMeJQo5GUsUT6m4/VBqLMAZcUFlUF6mVXeUAYmY3x9hK6TH+aDy8RvKrWeQ+5vqN0iH8H7WzeRVIoXpRfLzHDYkngh4qaGAxWSGUj0r4QwWqkL9gcb+HGWRpTVshUU= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=WPhJKa8k; arc=fail smtp.client-ip=52.101.43.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="WPhJKa8k" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=gJmQ8dZq+FJYzFs6OAU2bht66jwnc/AuoFc3JpM1PuDpstaHRV0kwEONPxyGdFnftAB2LteFjguiDGNicC1hEnW+beCmrPHjXQSLAW8wVGduenqVZlR4LgmY7qsdL+FVCh9u4mh0jAQ47PBr408Yf1s9FF28sLLzdZZr8qf61jJGfcgTjYUOlYZKCl/iyKVo8eUGqaEuqEZs+tRr0QDgBs7IHDHqhVpFa/P015IJvv8llQro1z2evmm7xBmwdojw9bm0ZP/NepAcjwwj8nkxFHyjkBupG0AeOWQrnhL4VNRVcDG10Pyef36R3z+fqHxKoAc65+4Ni/EKe0J5QsY2KA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=/mu84Kffu6HOuxI02ZvFZKS7xhqFhFvmzCJ5Re8VY40=; b=ObSnWrZO2uC9STMHrj4pAnT1u75gKXnOxJVHfsF2elFdr9plYnBjpkW3wcXE6ZCS7Y4NrxSBk1+SWCSgxjmeJ68JRlMAf+YX/lbLr6dLW432ThLTGMhATsLBOdgzuYIIG0uuaBsUbYv/xwEQtH2FppG2fSZY8MTFLp5N5OynweGwL2Ph1eVFDKmnPrUpU2rY6SYrWEdbS30nB3qnU6X55i+AdlRircdqTnQB895xCHDrt20uANabMs/iWOI2AZbchM1WWRIJKPkgXz0cT2QumErpuY/BiXkxfN+nk/I3pSZv/hMOqTigLkof4vbrg3eP5tagBeHoOQdzRqPOhmXaig== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/mu84Kffu6HOuxI02ZvFZKS7xhqFhFvmzCJ5Re8VY40=; b=WPhJKa8krL5FI37DqOipwj7ym1grqLwAGcGj+A3ZrCe1oCE7StaA3R1SasOzqIAZlV7rZQYXZ1fmkLRel4afWfXfPkgglfiOCPf83MGk3bUI0HCHG53HxDNH188qbkg6KNn7ZeapKTYpNaG35Ds7feFECs+QrwTlM8irOyWBIMM5lSrfx/9YWDMdbz+6M5nj3hdv0O94hLGT1Wr9nJpa1cvOIR2mH1EHGhA9NfG8WHZ0aaa9U4/6pnLugR8nKNlUlDZ5wmnfgkREICOGEbsDm3MFiJv7XI0+pZIPRqN0sO0D5ystao7xd4mn0mYdc3hpy9B2p7LzoATEW7/KZf3+1g== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by PH7PR12MB6809.namprd12.prod.outlook.com (2603:10b6:510:1af::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.12; Tue, 20 Jan 2026 20:44:08 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9542.008; Tue, 20 Jan 2026 20:44:08 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jonathan Corbet , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Huang Rui , Matthew Auld , Matthew Brost , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Helge Deller , Danilo Krummrich , Alice Ryhl , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Alexey Ivanov , Balbir Singh , Philipp Stanner , Elle Rhumsaa , Daniel Almeida , joel@joelfernandes.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, linux-doc@vger.kernel.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-fbdev@vger.kernel.org, Joel Fernandes Subject: [PATCH RFC v6 10/26] nova-core: mm: Add common types for all page table formats Date: Tue, 20 Jan 2026 15:42:47 -0500 Message-Id: <20260120204303.3229303-11-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120204303.3229303-1-joelagnelf@nvidia.com> References: <20260120204303.3229303-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MN0P221CA0012.NAMP221.PROD.OUTLOOK.COM (2603:10b6:208:52a::22) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|PH7PR12MB6809:EE_ X-MS-Office365-Filtering-Correlation-Id: a7527e2d-8bd6-4ec0-d425-08de5864a8c9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|7416014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?0Uo+2mWh1VUNY+XQHfNIG9JVC1Req3lCYzcfzbQC12/XPFNt9Oe5xbskvrvh?= =?us-ascii?Q?Fo4/ZFJJ4lM6uXocq3SgfbQT8ocaf3RmAFoZy6fiGke0ihpNA+jz5svwOLDv?= =?us-ascii?Q?AL3+3TY5O1jAZBQYGglLcQX0KOLbY5rEfLqGwzVbRbcV5kac/lBwb1EyQC9V?= =?us-ascii?Q?SLR1UQYSyL1aqMbz0SrMvG4Ar4UpA4GXmsuPDVUxWuar9jqK/srYdAu00fR5?= =?us-ascii?Q?SeL+YaTHsCCn0kbgBt8H7m6zWN+h0J3LnSAB2hVXiM/ubiJmMGXP8Xm+ndyQ?= =?us-ascii?Q?jY4p/Lf33Cj7Q7ST4LDU5qcpIeVKCLVM4s/oQWbJZBNpybJx1AUP6OaonYpD?= =?us-ascii?Q?PoGnny1Yj67Le+L8cSohFGLgKuW+gx/ISnJWjYH4gEBP0uX+jIX7B7Pa+3gV?= =?us-ascii?Q?gBEDmBDBziSzB5Oz4hjifbws9A8GVMwhXjsfQ++bCgQXB9x1VXc5bxyJgFnr?= =?us-ascii?Q?xrt2fYUN/1lDZZodAQleE2B5RbDlf3S1L89Sl9ktpHnE47sAVrgoQBz0QKGQ?= =?us-ascii?Q?yXv/sRhXvHyKLDEvjlAyC82gPASKSq5sYWjxXx1AE8jcb6j5GeSLLbYGVPLp?= =?us-ascii?Q?bKGihtp6z+rEh4Fd6B6hwclmyNxX4AY+IZYaVv3IoZSdKav52mN6aADJlku2?= =?us-ascii?Q?pGaYZOiBMI+KuY9BaS+8hVyiY9vWkxFPAkO6ptNbqf1JgdX5l4Uob5XZXfpM?= =?us-ascii?Q?dCb0vin61jO0s6nPkk3FoBXYIKy6qej/GJxaz/6fU2040qeecEQd1L3qKeiP?= =?us-ascii?Q?q7KykpYz9JULgUx2yU2/FYylahU9O38Xq1BDVPanYnrsp6zU0aHbYDauyZEx?= =?us-ascii?Q?UgX6xbCV7wmMXyJoicnQpJraQxL2IOEqC0iyMXZPKqihz36XqbclO+WJN7Td?= =?us-ascii?Q?LOFBRlWWedGrlc+BhDerWNS72X6692SS99rvzEicqKLUwmE8DywNPsGL49ZA?= =?us-ascii?Q?MVW1cYlD16cupKGm1iPm9Ol3QCEfMYuqpWRLHbHAaMfVIuZ5L6/Y8QhbCc7l?= =?us-ascii?Q?IxAxg7DpU0Vneg86CZ5K9bIKeFnNFDmygs5IS6VsbpiArFKrSjq4Ft9se1GE?= =?us-ascii?Q?IJ4m7G719Jmj+HV+jXj3L2ErY4596Za4cJn17qQGYMTWyIvKGsDtzpkK0LrC?= =?us-ascii?Q?gaqJ0Ow+/XqmdpZc1aHD8iQNR2Rx2ax9o17S7xdTmR07OXOypSbmr4j1ox72?= =?us-ascii?Q?oN1NZFXrU9IfRnhXVlQ2YS6q4LMANqaGUQyXgd6+W4t0dHadNRYeuGHPoaxm?= =?us-ascii?Q?rnbXz2TXdD+RVecuPwKv/Op7HSNAe6H6m9LdjBU1yvGIB0yLPVlRjF8GBfVE?= =?us-ascii?Q?1FjEIzOQ9n5MO/eX5J07MdyrBs7sCMOXXA5DUaa5nCICq471Cg0Fyt+COGzp?= =?us-ascii?Q?J6ELRcioLhZ/QMl4O7LaeLcLoubUWeuwk7tbye2WfduydoVmac8MyeI+WBx1?= =?us-ascii?Q?/ydaSJwWlYSAbBv9B82oZ/7POTA595RmJNboWbJtpkPvmlMQpcREVJEZwBXi?= =?us-ascii?Q?WRnuR7COjE6e34bs3GrqJ3/n1tk4AXNG8Hthv08G2rbg2FKuVLFnOVkFnUly?= =?us-ascii?Q?CNUpx04tOHpjh+eoV04=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR12MB6486.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(376014)(7416014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?AkQ3V0f097tqZyQ0T1/0y5M3JGnM5UFY3bdV1WETiuz8JCyFYcrOZHprZpxG?= =?us-ascii?Q?Fqgo1sDLsXLf5ewFYe+yd0mo2QV176HEqZbm2JhLwbSppq4rih2OXmHPOqFt?= =?us-ascii?Q?DerJJdE3oQbJn+eGZfgdpb20A81226vkcvxoB11FSEh4IgaWnQGrWYbh5Dmn?= =?us-ascii?Q?WhF13acSiobai2JgOOJVdacfCtDgPWUQ3Dcwe4DD5tLTmsq43lbyD8BxxgbN?= =?us-ascii?Q?9XS+xFyHB3xnYBYXbp4Oyf5ksOniBx5px6IAYBh8AWRqYdUSr5FS/x5hswau?= =?us-ascii?Q?LTcKix5tNOlpezoC8K2SpGDG5wxpDsCgxK0f61m8FOr+rfPnAowpToP6m9mO?= =?us-ascii?Q?Dqbb1aRkdQ5kr3i/Tce2UH3dlUtEZFOVnTArABqiXtVHyVqLfY19xhtDSs2P?= =?us-ascii?Q?biaNuHH7IgvSR1eoC7gDgjkrPtL6qcersJKco9A1qt/PzqvQNoreGGr+YPyT?= =?us-ascii?Q?1P3lfvlh9gQHt7eRPnpmaZfJB3Jb7Piuwbw4UywYbzoWcLZbeLCSPA6L+mlc?= =?us-ascii?Q?bQUh2cmZ6qMpIndNIjFODztQPf7L8JKyM5zXR6BKNh+Q0GgDR4/oQcLW/8r3?= =?us-ascii?Q?65+kcSJ5KmkMxORrxcxXlIJjASw3kFB3hMnqJwqNY0CbNR/D2P4e0VMFWG5D?= =?us-ascii?Q?eX7pkAlml86Q2juFm665dnS3okbVj3cI34pxE7cLDgKaqQdBN+whoxAkJAIL?= =?us-ascii?Q?6irDRXXj8jPwrkkUCVwFJW99JMHhvfc4+Rc5OhWfG5xophJn7+aUKJx+b6Yn?= =?us-ascii?Q?KbBSLOOExJqDVOCXlDkZeSywpvy6w9vVUYyh2Kru2f07RwSJJpqp79sIRkng?= =?us-ascii?Q?XImabem+LC6P6B595liPzPTeTy5+KZND+VRzhFx+npW5zgOybNrn56rxGHq/?= =?us-ascii?Q?wnWx3cRzS9YtduqRtyydqrLFcz2elc8Ue7wZSva2eUDSp1uOiIWe3fZi7ibL?= =?us-ascii?Q?SzvzBFVoBM5bGLOH0JNu2JHbNqMxvQkA1zktMJTwcAJfGDjmdWBxPbxDxd20?= =?us-ascii?Q?SeAveDgqg4S/+I7ZylyrFOzaOk2NAhNUAvHjTCynhAA8tU6ZhrYDshorYi1W?= =?us-ascii?Q?ro7FKgQMnFFkLoHxgXLkBXZKHwpxuIfoZN9gSAA5GRdMLHuSE/1iT9J4xXd6?= =?us-ascii?Q?pwOWJi+TMLHTfQ/JtvXCrmYA+SRp00vb/J5YOu9RBx+7QeLP52R1VIV+QOHq?= =?us-ascii?Q?gMqXzN6g4SnLz0vlJovrCnDkV/hUJni9E4XvPVuI8OSpZxI7LI/ZIgO4v1tq?= =?us-ascii?Q?RIYHjcA966Cns+ePQdbZE06U3+EZ4W8tSMKx1NdOn9tJH1O9n2YaWlV97f7u?= =?us-ascii?Q?AlsXrUZz5Y+iCFPm58NSBNsY3+vk3t1KfqwycRu68hnaV5ditzyaopS/YxyW?= =?us-ascii?Q?Py0d9pcE+VICkSRXIc1lzZmfRU0DIKioIc3DLt1I4iO8T7PciO7KuAvDo6R5?= =?us-ascii?Q?cBJaMdJJQN9qOd54+w49/qMy1YTN/hItxT2cRne0GXgwLwhYvaauV7xI9FZB?= =?us-ascii?Q?rhiyj5DO2UVREC2QQ8pxmkNH1y3NdbwA3zVZ4RIAm1DoKTM8Y4e0hFL/gdWU?= =?us-ascii?Q?QhmiXh5TsVhhLBdr8BbHED64EK387KzTsBEUfVlOZ1o4AqV5+8RadEiXoHi/?= =?us-ascii?Q?LoS9a3NIPnQU8jc2/pKpCOuN7BOeyfcPWe43DskTlriBc/jd8DPuo1otFx4W?= =?us-ascii?Q?mjwwIHFc5l+QAhK5YYB5O8l1T8kFQjxP0Odfciu4hELkjiw6HtQ53b7dr6Gq?= =?us-ascii?Q?FzQ7P0CqHw=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: a7527e2d-8bd6-4ec0-d425-08de5864a8c9 X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB6486.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 20:44:08.6721 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: yR/9uL8NhI9y5WABCy+vrJGKE4sq0tp02jzT6wvYpiyMNOhaEdF9mvSMzY7Vvd9ukBJrX1d9Z07ntiGqGxMl4g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6809 Content-Type: text/plain; charset="utf-8" Add common page table types shared between MMU v2 and v3. These types are hardware-agnostic and used by both MMU versions. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/mm/mod.rs | 1 + drivers/gpu/nova-core/mm/pagetable/mod.rs | 168 ++++++++++++++++++++++ 2 files changed, 169 insertions(+) create mode 100644 drivers/gpu/nova-core/mm/pagetable/mod.rs diff --git a/drivers/gpu/nova-core/mm/mod.rs b/drivers/gpu/nova-core/mm/mod= .rs index b57016d453ce..6015fc8753bc 100644 --- a/drivers/gpu/nova-core/mm/mod.rs +++ b/drivers/gpu/nova-core/mm/mod.rs @@ -4,6 +4,7 @@ =20 #![expect(dead_code)] =20 +pub(crate) mod pagetable; pub(crate) mod pramin; =20 use kernel::sizes::SZ_4K; diff --git a/drivers/gpu/nova-core/mm/pagetable/mod.rs b/drivers/gpu/nova-c= ore/mm/pagetable/mod.rs new file mode 100644 index 000000000000..bb3a37cc6ca0 --- /dev/null +++ b/drivers/gpu/nova-core/mm/pagetable/mod.rs @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Common page table types shared between MMU v2 and v3. +//! +//! This module provides foundational types used by both MMU versions: +//! - Page table level hierarchy +//! - Memory aperture types for PDEs and PTEs + +#![expect(dead_code)] + +use crate::gpu::Architecture; + +/// MMU version enumeration. +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub(crate) enum MmuVersion { + /// MMU v2 for Turing/Ampere/Ada. + V2, + /// MMU v3 for Hopper and later. + V3, +} + +impl From for MmuVersion { + fn from(arch: Architecture) -> Self { + match arch { + Architecture::Turing | Architecture::Ampere | Architecture::Ad= a =3D> Self::V2, + // In the future, uncomment: + // _ =3D> Self::V3, + } + } +} + +/// Page Table Level hierarchy for MMU v2/v3. +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub(crate) enum PageTableLevel { + /// Level 0 - Page Directory Base (root). + Pdb, + /// Level 1 - Intermediate page directory. + L1, + /// Level 2 - Intermediate page directory. + L2, + /// Level 3 - Dual PDE level (Big and Small Page Tables, 128-bit entri= es). + L3, + /// Level 4 - Page Table Entries, pointing directly to physical pages. + L4, +} + +impl PageTableLevel { + /// Get the entry size in bytes for this level. + pub(crate) const fn entry_size(&self) -> usize { + match self { + Self::L3 =3D> 16, // 128-bit dual PDE + _ =3D> 8, // 64-bit PDE/PTE + } + } + + /// Number of entries per page table (512 for 4KB pages). + pub(crate) const ENTRIES_PER_TABLE: usize =3D 512; + + /// Get the next level in the hierarchy. + pub(crate) const fn next(&self) -> Option { + match self { + Self::Pdb =3D> Some(Self::L1), + Self::L1 =3D> Some(Self::L2), + Self::L2 =3D> Some(Self::L3), + Self::L3 =3D> Some(Self::L4), + Self::L4 =3D> None, + } + } + + /// Check if this is the PTE level. + pub(crate) const fn is_pte_level(&self) -> bool { + matches!(self, Self::L4) + } + + /// Check if this level uses dual PDE (128-bit entries). + pub(crate) const fn is_dual_pde_level(&self) -> bool { + matches!(self, Self::L3) + } + + /// Get all PDE levels (excluding PTE level) for walking. + pub(crate) const fn pde_levels() -> [PageTableLevel; 4] { + [Self::Pdb, Self::L1, Self::L2, Self::L3] + } + + /// Get the level as a numeric index (0-4). + pub(crate) const fn as_index(&self) -> u64 { + match self { + Self::Pdb =3D> 0, + Self::L1 =3D> 1, + Self::L2 =3D> 2, + Self::L3 =3D> 3, + Self::L4 =3D> 4, + } + } +} + +/// Memory aperture for Page Table Entries (`PTE`s). +/// +/// Determines which memory region the `PTE` points to. +#[repr(u8)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)] +pub(crate) enum AperturePte { + /// Local video memory (VRAM). + #[default] + VideoMemory =3D 0, + /// Peer GPU's video memory. + PeerMemory =3D 1, + /// System memory with cache coherence. + SystemCoherent =3D 2, + /// System memory without cache coherence. + SystemNonCoherent =3D 3, +} + +// TODO[FPRI]: Replace with `#[derive(FromPrimitive)]` when available. +impl From for AperturePte { + fn from(val: u8) -> Self { + match val { + 0 =3D> Self::VideoMemory, + 1 =3D> Self::PeerMemory, + 2 =3D> Self::SystemCoherent, + 3 =3D> Self::SystemNonCoherent, + _ =3D> Self::VideoMemory, + } + } +} + +// TODO[FPRI]: Replace with `#[derive(ToPrimitive)]` when available. +impl From for u8 { + fn from(val: AperturePte) -> Self { + val as u8 + } +} + +/// Memory aperture for Page Directory Entries (`PDE`s). +/// +/// Note: For `PDE`s, `Invalid` (0) means the entry is not valid. +#[repr(u8)] +#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)] +pub(crate) enum AperturePde { + /// Invalid/unused entry. + #[default] + Invalid =3D 0, + /// Page table is in video memory. + VideoMemory =3D 1, + /// Page table is in system memory with coherence. + SystemCoherent =3D 2, + /// Page table is in system memory without coherence. + SystemNonCoherent =3D 3, +} + +// TODO[FPRI]: Replace with `#[derive(FromPrimitive)]` when available. +impl From for AperturePde { + fn from(val: u8) -> Self { + match val { + 1 =3D> Self::VideoMemory, + 2 =3D> Self::SystemCoherent, + 3 =3D> Self::SystemNonCoherent, + _ =3D> Self::Invalid, + } + } +} + +// TODO[FPRI]: Replace with `#[derive(ToPrimitive)]` when available. +impl From for u8 { + fn from(val: AperturePde) -> Self { + val as u8 + } +} --=20 2.34.1 From nobody Sun Feb 8 09:32:51 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013036.outbound.protection.outlook.com [40.93.201.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09578423172; Tue, 20 Jan 2026 20:44:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.201.36 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941865; cv=fail; b=MCB7/CuzWxiHV5XtJr8ItWYpLVHbK1azJttTqhkfYTfNiCATRUSb+qcDVpXcWzsbwnefxlbNChN42nCf0C7jF8y4LheUdjAhgDFEWYPb3gPPt3qjkicZOGTrS/vZp63otAglI0NdhF0moyakjvP7FMDWcR5EXd+kbCvWHilWsf4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941865; c=relaxed/simple; bh=ALh77y1uoUAkKsne/KX1ATJCtLzbmuoGI1OYPkJBcNw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=d79DedSqhY9nFrGCO1/FR4tNuC+vDcKJqdHYDZlNsvxL9U6KBjDZKvUQOKKswWkuRL/c7J6jX6i8fQ/9+isbmeo89Bs0IMq4pR0Fd7ap85DyLGthVI1gD5qfd/6oWDxZaA/dWXKcIPNhXwCwNxlnT/0Bovi/IWV8IVjBaABNO6s= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=WgZ/dzxJ; arc=fail smtp.client-ip=40.93.201.36 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="WgZ/dzxJ" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=bTihYCuNo7fsJesLt8FKebg15Tnyv6N0C/OvRMV0ApHPxd/rGZPQQlepvgFm8XgK1EuU/UlWev1X8ClpG3ERHkoVj7W+rBNFBEP8SwF7KxJjQse/yXk2ITc0i0I57I3YgBmfPR2F+tpEFzNiRkz7PHhASH1PO1/D2H1BkOMxfQuJhJz0uTHJPgT9DKj1zgCFaJp/x2Q3zZs6DpmtmmTKHx4ChGFrKQvyjV32K5/tfaTy9kPiq+6h0GJ5+PBW4e5yJ40LniE687vUjhkntpAR9ONS84GyXdP3YzYbnnKC7aaDFIOygBwEjGIrT2iX5F+zABXJGszUtotxdbx2EclbPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=/TcWxKjmeXwnq3UjSIdND9ieeM0i00wCMATYd6Xll/Y=; b=cWxGgoYKVRKF58DiCvHy1QseYHXhmjs0DyChYT39Q0r3yl5H8SYDoelIqepJdjJa4p6YODwgUrmMp0XcMY+pN7zzYCLmvAlJD3Y3fDKYJZuj+kD+ob4v+moVgxeB4HrUlnB+U2e14iwiJpNGaN3KpmG2vcZ4/v7hkNUFQ0YxlsupIXmNbfEIm8jH6rKgD2CZ0EqHAeMPeyOY09BPKyuiag0YxltTi05HUNfjGiatURcfdg3tVkC8qIiZ71dPZTaV02hpLo0927Rx8pLLn49P1e3VPrZU3Gb+3KMl4Ya+EttuZsBZPvoq42hNKjBRD9cIXjzFMUzAC41v/xVna+gsmw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/TcWxKjmeXwnq3UjSIdND9ieeM0i00wCMATYd6Xll/Y=; b=WgZ/dzxJ5cYQvEea3FN1+q2LCn1IwlhcYNQTHxHjytWjoGx5QiSLExXPnLRagHhYRX7QFsnjqYmueNXjw3SLdMjpDUgDlojGAxjcthBnCRu47G4zfAW3u7JSj3cbrwRplE/lnc4oZuXskHGrHcD8rdY2XLvYYJi4LNIxN/24ESbAZjkmdgtl+cYa3HMRx1IOQRFpoLIqfIfNChOvEzWZ2RNoERkL9yIEtd/oyd+1LFY0UQo/MK0vBBCPB7aXAYDxQSMIkSIQLSlWJc5pnuDI3PzkGWOU7EqA3GN7xFCo4tb/RuRIU6Q1kJ0dWJTGV8m+/oRAjy0esUfiV3HRFCBlXg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by PH7PR12MB6809.namprd12.prod.outlook.com (2603:10b6:510:1af::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.12; Tue, 20 Jan 2026 20:44:10 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9542.008; Tue, 20 Jan 2026 20:44:10 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jonathan Corbet , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Huang Rui , Matthew Auld , Matthew Brost , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Helge Deller , Danilo Krummrich , Alice Ryhl , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Alexey Ivanov , Balbir Singh , Philipp Stanner , Elle Rhumsaa , Daniel Almeida , joel@joelfernandes.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, linux-doc@vger.kernel.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-fbdev@vger.kernel.org, Joel Fernandes Subject: [PATCH RFC v6 11/26] nova-core: mm: Add MMU v2 page table types Date: Tue, 20 Jan 2026 15:42:48 -0500 Message-Id: <20260120204303.3229303-12-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120204303.3229303-1-joelagnelf@nvidia.com> References: <20260120204303.3229303-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BLAPR03CA0058.namprd03.prod.outlook.com (2603:10b6:208:32d::33) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|PH7PR12MB6809:EE_ X-MS-Office365-Filtering-Correlation-Id: 8101165f-2d3b-4ec9-d03b-08de5864a9cd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|7416014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?2Cl5yEUB1onXzu8BwatCq5Fz98e/pPtxgOJCdsiEPFFHEpFbULPnZFSsxRM+?= =?us-ascii?Q?pdBI0otIE317AhfRsHbvzpsE5TRF658clbRERAztzsTYtqadKSoq/SInVTM+?= =?us-ascii?Q?Uzg8RvFYPxAOVqTdl786jMpnTOYGVCWF23NKf6gf7X1Vsd/F2bRFXHgA9Ut8?= =?us-ascii?Q?NVB1qvpf/KzWzjj4P8mUxlqX6g4oDKm/dFDGfWRYmA95yo/jJj1VouZn0Bts?= =?us-ascii?Q?Bw6KkMfRYAzZr5Ewn0juL8qDdf2AhTxVTKq/m5+St543fPMQEo7i969lvOSb?= =?us-ascii?Q?I334bLCCWBHKD/pr1Ay7bZJOATVZ5UC1WSn1F+KSoZauBBViWhMGClYg8VbM?= =?us-ascii?Q?wN+tgDybp0SHpQfjC80KTbR9c7LZ/PwnYjNKaTmMCffPzLdOtO5M5Kb1qMKX?= =?us-ascii?Q?jeYUfuay+oh+izqKN6eQe+lX53RjRjOCu3DSLuEBG1chDik5NZcVakdF9adr?= =?us-ascii?Q?I0SNdugcGqvreCgXHB5rw92C5IU/1gtbSkZCQUYBaUHu/5B+9ROXCcJ2nmYD?= =?us-ascii?Q?ALn7/0zoT8gbuer8rKUam/AeXmVI/miDipgc4BXANwcTLy8AAXaAsCrBaxOs?= =?us-ascii?Q?nF52NYW5nxWjS8kJwwx3gTRgcmn7N7voFqYiZqVqmvlnO7wG7ecCy2ccDlOY?= =?us-ascii?Q?cQhNe1PIBGA4ALjiyj1kbY2Jw0p43qnzICFYqw52lgY0NCl0F6HfTQYr4gC/?= =?us-ascii?Q?vZUicCxRclbv6G7BpAD0LwlyCtkhm2EEiQgiqyiBfaUBKNDZDjRY2KqIefJC?= =?us-ascii?Q?CXVjeKpbsspF4m4LVj0BaBFCdQ/0HouuyeYkU4BOu4J7qcZaLVMQ4pYy+bM7?= =?us-ascii?Q?hDLDmcENSQ/CQy8Y3qX4HxcGKdI04YhbblPpDESY1jpGJcffZjXbaVErTpkQ?= =?us-ascii?Q?U1zLmEB4KZRN4wCUCMDePZXd59J1tGKd1bTUmGipDIJgX0DaCiWgv7UopCbi?= =?us-ascii?Q?maso0IQCziCorK/5TWhCpS80CWq739X7hsktqSFzxjRQ7puZ7GydWQvjq0Uk?= =?us-ascii?Q?VdsqP8/8Cpqhu54O3m/azkZH0zGrwvZX6zhrd7/IuPn/FNHftD4uzM7BlwFH?= =?us-ascii?Q?OpVVAavDtGhoIspW3lE4FdIS3q/k833QrPcUxZA+x/FeD8vhe88z9OwmVa43?= =?us-ascii?Q?FYgvr0IIBRvEOLAxSELzyV13zeSdgkEyLLZbwuWM7iubjmnQfrZtlgxMFMUT?= =?us-ascii?Q?A45IFZRfk0tQ1ov1quVMCbgLuKdVO6Om0cTIEgCLM2GWSpbOryW2vLxuwXzq?= =?us-ascii?Q?2LcusAykVkwbZamnx7kkIi1GtJzgNkGqnkAMKUjp5n3qCm5sLJs3PF0oJQbA?= =?us-ascii?Q?ZCk+Zs5HwPLWQCMrcF8VZvVR4F//6qFSLQ/IMHlww3XcTrTnoFR0EK2v1Ca3?= =?us-ascii?Q?0H5VxrjsKXsnaQ1o4PvevPYXbsQgh2/jdQc1fNueMB28EK/GyEUJ3DoZqLqi?= =?us-ascii?Q?vxK4Ij1h0ZEb1PoF2xRLHrFXX+zX0SiYg1ht0jxegOGGurEqhQT2Sd2rz1ov?= =?us-ascii?Q?nhVfZow2C1I7IPNrNlgakk9tVln1GgMCfoZB1Ez9EuqGw0xBZcO8xi18Sk+2?= =?us-ascii?Q?zZeOHs9IYR4sr4vFlY0=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR12MB6486.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(376014)(7416014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?UjLma0wFQ+3e8euVlQFSsoy1hmrb34zdT2VBhOHvpgG06lnoocy0AdrM7dhd?= =?us-ascii?Q?v/25CoUqPlVHOtQv7mZx+ZYv38vrwxwAHfQw/lbNiPV5VmrekaelfJX90NNs?= =?us-ascii?Q?B7t3B+wZPTsDyLLeU56peoLQ0UMQm8gE0K+AzVdUZkQ339NgPNBlwZhQrrhx?= =?us-ascii?Q?tgw3SMEWT0wMVDLf9YdopBODlI4cIhpscXn3D4Z/JD/MDsJt+F50aLna92q4?= =?us-ascii?Q?xgJ4xS+G1D8w/1Au+CIPB9xfL4uOszcOd78STWAR9fCV9+JPBZ49yuVxfyiO?= =?us-ascii?Q?ph438+N9btLvLR+fc7RFIcsOEmgb1Oi0jzXGFlhuYDTtYHedYtFLaLLqLwkn?= =?us-ascii?Q?K2fWQjjNGfDoHb/dqyO+bkJuC4Ix6x0jk6GeRETqkeX7NfyiRaqwu3lTFiOc?= =?us-ascii?Q?98ggulIryajDwjWGAL47nL5M3Z+s7ERzKJlopDPtrwiC4FblppaByvv02C7q?= =?us-ascii?Q?QkX5FFH+J7xzI5e1UPmjttS5PJraxAwurtGYStPUPauEqVPHiRDDDHdecjKB?= =?us-ascii?Q?UM0RVji9mTF073MuH2uGfo39xqcvZyI0uPnrRy7jfVtbglEeyPSU82vRx0rq?= =?us-ascii?Q?+7PBQrPI6IbpiZGmmVTSnLPKr6Q0QPQAlyJpw5BLxS19I4x95Q5ta94mW/2c?= =?us-ascii?Q?pHYGP4tS9u0US90aSOJnaE2j+2PHyLxwX+XAjsy7CtA55rZuHJoRtEuW3+ia?= =?us-ascii?Q?oa2dKHLAGgPTHCNkOcU5z+ByyqyKK/J07gJ9qrZTXenYcLgqVPkP2ta5gjhD?= =?us-ascii?Q?CJnNO96+xvdLo+Mo3IaotWv3a5dlq2dDNwKfNXJWiAV1x7y8Dil/oGr0HqBM?= =?us-ascii?Q?pkghWn+jFVGDGg1muYJNl5tSw32joJT+IUIJ00QDUOSS/6cIQEJQ4RcBRDLP?= =?us-ascii?Q?wZqvAY0b8y15jpVR8JhsyAsRrmBAC5fZjyYBXNdMLkuNMAujp4fesRBBafeb?= =?us-ascii?Q?V5iA0LuIHMquzXzdmJGm+tnnqZ2b5r14L7M3VRnGZVqoF43DPLCjkIm1Lqq0?= =?us-ascii?Q?wxiKzaHvxF5aVlDEsSse4le0yrPJerDN72dmeqv1Wuj67xIkI2j/aWHYrqQx?= =?us-ascii?Q?0ovWUQxkjz+Js5osp9bjcTDwkB+JBjCdKofbsuPMbvfNVUkTPK6i7F+MiLDm?= =?us-ascii?Q?URGYlxwJmhWEw/iRBY3zNnK+0GggCFYsD6phuxUsFZat1oYlnUANUJI6qJ4X?= =?us-ascii?Q?44W27oNL4I3/6Bmt2jJLby+6uZHzViCjIWz14dXM1jJ+R604PMdu0u9+wUwH?= =?us-ascii?Q?fVBq1bJgQP48lqZGFhfy7GJdcZzeVyCy4Jr3+DT4ZRrE+EYl6cvxV1GWe9QG?= =?us-ascii?Q?bSN/SKJt249kYQsZNk9ZprbXZdclrOb1Ly5Tll6eYG2TTjTZKsbmOJVS6480?= =?us-ascii?Q?z2t0riTMLyeivTUBHb54g8Jb4umbzuMEdLzigOoRWkT3X2TxLtn3JL+nyIct?= =?us-ascii?Q?pAS3zZsOH5iQrYaM/pgtA4fXgA2CDsahoHThQgQo7AqKMFE+QQmf6cmAVzkP?= =?us-ascii?Q?MxMF0oK03Hh4mxJgG8GgeKCkZKZBZ9L5so6yccypwaWpujYSJmfXbkye2PAk?= =?us-ascii?Q?J9z8DLWs62gFwXfKY6qIasd07H5zrOtEzrsRQSADPGLPdPU34EvB2jTddMpg?= =?us-ascii?Q?7BTX0YOXTrOS/Q9PMo4J91GskaeuM8cKczYO2M3ISVX1I/Zk0+uzQ2S9QdN0?= =?us-ascii?Q?9xdXFLkE6LcRdkhvxnlyR3mdQTs1Fz1f5DsSW202UrMWBR7yUcyEkdvQcm6o?= =?us-ascii?Q?7shA4QYmgw=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8101165f-2d3b-4ec9-d03b-08de5864a9cd X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB6486.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 20:44:10.3939 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: kp3Edxxwc1nb45Aovw0sjq+KGb5yGQMKv/VuYY3Y+k6Fp+rI+w1q4l68TICbV0LSUl7jbZ7lK8odIQtzmv+7fg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6809 Content-Type: text/plain; charset="utf-8" Add page table entry and directory structures for MMU version 2 used by Turing/Ampere/Ada GPUs. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/mm/pagetable/mod.rs | 1 + drivers/gpu/nova-core/mm/pagetable/ver2.rs | 184 +++++++++++++++++++++ 2 files changed, 185 insertions(+) create mode 100644 drivers/gpu/nova-core/mm/pagetable/ver2.rs diff --git a/drivers/gpu/nova-core/mm/pagetable/mod.rs b/drivers/gpu/nova-c= ore/mm/pagetable/mod.rs index bb3a37cc6ca0..787755e89a5b 100644 --- a/drivers/gpu/nova-core/mm/pagetable/mod.rs +++ b/drivers/gpu/nova-core/mm/pagetable/mod.rs @@ -7,6 +7,7 @@ //! - Memory aperture types for PDEs and PTEs =20 #![expect(dead_code)] +pub(crate) mod ver2; =20 use crate::gpu::Architecture; =20 diff --git a/drivers/gpu/nova-core/mm/pagetable/ver2.rs b/drivers/gpu/nova-= core/mm/pagetable/ver2.rs new file mode 100644 index 000000000000..d50c3e56d38e --- /dev/null +++ b/drivers/gpu/nova-core/mm/pagetable/ver2.rs @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! MMU v2 page table types for Turing and Ampere GPUs. +//! +//! This module defines MMU version 2 specific types (Turing, Ampere and A= da GPUs). +//! +//! Bit field layouts derived from the NVIDIA OpenRM documentation: +//! `open-gpu-kernel-modules/src/common/inc/swref/published/turing/tu102/d= ev_mmu.h` + +#![expect(dead_code)] + +use super::{ + AperturePde, + AperturePte, // +}; +use crate::mm::{ + Pfn, + VramAddress, // +}; + +// Page Table Entry (PTE) for MMU v2 - 64-bit entry at level 4. +bitfield! { + pub(crate) struct Pte(u64), "Page Table Entry for MMU v2" { + 0:0 valid as bool, "Entry is valid"; + 2:1 aperture as u8 =3D> AperturePte, "Memory apertu= re type"; + 3:3 volatile as bool, "Volatile (bypass L2 cache)"; + 4:4 encrypted as bool, "Encryption enabled (Confiden= tial Computing)"; + 5:5 privilege as bool, "Privileged access only"; + 6:6 read_only as bool, "Write protection"; + 7:7 atomic_disable as bool, "Atomic operations disabled"; + 53:8 frame_number_sys as u64 =3D> Pfn, "Frame number for sys= tem memory"; + 32:8 frame_number_vid as u64 =3D> Pfn, "Frame number for vid= eo memory"; + 35:33 peer_id as u8, "Peer GPU ID for peer memory (0= -7)"; + 53:36 comptagline as u32, "Compression tag line bits"; + 63:56 kind as u8, "Surface kind/format"; + } +} + +impl Pte { + /// Create a PTE from a `u64` value. + pub(crate) fn new(val: u64) -> Self { + Self(val) + } + + /// Create a valid PTE for video memory. + pub(crate) fn new_vram(pfn: Pfn, writable: bool) -> Self { + Self::default() + .set_valid(true) + .set_aperture(AperturePte::VideoMemory) + .set_frame_number_vid(pfn) + .set_read_only(!writable) + } + + /// Create an invalid PTE. + pub(crate) fn invalid() -> Self { + Self::default() + } + + /// Get the frame number based on aperture type. + pub(crate) fn frame_number(&self) -> Pfn { + match self.aperture() { + AperturePte::VideoMemory =3D> self.frame_number_vid(), + _ =3D> self.frame_number_sys(), + } + } + + /// Get the raw `u64` value. + pub(crate) fn raw_u64(&self) -> u64 { + self.0 + } +} + +// Page Directory Entry (PDE) for MMU v2 - 64-bit entry at levels 0-2. +bitfield! { + pub(crate) struct Pde(u64), "Page Directory Entry for MMU v2" { + 0:0 valid_inverted as bool, "Valid bit (inverted logic)"; + 2:1 aperture as u8 =3D> AperturePde, "Memory apertu= re type"; + 3:3 volatile as bool, "Volatile (bypass L2 cache)"; + 5:5 no_ats as bool, "Disable Address Translation = Services"; + 53:8 table_frame_sys as u64 =3D> Pfn, "Table frame number f= or system memory"; + 32:8 table_frame_vid as u64 =3D> Pfn, "Table frame number f= or video memory"; + 35:33 peer_id as u8, "Peer GPU ID (0-7)"; + } +} + +impl Pde { + /// Create a PDE from a `u64` value. + pub(crate) fn new(val: u64) -> Self { + Self(val) + } + + /// Create a valid PDE pointing to a page table in video memory. + pub(crate) fn new_vram(table_pfn: Pfn) -> Self { + Self::default() + .set_valid_inverted(false) // 0 =3D valid + .set_aperture(AperturePde::VideoMemory) + .set_table_frame_vid(table_pfn) + } + + /// Create an invalid PDE. + pub(crate) fn invalid() -> Self { + Self::default() + .set_valid_inverted(true) + .set_aperture(AperturePde::Invalid) + } + + /// Check if this PDE is valid. + pub(crate) fn is_valid(&self) -> bool { + !self.valid_inverted() && self.aperture() !=3D AperturePde::Invalid + } + + /// Get the table frame number based on aperture type. + pub(crate) fn table_frame(&self) -> Pfn { + match self.aperture() { + AperturePde::VideoMemory =3D> self.table_frame_vid(), + _ =3D> self.table_frame_sys(), + } + } + + /// Get the VRAM address of the page table. + pub(crate) fn table_vram_address(&self) -> VramAddress { + debug_assert!( + self.aperture() =3D=3D AperturePde::VideoMemory, + "table_vram_address called on non-VRAM PDE (aperture: {:?})", + self.aperture() + ); + VramAddress::from(self.table_frame_vid()) + } + + /// Get the raw `u64` value of the PDE. + pub(crate) fn raw_u64(&self) -> u64 { + self.0 + } +} + +/// Dual PDE at Level 3 - 128-bit entry of Large/Small Page Table pointers. +/// +/// The dual PDE supports both large (64KB) and small (4KB) page tables. +#[repr(C)] +#[derive(Debug, Clone, Copy, Default)] +pub(crate) struct DualPde { + /// Large/Big Page Table pointer (lower 64 bits). + pub big: Pde, + /// Small Page Table pointer (upper 64 bits). + pub small: Pde, +} + +impl DualPde { + /// Create a dual PDE from raw 128-bit value (two `u64`s). + pub(crate) fn new(big: u64, small: u64) -> Self { + Self { + big: Pde::new(big), + small: Pde::new(small), + } + } + + /// Create a dual PDE with only the small page table pointer set. + /// + /// Note: The big (LPT) portion is set to 0, not `Pde::invalid()`. + /// According to hardware documentation, clearing bit 0 of the 128-bit + /// entry makes the PDE behave as a "normal" PDE. Using `Pde::invalid(= )` + /// would set bit 0 (valid_inverted), which breaks page table walking. + pub(crate) fn new_small(table_pfn: Pfn) -> Self { + Self { + big: Pde::new(0), + small: Pde::new_vram(table_pfn), + } + } + + /// Check if the small page table pointer is valid. + pub(crate) fn has_small(&self) -> bool { + self.small.is_valid() + } + + /// Check if the big page table pointer is valid. + pub(crate) fn has_big(&self) -> bool { + self.big.is_valid() + } + + /// Get the small page table PFN. + pub(crate) fn small_pfn(&self) -> Pfn { + self.small.table_frame() + } +} --=20 2.34.1 From nobody Sun Feb 8 09:32:51 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012052.outbound.protection.outlook.com [52.101.43.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB87840FD98; Tue, 20 Jan 2026 20:44:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.43.52 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941867; cv=fail; b=g21XneAAp+F9ck0g1/0U2/Vh7fjieyHoCnYfY82u37po0B0/CUMBHFi69toTTCp06Z0G8EdOFjlQmL2lZ5tbU9Ew09X+eA2CaQNF59mIlKaj/P3S7qw3ntYWKgbTZ4jbTZEQr7+EjY/1EoiQwAIjfrs6vHwtBh3P4lBnyNtJy2o= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941867; c=relaxed/simple; bh=2byz0Dho8+WZGxEnR/tbj+OtPSu7O3fzbnpLORGFr68=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=HUPpNrRiJWCl+kEog73S6PtyAXHQ8Mg5au8eSmLzjzdmZo6hfjth9mg/lbNj4e8n3Hj/WMD0G0iCQ+TJBUvhy8eE1aimB2yCl1XvOCV03Bxl7o0bnj5xrLQJNHitOsjPzdTxlIB+1+880o66pSHBzepxNbUr26Rwdp06Sii9jrA= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=RdvGxp2Y; arc=fail smtp.client-ip=52.101.43.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="RdvGxp2Y" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=e7k8Gn4DviaqIUUG6IKuFOg541Z4pX+PLovZshoOwiMn4UNO9/1j5oPCyH3CGMKGHCqFEeHvW2ixw0JmtzzEQVWxCWk7y5p964+7LnobIh1NT+LmKSyi4vwhf0agqmoT8qxCSuFWX7M03ucBcEZoYMXuIBnR+99I30wN8TtbzzUS5U6nrWYj8WqJ3J3+T9DsXW3jGFpINhHQK4+mtZG9FcFvRN/N3FRft6fz31M81nz/Fy1240HMd1z6kjEacPb+94Irfg/97bPuWbhITe0UAg3U9/qNP8K/difZzZQh0zpbvA9Tn6bNjgVqnfKKuF3qjNuHESuKxlaFC2xggFfuMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=6yRVboplO90TzjcIjEANi6cuPnd6sJxAsHzQVkJvErI=; b=D7g8sI7kbNxzR4Fx7vQzt231BwTKIzyKLOkf8Ic6UdN2ny8SaWeFRvnM+vqrEk8EzX/uYWIJtKmmod9ZcvL4VOWSqSdJaTHsVKqEdETjjfNXEghG2vx3BGuir1Wnd6FJOsidZB9LloydYwCEVo/5ofbU1SslC5THqvbtk4t4BjU2QatLUjHTt6ZQzaCqQ11ISiKRkQ2Pm+J+nUoLNUY5J+g4MzHmmU9EAzhF3ZiCoopGjftHCVB0mgD2D2Aixzmps8aaCIItQ+CuyILHE9pMM7qzYqmB07UvqopqHIUB5/OheBY3lbpZXkVtQAgJnPB2C8jGUb/SafrLOKkIFWEtRQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6yRVboplO90TzjcIjEANi6cuPnd6sJxAsHzQVkJvErI=; b=RdvGxp2YWFW/H1iRdqEixgE8C20Zt3PUo1Tbq5itGEKSyuhudNFXzrRXETOc1vJLLxQrADKlNYdiVqbnQqfwhiZxFdFqTQl0rTqDfqA3hd+H9ohvxFrNIuMxARZx7LSol2fkNCmLBlW6Mw65q0v22cXtM3JZT7e8ihX/+Whhr6r63B2gM4lu14ZmgQedqVl4roD3dECVW2O/C4Qf2NkO7aRgwa8AIWWvIC5R2jBTMLeAw8YP3p6awIJ7Hex+ALbZ3Wb75rl2ysgvKALIM7AE+tSaU6Z3pFbaU7+l2hB/XDXRU206y5hPsvfxVw9cP0qB9yrqF/eewJjlVAbJh/VkDw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by PH7PR12MB6809.namprd12.prod.outlook.com (2603:10b6:510:1af::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.12; Tue, 20 Jan 2026 20:44:12 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9542.008; Tue, 20 Jan 2026 20:44:12 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jonathan Corbet , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Huang Rui , Matthew Auld , Matthew Brost , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Helge Deller , Danilo Krummrich , Alice Ryhl , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Alexey Ivanov , Balbir Singh , Philipp Stanner , Elle Rhumsaa , Daniel Almeida , joel@joelfernandes.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, linux-doc@vger.kernel.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-fbdev@vger.kernel.org, Joel Fernandes Subject: [PATCH RFC v6 12/26] nova-core: mm: Add MMU v3 page table types Date: Tue, 20 Jan 2026 15:42:49 -0500 Message-Id: <20260120204303.3229303-13-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120204303.3229303-1-joelagnelf@nvidia.com> References: <20260120204303.3229303-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MN0P221CA0013.NAMP221.PROD.OUTLOOK.COM (2603:10b6:208:52a::18) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|PH7PR12MB6809:EE_ X-MS-Office365-Filtering-Correlation-Id: d69d5491-326a-4df7-b63c-08de5864aab7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|7416014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?OSP6jTihiVoDJb5I3chf1ch4h1QBA1Z4H+711It8W1WzzVfr6LwARxV/ttVE?= =?us-ascii?Q?8ZTPEEGQZFJ8Njv8jCMyXKQdC5rcimZVEU9OCFMbHZurI0r7uehTEVwPrJvT?= =?us-ascii?Q?3lKcB8pQBtM21r/yE1pEUVsJI53mVjEFIAI/82m9tmk8PpU3w5O1j6cRGxPK?= =?us-ascii?Q?9+kvMcl65RdBv47eVz/Dt1aDXPnghw/cCw8ntDyPaf/GQEt4+ZTsM618LYNH?= =?us-ascii?Q?EpsAbzbH2yBhyzW2r7IoA/T5xOYgY67OsNOjxZtj3bdSce655nFq47OBo+So?= =?us-ascii?Q?XoWGw2qSGGHXR43P9Yra49aGIWyneCOZGNAaEQqFnCnBD42Dqo4wRNagk3W8?= =?us-ascii?Q?TvDuFRMF6oMbe0/QeK95KiEWVf5yJQTmyAMbGG8/BDgvou3MNBoD5VV1XTAE?= =?us-ascii?Q?jMsj4KC/HyU9/R3DUmm9XlhsHjZARUMhQKYmnb/3yCsiUKDo4fbQLmfJzTOH?= =?us-ascii?Q?zOLU/CbE5fRYGUZl7T+RMri4am/7ziGrgx9VJuYUGpWCgDEVB3sR0P3AvkRZ?= =?us-ascii?Q?ft5loyVYmYfiOkK+htEf3ypwEF1zKquJo7cNVyEcCvN9eaQaRyq1OIbaPQK0?= =?us-ascii?Q?0pur94QBjjKvqGt+Ag3CEjTJ0/PL0Iy9HG5dchlzole2Pq3Go2YzRZQ9AI93?= =?us-ascii?Q?YeensQmFg4rkRKU3aWHSITuogD9cpIhwCjn6bIe+LCCiiBri74VZqktN3V9i?= =?us-ascii?Q?PeQEIufA0ZDO58dV5qNbYsDzR4L54Nvcw+PlYLpReMndffit7lWVY8bqpPho?= =?us-ascii?Q?j+KmrGw/raUB1ZMxq/RkKI0NOlPXD/e1EdYxkQ0PImKUb8J7rH7hqW1pCbc2?= =?us-ascii?Q?4LyYolP+wWxgB4CdTJZd2kDqg37ZAhVqAEv5CL2p9oGbaIv0P3NrpxvMVVFf?= =?us-ascii?Q?S459qdlA2Oj++7hVFyJjBIo2ZrWUBi0mFGgt7PqjN27p5JSPwOvLA0IvW6a+?= =?us-ascii?Q?jAe/o7x+m7xQpPIM3T6F6fiQXmltcsptwnMYEdUYrc7JjLy2r9sFNYUQdsk4?= =?us-ascii?Q?PByyGmub6teDW3NqBPqXQNlwu6IYylCYWV634oOs84BvslSmb5N2y1kbt74N?= =?us-ascii?Q?AnGlW3sl7+Vc/NWi/yz8gDyOj2rSCP/ueiZBbCz27NkFMqrSaj9jJu6DEFZe?= =?us-ascii?Q?BHmzdfQ7RTJdp+m0UecIYvj+Fiv4wZTtFyOuq+nOd9dJn0ljQ7AFwkZGBCw2?= =?us-ascii?Q?ZCyYYRJs/PpgyK3hlQRraJXDT3cB0nO0Xrz+tZwk7vVFmdFSAkNAIz564gOz?= =?us-ascii?Q?a3/FFA1hfpTY2gWzzR7DSt8DvoZcmYNdPaxH4XwhMctDcgIZLACmaiNATdwy?= =?us-ascii?Q?fZ1rf+6O2YEtCysv9Re9N3j7DDcd0BI3qDAb0/SsqgTF0z0H5ql0FV4lQT7D?= =?us-ascii?Q?Zs2LiEfb4Yqw76UscM5iVPnC9XKNjZQ5vpSHxNWIFtfFDE2jXPilIFWI8hIp?= =?us-ascii?Q?QB2ERWvhpVWzoQQ42doES/K78+SDkMVbykDAUXeEuDQuKSm7K6GvQfkd1HPM?= =?us-ascii?Q?jhisYMlU75cR6C7or9yMWlC8XmeaykprKy7taDj3MzBtX+YDet3UgAj2bBua?= =?us-ascii?Q?yuTfP06ukH1dQSqgc+c=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR12MB6486.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(376014)(7416014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?wTnduWGBsLwt6lSTEfHoRAPVAu7N9aZ37t8QeblDEMAtHS8qsjAwCqk7mHih?= =?us-ascii?Q?bYsep0DQt+oVFbA77kJSBX4zpbmlVQ1PkKyecsGlLtNKwlX0fL+YxU/4RDcD?= =?us-ascii?Q?K1scFNsZjk8yL6zZYrPSJbF/W6J9dg+MvgyfVJJeAz38OHrb18oB7sIDSd8x?= =?us-ascii?Q?cemi3B7HI+KV33Rgno50UB3d4Usb1g0g56PpMpU8VaqD/DPbr0z6zY6XIgwG?= =?us-ascii?Q?vJC6OrEGMEk6bnYX9WMPCpTygBFBzuqpxzP3NsnC/vz1uYF/X5YdKvF2VaQV?= =?us-ascii?Q?/V/s/mcP6uTmVOwTjIlXKVCq/nX38IbK1bFZkbZhuq3HZ6w+VLCgvXMRK+ZX?= =?us-ascii?Q?LvRn+AWhsCF132LftyBkPKnA8iGp60kICHYf4NioFJmVuLHGvSMCY/DReRsL?= =?us-ascii?Q?XkDhdJxy8d97G/0/w6t6Hq3fucjeQsR20laikuT4LtB6bfuggAa/FmlSjY+a?= =?us-ascii?Q?89+gflvcQz4tLmkFM8sra6BvsjUUmXDK5BZqqAe+WxtQPww15uZ5TYKGcbHe?= =?us-ascii?Q?BZJw3tWWpLSSKpkx9QAxjrZmdoyhYF0opcde5gXNAmXBoohqPWxHCpK81oGb?= =?us-ascii?Q?KqvyujaUqBn7EXIFdInMHfBQdRMRsnQY4EP+OHsWnnrVQc3YN22+8QQaFea0?= =?us-ascii?Q?l3m8s+JuU+/z78ln3LWmwMdcVkxjVCDRf6s6vfgK2gwVwsI7eUx+Ndi6lqGS?= =?us-ascii?Q?6c7NESXTycUHL/lJDHmlz4PJS/Y2PsqaBiSHRHKVCeFcBravf/C8BJoM0Lxy?= =?us-ascii?Q?WP4XKMt8Ho7d+opvlFS+IsBB00xpbfEbTSS5C8+Fnc64TEV7ZLuHDYflg18/?= =?us-ascii?Q?hN3TegSNx91CMbBF2ScmVwzPhbKN42mJKFqPPgv7rkeBaRnWtpGzA6Ma0lqR?= =?us-ascii?Q?7WUiD+QR9DAl9hWD05MYffwMMyAyU2HzQ0AioC3GR5rHKYmzQG47Ndeol7sA?= =?us-ascii?Q?jdGf/y+suFA1r+xiRYJI+1dkI3F+TeNdWe9TblEFeGH0sc3muQJWuG7EE7Sj?= =?us-ascii?Q?5tkRsivyulryrYNTpFPJHN4Np971/8iNhkAlMrIWAbIDSTj2Tg2YT8egmw8h?= =?us-ascii?Q?5gA9RFUPEVAe3RZ4Eb8N5td3iGX6J6MAf+at0DU06RO5pKTGpUWQDXhJsHdz?= =?us-ascii?Q?Siy2TPDeS3yOlqo4+o7m/CIQ/jhKfOXPcMN8/lzccNN7S95r22OJi5xdJdTa?= =?us-ascii?Q?jtA34A9f76JTZ4riv/tWs5eRX+2tLg7XsnfgidHCm6zvuRj9kXcltgXfnxF6?= =?us-ascii?Q?fbbN7a5Li5TEpjdieuIxJgsmOtlTFMQKNkexY6/ZHowuXcqoypnQmigXjens?= =?us-ascii?Q?R7qMoCvkKLJV7iSb86IijcBgFD32hjfG/IDPaUci5k4bMifE61h1mlzkIZVW?= =?us-ascii?Q?3sV42eedfvUMFA1ga/Tf7ReQJvsWh9ye8firCU8EjjmB4T7jAtV7TifZXEK8?= =?us-ascii?Q?O9bc4xkklg/z0s3rXBg62984njT6wq7jcy90DhrcvgXpbsavpdkYo3IgbEC4?= =?us-ascii?Q?gxKfUkKp+OSTLOUIn8AsQDZgXtsYrv9RSS1KBld6MBwS1JOncl9+RAUNmI/b?= =?us-ascii?Q?1p3PEnD/gGkWHjvylLN45mogcwABi1XJ8a3zqBXt49uk3sDjG++YN+2Sm3d0?= =?us-ascii?Q?yZWKr/kY4pxXvbmKuxRZA/porirSGMpDjp1t1OgRkh7ZXCabZT25VIR4gXeL?= =?us-ascii?Q?lVBTglDTBHDmBKap/mJOtTHdr+hp+gX/duTadEOZ7QTh2/Okkvhy9E9Do2YL?= =?us-ascii?Q?Dq5zwzzDCg=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: d69d5491-326a-4df7-b63c-08de5864aab7 X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB6486.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 20:44:11.8968 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ClUQd2y/B7CMIAuujTIqCbgFc3jsbKb+1csBxvHOMYrPBmU3gbx8ZsWxSWx6nu2+pIHSiAm1Fvo6P8FSvvO00w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6809 Content-Type: text/plain; charset="utf-8" Add page table entry and directory structures for MMU version 3 used by Hopper and later GPUs. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/mm/pagetable/mod.rs | 1 + drivers/gpu/nova-core/mm/pagetable/ver3.rs | 286 +++++++++++++++++++++ 2 files changed, 287 insertions(+) create mode 100644 drivers/gpu/nova-core/mm/pagetable/ver3.rs diff --git a/drivers/gpu/nova-core/mm/pagetable/mod.rs b/drivers/gpu/nova-c= ore/mm/pagetable/mod.rs index 787755e89a5b..3b1324add844 100644 --- a/drivers/gpu/nova-core/mm/pagetable/mod.rs +++ b/drivers/gpu/nova-core/mm/pagetable/mod.rs @@ -8,6 +8,7 @@ =20 #![expect(dead_code)] pub(crate) mod ver2; +pub(crate) mod ver3; =20 use crate::gpu::Architecture; =20 diff --git a/drivers/gpu/nova-core/mm/pagetable/ver3.rs b/drivers/gpu/nova-= core/mm/pagetable/ver3.rs new file mode 100644 index 000000000000..6a5618fbb63d --- /dev/null +++ b/drivers/gpu/nova-core/mm/pagetable/ver3.rs @@ -0,0 +1,286 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! MMU v3 page table types for Hopper and later GPUs. +//! +//! This module defines MMU version 3 specific types (Hopper and later GPU= s). +//! +//! Key differences from MMU v2: +//! - Unified 40-bit address field for all apertures (v2 had separate sys/= vid fields). +//! - PCF (Page Classification Field) replaces separate privilege/RO/atomi= c/cache bits. +//! - KIND field is 4 bits (not 8). +//! - IS_PTE bit in PDE to support large pages directly. +//! - No COMPTAGLINE field (compression handled differently in v3). +//! - No separate ENCRYPTED bit. +//! +//! Bit field layouts derived from the NVIDIA OpenRM documentation: +//! `open-gpu-kernel-modules/src/common/inc/swref/published/hopper/gh100/d= ev_mmu.h` + +#![expect(dead_code)] + +use super::{ + AperturePde, + AperturePte, // +}; +use crate::mm::{ + Pfn, + VramAddress, // +}; +use kernel::prelude::*; + +// Page Classification Field (PCF) - 5 bits for PTEs in MMU v3. +bitfield! { + pub(crate) struct PtePcf(u8), "Page Classification Field for PTEs" { + 0:0 uncached as bool, "Bypass L2 cache (0=3Dcached, 1=3Dbyp= ass)"; + 1:1 acd as bool, "Access counting disabled (0=3Denable= d, 1=3Ddisabled)"; + 2:2 read_only as bool, "Read-only access (0=3Dread-write, 1= =3Dread-only)"; + 3:3 no_atomic as bool, "Atomics disabled (0=3Denabled, 1=3Dd= isabled)"; + 4:4 privileged as bool, "Privileged access only (0=3Dregular,= 1=3Dprivileged)"; + } +} + +impl PtePcf { + /// Create PCF for read-write mapping (cached, no atomics, regular mod= e). + pub(crate) fn rw() -> Self { + Self::default().set_no_atomic(true) + } + + /// Create PCF for read-only mapping (cached, no atomics, regular mode= ). + pub(crate) fn ro() -> Self { + Self::default().set_read_only(true).set_no_atomic(true) + } + + /// Get the raw `u8` value. + pub(crate) fn raw_u8(&self) -> u8 { + self.0 + } +} + +impl From for PtePcf { + fn from(val: u8) -> Self { + Self(val) + } +} + +// Page Classification Field (PCF) - 3 bits for PDEs in MMU v3. +// Controls Address Translation Services (ATS) and caching. +bitfield! { + pub(crate) struct PdePcf(u8), "Page Classification Field for PDEs" { + 0:0 uncached as bool, "Bypass L2 cache (0=3Dcached, 1=3Dbyp= ass)"; + 1:1 no_ats as bool, "Address Translation Services disable= d (0=3Denabled, 1=3Ddisabled)"; + } +} + +impl PdePcf { + /// Create PCF for cached mapping with ATS enabled (default). + pub(crate) fn cached() -> Self { + Self::default() + } + + /// Get the raw `u8` value. + pub(crate) fn raw_u8(&self) -> u8 { + self.0 + } +} + +impl From for PdePcf { + fn from(val: u8) -> Self { + Self(val) + } +} + +// Page Table Entry (PTE) for MMU v3. +bitfield! { + pub(crate) struct Pte(u64), "Page Table Entry for MMU v3" { + 0:0 valid as bool, "Entry is valid"; + 2:1 aperture as u8 =3D> AperturePte, "Memory aperture t= ype"; + 7:3 pcf as u8 =3D> PtePcf, "Page Classification Fi= eld"; + 11:8 kind as u8, "Surface kind (4 bits, 0x0=3Dpitch,= 0xF=3Dinvalid)"; + 51:12 frame_number as u64 =3D> Pfn, "Physical frame number (f= or all apertures)"; + 63:61 peer_id as u8, "Peer GPU ID for peer memory (0-7)"; + } +} + +impl Pte { + /// Create a PTE from a `u64` value. + pub(crate) fn new(val: u64) -> Self { + Self(val) + } + + /// Create a valid PTE for video memory. + pub(crate) fn new_vram(frame: Pfn, writable: bool) -> Self { + let pcf =3D if writable { PtePcf::rw() } else { PtePcf::ro() }; + Self::default() + .set_valid(true) + .set_aperture(AperturePte::VideoMemory) + .set_pcf(pcf) + .set_frame_number(frame) + } + + /// Create an invalid PTE. + pub(crate) fn invalid() -> Self { + Self::default() + } + + /// Get the raw `u64` value. + pub(crate) fn raw_u64(&self) -> u64 { + self.0 + } +} + +// Page Directory Entry (PDE) for MMU v3. +// +// Note: v3 uses a unified 40-bit address field (v2 had separate sys/vid a= ddress fields). +bitfield! { + pub(crate) struct Pde(u64), "Page Directory Entry for MMU v3 (Hopper+)= " { + 0:0 is_pte as bool, "Entry is a PTE (0=3DPDE, 1=3Dlarge p= age PTE)"; + 2:1 aperture as u8 =3D> AperturePde, "Memory aperture (0=3D= invalid, 1=3Dvidmem, 2=3Dcoherent, 3=3Dnon-coherent)"; + 5:3 pcf as u8 =3D> PdePcf, "Page Classification Field = (3 bits for PDE)"; + 51:12 table_frame as u64 =3D> Pfn, "Table frame number (40-bit u= nified address)"; + } +} + +impl Pde { + /// Create a PDE from a `u64` value. + pub(crate) fn new(val: u64) -> Self { + Self(val) + } + + /// Create a valid PDE pointing to a page table in video memory. + pub(crate) fn new_vram(table_pfn: Pfn) -> Self { + Self::default() + .set_is_pte(false) + .set_aperture(AperturePde::VideoMemory) + .set_table_frame(table_pfn) + } + + /// Create an invalid PDE. + pub(crate) fn invalid() -> Self { + Self::default().set_aperture(AperturePde::Invalid) + } + + /// Check if this PDE is valid. + pub(crate) fn is_valid(&self) -> bool { + self.aperture() !=3D AperturePde::Invalid + } + + /// Get the VRAM address of the page table. + pub(crate) fn table_vram_address(&self) -> VramAddress { + debug_assert!( + self.aperture() =3D=3D AperturePde::VideoMemory, + "table_vram_address called on non-VRAM PDE (aperture: {:?})", + self.aperture() + ); + VramAddress::from(self.table_frame()) + } + + /// Get the raw `u64` value. + pub(crate) fn raw_u64(&self) -> u64 { + self.0 + } +} + +// Big Page Table pointer for Dual PDE - 64-bit lower word of the 128-bit = Dual PDE. +bitfield! { + pub(crate) struct DualPdeBig(u64), "Big Page Table pointer in Dual PDE= (MMU v3)" { + 0:0 is_pte as bool, "Entry is a PTE (for large pages)"; + 2:1 aperture as u8 =3D> AperturePde, "Memory aperture type"; + 5:3 pcf as u8 =3D> PdePcf, "Page Classification Field"; + 51:8 table_frame as u64, "Table frame (table address 256-byte a= ligned)"; + } +} + +impl DualPdeBig { + /// Create a big page table pointer from a `u64` value. + pub(crate) fn new(val: u64) -> Self { + Self(val) + } + + /// Create an invalid big page table pointer. + pub(crate) fn invalid() -> Self { + Self::default().set_aperture(AperturePde::Invalid) + } + + /// Create a valid big PDE pointing to a page table in video memory. + pub(crate) fn new_vram(table_addr: VramAddress) -> Result { + // Big page table addresses must be 256-byte aligned (shift 8). + if table_addr.raw_u64() & 0xFF !=3D 0 { + return Err(EINVAL); + } + + let table_frame =3D table_addr.raw_u64() >> 8; + Ok(Self::default() + .set_is_pte(false) + .set_aperture(AperturePde::VideoMemory) + .set_table_frame(table_frame)) + } + + /// Check if this big PDE is valid. + pub(crate) fn is_valid(&self) -> bool { + self.aperture() !=3D AperturePde::Invalid + } + + /// Get the VRAM address of the big page table. + pub(crate) fn table_vram_address(&self) -> VramAddress { + debug_assert!( + self.aperture() =3D=3D AperturePde::VideoMemory, + "table_vram_address called on non-VRAM DualPdeBig (aperture: {= :?})", + self.aperture() + ); + VramAddress::new(self.table_frame() << 8) + } + + /// Get the raw `u64` value. + pub(crate) fn raw_u64(&self) -> u64 { + self.0 + } +} + +/// Dual PDE at Level 3 for MMU v3 - 128-bit entry. +/// +/// Contains both big (64KB) and small (4KB) page table pointers: +/// - Lower 64 bits: Big Page Table pointer. +/// - Upper 64 bits: Small Page Table pointer. +/// +/// ## Note +/// +/// The big and small page table pointers have different address layouts: +/// - Big address =3D field value << 8 (256-byte alignment). +/// - Small address =3D field value << 12 (4KB alignment). +/// +/// This is why `DualPdeBig` is a separate type from `Pde`. +#[repr(C)] +#[derive(Debug, Clone, Copy, Default)] +pub(crate) struct DualPde { + /// Big Page Table pointer. + pub big: DualPdeBig, + /// Small Page Table pointer. + pub small: Pde, +} + +impl DualPde { + /// Create a dual PDE from raw 128-bit value (two `u64`s). + pub(crate) fn new(big: u64, small: u64) -> Self { + Self { + big: DualPdeBig::new(big), + small: Pde::new(small), + } + } + + /// Create a dual PDE with only the small page table pointer set. + pub(crate) fn new_small(table_pfn: Pfn) -> Self { + Self { + big: DualPdeBig::invalid(), + small: Pde::new_vram(table_pfn), + } + } + + /// Check if the small page table pointer is valid. + pub(crate) fn has_small(&self) -> bool { + self.small.is_valid() + } + + /// Check if the big page table pointer is valid. + pub(crate) fn has_big(&self) -> bool { + self.big.is_valid() + } +} --=20 2.34.1 From nobody Sun Feb 8 09:32:51 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013036.outbound.protection.outlook.com [40.93.201.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D6D5427A16; Tue, 20 Jan 2026 20:44:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.201.36 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941868; cv=fail; b=lnCzmyMaiyzylmh7ngmkmizUcnAmDAxpPm9Ex/8Px+1dijdQb0RX52+N0UXeIW9JNvizOJcnlG2IWDLlcBQE14a+t3tPACRMDR3fND1hln9fEGlqGZVmJFx3M7rZwKXM/fHFx5jXkugL2z05bT+2EwR8NgRZWKfyYBJ3AAIS+1w= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941868; c=relaxed/simple; bh=Nik/zwuH7i/247TSDjx4Ql30fLTXevRh95PDh4jcwjo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=FHnarHu1dPx5sh/jRtneGv2t1Mkc7Or/jHy5DlxhmyL8vCu+JR9STENJEdRDywcRTFQsi+mvGDk0tNqmwvaotQSRrwjg/Jm7iJA63ry86/M3MO6Cmkl3tlROpSSXNc5tIKfPEaDQ44dD5N/fK5Rj/44kmNz7bE1rVZ9lZJ4NMpo= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=ipjOho03; arc=fail smtp.client-ip=40.93.201.36 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="ipjOho03" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=hPOELA4RCc1I4Kxh89qQdE3snwFH9dil9udr5WdQTk/+h5BipFCg3ZvAo8DAuqUaacU7YuOBEtE2ovUpQLjYUBm52IO8uleB1vdWOH+OrOrxknLQjFnpkBfNp52Nzmqq/r5sNDyT4AnkrISJ5Hr2/ElTyx2N0sfDGR8JcAQol2oDMVl+DtJwHUNDvcJbSANxpp5KFnTrysF1zn95IN7CcQy//MAEjrdJm9SuYGpCGxbru5U3hgwlR0fdxifHHNuYq9Or6rLtMzkbQ3/nF9YTUskVbb4ltjJcyr142kzTmgMHEbQxJp6CIHrDzNQW+Xewx2e8qrLIT29wVfZNLx3GBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=tTXG+TgdX/HtCScxD574jMcpp6DCh3lbzLSpC2RrNnw=; b=c46DdIYZ/raqVyprngzCAEpyVJLp0QQJos18PNUxmQ+M45MRO5+qLccMsHwVGtjfqtxf26nRdFquKUJvmoM3YOajKY0QB03dc5LGDZ3xt1QUA4MrrjSlk0VuAM9rC2Xs/KJDICpEvBqAXE78oCuUo79UCRecbjwajn+Ijavgx9ts1/p610MYCR7C0LhOQvbHS85SknFF5LFB1NnVwfTwQthM3hBL2WspXr3IOZ7YLWEsbT11itj8mmqipx9KpiD6Sodsc1TFfYDHcJJfHGKxo3hEuU6kcWWYjL+N0QLgSs0p2WELjbOFPa+79iULQEKB+wrNk/zYmnQzD1AG/L5AaA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=tTXG+TgdX/HtCScxD574jMcpp6DCh3lbzLSpC2RrNnw=; b=ipjOho03ibMI6G6KhZJxh4ToKjbqNr4rr8DjvKdchtpKEC1DJi8/cU0ChsyjWJ/x6LrCc6jvBe2NwobMgyBHlzAUFIYkQGUufeeBovesPN0UosXSdzYrokQVCyEe2C+UP2l3DZxaZsUhcCDYxh63qIRY6axcQuu84ou0xTnHahbBY7XEkDckwKWyQvbz0cGLX3TUqe1P2Y7wedFU+UJqB0pqhm5CbnLplafX+GObQV/ldjrtOAkL59AaCD9kzEDlNWSW2BiVaZee0P/tPp/bp4LXS/gltoUrxpEQZj2rwMHuxkMSiFMvOU19/vAegc8zxIsboeAKhMnZfCGtntN/Rw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by PH7PR12MB6809.namprd12.prod.outlook.com (2603:10b6:510:1af::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.12; Tue, 20 Jan 2026 20:44:13 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9542.008; Tue, 20 Jan 2026 20:44:13 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jonathan Corbet , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Huang Rui , Matthew Auld , Matthew Brost , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Helge Deller , Danilo Krummrich , Alice Ryhl , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Alexey Ivanov , Balbir Singh , Philipp Stanner , Elle Rhumsaa , Daniel Almeida , joel@joelfernandes.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, linux-doc@vger.kernel.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-fbdev@vger.kernel.org, Joel Fernandes Subject: [PATCH RFC v6 13/26] nova-core: mm: Add unified page table entry wrapper enums Date: Tue, 20 Jan 2026 15:42:50 -0500 Message-Id: <20260120204303.3229303-14-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120204303.3229303-1-joelagnelf@nvidia.com> References: <20260120204303.3229303-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MN2PR01CA0064.prod.exchangelabs.com (2603:10b6:208:23f::33) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|PH7PR12MB6809:EE_ X-MS-Office365-Filtering-Correlation-Id: e0d5d854-ca0b-4d37-5201-08de5864ab8f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|7416014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?YlVmRlpt9sQagsj+uGY6fQWq0DxRJhx6jnlQkALgoL66N74wRrykjhmOcfg1?= =?us-ascii?Q?+1hXxhI0Szq4tFgEqirrRQx2qlQlSguREduuHveIQHZ0IvBe17kJE4d26jCH?= =?us-ascii?Q?YsFYjVXQuEFJVjja68L3wjdVz7hoZwJSFIQopFdJ+bSFDJPAf+2EEwZSZHWO?= =?us-ascii?Q?5byyzXTUQAzVYrj2FK0fIOHtf7ZGiXaItvKvnjE57rc+QCel53+Wr/VuXiE3?= =?us-ascii?Q?WsHoZVdHCA++Jbm1SbL/E1AOErsBaDqHAHl6EkyglQBIaYLPYF6vG1QzElIB?= =?us-ascii?Q?Z7QB4EF5rSH39Pkf1k/9T4nUHpxxFJX12QD3UZmLj8jsgRWGUB5e+7j+kvT9?= =?us-ascii?Q?ocdvT4PjeZlS2XavROrOjN1Jr22tfIfYm1PPq5i7GuxTGB9jY9aAyezND8oP?= =?us-ascii?Q?B0ZRdfzxN3048q0ReJ5L7TgBXSlI64zAwUSrC9RaoiqY7hBSSTky9wV10459?= =?us-ascii?Q?SEEO48EuuNqoqWNa+Jy5yRjuHQSTMmRZKsLJQL0+cU1MTdGuOU4X45qfHCKB?= =?us-ascii?Q?DCbfHlGIyskyeuXtgDIKK/HeecvoX2LbW1UH376ngQ+0TGPAaPDiR2YIufA4?= =?us-ascii?Q?OrnNsN1CHMyvA13ytWUiSIJ58JNRRpRdx1d8QlSdGQ+iv1QlMbDZSTZETsqb?= =?us-ascii?Q?YM1LDKIb2rcfc6193QIcueefVPwXuShyEZGEVbgBZWOoDu5LnGa5WK4UsjzZ?= =?us-ascii?Q?jbwan/3SpyPpptSj94PH9Nv9cZGaK7ltgJVU7zknHyAGf7fVj/0Xjfw/vX4Q?= =?us-ascii?Q?vHIjV3pFObDOSxociTvCHVDeN5eVsY4NcCEpMbqgiC3Aq7piYSvLuL5283c/?= =?us-ascii?Q?IYVDJ07QBo0ZdN6p1QQ0Hk8bhU5m4gE8lhtPhCPE4uFeCOQfmruiGGovD3Yk?= =?us-ascii?Q?sS2YLhVShwpx7xo9tKx4fDMSyAmfgE89/pQ8Ih3rHHxDykpWN0+d8vXXooo4?= =?us-ascii?Q?BbGk9/kbq9eibgOGfhBgFOqH1iqrAdAO5xMq8nR+xS9CS0Kscl/xEsaLF7Pl?= =?us-ascii?Q?ln27VzaQcZnIMTbYPFnQtfKq08jRMY5VDOxl/747EgB/7OMEdBTxO5aXBad6?= =?us-ascii?Q?8FTPlWDGo0H4en1uarRCpmPYjgfp4jW1v2V9ljvwQ/EhNaV3xFRgUICutju0?= =?us-ascii?Q?lTKsUhwdpmaJ6b2VFlX2XLH2f5vG6CCMnCBt87N6Ah0RFEgBTm2OaGEXSuFJ?= =?us-ascii?Q?TFzufK11xgeynjzEuSvVKk5f5vCzohmYqAD/C2IdiEFE2GXMyujBEXC0byWx?= =?us-ascii?Q?IiffuunGPJffequftNi94MktowRsiCcO0ofyukWj+/lik3HyGqmkelpPbaLo?= =?us-ascii?Q?fjSyYim34StmhT/Wcum/YuDcFHHdjAayuHG86sB0UIC9ypTej1/4bwqxu3Kr?= =?us-ascii?Q?creMb+jJvUnw0JKqadb75UfiuZb4swLl6sZFYbGYct67MHUuJz6FKjJKTDX6?= =?us-ascii?Q?y01IN1DdotzvFWPy9NaOOjWTQxj5VDy1JfBbgPXNjsbYU2LVR0GPh6+KgZP0?= =?us-ascii?Q?BAOR5dP7zhjosAbpE21uPBieDDTjLZBDwApO2+NPyzGtYiERBolVsNI7oTtW?= =?us-ascii?Q?GHFEqYp6n1gGrESv6zE=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR12MB6486.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(376014)(7416014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?oeBrQVnnbSXXsfosj5lkK7jgcO5Jm0zT0gt7LGbabP9qi5PvE/hdEL9jTXBs?= =?us-ascii?Q?ftIulQOXn9fSnO42Na2MDHlOPlhHLxL+aEyT0iHwXKaqPSb5cF8+LE7ljFj1?= =?us-ascii?Q?yvZCIDi6D1P996yEEN5j82CAsCibLM9PMZCNzYlGFuDwKdLu7Qo3ov7Z64Ok?= =?us-ascii?Q?bKFYXFq10JxDUePsJDrpwn1ZlZp5LsG0w7L60/dWQiEnqiSbIJ0y2268B1Pt?= =?us-ascii?Q?+VJC+YwPdVv7tDMAvqAUYUP3L4/aiaxpEc2zrNsXitagLPX7bcPWkiVdf/NB?= =?us-ascii?Q?toCRY/lLy9YtlQenDZWyBy14ZKH5ykwGvDcFlrKKvvwlLQYs0BToLUGZNRq1?= =?us-ascii?Q?8ukD9kKxkU1pPx2dhNOm7m/20nYuL4aEd8DLmH9EtcYaEq/i904CETASfm5Y?= =?us-ascii?Q?5mYcGA7P+ybzjOaQmkwjBb9Ckz0xYuIMmwMjaB4c7XfNinVpURwj8FY6EGU3?= =?us-ascii?Q?G+WX014V78KxJBc5L0NAAzM7wnRcco8mkFVRscs7YDsM3PU988FE8wYrTrFk?= =?us-ascii?Q?ldtk5Ksa7rGZJhHgWPdBbwCZvFXfCnkuqVEHodB3Z7QWB940xc9TRvX4DGed?= =?us-ascii?Q?FeSePhjs67aQVT7Esk6Jhkkcrb7vIDm2xtsYV8LZdO1yug6yY58csXWeS3qw?= =?us-ascii?Q?lYgI+oORbJyJnqt9ZuY7tmY2Rjnsn6XHatNbVl3sA83re/XjohljzOSSL8Pg?= =?us-ascii?Q?YqFNmKmmSEJsGbTOIdEQg3vAIW9/F/nlyS5ZGXiCftr4RCr7exFxUGIcDsn8?= =?us-ascii?Q?ne3NaarlLnTuzjlG0COlfzspQKXPeLo5NuUFHcoUeaJIA7yganM5k6uQqBYa?= =?us-ascii?Q?mIbOBxyvfQ3GwL64X3kF74rQno0CjiPFDI8IYwOiMFPHqC1nGjrCrz0tzCL+?= =?us-ascii?Q?mvFDACD6UiMzFBqfZ+XM4bkauP9nyujEO03MnmkNphYYgbA84MZCdx8E72EL?= =?us-ascii?Q?xiqnAHAJIlpxBqawsK6Ue53m+UHbn7qEE8lcxQsX51POFW6AHYMQHxL0ASir?= =?us-ascii?Q?JpgnCWvaUZug5h+Eq6ZKIOfgClIXR1C8jirQF/iqC4Vkc/U1hz9WNa3foK75?= =?us-ascii?Q?2aHBQg94EtBmmT5dAXT1rVIJkeron35KG1CvUDRbzdm0CEQReqWp7NyxUdOd?= =?us-ascii?Q?0xZnQK12hIH5hYjc/cRm7272CYJnIqMKRHlH2AtwRs5RmCWQ+tKrhvOv9rgr?= =?us-ascii?Q?s+HuwvSx9TOJwtxKz0+B7MyW7rnxBgFGdQ43hRIQWdLHtCWbbbBX9dOCZTr0?= =?us-ascii?Q?+1OgbjHiO4nan/teXOmezR9K1I0p4FmjdctuU0Fh/VO35X+gtGL89x2m3nuw?= =?us-ascii?Q?46dL4hvRO2g+1HyNfoKyAQxljJitGrpxxbgulnfcTNUUaMWVx/dDZYeZgkD3?= =?us-ascii?Q?5Dnix1iAdu7HV+dph8cENCOEzIKs2FIjs+JiSoPmPY6tC7q0jdSLP83AjFRY?= =?us-ascii?Q?HO7xxPd9tTWXlLjGhQGMoWN2MYkULQgpPIO1Au5IKutR7rWbumniP4HkkWPn?= =?us-ascii?Q?OqUrQxNSRICBFutK3CSSDX3tBz/PhBImJeLKwIIvkjYWh/7GMnVWj+zHJGWG?= =?us-ascii?Q?JCPHl3Tcczn2vVw+iv877PzxVVYy2Kitx4rjeVi+bhmrD+8KzxFMW340XJ6x?= =?us-ascii?Q?qa1sE+fPQ7BEtXpu02rZHkA1qxLpfPZKna5TyJRmvNhNTK/f67eqaGQ1ftT3?= =?us-ascii?Q?KiB3XSJBm8zp4rzDtUN4rY1UNzbf3I/GwwtD12WQdkg8S01t9t/BD8v1KKWg?= =?us-ascii?Q?n9P7vUnFCQ=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: e0d5d854-ca0b-4d37-5201-08de5864ab8f X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB6486.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 20:44:13.2995 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: kvO0nXsnh6ipUjIZqHBCGRiLDldC6SuUoPJAul2aP44roDrNp/vlMqzCTXP7g4nlcPPh/hltj2Z72AOabr5YRA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6809 Content-Type: text/plain; charset="utf-8" Add unified Pte, Pde, and DualPde wrapper enums that abstract over MMU v2 and v3 page table entry formats. These enums allow the page table walker and VMM to work with both MMU versions. Each unified type: - Takes MmuVersion parameter in constructors - Wraps both ver2 and ver3 variants - Delegates method calls to the appropriate variant This enables version-agnostic page table operations while keeping version-specific implementation details encapsulated in the ver2 and ver3 modules. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/mm/pagetable/mod.rs | 194 ++++++++++++++++++++++ 1 file changed, 194 insertions(+) diff --git a/drivers/gpu/nova-core/mm/pagetable/mod.rs b/drivers/gpu/nova-c= ore/mm/pagetable/mod.rs index 3b1324add844..72bc7cda8df6 100644 --- a/drivers/gpu/nova-core/mm/pagetable/mod.rs +++ b/drivers/gpu/nova-core/mm/pagetable/mod.rs @@ -10,6 +10,10 @@ pub(crate) mod ver2; pub(crate) mod ver3; =20 +use super::{ + Pfn, + VramAddress, // +}; use crate::gpu::Architecture; =20 /// MMU version enumeration. @@ -168,3 +172,193 @@ fn from(val: AperturePde) -> Self { val as u8 } } + +/// Unified Page Table Entry wrapper for both MMU v2 and v3 `PTE` +/// types, allowing the walker to work with either format. +#[derive(Debug, Clone, Copy)] +pub(crate) enum Pte { + /// MMU v2 `PTE` (Turing/Ampere/Ada). + V2(ver2::Pte), + /// MMU v3 `PTE` (Hopper+). + V3(ver3::Pte), +} + +impl Pte { + /// Create a `PTE` from a raw `u64` value for the given MMU version. + pub(crate) fn new(version: MmuVersion, val: u64) -> Self { + match version { + MmuVersion::V2 =3D> Self::V2(ver2::Pte::new(val)), + MmuVersion::V3 =3D> Self::V3(ver3::Pte::new(val)), + } + } + + /// Create an invalid `PTE` for the given MMU version. + pub(crate) fn invalid(version: MmuVersion) -> Self { + match version { + MmuVersion::V2 =3D> Self::V2(ver2::Pte::invalid()), + MmuVersion::V3 =3D> Self::V3(ver3::Pte::invalid()), + } + } + + /// Create a valid `PTE` for video memory. + pub(crate) fn new_vram(version: MmuVersion, pfn: Pfn, writable: bool) = -> Self { + match version { + MmuVersion::V2 =3D> Self::V2(ver2::Pte::new_vram(pfn, writable= )), + MmuVersion::V3 =3D> Self::V3(ver3::Pte::new_vram(pfn, writable= )), + } + } + + /// Check if this `PTE` is valid. + pub(crate) fn is_valid(&self) -> bool { + match self { + Self::V2(p) =3D> p.valid(), + Self::V3(p) =3D> p.valid(), + } + } + + /// Get the physical frame number. + pub(crate) fn frame_number(&self) -> Pfn { + match self { + Self::V2(p) =3D> p.frame_number(), + Self::V3(p) =3D> p.frame_number(), + } + } + + /// Get the raw `u64` value. + pub(crate) fn raw_u64(&self) -> u64 { + match self { + Self::V2(p) =3D> p.raw_u64(), + Self::V3(p) =3D> p.raw_u64(), + } + } +} + +impl Default for Pte { + fn default() -> Self { + Self::V2(ver2::Pte::default()) + } +} + +/// Unified Page Directory Entry wrapper for both MMU v2 and v3 `PDE`. +#[derive(Debug, Clone, Copy)] +pub(crate) enum Pde { + /// MMU v2 `PDE` (Turing/Ampere/Ada). + V2(ver2::Pde), + /// MMU v3 `PDE` (Hopper+). + V3(ver3::Pde), +} + +impl Pde { + /// Create a `PDE` from a raw `u64` value for the given MMU version. + pub(crate) fn new(version: MmuVersion, val: u64) -> Self { + match version { + MmuVersion::V2 =3D> Self::V2(ver2::Pde::new(val)), + MmuVersion::V3 =3D> Self::V3(ver3::Pde::new(val)), + } + } + + /// Create a valid `PDE` pointing to a page table in video memory. + pub(crate) fn new_vram(version: MmuVersion, table_pfn: Pfn) -> Self { + match version { + MmuVersion::V2 =3D> Self::V2(ver2::Pde::new_vram(table_pfn)), + MmuVersion::V3 =3D> Self::V3(ver3::Pde::new_vram(table_pfn)), + } + } + + /// Create an invalid `PDE` for the given MMU version. + pub(crate) fn invalid(version: MmuVersion) -> Self { + match version { + MmuVersion::V2 =3D> Self::V2(ver2::Pde::invalid()), + MmuVersion::V3 =3D> Self::V3(ver3::Pde::invalid()), + } + } + + /// Check if this `PDE` is valid. + pub(crate) fn is_valid(&self) -> bool { + match self { + Self::V2(p) =3D> p.is_valid(), + Self::V3(p) =3D> p.is_valid(), + } + } + + /// Get the VRAM address of the page table. + pub(crate) fn table_vram_address(&self) -> VramAddress { + match self { + Self::V2(p) =3D> p.table_vram_address(), + Self::V3(p) =3D> p.table_vram_address(), + } + } + + /// Get the raw `u64` value. + pub(crate) fn raw_u64(&self) -> u64 { + match self { + Self::V2(p) =3D> p.raw_u64(), + Self::V3(p) =3D> p.raw_u64(), + } + } +} + +impl Default for Pde { + fn default() -> Self { + Self::V2(ver2::Pde::default()) + } +} + +/// Unified Dual Page Directory Entry wrapper for both MMU v2 and v3 [`Dua= lPde`]. +#[derive(Debug, Clone, Copy)] +pub(crate) enum DualPde { + /// MMU v2 [`DualPde`] (Turing/Ampere/Ada). + V2(ver2::DualPde), + /// MMU v3 [`DualPde`] (Hopper+). + V3(ver3::DualPde), +} + +impl DualPde { + /// Create a [`DualPde`] from raw 128-bit value (two `u64`s) for the g= iven MMU version. + pub(crate) fn new(version: MmuVersion, big: u64, small: u64) -> Self { + match version { + MmuVersion::V2 =3D> Self::V2(ver2::DualPde::new(big, small)), + MmuVersion::V3 =3D> Self::V3(ver3::DualPde::new(big, small)), + } + } + + /// Create a [`DualPde`] with only the small page table pointer set. + pub(crate) fn new_small(version: MmuVersion, table_pfn: Pfn) -> Self { + match version { + MmuVersion::V2 =3D> Self::V2(ver2::DualPde::new_small(table_pf= n)), + MmuVersion::V3 =3D> Self::V3(ver3::DualPde::new_small(table_pf= n)), + } + } + + /// Check if the small page table pointer is valid. + pub(crate) fn has_small(&self) -> bool { + match self { + Self::V2(d) =3D> d.has_small(), + Self::V3(d) =3D> d.has_small(), + } + } + + /// Get the small page table VRAM address. + pub(crate) fn small_vram_address(&self) -> VramAddress { + match self { + Self::V2(d) =3D> d.small.table_vram_address(), + Self::V3(d) =3D> d.small.table_vram_address(), + } + } + + /// Get the raw `u64` value of the big PDE. + pub(crate) fn big_raw_u64(&self) -> u64 { + match self { + Self::V2(d) =3D> d.big.raw_u64(), + Self::V3(d) =3D> d.big.raw_u64(), + } + } + + /// Get the raw `u64` value of the small PDE. + pub(crate) fn small_raw_u64(&self) -> u64 { + match self { + Self::V2(d) =3D> d.small.raw_u64(), + Self::V3(d) =3D> d.small.raw_u64(), + } + } +} --=20 2.34.1 From nobody Sun Feb 8 09:32:51 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013036.outbound.protection.outlook.com [40.93.201.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B6BD3A1E70; Tue, 20 Jan 2026 20:44:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.201.36 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941876; cv=fail; b=LFF9xzDmp8qKHjrpu0nQwuWBnmV7Cm5exa9DEYtoefS0mCHbY1AD2/3mj0htImjbAdvaapkPVKQk6MsYVS+29j5X/N39AwzaK1M8SOyAe2p4jGOD1j+q2D6JS87Mh9kss+MqIaFAaQecQLp65NtP+wemCsmmVT95VAOz2U9Ntxg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941876; c=relaxed/simple; bh=Qv+iobgHXladWduzxbT77ZKes7VuiRgya8kZSlPXXCI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=ssruFlUQfk5OuwpMlyN7v1dnO5fCAEQb8fq/Y70spLNW/JxfIfXeuDjqGP8IAiZ4iv8wW2UhM1Mp2ikn6GTKtaJ3z0Kjxy4ZOLRgMx4EJgyXS4A5YsTcYLhKnT99JFtktyNDXTJlgbj06DUZ9rXf3L1o9synsQ09J7ZjNF/f/ko= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=Zuzkc0lm; arc=fail smtp.client-ip=40.93.201.36 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Zuzkc0lm" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=SRgf2Aun7vdu1c9ixTfdhiJc9+hsOaeEc2zu+vNJ7tTZuDYX3hYljCNwxYrn4hrlNgatiy4kBZ3njc+McGWJs362KzFAuYhI1WKycmKdHL9BseluTfLVdrhhbBKoIrn2NH/n7vGhjTZdYpLX+nONh/A8YNP+1tKcjRdbtOpePbYqw+CoPGggtmvkPgUO6TQw0CJ6kfVzwD5EuDOxuvI+yPt8n/Gw2G34+0OQgqX4uEPic5qvG8j6AEuEYWfZF1vQTmmYvNXmGjbYieQtj2N29izQ5ICa/1BJuqrHPwSC6Agm3gDa5p6Fej9B4oOypRmowXIgFgVisnY8qXjGQH0XsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Td5seor6YcwL8U3MguhSeXZvuzOQUJHDD3RB5hCjIUs=; b=NKxSne5Hql6dPfOmVBLfjL2OXHKfJaRLwuVVKa9CPhlCV14SvQ56k19XRZuq+dN0+67VbEDc6QDhxXq13PSew0YAzWIy+UOx26pR0DNy9gPW7qEDn/ernCUMXDWg/iX+/TPSci2ixC6Iydi1MEK1Z1AJDo6fjik8IG/wCEbAQTjpWr3pnR4ehw1HcJ2a00I7+ZjgUVf+SdVVlBQ+E7QP2xMZdIwYPnB+VOjZ3Px6rsi0KoraL5WdTr8f2D4bfG1UP9xMwfeQmyBt8yVRwzraZWmyNucmXTA1oyLGRqBhMX0hZySjc8zhaI9TA2ji8QToyJ9DQhuhS/YBM+VIgb3xjA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Td5seor6YcwL8U3MguhSeXZvuzOQUJHDD3RB5hCjIUs=; b=Zuzkc0lm3YJFko7rPbWQsVcerUkYcuQ6vAp5Qh7XrnBgD9l/lzcz3lzC6XhDHtdcHnlMaLQBW2SoZ7TT4AL/omZ+LOZkvQAoXN0a0eOBZ5yti5hdw8hbqggjeouoEzKax/Mmq0kyZ9oohj5Zo11c3g/NZFQiy1XxFzVG4Yfj2t2yfkpy1kRl+hKYQQqVZtc6I/xJXWyindi9Dj6hMrmDXyqOaCqVNkZo01cWBLxKsby5Cw916ih0eAe6N2LGToWBbNAADyThHK9vZhGBPpgVr3xDatIuZr5Z03OG1QuZVVQBa1DrK11Hs98mKfHJyrDN+mV+G0TKO+zhGRvhgHqCtQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by PH7PR12MB6809.namprd12.prod.outlook.com (2603:10b6:510:1af::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.12; Tue, 20 Jan 2026 20:44:14 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9542.008; Tue, 20 Jan 2026 20:44:14 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jonathan Corbet , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Huang Rui , Matthew Auld , Matthew Brost , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Helge Deller , Danilo Krummrich , Alice Ryhl , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Alexey Ivanov , Balbir Singh , Philipp Stanner , Elle Rhumsaa , Daniel Almeida , joel@joelfernandes.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, linux-doc@vger.kernel.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-fbdev@vger.kernel.org, Joel Fernandes Subject: [PATCH RFC v6 14/26] nova-core: mm: Add TLB flush support Date: Tue, 20 Jan 2026 15:42:51 -0500 Message-Id: <20260120204303.3229303-15-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120204303.3229303-1-joelagnelf@nvidia.com> References: <20260120204303.3229303-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MN2PR01CA0043.prod.exchangelabs.com (2603:10b6:208:23f::12) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|PH7PR12MB6809:EE_ X-MS-Office365-Filtering-Correlation-Id: ab838b71-f9f1-4d4e-09ce-08de5864ac6f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|7416014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?EMm+panFU9btzc+Qx95DPXy/keTnFSOytfvH8JbEkGsky56ZrxQQhuIqwyqK?= =?us-ascii?Q?7v7Nhi3xFGxIqlgst0GotDofg9qItjol2z7VXU/Dj5yv7IfXkLF2R7eFi9pf?= =?us-ascii?Q?jy5opYCJAkFX7tes9Y8P5es7xGGdeCQbkaWnFqPcY+qGl3ShM7z8G688CW0S?= =?us-ascii?Q?sX4SEFb1YNbSaZQjmKXQMT0KCL3OJ9gxBYgHCuzZ3faXEVHZo5HcaZKDdzqm?= =?us-ascii?Q?Ad4VAdjUXP2UZlR1mIB7sqNtLZ05EQV3LfkIT/xjVoyedZtgT91zxyFwXUX+?= =?us-ascii?Q?PLCU6bEdr8Mjo9dPPNfuVu4AvIWoME3arEycM+y7tlP4dd4Og6ozJud7SZIL?= =?us-ascii?Q?gXx9mHeWxFTb9u8qcxnD6Y3dPOSUA/WABsYb0OdTNHBP/Qpmvd3X4tTRzAGE?= =?us-ascii?Q?2EQYkH9gpUrMJaiDh97DWR9dz8cnhTadzzQzP/+QNWyo+J7TJvBhA7zSs4DZ?= =?us-ascii?Q?S2aHT8yNoZSsC9edoA5ylBIH69l0hZUMQionqUart3nJ956MSoVks4Wg6aZy?= =?us-ascii?Q?zTQ0m/QDro+VxIkVijgebWqk2xN3Arw/Cztg5pNbvFAILNMq1tORVjThE9l5?= =?us-ascii?Q?OqtN3iGDJZbFWe4QwvNuYGBcyYSmXsKfKNIfLMBxTNvui53oResuA//kX3hM?= =?us-ascii?Q?hxr4u6qBPdtbhGD0u2E1p8o++CUHdUWSfg1gRUyPdV1u4M9TTyr2VFST+Vv2?= =?us-ascii?Q?0BXH0a4u0MTulybi9xmy7vfA5bjEfZYFji+PLn4btqHT/4+d4vPL5lDO2ONa?= =?us-ascii?Q?uyCBww/leHEZfw/uy8oOtJPbFMMHuBNr2rk4NicE91ajoxCdSkIxpm9N86fq?= =?us-ascii?Q?Xr7QOVuZ6cFg8uxvN4hk+zZLpFJZyoGnmvMBLmd7UvgnoRH8BVZYRNk2H96C?= =?us-ascii?Q?s8D6uYDrGjNnDnGxp0aAosvxEOR9rIAsgEmpwNpgQhTe5Eq7x10MysmOt6zy?= =?us-ascii?Q?/Gkkbdtbj6Tbeg1mZaGibdgmaoCdhLLwUW2/0344pHWajvzfmbmlws9Vn8X6?= =?us-ascii?Q?tEmk96aMHR3TiDkP4XQpq9unveN31/MrW2eUMu76F94MRa6ZFa93PVsgCXRK?= =?us-ascii?Q?VMGAi4H9w4limTh4fX37UwrrZJMTGBKY78vZ1yUiBP7OHZkK7wEncTiUOZv8?= =?us-ascii?Q?k9L2wrwcQq5tH2aFAEzOksMfTfy6YnE5mRfMJS+UjGTbfkuziFMRqGikdEk/?= =?us-ascii?Q?fFxA7u/UiQhxG1jrREy/DTj7Ltnl8olADSsEpVp9YSKKlI5daPwpeh4nSUoo?= =?us-ascii?Q?C3na0FOqptZqkeEVxO+gGwbySHqD6RXrpBRbXGQZfg71RGzHQdiuIV5x5sTP?= =?us-ascii?Q?fWuQB45J9b/55CtKgUZ5Tw+5vtvCvp74HL913a+V0uEkAcPSk0Pjrqy00P3L?= =?us-ascii?Q?V6jksRAOJi75HNHi/CEiw4X6ekejQ17+4G4CbL07S052BY19DbfYTD94JisG?= =?us-ascii?Q?O624UgN4E+EMLlJrZ4sDbnQnsbiWK60dZVRMTWFn68WQ0hM9DEY133Kpb08Q?= =?us-ascii?Q?vEneFyeqyQzSYCCBK/AES1t3L2oL0hK6g48ZijFeTzuvfYBRmxCuZGdcRTU6?= =?us-ascii?Q?ogfk5dYuv3BR1dOFi+4=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR12MB6486.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(376014)(7416014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?+f6AZBAAagst1G2jPm0Q3kDmjbDeHWJTuzXL7RVx9XDofRs4+LGBcKD65D62?= =?us-ascii?Q?+gAUtYrdKO0cibQns/UyQqZi2YpR5VxmTgr/cWWkskUNCX12CCebWtKxKvu4?= =?us-ascii?Q?HhuR21/cELZuM7miL7o1z3H6g4Gn4S+0XUA8YUx9M9St6JrbZwwirFL1Z80b?= =?us-ascii?Q?R0U3nYk7Dul9WxhpuUQFrPFb6LXcrtiq0R4ShOtKwWEuwOybbbaNboO4kqKo?= =?us-ascii?Q?w3rcIJnarfHc01zvm2TtFBOMArZ8DkjAJF5C/qcOOd3i22H6ZbtC0ckYPFHd?= =?us-ascii?Q?4GJWf0McY6zZHTHtBz3hzE8M8e1RISIlaMDDOd6mn0vK/akLccgzjyhHvUgZ?= =?us-ascii?Q?Msthfs2qXHmCICSD/Sh0Cg4bBJMTFXItg+QvuCeNcbsYFW3/SFq1akCZH47r?= =?us-ascii?Q?cbrKdldpzo5ZDmo+vp4NjA1AuFVuFGL2fT/M9a0hPUgk6ZFeUp4/PqbbEOy5?= =?us-ascii?Q?9TDlHnSVP7GyXiRVRLy3r+vOltR+dY7blOpAhx5VeyHUCS0ysckghGB14Nub?= =?us-ascii?Q?+HA78x3/9wcFa2ZIZT/Ok7a9+NO14nBQElvFmwndxjKy4PUJ7MZJcLvQb8PB?= =?us-ascii?Q?VQSU+qJywM4Rwcp4Lo5JRHiZEk+LpxP5N28MTpL7BzKozfFmMpMHcJNUJyuK?= =?us-ascii?Q?ON7YXPutqFg1lPhNeaAI0UWtZdGGnWwu4Ou0vDQ5sTauyPl7qiGRNUX5Inv1?= =?us-ascii?Q?CsUAjQKDaFezqrjm5Y8h+RpLFr+jnunbh+Wpp998PnPe4XkUsjEyugbswWY/?= =?us-ascii?Q?bsnoiBbwe1ucJZL63GXKx7/BwtVMQCa5z9JUW5v5F1nqRP1u0ZWkE9Rdm9Cd?= =?us-ascii?Q?05vI/R/eLINVn4KZqXqsiypJ9SybCj2DYIrc3YrQhQ052qCNnoB0jl8UQjzb?= =?us-ascii?Q?/Ylu1+I52GbfUqN9u3/JkZgyX1OmA/mxf/eDUhlQiljAJvoG82Urpyk+C2rz?= =?us-ascii?Q?WTLaQzu+hcTNRxQuZ9Hrxig22H6sziHxJSkF2AgLnDm6VTWjR1+VORPFVnkG?= =?us-ascii?Q?jKh//g97GZaUJUyTvMUsWHSKx4IAWkGKSx6PfQadSg002ZKoKuUveqCn0+ge?= =?us-ascii?Q?v9PDtH/dei4RApGOy0Fp8Av0cg2iPT0OpmZKmYp5zdgyyN7EPj8pPODWAWNy?= =?us-ascii?Q?lX1+gAxKosEadfSZ/mrwg2aURASd7ws6bI9ZNeVHl4cEUPXQR6Vv/LnVXX8O?= =?us-ascii?Q?61poJGJfZT2n7kPBuPhIZ6G/BkY3UoBmlkEbNcZhsPmfeECjc4Njtp1VKtfu?= =?us-ascii?Q?vgXaKUI5agrEjzy5mS6waA6SPq923NsLGoRfNu5HN6Oku1iloFAkLkK1KIh4?= =?us-ascii?Q?gLOGs/fqK4l/XeKvABfsp8dzbCEVZvwLrY1pqes6je5vAc6RmeqKKHUz7rNH?= =?us-ascii?Q?uZKv4snLYBm6ISgDovx7c0gedZKWzovkkU4nOmN1i9cmH/AvK2LviOdqhKRl?= =?us-ascii?Q?U+63cpNxR/Pwr5KfFj48OzCTewuzgIxeoTjvf9+hEvwcjk6Gu/jtVkdFpFJj?= =?us-ascii?Q?1PmpZOI+kiUt7x7EUNlJDFCY0kUD2ujVjMtapiCyeOoXaZMBkeBUpSk6Bz6M?= =?us-ascii?Q?kFC6Et7GAf3BzR5/xFe4xRwU/eLXSbNCcMuM7Gnnb93/npSNgqhLTJrKn5mz?= =?us-ascii?Q?CDbTZVvAZsYdQv+TiqXZTDktXzyuFEC0i/kOglRjgbKMH9ZRSfTA34owi9t7?= =?us-ascii?Q?XIf9KNErLbfGh8Vm8aIKMCa104t1eUvkuN1uvkfHwwTjIxa+Kk+sd1FkFbB8?= =?us-ascii?Q?20+Z95YNIw=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: ab838b71-f9f1-4d4e-09ce-08de5864ac6f X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB6486.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 20:44:14.7841 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 2lk49y12UumFf7IkwuSFmtddv3YDPa3qBoYPXj6dtzMPBGnxWaMFBtVk666Yi9TcfrqUyEYMIKGQZqcsgBfErg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6809 Content-Type: text/plain; charset="utf-8" Add TLB (Translation Lookaside Buffer) flush support for GPU MMU. After modifying page table entries, the GPU's TLB must be invalidated to ensure the new mappings take effect. The Tlb struct provides flush functionality through BAR0 registers. The flush operation writes the page directory base address and triggers an invalidation, polling for completion with a 2 second timeout matching the Nouveau driver. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/mm/mod.rs | 1 + drivers/gpu/nova-core/mm/tlb.rs | 79 +++++++++++++++++++++++++++++++++ drivers/gpu/nova-core/regs.rs | 33 ++++++++++++++ 3 files changed, 113 insertions(+) create mode 100644 drivers/gpu/nova-core/mm/tlb.rs diff --git a/drivers/gpu/nova-core/mm/mod.rs b/drivers/gpu/nova-core/mm/mod= .rs index 6015fc8753bc..39635f2d0156 100644 --- a/drivers/gpu/nova-core/mm/mod.rs +++ b/drivers/gpu/nova-core/mm/mod.rs @@ -6,6 +6,7 @@ =20 pub(crate) mod pagetable; pub(crate) mod pramin; +pub(crate) mod tlb; =20 use kernel::sizes::SZ_4K; =20 diff --git a/drivers/gpu/nova-core/mm/tlb.rs b/drivers/gpu/nova-core/mm/tlb= .rs new file mode 100644 index 000000000000..8b2ee620da18 --- /dev/null +++ b/drivers/gpu/nova-core/mm/tlb.rs @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! TLB (Translation Lookaside Buffer) flush support for GPU MMU. +//! +//! After modifying page table entries, the GPU's TLB must be flushed to +//! ensure the new mappings take effect. This module provides TLB flush +//! functionality for virtual memory managers. +//! +//! # Example +//! +//! ```ignore +//! use crate::mm::tlb::Tlb; +//! +//! fn page_table_update(tlb: &Tlb, pdb_addr: VramAddress) -> Result<()> { +//! // ... modify page tables ... +//! +//! // Flush TLB to make changes visible (polls for completion). +//! tlb.flush(pdb_addr)?; +//! +//! Ok(()) +//! } +//! ``` + +#![allow(dead_code)] + +use kernel::{ + devres::Devres, + io::poll::read_poll_timeout, + prelude::*, + sync::Arc, + time::Delta, // +}; + +use crate::{ + driver::Bar0, + mm::VramAddress, + regs, // +}; + +/// TLB manager for GPU translation buffer operations. +pub(crate) struct Tlb { + bar: Arc>, +} + +impl Tlb { + /// Create a new TLB manager. + pub(super) fn new(bar: Arc>) -> Self { + Self { bar } + } + + /// Flush the GPU TLB for a specific page directory base. + /// + /// This invalidates all TLB entries associated with the given PDB add= ress. + /// Must be called after modifying page table entries to ensure the GP= U sees + /// the updated mappings. + pub(crate) fn flush(&self, pdb_addr: VramAddress) -> Result { + let bar =3D self.bar.try_access().ok_or(ENODEV)?; + + // Write PDB address. + regs::NV_TLB_FLUSH_PDB_LO::from_pdb_addr(pdb_addr.raw_u64()).write= (&*bar); + regs::NV_TLB_FLUSH_PDB_HI::from_pdb_addr(pdb_addr.raw_u64()).write= (&*bar); + + // Trigger flush: invalidate all pages and enable. + regs::NV_TLB_FLUSH_CTRL::default() + .set_page_all(true) + .set_enable(true) + .write(&*bar); + + // Poll for completion - enable bit clears when flush is done. + read_poll_timeout( + || Ok(regs::NV_TLB_FLUSH_CTRL::read(&*bar)), + |ctrl| !ctrl.enable(), + Delta::ZERO, + Delta::from_secs(2), + )?; + + Ok(()) + } +} diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index c8b8fbdcf608..e722ef837e11 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -414,3 +414,36 @@ pub(crate) mod ga100 { 0:0 display_disabled as bool; }); } + +// MMU TLB + +register!(NV_TLB_FLUSH_PDB_LO @ 0x00b830a0, "TLB flush register: PDB addre= ss bits [39:8]" { + 31:0 pdb_lo as u32, "PDB address bits [39:8]"; +}); + +impl NV_TLB_FLUSH_PDB_LO { + /// Create a register value from a PDB address. + /// + /// Extracts bits [39:8] of the address and shifts it right by 8 bits. + pub(crate) fn from_pdb_addr(addr: u64) -> Self { + Self::default().set_pdb_lo(((addr >> 8) & 0xFFFF_FFFF) as u32) + } +} + +register!(NV_TLB_FLUSH_PDB_HI @ 0x00b830a4, "TLB flush register: PDB addre= ss bits [47:40]" { + 7:0 pdb_hi as u8, "PDB address bits [47:40]"; +}); + +impl NV_TLB_FLUSH_PDB_HI { + /// Create a register value from a PDB address. + /// + /// Extracts bits [47:40] of the address and shifts it right by 40 bit= s. + pub(crate) fn from_pdb_addr(addr: u64) -> Self { + Self::default().set_pdb_hi(((addr >> 40) & 0xFF) as u8) + } +} + +register!(NV_TLB_FLUSH_CTRL @ 0x00b830b0, "TLB flush control register" { + 0:0 page_all as bool, "Invalidate all pages"; + 31:31 enable as bool, "Enable/trigger flush (clears when flush compl= etes)"; +}); --=20 2.34.1 From nobody Sun Feb 8 09:32:51 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012052.outbound.protection.outlook.com [52.101.43.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F589429825; Tue, 20 Jan 2026 20:44:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.43.52 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941877; cv=fail; b=UGWtFP7xC5tYAp2U9stGLQ2Svoeh6JLpTOaJ0Hx9rTo4NIoKBPlhrx8J3O8WGVY8ysjH8vlbX9JIuu5sGJkbHY8AhU6jRJ9/HoYo/vL7lR+HI/1GP5tmis2a59SdiOGs5IUxJVpCCXRrs4xdaWRb199cOOgXYZVd40TMCX1WfNA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941877; c=relaxed/simple; bh=OC3c6pGavFQpIAf2Lggesnn/u2QDN+n8wKLvb9R9Fos=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=nI79b/oKSgCcA4U66q+C8KtHwQ4owtRI39XVgS1As0W2DA46l6U0pdKV4calq0lTNEEmqDYIcd7Eqo+kN2sKeO6E38hbmJxGVzZbhlprwKifMgwuguGSomDOU5maCYjiNe6+53QGCje1nAlLcQyEQ9xMKdXJ5NulL9i+yowWvf4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=iINq9nxG; arc=fail smtp.client-ip=52.101.43.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="iINq9nxG" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=FWZ2VG4Odnz38iYyL2KWE7mAoaK9iWyoVu89Rm8ige/byVboS3zT37FVosSKG2u8EIAETVrzKnLiE6/OqzBPuD17Bc+T15lbMEPB/4lz4oHdzv5KfR86651Q6H/Ph3JFnJbf2zfSKucAdp5+W8I/57JMssvnUfg3OXiYSbOogCh/9rYPdjKGJyBGB9WdArO7/7bLz9WhG7uxoCvlHvet47l5Yp3RbsuJ8OCXUIf5ksTBvwa66AUxlqIdklFkrHnKn7X7MTtjpM9T42MLesy0HTuTD1/6pG1IOlfWs7Mx9xqbw124fNIxEIgPjLYSzDA9voHe4JgA1nZKQMqRuK4mUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=n59T/sI62CfsToz/1MW58q4KPy+lMHIfvqiYHqkPmeA=; b=XN0QmJc5XUqhpQ5FlM+kqlrTPFKFG+mipbi63+0AoDuTDpLSaaH8JExmCBaXFcMsoxfbNg6tAPXVUKsKjCwP2rjHldxcJqW9yNIO2XxiKoy35nEEFvM3o0h+0mt1yV36NjNIEWtiryS2buUpff9tQGF8Hpgpfhw5yev3DQehZ+CP+GnQQKoqm6J/WuBOJnuOCvRcupKJIvR9G/is+fYYhYJESjRvF38p7ZwLs0Wta8AcOB30kWY8D33ijcfz6GGCiZbfj/kliDeD9vnuUSTPMrM5KDNnlLFZv5uRgd7OYkvQ4OJEwp5ybcvbRctqvSbP5YZgbPpwUznCaxNmdY23SA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=n59T/sI62CfsToz/1MW58q4KPy+lMHIfvqiYHqkPmeA=; b=iINq9nxGcEb+TGYS97y3/UtwuD0DowUJKjsnFmN4aG8Qw8W2Vqz2dvL9b4xqskjaZdVI1zJ2ZPHhFnqGfFxptF83XhsrkB32aFyH/6da3+j2467PI0ST8L5Nv8LAW599jCRIWDjYcZfU/GGxCGhygUwkRzyNYytaQFJ4XZPCHlOZ6ZdlY8sgJMxWPSVcKzZwlcF39rVFK2Mbx2FmbRv90PeihE8zmqaz6d/JnWpG+hExOK28ZRhbxuZz9wxq40WKULr7nxAid/4ysfQFuA53Z++fjIs+RQrfgTB+nd7/OuvbRMNsVqEu3od5NSaia30YzrnC2EvdulyGSs0R1OwpOQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by PH7PR12MB6809.namprd12.prod.outlook.com (2603:10b6:510:1af::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.12; Tue, 20 Jan 2026 20:44:16 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9542.008; Tue, 20 Jan 2026 20:44:16 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jonathan Corbet , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Huang Rui , Matthew Auld , Matthew Brost , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Helge Deller , Danilo Krummrich , Alice Ryhl , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Alexey Ivanov , Balbir Singh , Philipp Stanner , Elle Rhumsaa , Daniel Almeida , joel@joelfernandes.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, linux-doc@vger.kernel.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-fbdev@vger.kernel.org, Joel Fernandes Subject: [PATCH RFC v6 15/26] nova-core: mm: Add GpuMm centralized memory manager Date: Tue, 20 Jan 2026 15:42:52 -0500 Message-Id: <20260120204303.3229303-16-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120204303.3229303-1-joelagnelf@nvidia.com> References: <20260120204303.3229303-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BLAPR05CA0019.namprd05.prod.outlook.com (2603:10b6:208:36e::24) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|PH7PR12MB6809:EE_ X-MS-Office365-Filtering-Correlation-Id: 65527064-d98f-420e-65fa-08de5864ad4a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|7416014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?zCvglsB+xuoYhW333MrXxWNpXxjZkrJR44eAewxgp8bgabadP4RR+hgyoXa0?= =?us-ascii?Q?MvJVEhC9B+P1m1jOsJfbHxije5vjNAaxK8H4pusvzCtVegW7CVYrznuTNiLU?= =?us-ascii?Q?XRgdKRnO8j9QE3hAqH7mcBwD9s8Vma6oNb3pTorQVeWflqk+sPHwMrut/i3E?= =?us-ascii?Q?Y9rOjtT+h78azlO21SOyH43w7MZo70VACK+7TKpm4q5reZ5sgEhqKcS8KHje?= =?us-ascii?Q?gVrF3gcvtP/kzNGXlAElimoj1roVLiu8mK27vKOJYEEOW8PAn9HAyPuMa/4X?= =?us-ascii?Q?dzdOlpgCjdmQKDyDhoRXeK8q1VaqMDMV4hTqAypQou6BvuOws4V/GdyPncZM?= =?us-ascii?Q?XTaLFdDFLq5tQLfBfiEYlm47U5LWpI3qzgiCKfEfMDPyS+y4eyDJ+6qSPwe+?= =?us-ascii?Q?KXQ9h7QDwwThhJFuztcTQE0a2KmheUmASyq1IZWwnvdgrGhVZ0PQOmC2GYg8?= =?us-ascii?Q?DUCfa4nuhT5kcDFfgbfjr4H6J9zPkSerHKBNlO2/ZWmvgqTj5rYLWiq5ndcJ?= =?us-ascii?Q?Mi8Ob+v1et6LOgesNGgzRDOXikLZnGnff9xWAXuZjceFeGiQ6BzoM+yuEQ8B?= =?us-ascii?Q?rDfZupi7bi9tcUBhxGFoQ2MVZgtyI15OtH9sIhyzd4rVPFd31vcIq6j9G4tq?= =?us-ascii?Q?9Velixhtk+5P6i4XNVCybKC5vp9w0cuyj5Vaz/b1FDd/5I5xtjIeo4e+QLlI?= =?us-ascii?Q?oXZDTHuKYBrz1FkA0Abs6Vn0L9sxr99vl7zE6713uSCzT0iVglX1ohKfbWiA?= =?us-ascii?Q?TV1+EnABk+D4z4o07PbwJz/vspVVJI7FYC5fIYZZyv55DCVXCbAC0SG59PPc?= =?us-ascii?Q?/Ch9gF9HfcCgVRdwtdlTf6acYfY4+hd9qBDX8nIFpKy/MEFrjfZu/msEYLFj?= =?us-ascii?Q?kmtHxt+qh5TJSK9TpW+dw4VSHsmWS7VJFHez0fvLDlkXeHnQ4p5aCSXUJ54P?= =?us-ascii?Q?5wonK/JDOuiCNo0XlheEsqsBKYKxjiiOkQWZmFAMVRjohtaFJgUlYxXsueYp?= =?us-ascii?Q?GVA1pGmqQPYtuq3Cf6ndwKRA+8nkNDUEVC7dXyg03tlXazDpT+PJz0gZrHhk?= =?us-ascii?Q?2ALXik/c3VJWHv8p8jNnd6+aAakvldhYBrkI/WhQqxnkL9uGpn2wkGJU8nL6?= =?us-ascii?Q?4mPiq8GRmziRsn+KPaniV1+nMRz3Ggl3dO0ULY744ALZZm5H9Q/8v4KYUz8r?= =?us-ascii?Q?DYh27TwxSvpgzlrlQVMureZm0E1vUl881vtJ9oR1cWV0jWIhd+ROiBuCHkfZ?= =?us-ascii?Q?Ann0efN80oYJ1IxAF63XtGexrpi6z6lTwUXTnghyoKU6g6iVaxQQeSxHnh0r?= =?us-ascii?Q?8PYtyewE8xIFcq6gKCDm//82v/6+oo2QaGbjgR9taFsaFSHyN6SSHR7q43l8?= =?us-ascii?Q?uVUpzRf8dPqzmBstM1w5CCr6vDizWrlUmV4Qq0p7h3rjlyKefNndzFL9WYvD?= =?us-ascii?Q?pWUKqPRbPgluINvHa/QNYShT7HRIjxMrZbwjNFjRnYHtrCX6wmie1EoHM626?= =?us-ascii?Q?idsCVKqPLe5cWwGvNmTikRPASFiBTCIba3XrrLgODTzGh48uPtjmdgFCTM0s?= =?us-ascii?Q?Tznp7cOgrFJi7mgyHSE=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR12MB6486.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(376014)(7416014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?hXWbXFmqzucuA13V/XT8sWg10uGAky6Zta7BoDXBWdT5NLjAmluFotCDcwRY?= =?us-ascii?Q?Z2HxUv1MG/eFdmhx7RGCXkyW8X66x0IIgfin2S/V0tYja0iLpylvEvy5pQdE?= =?us-ascii?Q?p4qQ/bUUjzG5oMp+ZNlKKxPE/D/DOMeSy2POgQ/gUOpAKKv87VMQ3iDsTzac?= =?us-ascii?Q?/lSlZkFz368eGb1LTp7mjN46tKgqTGcVFjg8eqVCaP695vH/Yxw+I/VGI1WX?= =?us-ascii?Q?VHR1P7gJedIWagbItx0MPOuiTjQ0+vmlRwsp98JeItZW3ADQWhebmTnj2n6j?= =?us-ascii?Q?jo9uPXwuYFlqbTelVAjj1tNPUvW1R2nVbj/JLl/wHYyTtOpaJXGOhP+lrvp4?= =?us-ascii?Q?dFIQEYLjKwkp25V9O4zqoVpww7vpFLuEseFdDMQAuSaDVu+C8oWnj6fJYJBo?= =?us-ascii?Q?UuwSBSHBJjv0TWHg9GRnn/PsNmFdp/u99CBK+fOONex2YDz10aslzz8vEr7p?= =?us-ascii?Q?TtEowIhO/wrK6Yksj9VnQyhTwLkrcQ+isqD3y5Pao5hlTT8nqJ44XNae9z7W?= =?us-ascii?Q?u3JUSn8qrjXYJIuy2Zn/VQfzGu00V360Ei/8nHEx5lpkVEnLP6TeEJZ2Fgl/?= =?us-ascii?Q?EYkT6psAVBsgHhA2D4txIHXW7I2WqKxjkrYh2IphA6gZiIP/1vx8WVvr1gSZ?= =?us-ascii?Q?iv+bz4OtuCBwkvzrU/2ZbebxTvUnbtKbkKU2atcQP6lqIVvQKiur7RyC/qBN?= =?us-ascii?Q?rmGc5jEYD08dT9dDsKEMJPw9ovtSc0WME9P+n3DH4KxPScV/Jz4vvh/rIoKw?= =?us-ascii?Q?r9xNUW628AY+fibw1nl9DxOT9BGJz0Ec/4KdoR57odmW09vjEsXiXoP7oXbR?= =?us-ascii?Q?lyFYYtRiZcE4buYMqiEJhs8s1uUMCmQ4jL4LkVPIshuEQcq6GA3QHDcPEWmR?= =?us-ascii?Q?5ln4xka7N3Rg6a2ePXlifgaTl/fiJmkyyLZ155bakOWsXRnHDwFKieH/E8Bh?= =?us-ascii?Q?xo0U7GUtx52igvf5tXGDmZUMoF/tPTHKx1GjPbKxNruxsWVr7O4V08006epX?= =?us-ascii?Q?YLGTYzza5NI8sg/MuJ8wIuCny1i60qc7zVBWzQxy/pfI147pftcFZ3gvMIt6?= =?us-ascii?Q?mvge/33Koh8O6dyIPeCHxdOpnI5tB1xFHABtohMM9EyFBuJDvMsGobwBVAOd?= =?us-ascii?Q?aaFtfu6f0H+0ZTl8i2hoxTv4lQd/MV9GVZiUK94u5ouo7XqX5oAI9SDkE21C?= =?us-ascii?Q?e2KmL1xRoG/BqUDxvFe0ovG1RU88TChzGPdSciNwDz9YccF8Fd6PO8Hhk8Nj?= =?us-ascii?Q?TO+lctGffxil8RBgh9a6CdskIH7GkeowR3VSX2U1AEHTETE+Dd3AAOuQwN8H?= =?us-ascii?Q?ND0Q29lVsY0v6As0PtHDd8zE+u5+RFFuEC1bJaB/VfTdmj0EX70YJvvMXD17?= =?us-ascii?Q?+OUmwi41g1psYe3CiYg4qpBNyw5OMWrhm0jBYN0UK/VjpWOd+HbzdM6Sd04I?= =?us-ascii?Q?h61aE93AAbYGgG8Xbz0F5Qhu4ovTUFMzMDRxr68G2qiE/cl953cATKxXUgXv?= =?us-ascii?Q?H+yU3wWJ7a/iY2hnXzgts7w9jpGO9hkdRV7xlXFO5EcLkprkD6WBRA8nrr3A?= =?us-ascii?Q?XTJ89rYB8iGV+Y+dUlUt0MepANeKCQRpigWiHXc6GLfVGMBeBsD67isfd7ft?= =?us-ascii?Q?1pH0sQ1TAn54Z883RqyhB2haN18fsqk/a9KY0GFoAsdUGaz/EzFhfrvr6z+N?= =?us-ascii?Q?ZWwdvlSWL5k39ftfNnpkUkAFgzzdwCbqpSZKVpyuA/7ki9vFOr7rOU8TsvpG?= =?us-ascii?Q?DvlY15OpPA=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 65527064-d98f-420e-65fa-08de5864ad4a X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB6486.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 20:44:16.1794 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: k9uMqTDR7dlA5H7w4wm5aknAO5sqxFG+ewLM6FdWSCEZ6LTZD3/JtxVa4g0Jrnx6a6dsuof1/dbMIkipw1KexQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6809 Content-Type: text/plain; charset="utf-8" Introduce GpuMm as the centralized GPU memory manager that owns: - Buddy allocator for VRAM allocation. - PRAMIN window for direct VRAM access. - TLB manager for translation buffer operations. This provides clean ownership model where GpuMm provides accessor methods for its components that can be used for memory management operations. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/gpu.rs | 14 +++++++++ drivers/gpu/nova-core/mm/mod.rs | 55 ++++++++++++++++++++++++++++++++- 2 files changed, 68 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 9b042ef1a308..572e6d4502bc 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -4,8 +4,10 @@ device, devres::Devres, fmt, + gpu::buddy::GpuBuddyParams, pci, prelude::*, + sizes::{SZ_1M, SZ_4K}, sync::Arc, // }; =20 @@ -19,6 +21,7 @@ fb::SysmemFlush, gfw, gsp::Gsp, + mm::GpuMm, regs, }; =20 @@ -249,6 +252,8 @@ pub(crate) struct Gpu { gsp_falcon: Falcon, /// SEC2 falcon instance, used for GSP boot up and cleanup. sec2_falcon: Falcon, + /// GPU memory manager owning memory management resources. + mm: GpuMm, /// GSP runtime data. Temporarily an empty placeholder. #[pin] gsp: Gsp, @@ -281,6 +286,15 @@ pub(crate) fn new<'a>( =20 sec2_falcon: Falcon::new(pdev.as_ref(), spec.chipset)?, =20 + // Create GPU memory manager owning memory management resource= s. + // This will be initialized with the usable VRAM region from G= SP in a later + // patch. For now, we use a placeholder of 1MB. + mm: GpuMm::new(devres_bar.clone(), GpuBuddyParams { + base_offset_bytes: 0, + physical_memory_size_bytes: SZ_1M as u64, + chunk_size_bytes: SZ_4K as u64, + })?, + gsp <- Gsp::new(pdev), =20 _: { gsp.boot(pdev, bar, spec.chipset, gsp_falcon, sec2_falcon= )? }, diff --git a/drivers/gpu/nova-core/mm/mod.rs b/drivers/gpu/nova-core/mm/mod= .rs index 39635f2d0156..56c72bf51431 100644 --- a/drivers/gpu/nova-core/mm/mod.rs +++ b/drivers/gpu/nova-core/mm/mod.rs @@ -8,7 +8,60 @@ pub(crate) mod pramin; pub(crate) mod tlb; =20 -use kernel::sizes::SZ_4K; +use kernel::{ + devres::Devres, + gpu::buddy::{ + GpuBuddy, + GpuBuddyParams, // + }, + prelude::*, + sizes::SZ_4K, + sync::Arc, // +}; + +use crate::driver::Bar0; + +pub(crate) use tlb::Tlb; + +/// GPU Memory Manager - owns all core MM components. +/// +/// Provides centralized ownership of memory management resources: +/// - [`GpuBuddy`] allocator for VRAM page table allocation. +/// - [`pramin::Window`] for direct VRAM access. +/// - [`Tlb`] manager for translation buffer flush operations. +/// +/// No pinning required, all fields manage their own pinning internally. +pub(crate) struct GpuMm { + buddy: GpuBuddy, + pramin: pramin::Window, + tlb: Tlb, +} + +impl GpuMm { + /// Create a new `GpuMm` object. + pub(crate) fn new(bar: Arc>, buddy_params: GpuBuddyParams= ) -> Result { + Ok(Self { + buddy: GpuBuddy::new(buddy_params)?, + pramin: pramin::Window::new(bar.clone())?, + tlb: Tlb::new(bar), + }) + } + + /// Access the [`GpuBuddy`] allocator. + pub(crate) fn buddy(&self) -> &GpuBuddy { + &self.buddy + } + + /// Access the [`pramin::Window`]. + pub(crate) fn pramin(&mut self) -> &mut pramin::Window { + &mut self.pramin + } + + /// Access the [`Tlb`] manager. + pub(crate) fn tlb(&self) -> &Tlb { + &self.tlb + } +} =20 /// Page size in bytes (4 KiB). pub(crate) const PAGE_SIZE: usize =3D SZ_4K; --=20 2.34.1 From nobody Sun Feb 8 09:32:51 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013036.outbound.protection.outlook.com [40.93.201.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72C7F44D026; Tue, 20 Jan 2026 20:44:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.201.36 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941882; cv=fail; b=rwms+WS4vjoU3YRx2NtLATXG6RFhhpfAYCm67o9vTEIr5eSdfJ3HjvskZT5NhbIohX/ixtuP032qTEzMFjQ8lpwjEplQxRxtmwNywwtUWdedRRF5olztKnFGAVZMEVLsBjfTtYHqBBM1kQ4efEY8vzJxMRd0c8rIkPtRB64DUrE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941882; c=relaxed/simple; bh=yUfxYh8UhqiO+TKXhjFf5cXGtP4kyZyK+kij775+lVQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=LMhCbBtbS+0bDugz8dzzime1u5VQFU4Khhxu47VHlBIdQbUM3gfZdum3PY+42HXzHcgjPaFcqbd+T/p892PzltNmv8mYm4F9g1cewjZYkvzDzgsQ8PaO5BkCFM+1fLiBLKWn0q8nMFFnyuwCZllXLUI/ae7NSHmiIG3uOqQmITo= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=sMP6RG6l; arc=fail smtp.client-ip=40.93.201.36 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="sMP6RG6l" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=mFP5GRT7jHgFEBtQzFC2RhFWqe8If8PZYMVQFQuyZ8id0QlRy+mY8PKOeRRD4ggG7ednsaF7O6wx9QIICRxHocxV1+cDOOy5IrJMlJduSLNbXVgzykQQkf6afoM9QI9eC8jn3C+tJ6XbBvRUxk1MoPdAXr6UGu084Fin9b+WvDb7DeK3wg0v+CJDBZgzbYu2bRP9pNCpVl8KmLeY6KHHbxOG4uKKioQCwecjUE68hZ9vVRTjjLHQHjAKDgv5nh6iU6RiZpdKUFtmCov32Yhtc1CS658oWzAmFNi4TSiaq+Ivi4tP4510847MpXpF+OHpW3Pw220GMs+iU5wtLjAdOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=IdALN0+ugbE7soKMWIcyQimRjhw6yH36lTEVBrFkBGI=; b=aF2dmZSZ1Lrkq10dZzoMgIi7uoDgwuG3vekZ+QCoOJOoLS4VeEP1jzT9tZLGSy4Zris6hcHyqOiyzgJ9OMk4ar5mWUZh1G69SfAWC/3JwWHnix9zqlT8QIT4wHoMuoUNCM4B8Bo5o9WTZoJFsHqTUKLMeeTF0Rr7OmEkQk6pI7DJPUHgtFKqD1CGZsD/l6+Xc+tPiDktTegCX4DeVnxaQFsgdXP6dnzWnwQOvIC+GfuoYxLl3fIhw8zCCbAyoOVjLRakos/1LLN3/2gJVIOoyqxG8exbqJefN9ZXRxjA4COq60N/PYovy4IaqRORgGzavbkAf1VJyaLLjho755uqTg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=IdALN0+ugbE7soKMWIcyQimRjhw6yH36lTEVBrFkBGI=; b=sMP6RG6liok1U4yS4ThVRHCKNQhFgsz1DZGh1CHmVd7c/I+vsZdcG9itLcl2eQF2GHUHrhg+bjlFESP+r7c1t1nAA1kINhNwjSa8to/wOk6OZeQ2tKavzxoHT8pwhO9CdbagHMWPjVGLsfFEJYuh9TnrzsOfVJJntSgsFbX5DP+M4BgJDceF+2O8RuusgTFxje8pFf7w8doXrSsVIBaTKDLjT6urz3yKqe4uKEo36wqYczrBWHx/uXgQb5o2f50Ekxe3ojUr6Vpr117NkR82l1VZwWsHh0L0RToCKKLsWagKteNoP28iZbTAPbLhZ4hOnXe6Y6odNfCINXbNTqdGkg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by PH7PR12MB6809.namprd12.prod.outlook.com (2603:10b6:510:1af::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.12; Tue, 20 Jan 2026 20:44:17 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9542.008; Tue, 20 Jan 2026 20:44:17 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jonathan Corbet , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Huang Rui , Matthew Auld , Matthew Brost , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Helge Deller , Danilo Krummrich , Alice Ryhl , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Alexey Ivanov , Balbir Singh , Philipp Stanner , Elle Rhumsaa , Daniel Almeida , joel@joelfernandes.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, linux-doc@vger.kernel.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-fbdev@vger.kernel.org, Joel Fernandes Subject: [PATCH RFC v6 16/26] nova-core: mm: Add page table walker for MMU v2 Date: Tue, 20 Jan 2026 15:42:53 -0500 Message-Id: <20260120204303.3229303-17-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120204303.3229303-1-joelagnelf@nvidia.com> References: <20260120204303.3229303-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BLAPR05CA0020.namprd05.prod.outlook.com (2603:10b6:208:36e::23) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|PH7PR12MB6809:EE_ X-MS-Office365-Filtering-Correlation-Id: afc0fb6d-94f1-4f0a-1c52-08de5864ae1d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|7416014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?OIELYioqrIeMAAuJDJ9PcviPMa5bDUhs37n4Y+kqS3ivu6wZc+vc5yp3abqu?= =?us-ascii?Q?YjyK6JjHD22cESO7eU+kEHBoegLOLCrQoZinbY4t5RZMdtwNBd39TVj/dzY2?= =?us-ascii?Q?E5x1ZWDAzStMqaJhbW8dof1dibjDApp236DgQ/BGPPTZOtG2x4ZuqKXYrjPE?= =?us-ascii?Q?f5dOBGOECqclTuj05ntKHetrx31c4VdzjpTN4cj9jwGx7dxn0WwCA4SJkt4u?= =?us-ascii?Q?UF3Hl1XW4y+kdZImt1J+WX7HHobN0F1EupQz+NrobzUHPlazoOt8MBBGEDnQ?= =?us-ascii?Q?oUDhNxSAyJQCZA2ZP2Yf1uKq8jImu6O4izbUtkuwEpAI/muoQUFNreG038Ad?= =?us-ascii?Q?gme+LT87ffTwovLYoAepSNCgsWM6kkhBsyqSD42Bpp4qTIvgZ5tWsZLIkwW7?= =?us-ascii?Q?ip1E47+GQxOwrniFakXe6P6+Ei+RDUw/LLvM5GymcKQ1v+xm5DswIfaT1OGU?= =?us-ascii?Q?b03KC8tefU5cT2TrLZ2ytHxkPZ1tLVnPJxivmAqI9kwHAu3lb7jGOcW67ge3?= =?us-ascii?Q?iOZmpPcke0ScpZq0I0rm6haYlnrZxoAerrXDqOf0UgdUvSPAFX6TgPwNaLoC?= =?us-ascii?Q?MhYTI5MPrMwt+nkyIbCa4OAWlvYf/NcnAR7G3Hsu0g8/9TjN0ZWxaV8IGgAx?= =?us-ascii?Q?bOx54vcWMc4HHIPHWmCw61OxG8LGWvSjrKo1N00Qbw5DBH7yEYrWMaV9ZFR0?= =?us-ascii?Q?tQJBfKOZPbk5PW/8tJ1VqeQlE8s+HQUmlnNGqd1vP983m1zo1hat8/8jxcEb?= =?us-ascii?Q?gXLysrX2GR93BU0W5bDoRDXSG7YpTd0jLPPcSff2WBT4ye1mQswtx4QxgG/M?= =?us-ascii?Q?yIStIyL1C/cA/pRmFUpT+38eljLDcfnoNEGdMKo5KV+WbFHlVGaqm/A8w6No?= =?us-ascii?Q?4KFFWJ97Um3uPo1e8jE2XbQAwlhd9NBbC2stpMZMKhmyT+q1x3jL7LI2mXHf?= =?us-ascii?Q?TdxulYw+VC71G+H6APusnqtnuBnE7dUmvHDNuDpyxqG/mExxG8NaAYCA7HAf?= =?us-ascii?Q?+QM4zoVX23ejCgfZl0oTj1+X+gfyJelXm58TXQr/mQHyR8jYev2xp5IUWXXH?= =?us-ascii?Q?OGCzdSo7zpIZQFOP61z2B8AYp1Def8VONktb7LqGCoUNqLj0Iif0K9/nt//H?= =?us-ascii?Q?kh9w+GIryjSJnnEoHWTTenKzYhlMSgJNU9faWF/bTIbmjFuHO8iylbmAosdL?= =?us-ascii?Q?3nxVU/nk9TpSPBLEzNRaK5tuvE00Pe3WFdbYi6Fo1HqVNu3nlb+hlJzS82mL?= =?us-ascii?Q?/B0kd8P59prdvWIX6D1ugfO5pK1JONe/XurGLCUYcJEOVYPCmVGDpJn8rp06?= =?us-ascii?Q?I/UldAY3XDwdUAW9/cQ79Uch5xKXzT3QEgztljB9mwJbxpJfzuRHZKfbfOGa?= =?us-ascii?Q?oqC6Lpzxg0WN/wxnEeX7FRVsTIRhrXAhMzgPDxB8GhgmVLnhRGm8HzGN6ewB?= =?us-ascii?Q?CPii2GLXqvKnhtoF8cWE9UCliV4zSbSAubcaXUk8eOhRAy3db3Bk9ftDBPMx?= =?us-ascii?Q?bOhPfFH7mDszP8v7P5vy9JDp601BWDLy1phUTi5O4AUeBBHSffkOF9ouZDsu?= =?us-ascii?Q?cxGLzX7xx//gc0Esgyk=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR12MB6486.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(376014)(7416014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?3ghF85w9HCeLIleeSomMGDU+ntK3P7pvMVjm/queaIB11JAAJ3hhRqEk9EvN?= =?us-ascii?Q?c48/XyojX8Y/oNQuaicqLuhRFfByNh17cT0QdUuerlbqJlEMBs2hmbJStT3M?= =?us-ascii?Q?qiNjhrlKfKcPoUHBrLxAhAdoLVd3PvKwO1cV8/9rWnjbZW5OBrUSKCBZg3Ha?= =?us-ascii?Q?ukNO1uyLjh0QnyYH65Ueog0o9TImbY15Fv374ri41XHOSQAENQjgqjR5yFb1?= =?us-ascii?Q?XPcRblrL+mTTAyTluj79GjXvM8i1PETtDhEwFVFfJf7N+lB1tpp54uAu0SjX?= =?us-ascii?Q?NfQnHW33aGEBYXJTxQcBWZsk6tivElKKOpDeIBHrkYo6mBzprDxMpUcQnYgF?= =?us-ascii?Q?gFKyjQI8wrTUVJjTp65i0B+r8ZuzQujcG7o/IEi8buswkrxDa+yEhZDF046a?= =?us-ascii?Q?HxVzhugLU3FXPFn14wJhstuMdkHhP8tkf1lhhe7C96GJi1Myf0/5hUGmcwBM?= =?us-ascii?Q?hm8JA222cOhkqUra81x1h/jAueSqRyJJXO8jM5G9i1D3rX+pYggRl0Ykvd2D?= =?us-ascii?Q?vFKAWYgs5athXcDcselJWtEWj0RA1EmimvWlVNQ3OdLG1m2OFwrBlgbysC8y?= =?us-ascii?Q?gvuhiifP7O4ZYWcdbU2ejFBOjyzuZe8zbwJM0hHhRNgf1oJTtcni/RUiZPy0?= =?us-ascii?Q?ynK700YeYVc2btzBJVvnS7fsErjgpeAp/Xn7U9C4+qXxKQVTMMankPQdlmF3?= =?us-ascii?Q?4KNJeyadCNWZroKcgvUE1cfnEfFdlpzQM2wWgAvg16y5kXZtS7i5C1GsgKB4?= =?us-ascii?Q?FJrOxIMrDanaaf7R+6zv5+X7WDWhTeosnSa647dT7+GSvsKJEvKkIlYZBwhA?= =?us-ascii?Q?7zodLr/3iEvOghxVcobBWiYYbIMX29inKZt3V8H2LOBIbOzwiQryGRhHnHye?= =?us-ascii?Q?S/iGaKfKL3/sXmk3FsoWWlG1tzfM2l1X0QaQlaVzrygtASH5Jga6yu9GL5pF?= =?us-ascii?Q?/Ftm3YzI9QbmWQF/BpkE2DpaP4VzOsfMDWef0iIexzhNKba6ZLmGWScakRj/?= =?us-ascii?Q?zc432uTnyuxGd8AkyvbFaAJJuKkyON06og2ucUWbi9jwE2V3YiUk+7EHdYX5?= =?us-ascii?Q?8CmqAbceCzAuFvpnrx4eSwNTPt2CnL4bKDPEeMovnPPL58W5Va2v9JKkyNKV?= =?us-ascii?Q?YAk3TmlFt3ktIGyMaNdIh3Pt/9P+lQo3KyGlYXazSU/CfXUBdFP+8URwNECW?= =?us-ascii?Q?uD6XfJ2sVgeb3gvwj5G0Hl4Ueh0/NkdKvgle/ByS54/2NiDSsSr7jz448V72?= =?us-ascii?Q?3bAKCTzSATvuClCGA2yi3ZaG1PIzPYyM/SAGBGNP6Edkt38B2SJsxSomqekP?= =?us-ascii?Q?8YQdRwbMQYvF+xhjRJAchd0dkc1itzAuwOC5FcSgQ/AEIjMIlLa9YAOQqi3k?= =?us-ascii?Q?/2cKbVi7z0zj71Ot2oPV+K3t49Dm3NNpvBT2bcGET0jbyfQNdv0PfmSAhVsi?= =?us-ascii?Q?G98I2lKy+f5ShZTrSmNh1xiyRA3E9WwnbKjYwFDVWdmB9Zwqyugo2XDqSp0A?= =?us-ascii?Q?81TbHhUPOhuaqLvx6Pbk/WqkkttPg3vmtdGbrdnTgeqSp83ZVunLuz6Wu4Fz?= =?us-ascii?Q?Ep/QsawyizyrFw4abbgPUZidB7Dln8jzazjW7Lb7YD+NOsHssUOMWi06HeCq?= =?us-ascii?Q?UrPTi5ocxVUl2LVNQWIRcd9V309eU29JD1NScnbHncN8icKA4BXHVyXPYcO/?= =?us-ascii?Q?108RjqOfgxl30x0vv066PwZbJoCzjQDDwsKUyo+YYSwIJKkPxPpzkg5SFIWl?= =?us-ascii?Q?EYzzi9E/cQ=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: afc0fb6d-94f1-4f0a-1c52-08de5864ae1d X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB6486.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 20:44:17.6162 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: I5bx4xCiedV5YDHzVUo5Q+Esl0wfI9qp3jdd+ec1NLiQ6OevaeARg89wrrTFREFzUw/aBb7AgX+WBYsFP++1bA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6809 Content-Type: text/plain; charset="utf-8" Add the page table walker implementation that traverses the 5-level page table hierarchy (PDB -> L1 -> L2 -> L3 -> L4) to resolve virtual addresses to physical addresses or find PTE locations. The walker provides: - walk_to_pte_lookup(): Walk existing page tables (no allocation) - Helper functions for reading/writing PDEs and PTEs via PRAMIN Uses GpuMm API for centralized access to PRAMIN window. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/mm/pagetable/mod.rs | 13 + drivers/gpu/nova-core/mm/pagetable/walk.rs | 285 +++++++++++++++++++++ 2 files changed, 298 insertions(+) create mode 100644 drivers/gpu/nova-core/mm/pagetable/walk.rs diff --git a/drivers/gpu/nova-core/mm/pagetable/mod.rs b/drivers/gpu/nova-c= ore/mm/pagetable/mod.rs index 72bc7cda8df6..4c77d4953fbd 100644 --- a/drivers/gpu/nova-core/mm/pagetable/mod.rs +++ b/drivers/gpu/nova-core/mm/pagetable/mod.rs @@ -9,12 +9,25 @@ #![expect(dead_code)] pub(crate) mod ver2; pub(crate) mod ver3; +pub(crate) mod walk; =20 use super::{ + GpuMm, Pfn, VramAddress, // }; use crate::gpu::Architecture; +use kernel::prelude::*; + +/// Trait for allocating page tables during page table walks. +/// +/// Implementors must allocate a zeroed 4KB page table in VRAM and +/// ensure the allocation persists for the lifetime of the address +/// space and the lifetime of the implementor. +pub(crate) trait PageTableAllocator { + /// Allocate a zeroed page table and return its VRAM address. + fn alloc_page_table(&mut self, mm: &mut GpuMm) -> Result; +} =20 /// MMU version enumeration. #[derive(Debug, Clone, Copy, PartialEq, Eq)] diff --git a/drivers/gpu/nova-core/mm/pagetable/walk.rs b/drivers/gpu/nova-= core/mm/pagetable/walk.rs new file mode 100644 index 000000000000..7a2660a30d80 --- /dev/null +++ b/drivers/gpu/nova-core/mm/pagetable/walk.rs @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Page table walker implementation for NVIDIA GPUs. +//! +//! This module provides page table walking functionality for MMU v2 (Turi= ng/Ampere/Ada). +//! The walker traverses the 5-level page table hierarchy (PDB -> L1 -> L2= -> L3 -> L4) +//! to resolve virtual addresses to physical addresses or to find PTE loca= tions. +//! +//! # Page Table Hierarchy +//! +//! ```text +//! +-------+ +-------+ +-------+ +---------+ +-------+ +//! | PDB |---->| L1 |---->| L2 |---->| L3 Dual |---->| L4 | +//! | (L0) | | | | | | PDE | | (PTE) | +//! +-------+ +-------+ +-------+ +---------+ +-------+ +//! 64-bit 64-bit 64-bit 128-bit 64-bit +//! PDE PDE PDE (big+small) PTE +//! ``` +//! +//! # Result of a page table walk +//! +//! The walker returns a [`WalkResult`] indicating the outcome: +//! - [`WalkResult::PageTableMissing`]: Intermediate page tables don't exi= st (lookup mode). +//! - [`WalkResult::Unmapped`]: PTE exists but is invalid (page not mapped= ). +//! - [`WalkResult::Mapped`]: PTE exists and is valid (page is mapped). +//! +//! # Example +//! +//! ```ignore +//! use crate::mm::pagetable::walk::{PtWalk, WalkResult}; +//! use crate::mm::GpuMm; +//! +//! fn walk_example(mm: &mut GpuMm, pdb_addr: VramAddress) -> Result<()> { +//! // Create a page table walker. +//! let walker =3D PtWalk::new(pdb_addr, MmuVersion::V2); +//! +//! // Walk to a PTE (lookup mode). +//! match walker.walk_to_pte_lookup(mm, Vfn::new(0x1000))? { +//! WalkResult::Mapped { pte_addr, pfn } =3D> { +//! // Page is mapped to the physical frame number. +//! } +//! WalkResult::Unmapped { pte_addr } =3D> { +//! // PTE exists but the page is not mapped. +//! } +//! WalkResult::PageTableMissing =3D> { +//! // Intermediate page tables are missing. +//! } +//! } +//! +//! Ok(()) +//! } +//! ``` + +#![allow(dead_code)] + +use kernel::prelude::*; + +use super::{ + DualPde, + MmuVersion, + PageTableAllocator, + PageTableLevel, + Pde, + Pte, // +}; +use crate::mm::{ + pramin, + GpuMm, + Pfn, + Vfn, + VirtualAddress, + VramAddress, // +}; + +/// Dummy allocator for lookup-only walks. +enum NoAlloc {} + +impl PageTableAllocator for NoAlloc { + fn alloc_page_table(&mut self, _mm: &mut GpuMm) -> Result= { + unreachable!() + } +} + +/// Result of walking to a PTE. +#[derive(Debug, Clone, Copy)] +pub(crate) enum WalkResult { + /// Intermediate page tables are missing (only returned in lookup mode= ). + PageTableMissing, + /// PTE exists but is invalid (page not mapped). + Unmapped { pte_addr: VramAddress }, + /// PTE exists and is valid (page is mapped). + Mapped { pte_addr: VramAddress, pfn: Pfn }, +} + +/// Page table walker for NVIDIA GPUs. +/// +/// Walks the 5-level page table hierarchy to find PTE locations or resolve +/// virtual addresses. +pub(crate) struct PtWalk { + pdb_addr: VramAddress, + mmu_version: MmuVersion, +} + +impl PtWalk { + /// Create a new page table walker. + /// + /// Copies `pdb_addr` and `mmu_version` from VMM configuration. + pub(crate) fn new(pdb_addr: VramAddress, mmu_version: MmuVersion) -> S= elf { + Self { + pdb_addr, + mmu_version, + } + } + + /// Get the MMU version this walker is configured for. + pub(crate) fn mmu_version(&self) -> MmuVersion { + self.mmu_version + } + + /// Get the Page Directory Base address. + pub(crate) fn pdb_addr(&self) -> VramAddress { + self.pdb_addr + } + + /// Walk to PTE for lookup only (no allocation). + /// + /// Returns `PageTableMissing` if intermediate tables don't exist. + pub(crate) fn walk_to_pte_lookup(&self, mm: &mut GpuMm, vfn: Vfn) -> R= esult { + self.walk_to_pte_inner::(mm, None, vfn) + } + + /// Walk to PTE with allocation of missing tables. + /// + /// Uses `PageTableAllocator::alloc_page_table()` when tables are miss= ing. + pub(crate) fn walk_to_pte_allocate( + &self, + mm: &mut GpuMm, + allocator: &mut A, + vfn: Vfn, + ) -> Result { + self.walk_to_pte_inner(mm, Some(allocator), vfn) + } + + /// Internal walk implementation. + /// + /// If `allocator` is `Some`, allocates missing page tables. Otherwise= returns + /// `PageTableMissing` when intermediate tables don't exist. + fn walk_to_pte_inner( + &self, + mm: &mut GpuMm, + mut allocator: Option<&mut A>, + vfn: Vfn, + ) -> Result { + let va =3D VirtualAddress::from(vfn); + let mut cur_table =3D self.pdb_addr; + + // Walk through PDE levels (PDB -> L1 -> L2 -> L3). + for level in PageTableLevel::pde_levels() { + let idx =3D va.level_index(level.as_index()); + + if level.is_dual_pde_level() { + // L3: 128-bit dual PDE. This is the final PDE level befor= e PTEs and uses + // a special "dual" format that can point to both a Small = Page Table (SPT) + // for 4KB pages and a Large Page Table (LPT) for 64KB pag= es, or encode a + // 2MB huge page directly via IS_PTE bit. + let dpde_addr =3D entry_addr(cur_table, level, idx); + let dual_pde =3D read_dual_pde(mm.pramin(), dpde_addr, sel= f.mmu_version)?; + + // Check if SPT (Small Page Table) pointer is present. We = use the "small" + // path for 4KB pages (only page size currently supported)= . If missing and + // allocator is available, create a new page table; otherw= ise return + // `PageTableMissing` for lookup-only walks. + if !dual_pde.has_small() { + if let Some(ref mut a) =3D allocator { + let new_table =3D a.alloc_page_table(mm)?; + let new_dual_pde =3D + DualPde::new_small(self.mmu_version, Pfn::from= (new_table)); + write_dual_pde(mm.pramin(), dpde_addr, &new_dual_p= de)?; + cur_table =3D new_table; + } else { + return Ok(WalkResult::PageTableMissing); + } + } else { + cur_table =3D dual_pde.small_vram_address(); + } + } else { + // Regular 64-bit PDE (levels PDB, L1, L2). Each entry poi= nts to the next + // level page table. + let pde_addr =3D entry_addr(cur_table, level, idx); + let pde =3D read_pde(mm.pramin(), pde_addr, self.mmu_versi= on)?; + + // Allocate new page table if PDE is invalid and allocator= provided, + // otherwise return PageTableMissing for lookup-only walks. + if !pde.is_valid() { + if let Some(ref mut a) =3D allocator { + let new_table =3D a.alloc_page_table(mm)?; + let new_pde =3D Pde::new_vram(self.mmu_version, Pf= n::from(new_table)); + write_pde(mm.pramin(), pde_addr, new_pde)?; + cur_table =3D new_table; + } else { + return Ok(WalkResult::PageTableMissing); + } + } else { + cur_table =3D pde.table_vram_address(); + } + } + } + + // Now at L4 (PTE level). + let pte_idx =3D va.level_index(PageTableLevel::L4.as_index()); + let pte_addr =3D entry_addr(cur_table, PageTableLevel::L4, pte_idx= ); + + // Read PTE to check if mapped. + let pte =3D read_pte(mm.pramin(), pte_addr, self.mmu_version)?; + if pte.is_valid() { + Ok(WalkResult::Mapped { + pte_addr, + pfn: pte.frame_number(), + }) + } else { + Ok(WalkResult::Unmapped { pte_addr }) + } + } +} + +// =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +// Helper functions for accessing VRAM +// =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +/// Calculate the address of an entry within a page table. +fn entry_addr(table: VramAddress, level: PageTableLevel, index: u64) -> Vr= amAddress { + let entry_size =3D level.entry_size() as u64; + VramAddress::new(table.raw() as u64 + index * entry_size) +} + +/// Read a PDE from VRAM. +pub(crate) fn read_pde( + pramin: &mut pramin::Window, + addr: VramAddress, + mmu_version: MmuVersion, +) -> Result { + let val =3D pramin.try_read64(addr.raw())?; + Ok(Pde::new(mmu_version, val)) +} + +/// Write a PDE to VRAM. +pub(crate) fn write_pde(pramin: &mut pramin::Window, addr: VramAddress, pd= e: Pde) -> Result { + pramin.try_write64(addr.raw(), pde.raw_u64()) +} + +/// Read a dual PDE (128-bit) from VRAM. +pub(crate) fn read_dual_pde( + pramin: &mut pramin::Window, + addr: VramAddress, + mmu_version: MmuVersion, +) -> Result { + let lo =3D pramin.try_read64(addr.raw())?; + let hi =3D pramin.try_read64(addr.raw() + 8)?; + Ok(DualPde::new(mmu_version, lo, hi)) +} + +/// Write a dual PDE (128-bit) to VRAM. +pub(crate) fn write_dual_pde( + pramin: &mut pramin::Window, + addr: VramAddress, + dual_pde: &DualPde, +) -> Result { + pramin.try_write64(addr.raw(), dual_pde.big_raw_u64())?; + pramin.try_write64(addr.raw() + 8, dual_pde.small_raw_u64()) +} + +/// Read a PTE from VRAM. +pub(crate) fn read_pte( + pramin: &mut pramin::Window, + addr: VramAddress, + mmu_version: MmuVersion, +) -> Result { + let val =3D pramin.try_read64(addr.raw())?; + Ok(Pte::new(mmu_version, val)) +} + +/// Write a PTE to VRAM. +pub(crate) fn write_pte(pramin: &mut pramin::Window, addr: VramAddress, pt= e: Pte) -> Result { + pramin.try_write64(addr.raw(), pte.raw_u64()) +} --=20 2.34.1 From nobody Sun Feb 8 09:32:51 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012052.outbound.protection.outlook.com [52.101.43.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7328444D02C; Tue, 20 Jan 2026 20:44:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.43.52 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941880; cv=fail; b=lKLcShgWfJBOenu3lCsAA+FK01DGd5GuBlUfUeu6vua+5cwsH8e6UrMkKYEpNYlIzQnafwHV7mvmd3ULYdYvW5j9hZKBdpQAggbkSRaVFf5Gis5qy9OH8wjOEVm0CgIm/FbhRKAsF9e73bUpA2cTkpbqHuRwEL4cuSHdwkLiB70= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941880; c=relaxed/simple; bh=PCFNpxOCNfyUpI7sFIp7+JNYj3dEUowQSCPN2tvAHWc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=lNjj/YQfOtY5DP1ta/spjsE++nA8IkJ5KPMi6X2ysinwQye2yB0PZBLesJ+xRORDF0ezWJhvuBjT3hNZWHD3Z8KEeSgSncS4smZuoVFhyiO2rCxcY3hvnF/bWucb75M+ZcZ4G9VYCstZf+EhvdGRI40ghJmk7KTlI/Q+cmHGqQ0= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=m4kyjckk; arc=fail smtp.client-ip=52.101.43.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="m4kyjckk" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=LZs9evmn2BGRhj35gG3BqOUO6dHSAcNo2NhPKtj8rAQl2Su1cVT+r4YhHJ0AOUgoAl7EIc0ScIlXgz4eseg8SAfZ8HD5HEehR/AVO5hUV3SQzzSCP2KCea5WRFGiKmid9iYN/6s1OvGpV3MzoEVr2rj8V1lM5SoceFy9Xh2EDH2ygco399WHgPwSxqqFjjBhspIKhwfvEbbDh/0anMPYr/7kDIG2VmaZ0aXtTxd2gu/uxK+EwHe2cTmocRfyzdX4X7hFJyc0EGS540A6/v6r0t/9F6G0/rv4ip7mHoHPp+WbaQdQyNJfvo7O8EbqtmQ62vdbZhd8hRKNVTGdNNHD5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=3B6BwPSG7uPgdLz7djf2QctppdbLx2NhrqSzuC8zHsM=; b=iDuAIcEzmPltioUKi4nmViMAvOVrb/d0yfp++P+1qVIyOXIUFmtTE5ZJzRLC3THcAaiek4KLdFc2Hxvk9kPS5/GAM06Cmiw3cBBljjgb4L3aLaG0EhrDG8BTagxR9cgUio8DSYWZULQG1Kforhw9PDt1FSuwfuxNMNxGoqDHvJe/xUqf7pM7Mx7AH/04fNl4PpMHZKH+GusnUwqGPVROMkm/xINFdfHKM/NRlzOZR62GfDtnkKxgDs2I8EsGXWB4P9ari7iOidp6LpPXcUg7QrEkvBFk50JV0tz2p3q3QhiJ3V26073WbEbXFfsrRmz00Al5QG7+suSwUyhw7FcGCA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=3B6BwPSG7uPgdLz7djf2QctppdbLx2NhrqSzuC8zHsM=; b=m4kyjckkcnvU8g5gZk/XtsNYhfr2/dUpLLpCVUr7J8vkCiyfdejjDdqNnmBkgR/208rwi07eIrgiyNg15kpO8zoIylQKeQ9NcwO+E2sUm9we5sqGqfgbDns82Xer14R6zyRIAwjD0uzNqTMRn+YcQQi50Oj14Hl5+0zInjaz0g7IaGyJ1V98mqOwCnEtsWPq6CB/zD/yBHvQgjE2aHnK/b6akBg1IBg6pagRTH2ptrnqBRh3L0de5eBeYGASHEIPaoiEenfFvc5AQZnYsmKgqKPfBZMqVnOROPoaCgZawaOHbK3aAfxAqZuk0FwB3jaJgfObQDwQ9pfUErPQdUhODQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by PH7PR12MB6809.namprd12.prod.outlook.com (2603:10b6:510:1af::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.12; Tue, 20 Jan 2026 20:44:19 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9542.008; Tue, 20 Jan 2026 20:44:19 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jonathan Corbet , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Huang Rui , Matthew Auld , Matthew Brost , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Helge Deller , Danilo Krummrich , Alice Ryhl , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Alexey Ivanov , Balbir Singh , Philipp Stanner , Elle Rhumsaa , Daniel Almeida , joel@joelfernandes.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, linux-doc@vger.kernel.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-fbdev@vger.kernel.org, Joel Fernandes Subject: [PATCH RFC v6 17/26] nova-core: mm: Add Virtual Memory Manager Date: Tue, 20 Jan 2026 15:42:54 -0500 Message-Id: <20260120204303.3229303-18-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120204303.3229303-1-joelagnelf@nvidia.com> References: <20260120204303.3229303-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MN2PR20CA0055.namprd20.prod.outlook.com (2603:10b6:208:235::24) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|PH7PR12MB6809:EE_ X-MS-Office365-Filtering-Correlation-Id: 6ac031ca-be4a-468f-6028-08de5864af0e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|7416014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Mv2IUTHe7HHKzs1exZAgzBnNba0Z5sDDq0Igfg5xMwPWuUMLg+BBuN1BLa1o?= =?us-ascii?Q?jbA+Vth/zMR5KgOvuV6pbtVTJL+ER7tNE6pM3/bAtfr4LYHc7oX2sCKraGV7?= =?us-ascii?Q?7z9bw26cmu1chW6k1t+p7EIKDeBfVv5TMdQorycG9qvvTz3DJ3aKepx8mWgS?= =?us-ascii?Q?e5RJTQ3O8SnoCyluNrXx0R7kMSqQkW7+2c58ly0F/SWhs0eKNRsZE3cMV75R?= =?us-ascii?Q?sJXeBPdWc9RaK8NQ6y1vlkJat53qkxlF7XsLFlepi+bn+ZpGt37m/PI7jPHM?= =?us-ascii?Q?oafrodDTy0YHZHlsOKN1DO1dA16DSjGZTqtHOSwuGbs5mWvfbjIH9JTIBp5q?= =?us-ascii?Q?VQDbL+7yX4WM7xoN8o4w2M0pfEe/nTPYbDpr9kMd8zQT1vhgmlTEaRMHDJaV?= =?us-ascii?Q?0qf0Zg/+rt4vM4E70+p4mBjzgQJZXDIBcrNwYQu4MhuI8oU+lLoT88MBRB3s?= =?us-ascii?Q?4qnSgfBzIZCMCVhwTFGfEWpeWhbPwIUCCBogxayvPhs/0lN3mhG6QiUssL+z?= =?us-ascii?Q?FT2d7kdG0gzBelzrHtivixSOTaRQmpKL4LZOKiP3Q7fNc2mojoMBppcRnmrf?= =?us-ascii?Q?wAfdGnR1EwGCOin5krzqZ1VYtreZNXwQ2V8FquJ4al+e4Obun6e7yMyfoyEy?= =?us-ascii?Q?zymp0vCkhaWt0CIk/NFog/K3AEh4R1p1otjX0hqawyHtAwFvAKTsSljG5xim?= =?us-ascii?Q?QgVxOk6LHmTEQMjhNqVeLWMCc4ek0wM01Mra0dFeyTAPlDcO/pyC0XUO1Bj0?= =?us-ascii?Q?GnxiJE3n3+fhmCS3LexhV4elMmd9PiD4S7tTwTpOgnnFsztWkPy8fc//Mn++?= =?us-ascii?Q?2XUNNW2qR5mLodSPvUEDTuzr7T7IAdyWdDI7FNhfhpquVDnjyrgJ3koGDdc/?= =?us-ascii?Q?Z+RULRUhvYjz/NP0sAiBENsuG2HhhhUAVpNDeXY/q3ahyhk3o/1okVTnlmfk?= =?us-ascii?Q?185wlFR+Xb2Ze6HSRBMtfPO1mBbEm08G50gzikeKHlD8wegRQhQEPRZvA+In?= =?us-ascii?Q?tuGiWOyexSuYOHSkrhL7nV0FIgjQ5Na1Fd9gz6maJovhjR1JPRQawHmKEoPW?= =?us-ascii?Q?h6zFhJ7huGWWTvgtUf9MoCM93H76dc8ekQfTjmeOfRLpXFquQTs3eJ2Gi/vd?= =?us-ascii?Q?D9gCHrUoTYz7wmjAN7ruvhKKacmXTXKZGKT/JIb6Vk95jRspe3Ke4VMtqidz?= =?us-ascii?Q?+vHET+1tjAsygx5YKK6v3LqkDxrNIqoD/5Bthbvj1JTHx3p4i/vBNQ8sjgIP?= =?us-ascii?Q?CWjxYQmFZc106pj3wE4ao4mAJ0KFyHZxl+BJyv+X4QBVPqC4DtceNhseJyZe?= =?us-ascii?Q?XA4N7SPxPSBQGFYjnNTDH/xCKsERsQKAAAe9E9b5wjUB6DyU1CY6Vqy5S+yD?= =?us-ascii?Q?bztmGQNNULOC2UF8DUAI6I+/YFhQTCxybypbyEE6plW0yukgWpU357N+gSIO?= =?us-ascii?Q?jZrSP6bjaceijwd8ZdJpuCmQgCD/iNhovoBnydKHSI3IDfAb88NQcLY7U40O?= =?us-ascii?Q?lZ0JzqgE216c1en00L7tfNO/FYHwWiFdYkDU9tJTNOnsRelIffakyMtHipww?= =?us-ascii?Q?vtSvef7H9OtzrxSuEE0=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR12MB6486.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(376014)(7416014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?cYHvAC6RMBqd8pNjtglYPzziiZY7j+uT9SAbKfAZ/C31gP4//12XopEjo6Pg?= =?us-ascii?Q?0a/st+5ff57y+pdyj2/ZTDQt2Hx6FXjoVUd6+4la01yiI/fysOdgNzSoTtje?= =?us-ascii?Q?bQQ99M2G0uCGiSnX/yLya4qMH2CVqmg7QP0MecHFEU8l1H3bEliAxgmLvxEC?= =?us-ascii?Q?KJT+7/86gKVuJqCwwPFdY10jeEb1+DvuPXRmnMD3Ii6lpsP3Vv7uxRDSiUKj?= =?us-ascii?Q?wkYzcZSru+fUTcG0EV2cg8kq6mYrROWqKQQzoPJg4W4LoiyJfKxUMxLox0HE?= =?us-ascii?Q?x50gv8l8c+oYRbrRo1WbX8q3YxHsu7il17hw6x5EZmg101B/X/4aKMEByVJc?= =?us-ascii?Q?8AllOMtm44joxv2URnOjCV1m98jGNtuarHnYMLJCxs8fEx/0zXb/kuKmbSiQ?= =?us-ascii?Q?DQmi1c0yPFyTFWRQZVNR3K9MUtIj5F7ZnbAPbkoxG48RU9lzPezQEPgYrnBE?= =?us-ascii?Q?mzAm4RBOZDzCmsZQ8Hoz64R3ISLSYNwxj/6MIbpVDWloINjpVyfzR52gC2iE?= =?us-ascii?Q?YMcfEEPWmt0LyXqfNO7jGKiE1ThKuUc7v298KOQSjL6+uK14Y+JhXlqbKry8?= =?us-ascii?Q?3r7gRsVOnFlq2SrkutaYa/sAejJug5CqM3d4OdiWqpKnTFccGV7gUaqXx+Rf?= =?us-ascii?Q?pQFT6An5ePgxHP29dLoLDb5zuPikg7zudg/0ejdDtHJh9lBVYLWDHJPn1aE+?= =?us-ascii?Q?B6ri0QNFGIf1bk5MYrMAXVbFUwqm2EejPZ8bW1AVorihk1vXSFPYEOnrG6zt?= =?us-ascii?Q?Ml0MTNPMz2X10SR/L3VTPaopHvt8iSjUVWMb/qml5nuOdg3ksQCIaIRrlldt?= =?us-ascii?Q?e6cymAtdn+pr8GHvkgeF6XMgStxRPkUOmxtwG0o5s6KbElsoGPHQc+QROe+c?= =?us-ascii?Q?wQe46P+7hFZb9K7MuxbwZezqA5JIH+kZY4aitWg9W7nUp8QjecNv3QICG1gz?= =?us-ascii?Q?LeRE2mrO00+btJLB3RSXmxDx7zpDSkrgXV/HNBJ1cGEuElqRdy4HkF2dLbtH?= =?us-ascii?Q?W/rRyVQFIYJms//XIMMAk8czLyM8l3qYO/L2gygGci9pFK5nog6P6r+ryQJO?= =?us-ascii?Q?eboNDqPKiO239SzHdlGFIsKjis4eazfF+hf1bJfcZLJRrlYLCsFO4crOGZfj?= =?us-ascii?Q?cGiw9alfM6ghZxvyu2kS0n2XmVjcHGHxPfnF77/kiYdssMxXh31nJoXeOoS5?= =?us-ascii?Q?q6L16A8pUvDXpZhcRX0k/iT+U1eNAr7RtCXCII55bQxYwXauawQ7ZdoG2Pxd?= =?us-ascii?Q?yekRy5vAyvMWevG+E8aaWSxqQLRgpxCbCVazopJoYVsdRkEkzjjgKNlTY+4v?= =?us-ascii?Q?kzSkZdz1it9s0iL8dmR0wZniceArwsANJ8ST6BMiglE4HAZ8gVZmtXL1T9I6?= =?us-ascii?Q?FiEYTUu15GbrvMCStXUj5OPLm+3goytl1eNMNwEWPp6AHkLTgE3fhHd2D5sa?= =?us-ascii?Q?mY3fsbl+Ah3rhFTRKSufL/3fWeEMrokaffoJHeimENbo/W9kr+Q6MShODf8T?= =?us-ascii?Q?GnUuzsX7tcePno/6P5YQCS5YuRh2orcSskzWQUs20gM/X04S0aMz//Pbigaa?= =?us-ascii?Q?h4/nrQdHjvKy33Z8v/15CnPhS02FwQnf+6t365RLjAOXxvvvYeemByxjTbOV?= =?us-ascii?Q?beA1+k3pdjPgR8Jx8zcxIl5w3pfkRJ25PxjHyAK48GucqH4uA39JbBrZQfnU?= =?us-ascii?Q?r477Bli6u/sebdmVhBDMQi535VJHDpYYddvClRmAmj8LN8WwZnpjCRU59Fep?= =?us-ascii?Q?n/Jm6E5gWw=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6ac031ca-be4a-468f-6028-08de5864af0e X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB6486.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 20:44:19.2015 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: PB5lB8uuv5y/N4XP3nqJAckqBxq6waiuNVeTLI3k4lY32ZMi8s9D3yF/3+GNlkqG1EhrDCeI4L0ETTKxM+KiHw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6809 Content-Type: text/plain; charset="utf-8" Add the Virtual Memory Manager (VMM) for GPU address space management. The VMM provides high-level page mapping and unmapping operations for BAR1 address spaces. The VMM provides mapping, unmapping, lookup, and page table allocations. Uses GpuMm for access to buddy allocator, PRAMIN, and TLB. Extends the page table walker with walk_to_pte_allocate() for on-demand page table creation. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/mm/mod.rs | 1 + drivers/gpu/nova-core/mm/vmm.rs | 204 ++++++++++++++++++++++++++++++++ 2 files changed, 205 insertions(+) create mode 100644 drivers/gpu/nova-core/mm/vmm.rs diff --git a/drivers/gpu/nova-core/mm/mod.rs b/drivers/gpu/nova-core/mm/mod= .rs index 56c72bf51431..53d726eb7296 100644 --- a/drivers/gpu/nova-core/mm/mod.rs +++ b/drivers/gpu/nova-core/mm/mod.rs @@ -7,6 +7,7 @@ pub(crate) mod pagetable; pub(crate) mod pramin; pub(crate) mod tlb; +pub(crate) mod vmm; =20 use kernel::{ devres::Devres, diff --git a/drivers/gpu/nova-core/mm/vmm.rs b/drivers/gpu/nova-core/mm/vmm= .rs new file mode 100644 index 000000000000..a5b4af9053a0 --- /dev/null +++ b/drivers/gpu/nova-core/mm/vmm.rs @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Virtual Memory Manager for NVIDIA GPU page table management. +//! +//! The [`Vmm`] provides high-level page mapping and unmapping operations = for GPU +//! virtual address spaces (Channels, BAR1, BAR2). It wraps the page table= walker +//! and handles TLB flushing after modifications. +//! +//! # Example +//! +//! ```ignore +//! use crate::mm::vmm::Vmm; +//! use crate::mm::{GpuMm, Pfn, Vfn, VramAddress}; +//! use crate::mm::pagetable::MmuVersion; +//! use kernel::sizes::SZ_1M; +//! +//! fn map_example(mm: &mut GpuMm, pdb_addr: VramAddress) -> Result<()> { +//! let mut vmm =3D Vmm::new(pdb_addr, MmuVersion::V2, SZ_1M as u64)?; +//! +//! // Map virtual frame 0x100 to physical frame 0x200. +//! let vfn =3D Vfn::new(0x100); +//! let pfn =3D Pfn::new(0x200); +//! vmm.map_page(mm, vfn, pfn, true /* writable */)?; +//! +//! Ok(()) +//! } +//! ``` + +#![allow(dead_code)] + +use kernel::{ + gpu::buddy::{ + AllocatedBlocks, + BuddyFlags, + GpuBuddyAllocParams, // + }, + prelude::*, + sizes::SZ_4K, + sync::Arc, // +}; + +use crate::mm::{ + pagetable::{ + walk::{ + write_pte, + PtWalk, + WalkResult, // + }, + MmuVersion, + PageTableAllocator, + Pte, // + }, + GpuMm, + Pfn, + Vfn, + VramAddress, + PAGE_SIZE, // +}; + +/// Virtual Memory Manager for a GPU address space. +/// +/// Each [`Vmm`] instance manages a single address space identified by its= Page +/// Directory Base (`PDB`) address. The [`Vmm`] is used for BAR1 and BAR2 = mappings. +/// +/// The [`Vmm`] tracks all page table allocations made during mapping oper= ations +/// to ensure they remain valid for the lifetime of the address space. +pub(crate) struct Vmm { + pdb_addr: VramAddress, + mmu_version: MmuVersion, + /// Page table allocations that must persist for the lifetime of mappi= ngs. + page_table_allocs: KVec>, +} + +impl Vmm { + /// Create a new [`Vmm`] for the given Page Directory Base address. + pub(crate) fn new(pdb_addr: VramAddress, mmu_version: MmuVersion) -> R= esult { + // Only MMU v2 is supported for now. + if mmu_version !=3D MmuVersion::V2 { + return Err(ENOTSUPP); + } + + Ok(Self { + pdb_addr, + mmu_version, + page_table_allocs: KVec::new(), + }) + } + + /// Get the Page Directory Base address. + pub(crate) fn pdb_addr(&self) -> VramAddress { + self.pdb_addr + } + + /// Get the MMU version. + pub(crate) fn mmu_version(&self) -> MmuVersion { + self.mmu_version + } + + /// Allocate a new page table, zero it, and track the allocation. + /// + /// This method ensures page table allocations persist for the lifetim= e of + /// the [`Vmm`]. + pub(crate) fn alloc_page_table(&mut self, mm: &mut GpuMm) -> Result { + let params =3D GpuBuddyAllocParams { + start_range_address: 0, + end_range_address: 0, + size_bytes: SZ_4K as u64, + min_block_size_bytes: SZ_4K as u64, + buddy_flags: BuddyFlags::try_new(0)?, + }; + + // Use buddy first, then pramin (sequential to avoid overlapping b= orrows). + let blocks =3D mm.buddy().alloc_blocks(params)?; + let offset =3D blocks.iter().next().ok_or(ENOMEM)?.offset(); + let addr =3D VramAddress::new(offset); + + // Zero the page table using pramin. + let base =3D addr.raw(); + for offset in (0..PAGE_SIZE).step_by(8) { + mm.pramin().try_write64(base + offset, 0)?; + } + + // Track the page table allocation. + self.page_table_allocs.push(blocks, GFP_KERNEL)?; + + Ok(addr) + } + + /// Map a 4KB page with on-demand page table allocation. + /// + /// Walks the page table hierarchy and allocates any missing intermedi= ate + /// tables using the buddy allocator from [`GpuMm`]. + pub(crate) fn map_page( + &mut self, + mm: &mut GpuMm, + vfn: Vfn, + pfn: Pfn, + writable: bool, + ) -> Result { + // Create page table walker. + let walker =3D PtWalk::new(self.pdb_addr, self.mmu_version); + + // Walk to PTE address, allocating tables as needed. + let pte_addr =3D match walker.walk_to_pte_allocate(mm, self, vfn)?= { + WalkResult::Unmapped { pte_addr } | WalkResult::Mapped { pte_a= ddr, .. } =3D> pte_addr, + WalkResult::PageTableMissing =3D> { + // Should not happen with allocate mode. + return Err(EINVAL); + } + }; + + // Create and write PTE. + let pte =3D Pte::new_vram(self.mmu_version, pfn, writable); + write_pte(mm.pramin(), pte_addr, pte)?; + + // Flush the TLB. + mm.tlb().flush(self.pdb_addr)?; + + Ok(()) + } + + /// Unmap a 4KB page. + /// + /// Invalidates the [`Pte`] at the given virtual frame number. Does no= thing if + /// the page is not currently mapped. + pub(crate) fn unmap_page(&self, mm: &mut GpuMm, vfn: Vfn) -> Result { + // Create page table walker. + let walker =3D PtWalk::new(self.pdb_addr, self.mmu_version); + + // Walk to PTE address. + let pte_addr =3D match walker.walk_to_pte_lookup(mm, vfn)? { + WalkResult::Unmapped { pte_addr } | WalkResult::Mapped { pte_a= ddr, .. } =3D> pte_addr, + WalkResult::PageTableMissing =3D> return Ok(()), // Nothing to= unmap. + }; + + // Invalidate PTE. + let invalid_pte =3D Pte::invalid(self.mmu_version); + write_pte(mm.pramin(), pte_addr, invalid_pte)?; + + // Flush the TLB. + mm.tlb().flush(self.pdb_addr)?; + + Ok(()) + } + + /// Read the [`Pfn`] for a mapped virtual frame number. + /// + /// Returns `Some(pfn)` if the [`Vfn`] is mapped, `None` otherwise. + pub(crate) fn read_mapping(&self, mm: &mut GpuMm, vfn: Vfn) -> Result<= Option> { + // Create page table walker. + let walker =3D PtWalk::new(self.pdb_addr, self.mmu_version); + + match walker.walk_to_pte_lookup(mm, vfn)? { + WalkResult::Mapped { pfn, .. } =3D> Ok(Some(pfn)), + WalkResult::Unmapped { .. } | WalkResult::PageTableMissing =3D= > Ok(None), + } + } +} + +impl PageTableAllocator for Vmm { + fn alloc_page_table(&mut self, mm: &mut GpuMm) -> Result { + Vmm::alloc_page_table(self, mm) + } +} --=20 2.34.1 From nobody Sun Feb 8 09:32:51 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012052.outbound.protection.outlook.com [52.101.43.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 497893C00BB; Tue, 20 Jan 2026 20:44:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.43.52 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941885; cv=fail; b=exNV4U9lJZS5xapFSaT5vkxnZyzacWYiBuwxZDKJ/AehYpHIwxlMPtIKB0e6aPUyvA2YHB3hgQFufYT5PXOqtBz4OXp2kRAcUJMGoUYHVm0XYJ69XMTqjaOvhAuw4lDLRMqnWDcnOvCZmiWZWs8eN1coyDuzqCOHhMOejZhdz38= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941885; c=relaxed/simple; bh=PyGWUjgeXKUIm3MvyUgWMEAEQYKAJjE2vPAvaJuTzv8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=J7hE15/QqldokGidFzjw+EMectj6vwavn8fw6IquhuKS14wQ0pCli3Gx4UZ7I6m6NUKUu4sPMZHG9+KJ91ZiTC0uRubNmqiF5hJbMxeiZ/6fl+wFhN395M8WhIhubem5DloprTNop93oQGcf2jJolnjy2OLadYkPHr2T9mFaygc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=pyhUDeQ7; arc=fail smtp.client-ip=52.101.43.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="pyhUDeQ7" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=LDqd9V9n8uIi4MEehfUfz1SYuJqcEV9EhzJsHOpA0EFh1ZzmK37H64lekdORHoDz3uSgaigBubgRYPydE+sZnipOJ+CmrrhL+PUp11dm5SAS3z8u5gv29Hr+cqp3+6QSRIKsvcr6QODAVxT1hDAa6SGSpK26Q2AwMphAQO7nVlzHbOFidqsmSsOM5PLsBGosOgRVdJBvtRGO2PMYv9cNKncc9weZUa+LewJzR30L9KOshpqv6DyRoxzPj5oUKLb/gSgQPKf8oX27deXeQe6teaVt+caxFit1iVXMMXULzTgN+X+0QlJjxdAtLGmvbe6t3pNyZvfTSVVoHICBAKw0hg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=lHmcAGEiTYK77mHMYBKw9XFluu3TXACJqJwbH39uDDI=; b=A6VLKU41ui6QwwgEciq2A5GApgEEjRXYdMud8jv2VRcXz/r16I8zcUcAvjksIJrqIlcxxlRmTl7mk8wAo20LoicZ3P1l4y+aPN6z6/K3uQ8kye9Q1gJqU41ADIzb1aiHaL9gxzvJTxKLy+xyGD54WVvf7gBCE3Z1ZsjimQUfY2tukGtq1uUAKzuROnOo9lXbAuF1dm0derXYjqtStek+U4bxE3xwTpEC95pLRaFmPL7IociSecmvwCI0j2PNSGCNTB1/sa0GMWY2Md3wztBQSp65dsTzh8Ma4j50TL1o9uyjW1NDLiW/p2klTkR2FkX3QPAYEjJYPMKAotzYPiyaPg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=lHmcAGEiTYK77mHMYBKw9XFluu3TXACJqJwbH39uDDI=; b=pyhUDeQ7uHWixP5l3391WCEbmJOMM0wGfA4/e3egyet5bH7nHT6gmE6Kc7dDTz50g3zzPpzqPTilc4cbqSfETg+8wkRM6fF0ENjgGKGLqonpozpKK/XqyXy+SGoFDDlea8X9O86U6yJksyQGXb8KYfsHQ04C6Xo9vN5XFZEFUDsSjtG1ktos15e28D7zo7dECvsN/pa9f4H5/+gmbS+zOQJdHWeN5IF39H7j97GqFAKnIYXLvyfVgBMBLMFFfdePNTIGOsIjEigAu0UWgzxzU9SJtdlE8lzP/4olLTyu8HdsXVsy2qespkeTDikY/dQQYRuz4gG+x6uov/cIo4pIrw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by PH7PR12MB6809.namprd12.prod.outlook.com (2603:10b6:510:1af::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.12; Tue, 20 Jan 2026 20:44:21 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9542.008; Tue, 20 Jan 2026 20:44:21 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jonathan Corbet , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Huang Rui , Matthew Auld , Matthew Brost , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Helge Deller , Danilo Krummrich , Alice Ryhl , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Alexey Ivanov , Balbir Singh , Philipp Stanner , Elle Rhumsaa , Daniel Almeida , joel@joelfernandes.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, linux-doc@vger.kernel.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-fbdev@vger.kernel.org, Joel Fernandes Subject: [PATCH RFC v6 18/26] nova-core: mm: Add virtual address range tracking to VMM Date: Tue, 20 Jan 2026 15:42:55 -0500 Message-Id: <20260120204303.3229303-19-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120204303.3229303-1-joelagnelf@nvidia.com> References: <20260120204303.3229303-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MN2PR03CA0029.namprd03.prod.outlook.com (2603:10b6:208:23a::34) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|PH7PR12MB6809:EE_ X-MS-Office365-Filtering-Correlation-Id: 848f9b27-4227-4d0d-ed1e-08de5864b048 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|7416014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?GPUewjorFqTjGyc+jkG55pMB5NqpxEGexLwAVVeyQOx6kp1LWd2pWPgmA+2L?= =?us-ascii?Q?ie30i+KVgVl/m7TaLZmVbDsoJaGGdaBP1DBp9hAAXfTubugDZJ0PWvylSNUl?= =?us-ascii?Q?CSFK0iBZoNM0R91+EaJYaR9KH06yHckBHlNv3Y9z/hcj7nqlnA7bYidDmcks?= =?us-ascii?Q?HAptkfToevIXsx8VL3wv7BrkLyniXnTjZjA/+ee2P0MzG2zS9bpjhJGOhOmE?= =?us-ascii?Q?NUWQkMI9oJhlxjiLB5kfaNuSX12um/TyW+qCBmKsA/fYZb6WpaeJHPFig40F?= =?us-ascii?Q?pks+oZDqI/C7O2s1/Lj+wZdQCKwkfcu1oRD+YY6geqgF8R4RPLcMoAfuZht/?= =?us-ascii?Q?i5tcpAquC4DY7mJlUXt8wyNjjDTbUwWi/4OYpsEyp+UioNz+JY3T35yZQ59Y?= =?us-ascii?Q?tSrBFvK9Z41CPPsRhrj+L0YSTN1Qe3CgYmURbRrfHNx20fnxWhDyJ9h7iFjY?= =?us-ascii?Q?n/RURAV+cI3JSXnSCage3HBjrXUIS47guWENlR3o+BFmnq0vv/lx21Cj1lqH?= =?us-ascii?Q?mT2mIp3I1L4OYRIybGD1saM/1WxgMpjCq8K4Fpc9KapbZZCqrmnJ4TS393sn?= =?us-ascii?Q?VWw3kbX/LYBz12vRcqNeGbAJgZ1cOLo3wl/UNTe/lpWRMkARQdz98EvRAJAk?= =?us-ascii?Q?Qvc/Onr23Aw+Jy7sGT1p8qF8CbtUfnMDnMykt+k/JTESePS8Ge8qg0qXmNxw?= =?us-ascii?Q?UXcqqesYrTpvHzZmSaaPdSqbqhtduDJnAVOmnKL4tjKtNWX/rOOXUkzWG9be?= =?us-ascii?Q?rcTtfkLBqSitU13imUrUbzwe87w5qSrVmqxbpMXR47GOA7b5ED7lEsbxg/Yt?= =?us-ascii?Q?9qwOkMsmMan3Fhcpmuk/hBel20qcFtkKpY7R68VO7mivflDbFVo3Xf2+qY6X?= =?us-ascii?Q?pa4gD1O9f7Aeg0YWPeV4vSZsehQLv5yCPRFbChOMhvNAdGGotiPUHxcndQnj?= =?us-ascii?Q?TMuJvmO+EoKWCvFceVU8dq8vpkzGhEI8/yerKfUzzsQC5Q752UP8KkvISAy4?= =?us-ascii?Q?U7ZBX50gsb7y6yOqMg6zh3vfiGumHv1uaVw45Y2IfvBI7mwnzBy5LUaPicPe?= =?us-ascii?Q?IgXKMkX4zOA3wRXR16gahhFUJsl/H3XgSC1Aub6ng8eOTDhqMLy1OMlE0toI?= =?us-ascii?Q?8ZuYD3Uukwo4MunquxZ2f021b2TiChBT74TGo7UfN4+VBq0PgY59Op88Gx/A?= =?us-ascii?Q?OuB2SqMnVyrLTgEF9B1UvezmCZOHgKQdPd4QEUtNVpRf4n/FT47KVApz+e5f?= =?us-ascii?Q?0RWbr+J+T9u0MoGiW3ldOvUzIthTRVdKWrz3bwty6JSH+D5mqeyWYpC37OGX?= =?us-ascii?Q?dQrI5ss85gqHQvpGErnznjAY0uV4wfw8qsKYvvfNSg3r0hDjbDYJ1B8cSmCe?= =?us-ascii?Q?q/UA8wVShcR9foHLsvNlOvVFi/6Y2L+Pxj3X2XJ9fGbE85dl/LajAEt6rd0o?= =?us-ascii?Q?e6JXfPoGo+6Xe7xj9WxmsRsoNeqDCkl5CaBnsSutaO+0wl+DbEKyyZLTMEHj?= =?us-ascii?Q?rik6iDO/kAX1o5wV52QgAraq2CTJlalUO1Gu8tm+MUy64Am5Jl+hs3DohVbD?= =?us-ascii?Q?oc2q3DVBPTZ9pyJO0Eg=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR12MB6486.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(376014)(7416014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?7x7Lby0yVaBWCaXHoN3ExBONqwfcIWXZpfgfMOt3kRejVLGrpr4JQWE0WYsh?= =?us-ascii?Q?ePFNc8Yd/q99m693zCEWWI2TSeNXC8lhOCtNDiMvN++LhbV2j5mteSeSKa6x?= =?us-ascii?Q?ygKQsExkmnKIGial8e5GXuZq7U5H/qEKFGVI91ajprfUunGiTPv0QAWPgktd?= =?us-ascii?Q?hUCkaOP80PwUdU9d63LFaVb+wrUUoIVqUYHZZXB//PPlnHAiJrmpIgJF7K+9?= =?us-ascii?Q?FxNxYtz3I61dV3QYlA4w6fU3O9gXsWLWsmO3cNAfqfXrRMDFJevsMkWC5Z7z?= =?us-ascii?Q?VxiKyQpZDquLX7y9fkUhLFr2gWbR+OTC3cqYI+JpWt1T3g8E9Lrgoy1NUz0v?= =?us-ascii?Q?7Ebm1zojG1IIyr3p/Rx2AMQ02N/2Hg6K7U+ZBZXisksbuO6T1azrJFi6LV3/?= =?us-ascii?Q?ZQVhKmV2j3klDCLN4swC6PG8xkptW4UKTtpoikmDOW9XGla54gr8L3FWAT4V?= =?us-ascii?Q?uI15E0D9qt+jPy7E5Cq5jMOLEZgmRfDiTp2N4t6tLFWkkMeCAOjtCkF0Q8IX?= =?us-ascii?Q?iEl4HogM0278p3q96wzb8Iqw5miWZo2jYRPfufZpi437ZQdvkAO14zInl43J?= =?us-ascii?Q?eP4JkXYjZQ5ZgOY77VrtJWYF5zY/4wHny8oTrh4ltDhrGh8Bfrz+C/I16NSF?= =?us-ascii?Q?42AEGy+pVi/AqsGXaAXWOq/1t9XQLJNtejyezJEyecRt5kpuqdoV0cMio6DA?= =?us-ascii?Q?zkiBVkBp6j1rNQuQu8aNm0DN+6pNzienI5SmZUYnNcv3GR48BMQBk7YuX/Wx?= =?us-ascii?Q?qtPyrq5hJO1nVYnZG6nNgt4iir3zcXtWLiUMVdJXjaiAk/kdZy6Vlrbk0zGV?= =?us-ascii?Q?4rCK/sF2bQBDU33FA6JVwUb1n/JZMaJYIaL8TLldHFaRRdi7FoQ1pUjycld8?= =?us-ascii?Q?X5bIAUDk4X5gvYAufVeuBINBQjQbZ6+YsVOJoLlVTW5a7bCA7bn8rxb5qXOW?= =?us-ascii?Q?kC3FsE7u1EuHN3vzn1PmVvKstcUp0zGa9rP6RXW+zZ+eeSjL+2cLdMDg1p6s?= =?us-ascii?Q?tB1HxfTqfFujecSOeR5LQux9Ohe/aiDMaU+P2eqQyjE83YaPBRCiyCZqXajD?= =?us-ascii?Q?Kx3NI4NHHSkgY43xRSWltqfdbROF45YmH92GWiFI8WcMytrCRrb3h4gjCJBJ?= =?us-ascii?Q?ho6uJHz3CDgIXsjXvMALvd4by8/W1jBXWTxi+8ZDTjRgCPqM7hVYB4qPCbrJ?= =?us-ascii?Q?FQQYrD9RPN23kxeoPxdX4mb3QMKkeSwN2Y+oz+zlUsp52RqwJWDJ63m6ba0u?= =?us-ascii?Q?xjq6uxLGGX4+X8J1+irmuN15RJNS1++5HRR5mvthX/ZpR0BV2d1tmYok16JN?= =?us-ascii?Q?jH19WO0hNFRP5cxEZNap4PlKQdfNbWDqdj+v2Rd/gNssA4GU5b7QZ/SdY0g0?= =?us-ascii?Q?C9mW5gSon45kgFSFdmf0m1AfwQBHXLWmCZ7mKS95+AfTpgKxRupQXetPJTgr?= =?us-ascii?Q?Wkk7dScJWPkDt5v4cQJsNCPwIgZgmg7U/VBW4pEenTrfogiMo1hp/Z65OS/C?= =?us-ascii?Q?CNHMPUf/kjylRwP+CO2/i9bWVNbTjdbiqPmsINDcAxSGAxL4bvXw4T6pxo4g?= =?us-ascii?Q?kBHZW/QfZQpBvWvoFu7xwu9s7Z0m4wA9YaFaOQeeaSIBg5ZO4mhUtn3TObhJ?= =?us-ascii?Q?P3cRYesAckVXpDYZoDLlKDUxsURIk0NM6XLsyHgWkITLVkTSX7VXMNCW68DT?= =?us-ascii?Q?dn7rR7MdEAVe3cMnqBGhWCgTIybl9ccdkMKWnxYkF3/kQ2FtCbmn2WvnWBD+?= =?us-ascii?Q?IiM1+lO1zA=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 848f9b27-4227-4d0d-ed1e-08de5864b048 X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB6486.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 20:44:21.5087 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 7P/i25fspCUL4RznfxVlLYVSYR94v3X2WYIpZwx3ylG3C+STeuWw+rctqGP1w0vryhSH6GunQYDZWyqSyLpSrA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6809 Content-Type: text/plain; charset="utf-8" Extend the Virtual Memory Manager with optional virtual address range tracking using a buddy allocator. This enables BarUser to allocate contiguous virtual ranges for BAR1 mappings. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/mm/vmm.rs | 49 +++++++++++++++++++++++++++++++-- 1 file changed, 46 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nova-core/mm/vmm.rs b/drivers/gpu/nova-core/mm/vmm= .rs index a5b4af9053a0..0ab80b84e55a 100644 --- a/drivers/gpu/nova-core/mm/vmm.rs +++ b/drivers/gpu/nova-core/mm/vmm.rs @@ -32,7 +32,9 @@ gpu::buddy::{ AllocatedBlocks, BuddyFlags, - GpuBuddyAllocParams, // + GpuBuddy, + GpuBuddyAllocParams, + GpuBuddyParams, // }, prelude::*, sizes::SZ_4K, @@ -60,29 +62,48 @@ /// Virtual Memory Manager for a GPU address space. /// /// Each [`Vmm`] instance manages a single address space identified by its= Page -/// Directory Base (`PDB`) address. The [`Vmm`] is used for BAR1 and BAR2 = mappings. +/// Directory Base (`PDB`) address. The [`Vmm`] is used for Channel, BAR1 = and BAR2 mappings. /// /// The [`Vmm`] tracks all page table allocations made during mapping oper= ations /// to ensure they remain valid for the lifetime of the address space. +/// +/// It tracks virtual address allocations via a buddy allocator. pub(crate) struct Vmm { pdb_addr: VramAddress, mmu_version: MmuVersion, /// Page table allocations that must persist for the lifetime of mappi= ngs. page_table_allocs: KVec>, + /// Buddy allocator for virtual address range tracking. + virt_buddy: GpuBuddy, } =20 impl Vmm { /// Create a new [`Vmm`] for the given Page Directory Base address. - pub(crate) fn new(pdb_addr: VramAddress, mmu_version: MmuVersion) -> R= esult { + /// + /// The [`Vmm`] will manage a virtual address space of `va_size` bytes= using + /// a buddy allocator. This enables [`Vmm::alloc_vfn_range()`] for all= ocating + /// contiguous virtual ranges. + pub(crate) fn new( + pdb_addr: VramAddress, + mmu_version: MmuVersion, + va_size: u64, + ) -> Result { // Only MMU v2 is supported for now. if mmu_version !=3D MmuVersion::V2 { return Err(ENOTSUPP); } =20 + let virt_buddy =3D GpuBuddy::new(GpuBuddyParams { + base_offset_bytes: 0, + physical_memory_size_bytes: va_size, + chunk_size_bytes: SZ_4K as u64, + })?; + Ok(Self { pdb_addr, mmu_version, page_table_allocs: KVec::new(), + virt_buddy, }) } =20 @@ -96,6 +117,28 @@ pub(crate) fn mmu_version(&self) -> MmuVersion { self.mmu_version } =20 + /// Allocate a contiguous virtual frame number range. + /// + /// Returns an [`Arc`] representing the allocated ran= ge. + /// The allocation is automatically freed when the [`Arc`] is dropped. + pub(crate) fn alloc_vfn_range(&self, num_pages: usize) -> Result<(Vfn,= Arc)> { + let params =3D GpuBuddyAllocParams { + start_range_address: 0, + end_range_address: 0, + size_bytes: num_pages.checked_mul(PAGE_SIZE).ok_or(EOVERFLOW)?= as u64, + min_block_size_bytes: SZ_4K as u64, + buddy_flags: BuddyFlags::try_new(BuddyFlags::CONTIGUOUS_ALLOCA= TION)?, + }; + + let alloc =3D self.virt_buddy.alloc_blocks(params)?; + + // Get the starting offset from the first (and only, due to CONTIG= UOUS) block. + let offset =3D alloc.iter().next().ok_or(ENOMEM)?.offset(); + let vfn =3D Vfn::new(offset / PAGE_SIZE as u64); + + Ok((vfn, alloc)) + } + /// Allocate a new page table, zero it, and track the allocation. /// /// This method ensures page table allocations persist for the lifetim= e of --=20 2.34.1 From nobody Sun Feb 8 09:32:51 2026 Received: from SN4PR2101CU001.outbound.protection.outlook.com (mail-southcentralusazon11012013.outbound.protection.outlook.com [40.93.195.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8166643DA4A; Tue, 20 Jan 2026 20:44:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.195.13 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941874; cv=fail; b=mwLP/utniL+OvECOmxI7buDQKxzjqSr3EuBSfK1miUFj+cc07cauCxE+UhFbjif3fa6q0veBr6+K6Tzfn4wOivnQqDMLAlbjd1tc0uRFUzkiqD2l/aC9tXlJEe8f9a6FvWP7VEPAdc7kMjit4RqW46uNAo/rD9O/WKW1XGUM8lc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941874; c=relaxed/simple; bh=MHJxnIugNJF0XO+lDeMQHOHHxl9UHH/Ic33oVVZ95w8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=ba3SU8Ci1Kily1iSyHIlUwxQQQLTR3+YwngPv22qX18fB7agPr5i4jHGd6ln5RqRJBCDCtqAGRXxAfHW32VRmnjPtZkr1eXceVs98nx6MLdwVMxPtcuGtwJnP1UnBxrymyRXvAe46fUXgcbgAC0zrDsRXQnCPa+AOPL1x9yOlO8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=SFbaOI9n; arc=fail smtp.client-ip=40.93.195.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="SFbaOI9n" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=yPssT70Q7iX+Ne8qhl9X3sW+f7RIp4/2urzrr+N09Lrq8o2vhiAqVWsyDqHV4IejhXiOw2+t8lf1uw02ipm6pIwr64/B4PKit8XAWAXFkg/ZXZt4c6LtgQmUQHpwD07BDEn0XlhBBTjiSAzvCA6fgWl1UReVMDh1RIiJv+If43xf7C4DTNIvEZtWGs95H5Icd3Ily7bYGudvR+/YEeX7mOy71ub7Mx5ZmEj8f7pbY9KjNu6rmYHId6C5h4PA8QtryIxhxXeBOJT0qHCv6ytUu/eDHptw3a4a/0zsuqJoLepU4lPJoBa3Ur7Y1tXhnSV0lYb4s34KKZmYe1opkhiQeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=UgTvhrFc94ewpmDmJnjeTW6p43ibTABd9ly9FRs8LHU=; b=srkZLIY2eYn9OUxXu5Vl8KhQdfBtpiN2AOlr5hWtiV/0TQhGsdhXTSK8DNRnQT3iDGYS7GddaLn5AhyvY0W0o5UnmVkWI/R2toxtLrV9THqhC5JVuPE7PtoMVWFih36YylrSKLRJR065KMwMXLtrUuZGqRW5A0UxsMEbx224RkNOphhVoeGN5JuYF9nddiljb+m2QRl8hm1dYhDrQkUok8IdYMbyK2MN5xxLSu/wdN4kRNTjC1ZmGraWinSulvj0HPr2kR5+nb4/BTYEs/yEwvZ4KCV+Q6GtHqXZuEm0U2ZaZsswpeUSlyhJk1CLxZkkpGPelD9VaTEQVkY66RcppA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=UgTvhrFc94ewpmDmJnjeTW6p43ibTABd9ly9FRs8LHU=; b=SFbaOI9n9G6zFAmwiPyRAh/vrFbPsH5yel2lUyN2DzG6QAt71H/snseSZ6zHhS5YVAwu+4y0qXlN3m6JaaInjPyVNUPowvNexEoJzN0bGOi72djgWbJNIwVTqUGE0mdk+/jC4QsljId32/M/5kH0GRyDLHrSV3/WgeITj5Cwq/cJgl4crdKqOxkF0uLTLKKMvX8uZ2YGMb9G95bRAMqkpNYfytIoHJddvbo3A78Q3iWAt64dr9BrZ3MV6YEeJXCjzq6CjEkG3/cOoxe5Es3GojLCmURW7dYGtf8V2WomV3mL0Ykgm1PlGYru0vpm2bDkBH0lr3X5lgg9Vax3jvEPrQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by CY1PR12MB9651.namprd12.prod.outlook.com (2603:10b6:930:104::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.13; Tue, 20 Jan 2026 20:44:23 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9542.008; Tue, 20 Jan 2026 20:44:23 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jonathan Corbet , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Huang Rui , Matthew Auld , Matthew Brost , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Helge Deller , Danilo Krummrich , Alice Ryhl , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Alexey Ivanov , Balbir Singh , Philipp Stanner , Elle Rhumsaa , Daniel Almeida , joel@joelfernandes.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, linux-doc@vger.kernel.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-fbdev@vger.kernel.org, Joel Fernandes Subject: [PATCH RFC v6 19/26] nova-core: mm: Add BAR1 user interface Date: Tue, 20 Jan 2026 15:42:56 -0500 Message-Id: <20260120204303.3229303-20-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120204303.3229303-1-joelagnelf@nvidia.com> References: <20260120204303.3229303-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MN2PR03CA0002.namprd03.prod.outlook.com (2603:10b6:208:23a::7) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|CY1PR12MB9651:EE_ X-MS-Office365-Filtering-Correlation-Id: 2472d1dc-b7a6-4f1b-74ed-08de5864b155 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?RxtV1sXTjfcw9QgdDJwhh9v4KuZlEAthSvkVOpBbOBXHYqTeYX0HfNUyl7Qz?= =?us-ascii?Q?xUnid4DvcP+FEbf2IkgBFheTpltv4DACgzHPbGk81s6eSdlv8fB+Z+n+UVjp?= =?us-ascii?Q?l/roHCch76mALmAlORlvzSqUeOKf6MO1bQlDKTREhMBRKWuIII6B7UIP7Z3T?= =?us-ascii?Q?MYa77Jr3ZSinTVxQ2TM2UpEz4+tzAzovz5nOsUxrMOa/G5fc/hZoreGEinPD?= =?us-ascii?Q?pqeCZo4GXSOVwAMrA4RCQZs+tjZM+mFp11KkEmCbJF1zn9VHAhyFRCkB4X8e?= =?us-ascii?Q?dz4ruOY08hk8GI367+jinoSwUAgz6Lw/2ufwbhb1DIO5WOEMuPcHvkAfj7W5?= =?us-ascii?Q?EmXRtLg5KIQvtSyW6sM/HO81XuZ/UZK24F60lyy9jYbvlTHIQcncPhDc0JJO?= =?us-ascii?Q?nJEOn2lWlP0ugm2usMLNJjUeWqLoYVxjesuQ+0dVoNFWR/MUEa2q9g4689g6?= =?us-ascii?Q?6hi2CR7I/lfbpfxYHsxjbK4JHA3teZ35HLFNXButEoAbSqnj2jD+eq2YVmj4?= =?us-ascii?Q?PRiTQY+saos9qweJlryZmDnQ+6c3hzLHTIO2eP0PcWHSvX3gb1iNacr0BBzL?= =?us-ascii?Q?krs31f/tsQC3zOCh3LYd4l7oW4mGzw+capbS0i0aPGEcWKv6gj21ZnNcq3XI?= =?us-ascii?Q?vSqWg4DfYHUZ1FI+d/7CAtuNicCtd1L/P+a2ZEgsJxABCzWJKEyfx5i9paKW?= =?us-ascii?Q?E0Mi/lYTkvyGMXIPrYiULe7v7k/U69W77qJEOlo7iol+vMdGNfMS0XIZ5GX5?= =?us-ascii?Q?KrpbEmqUWX9lgkFqJqNUHPRUe1wgENwmB1rhwaDTfp2DmmvkLOAiiPYFinCL?= =?us-ascii?Q?3K3LaPNCaSZ4NAW894FJFAf13oEYXu4WguhPa9eUWaDmtfuNFnl9e83fsbZZ?= =?us-ascii?Q?/Mcm11L39uQWy79nckNE+wQUmmQK53AgkvJzucWC0S5ajN4+Xr+RT5kJmsPa?= =?us-ascii?Q?8KLz36Emtbs1mBGu4hFAaqB6/WYJKFJjP3ah586BEx6mm3q45/6sIYukXAxl?= =?us-ascii?Q?cic9+DEkhf4DtcgP82po4gKCN8FmwJ1nMF+92yyv6U/KBfIni0o8lgpkHiBm?= =?us-ascii?Q?1+Rljjh+uX4zwpOo+FgCJ4JUTvQIqQoz8lL1vFX4PpW6rMNXUrnyZ66cNKo1?= =?us-ascii?Q?v1Xb2FfBCQdUFNr2wjiA/OE1Mavb3uQAZJSKvcnaJcinWANDc61x25a4SkRx?= =?us-ascii?Q?K7Xwa9uAzl73bvRPrvsjEWg+Yiru632N1YlRlHwHHXjLcKev978de4xvumAH?= =?us-ascii?Q?vkl9XlWbb7C3v7swEZq+m7fUzjrmDORNtq7jQN6XsjrRPBvZ6gxz/bQbZ3d2?= =?us-ascii?Q?q3dROm77nrYcFQmq2BK1gPSG9btyABTNhzX73BpuaF2X4DoPTiOUeJ45XxbM?= =?us-ascii?Q?/hQOqGacZbkYmkV0MCraHiKnmY+aan4D0YyGziUjbspJivuNdZ2U43/XYdqB?= =?us-ascii?Q?dUBEWREPSK3i1r9jMeI0pSXom1YLRiToDQlW1A0VlKvBe72CTxMypIiWnRL3?= =?us-ascii?Q?qvxfRlynpaPYqj7HEBxb+/D9quyvPqfWJMWgrUI6gmhMKZIefIXYq3AiGa+A?= =?us-ascii?Q?SHH1EHQCpDYf6CGk1H8=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR12MB6486.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(366016)(7416014)(376014);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?tmfvBXXZakrNS6076cJx3xgGtb0haPnKS2CwkunsQ1syPdgtP7AS1YSZZU1E?= =?us-ascii?Q?cMf/C5y4FH5D25ANKISaXnx4t3ZO4wURAQdwaat5BRkYzPRFmvMgmdcETylW?= =?us-ascii?Q?G8hmYDec8qhjYv5q/g+ac6JTRfQs8uJmeAjLazyq+a96cngJC8r4yWeNYQ+I?= =?us-ascii?Q?JSMLbcdI6NqzlCdU4n0hzTm6tVYmshj0UXQD4noo/VtS7ojxJwNvzDHkVuQd?= =?us-ascii?Q?WhbQ7aREm54X5xBtb0uTVjy6d7lDzxz+QmH8kOj1+Ab3jnCm3t79x5iThnJ3?= =?us-ascii?Q?3+O+rFdQD6DOpBNjg0Ft/foT5ARYBlhFHXKpVEasuhWgWzGmQ0pFQy5zRHa0?= =?us-ascii?Q?GWwkVGBfPzTMzdzv0TiEcoUqPujFqzE3okZHGyP9OD4cCq0u/R6TYxAIcE4Y?= =?us-ascii?Q?3hFf5rv7LVT5Oh8aEf8Rqff21bvm1A0cYZNhy+bD6TCk3S3LwxMQOi/odsWC?= =?us-ascii?Q?00Tj8Y92AbQM9mP6tFdHimUExPKYvvkK1LK/2wWo0tgekuIFVZ3R1u20gEse?= =?us-ascii?Q?cg5a8u5lB/h25GCOwXXJgP1ZGS46ltAxlo23M56X5j0GPF2ygjgMGF56z24i?= =?us-ascii?Q?FnkRyRM8qt77GvdaymgpL7gvbS4vnxuOuUA+Nh7OGZ20kx0cSiSoEBrEFvqc?= =?us-ascii?Q?EVzq1drsjLs16WinXe45PKKlUth5ssGh36MdABTb7kYvSQdCEnMijowf4dF8?= =?us-ascii?Q?IISrX9aF2jEW1V9B95BdHHAUJl9DjZNWqKTkvXyxVtcuJaki1/6yYHBWn9kT?= =?us-ascii?Q?skwd1hYw3jEZB4wtjI/nvLEZ2LHTgSCZbD5B9B3yFhPqEAZRRMDzavswIQg2?= =?us-ascii?Q?AUEpVbRGuZGIEz5BF7SMNOIGRcum8AI3VFa5PWX9nJHKhY+tAqq+UHXFLGfL?= =?us-ascii?Q?qlstM3tuydtCIaDty5rpfAaMv30tCVrEQ8aKNNXqxBrlhSxY7usOofI60MbU?= =?us-ascii?Q?E+g5tkTXrjtfAlWYWGEo5RxHoorqwKKkCHw/0yfGy+CRoxvE385NkNVmB0EJ?= =?us-ascii?Q?hpVbNCe8RJmt+6z9Omxo9fbrX7VgxRcN0Oy+ngeTTm01MWMHeCnghSRt+cSd?= =?us-ascii?Q?Yc9oU/sLbKX7aQ8dkFikuzzgUgqh4SnaglKxBqq1i+HCqm2FxpiXYWoRtAtV?= =?us-ascii?Q?pYcJj2lCrGi0EtpeT0szZNakcxvslaNSwFO8ebJPBLu0betfvtmILC0pfB+i?= =?us-ascii?Q?wkvYyiszV5HvGl1iIaqO/kLgS5JZ7irw28g3cC21SN9GfPcC0bGd1LpW96T0?= =?us-ascii?Q?peO9H6jgWLaT8+KXut3a1zVub5TvFiTvcVHBMGi056jNXY1vsK1s5x330rwP?= =?us-ascii?Q?8A4pNtrcM8tWSUnX1brV1g/DJvQNCGDlqJdT97JWtjQcUuIkLmuXUFKSwJ/L?= =?us-ascii?Q?f3as0EKx9VLfGJOJ/rCDb2ZcNw4SNbOXtxk5XnRYKOzHDhQKLUY8mcAgFeTr?= =?us-ascii?Q?dfpH3WQAOyhwT9QVPBTE6vLob1Ru5olvg2Va3SQkNBOvjQiW4IROmUKcs8DT?= =?us-ascii?Q?o+EWf0MVrzLoeefWuP03JOh2/itLjgZt2muz0ZHEx2UBx72oyLSUgt5wC+zX?= =?us-ascii?Q?LYKWpPXFOkS8TdQyEL0QIlTrtEeXMQm5sL+GRaYFVQvW9CE4nDYdtCnhpYsZ?= =?us-ascii?Q?7i5iPu5yMGh1wAvh+qHl5ZpiNPa92ZMqG3oZP/IaHXUcoFf2crkzogiFHBlP?= =?us-ascii?Q?Gx/7UwKbMO8rRWFLGWEwicNLqZ3Sr8z4ElC70fov4lEvC1oYO39Pg2dMxW7q?= =?us-ascii?Q?RCwdVKTgGg=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2472d1dc-b7a6-4f1b-74ed-08de5864b155 X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB6486.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 20:44:23.2422 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: mXDBl8Sl8QVkcacUJdvDgtSeR7pNtb6ZSTTKP41q0p2Q2EhRaHz0ZSmppeiNjkDORlvt2HdjerVoweSNTz+Avw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR12MB9651 Content-Type: text/plain; charset="utf-8" Add the BAR1 user interface for CPU access to GPU video memory through the BAR1 aperture. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/driver.rs | 1 - drivers/gpu/nova-core/mm/bar_user.rs | 195 +++++++++++++++++++++++++++ drivers/gpu/nova-core/mm/mod.rs | 1 + 3 files changed, 196 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/nova-core/mm/bar_user.rs diff --git a/drivers/gpu/nova-core/driver.rs b/drivers/gpu/nova-core/driver= .rs index f30ffa45cf13..d8b2e967ba4c 100644 --- a/drivers/gpu/nova-core/driver.rs +++ b/drivers/gpu/nova-core/driver.rs @@ -42,7 +42,6 @@ pub(crate) struct NovaCore { const GPU_DMA_BITS: u32 =3D 47; =20 pub(crate) type Bar0 =3D pci::Bar; -#[expect(dead_code)] pub(crate) type Bar1 =3D pci::Bar; =20 kernel::pci_device_table!( diff --git a/drivers/gpu/nova-core/mm/bar_user.rs b/drivers/gpu/nova-core/m= m/bar_user.rs new file mode 100644 index 000000000000..288dec0ae920 --- /dev/null +++ b/drivers/gpu/nova-core/mm/bar_user.rs @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! BAR1 user interface for CPU access to GPU virtual memory. +//! +//! BAR1 provides a PCIe aperture for CPU access to GPU video memory throu= gh +//! the GPU's MMU. The [`BarUser`] struct owns a VMM and provides BAR1-spe= cific +//! mapping operations with automatic cleanup. +//! +//! [`BarUser::map()`] returns a [`BarAccess`] object that provides read/w= rite +//! accessors to the mapped region. When [`BarAccess`] is dropped, the pag= es +//! are automatically unmapped and the virtual range is freed. +//! +//! Some uses of BAR1 are: +//! - USERD writes: CPU submits work by writing GP_PUT to userspace doorbe= ll. +//! - User-space mmap: Applications access GPU buffers via mmap(). +//! +//! # Example +//! +//! ```ignore +//! use crate::mm::bar_user::BarUser; +//! +//! fn setup_bar1(mm: &mut GpuMm, bar1: &Bar1, pdb_addr: VramAddress) -> R= esult<()> { +//! let mut bar_user =3D BarUser::new(pdb_addr, MmuVersion::V2, 0x1000= _0000)?; +//! +//! // Map discontiguous physical pages to contiguous virtual range. +//! let pfns =3D [Pfn::new(0x100), Pfn::new(0x500), Pfn::new(0x200)]; +//! let access =3D bar_user.map(mm, bar1, &pfns, true)?; +//! +//! // Access the mapped region (offset is within the mapped range). +//! access.try_write32(0xDEAD_BEEF, 0x0)?; // Page 0, offset 0 +//! access.try_write32(0xCAFE_BABE, 0x1000)?; // Page 1, offset 0 +//! +//! let val =3D access.try_read32(0x0)?; +//! assert_eq!(val, 0xDEAD_BEEF); +//! +//! // Pages unmapped when `access` is dropped. +//! Ok(()) +//! } +//! ``` + +use kernel::{ + gpu::buddy::AllocatedBlocks, + prelude::*, + sync::Arc, // +}; + +use crate::{ + driver::Bar1, + mm::{ + pagetable::MmuVersion, + vmm::Vmm, + GpuMm, + Pfn, + Vfn, + VirtualAddress, + VramAddress, + PAGE_SIZE, // + }, +}; + +/// BAR1 user interface for virtual memory mappings. +/// +/// Owns a VMM instance with virtual address tracking and provides +/// BAR1-specific mapping and cleanup operations. +pub(crate) struct BarUser { + vmm: Vmm, +} + +impl BarUser { + /// Create a new [`BarUser`] with virtual address tracking. + pub(crate) fn new( + pdb_addr: VramAddress, + mmu_version: MmuVersion, + va_size: u64, + ) -> Result { + Ok(Self { + vmm: Vmm::new(pdb_addr, mmu_version, va_size)?, + }) + } + + /// Map a list of physical frame numbers to a contiguous virtual range. + /// + /// Allocates a contiguous virtual range from the VMM's virtual addres= s range + /// allocator, maps each PFN to consecutive VFNs, and returns a [`BarA= ccess`] object + /// for accessing the mapped region. + /// + /// The mappings are automatically unmapped and the virtual range is f= reed + /// when the returned [`BarAccess`] is dropped. + pub(crate) fn map<'a>( + &'a mut self, + mm: &'a mut GpuMm, + bar: &'a Bar1, + pfns: &[Pfn], + writable: bool, + ) -> Result> { + let num_pages =3D pfns.len(); + if num_pages =3D=3D 0 { + return Err(EINVAL); + } + + // Allocate contiguous virtual range. + let (vfn_start, vfn_alloc) =3D self.vmm.alloc_vfn_range(num_pages)= ?; + + // Map each PFN to its corresponding VFN. + for (i, &pfn) in pfns.iter().enumerate() { + let vfn =3D Vfn::new(vfn_start.raw() + i as u64); + self.vmm.map_page(mm, vfn, pfn, writable)?; + } + + Ok(BarAccess { + vmm: &mut self.vmm, + mm, + bar, + vfn_start, + num_pages, + _vfn_alloc: vfn_alloc, + }) + } +} + +/// Access object for a mapped BAR1 region. +/// +/// Provides read/write accessors to the mapped region. When dropped, auto= matically +/// unmaps all pages and frees the virtual range. +pub(crate) struct BarAccess<'a> { + vmm: &'a mut Vmm, + mm: &'a mut GpuMm, + bar: &'a Bar1, + vfn_start: Vfn, + num_pages: usize, + /// Holds the virtual range allocation; freed when [`BarAccess`] is dr= opped. + _vfn_alloc: Arc, +} + +impl<'a> BarAccess<'a> { + /// Get the base virtual address of this mapping. + pub(crate) fn base(&self) -> VirtualAddress { + VirtualAddress::from(self.vfn_start) + } + + /// Get the total size of the mapped region in bytes. + pub(crate) fn size(&self) -> usize { + self.num_pages * PAGE_SIZE + } + + /// Get the starting virtual frame number. + pub(crate) fn vfn_start(&self) -> Vfn { + self.vfn_start + } + + /// Get the number of pages in this mapping. + pub(crate) fn num_pages(&self) -> usize { + self.num_pages + } + + /// Translate an offset within this mapping to a BAR1 aperture offset. + fn bar_offset(&self, offset: usize) -> Result { + if offset >=3D self.size() { + return Err(EINVAL); + } + Ok(self.vfn_start.raw() as usize * PAGE_SIZE + offset) + } + + // Fallible accessors with runtime bounds checking. + + /// Read a 32-bit value at the given offset. + pub(crate) fn try_read32(&self, offset: usize) -> Result { + self.bar.try_read32(self.bar_offset(offset)?) + } + + /// Write a 32-bit value at the given offset. + pub(crate) fn try_write32(&self, value: u32, offset: usize) -> Result { + self.bar.try_write32(value, self.bar_offset(offset)?) + } + + /// Read a 64-bit value at the given offset. + pub(crate) fn try_read64(&self, offset: usize) -> Result { + self.bar.try_read64(self.bar_offset(offset)?) + } + + /// Write a 64-bit value at the given offset. + pub(crate) fn try_write64(&self, value: u64, offset: usize) -> Result { + self.bar.try_write64(value, self.bar_offset(offset)?) + } +} + +impl Drop for BarAccess<'_> { + fn drop(&mut self) { + // Unmap all pages in this access range. + for i in 0..self.num_pages { + let vfn =3D Vfn::new(self.vfn_start.raw() + i as u64); + let _ =3D self.vmm.unmap_page(self.mm, vfn); + } + } +} diff --git a/drivers/gpu/nova-core/mm/mod.rs b/drivers/gpu/nova-core/mm/mod= .rs index 53d726eb7296..449c2dea3e07 100644 --- a/drivers/gpu/nova-core/mm/mod.rs +++ b/drivers/gpu/nova-core/mm/mod.rs @@ -4,6 +4,7 @@ =20 #![expect(dead_code)] =20 +pub(crate) mod bar_user; pub(crate) mod pagetable; pub(crate) mod pramin; pub(crate) mod tlb; --=20 2.34.1 From nobody Sun Feb 8 09:32:51 2026 Received: from SN4PR2101CU001.outbound.protection.outlook.com (mail-southcentralusazon11012013.outbound.protection.outlook.com [40.93.195.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B0D44218B2; Tue, 20 Jan 2026 20:44:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.195.13 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941879; cv=fail; b=JxJX1vK1cnz5GsAjywAhSmweEzlm0CJ1kJtwoaKiBECNY1G5+GXo0GXMfVHofJk7EwtCPbHvPoVnMU1PHIV9jcXFnvP5Py7r5uIARYyr6vJzkmpNITFXtiURiknDNSfqFF1WrGfuyozThOOD0qpOZ5LfpZXTv9MH4c/qZKBeyP8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941879; c=relaxed/simple; bh=Rn5zr82JsVxIwklT7N5ivdmzKmJjmnrwwoTOEVV5/1o=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=D6v9X1h1L3/l6y/MfsClONiq324+P2PicHLf/KKvg8MRyl4T3dayFp6kWa2L77DCdWn3Jbmrl3yZGydr+14opbxS/SX4XEdmF5ToE9jOy4W41ce/vIYXJNEPfi8AhMYvUkKm6bNLufO+Fx3nl/AtDMt/JQ/s3KhMuszukLxgk68= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=toT30Znn; arc=fail smtp.client-ip=40.93.195.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="toT30Znn" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=dPgfZAc3czQKem7FCM4cSd9BGeBbyunqHawbI0zt/J9DOwMJHKh8bpkPQqZHqoJsuqjTk//0dCJKbLRbEUdXXJDnTduvMyVvzr/PaoRwr2/uGIt0lKB3HbQpADgQS40wUM/dcbZcMgMGTCBGZp8SWAKeGZOIN/qTeyvPXXiu4QNty7pqR4N5FtAOqJUcXxxIImzA7etQ9B/SEbQK7rFf+IaEJN+51LO3SsbeY2tbef5HsutUAJ1ILhc+JK/Pw4RMS6cpEDC0wfEWxmEngay6pwTubDvU5UrjCytHBero8ZK5LNawyfpHLd5MCEkhLHQ2hj3VzPBrUmmwQkoCtTWBBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=l6Fym6IOxLH1oGvPyGRIWX/L4NxJ8hy/yyw44QYQMrk=; b=mkAzFFKGdwkxt3hmBS3Vh5C4OWP3LHWDsEfKzztarvi647/Il0WRWORcjyZdF97tAYux7q00g9+jjkXuLPAfMMMN3OCIWsrxgoi8J2rjBRTlFY7TsjAg81To4IKxEpLTZLK2+m8zx5MItTc7SoHlYtyRpVJ6l7xDwFduOH3lxY6Q87AfrnDKWWhA3+7+I8oqLsm1T6nUqXR+2VKt3ACjB7x1YknwF9LBNvpOtnw2/OgsC3aXk4hrJ6yzOZ8JhOI9Aey75F4wZeOVrRXJpyNXOTYyoueGUOaBvMCflUenYcJV7q0NvP+q/zMWDl6sxOcu/k1TfS33ICeGkaO0keujFQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=l6Fym6IOxLH1oGvPyGRIWX/L4NxJ8hy/yyw44QYQMrk=; b=toT30Znn/Re0xdwSCrHUFnM373jquqmzFhlWUmBBHNpn5Jrz8ce39+/HfrlF03g5ESI0c/QODiqBZ6APX/qnlQXx38g11DgT1FH0vwsWI4WlAlhSmQtq8vsP2kE4LsZl/tVmES94zv9zsOUrhJJ02JS8BlLEqYTdOWdZwbnqV8G3UvR3TIZZxlCICC+1I9ypJ2AEW1tNWs194BgefLfpNl888h7XL5uIiuwjAoDe2BeX4ErynnXgBmbTqC4pDQJPKcsYFSU0g8y4MEh2BqKtvw2SvXqZduBV8+iji9Q40OnonuwNorCWO6CdNUWgTTybrSECJvjbBMszUyeLhjmRag== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by CY1PR12MB9651.namprd12.prod.outlook.com (2603:10b6:930:104::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.13; Tue, 20 Jan 2026 20:44:25 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9542.008; Tue, 20 Jan 2026 20:44:24 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jonathan Corbet , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Huang Rui , Matthew Auld , Matthew Brost , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Helge Deller , Danilo Krummrich , Alice Ryhl , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Alexey Ivanov , Balbir Singh , Philipp Stanner , Elle Rhumsaa , Daniel Almeida , joel@joelfernandes.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, linux-doc@vger.kernel.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-fbdev@vger.kernel.org, Joel Fernandes Subject: [PATCH RFC v6 20/26] nova-core: gsp: Return GspStaticInfo and FbLayout from boot() Date: Tue, 20 Jan 2026 15:42:57 -0500 Message-Id: <20260120204303.3229303-21-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120204303.3229303-1-joelagnelf@nvidia.com> References: <20260120204303.3229303-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BLAPR05CA0024.namprd05.prod.outlook.com (2603:10b6:208:36e::20) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|CY1PR12MB9651:EE_ X-MS-Office365-Filtering-Correlation-Id: 59890a79-e509-448d-11e3-08de5864b262 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?VOBJ69LBQQbwbDf/iom5qc11vHrWGDJ063aEmgdIT0xWKAlpqxT2vuh0gDCZ?= =?us-ascii?Q?IflDYYucYmVdYaxaXMz8D4N55Jm2Coqc6/3N8S1C4AEe6mIJsiZwxwtAdenc?= =?us-ascii?Q?zrsKhfzCbRduuXA3axmj4bZ7G8pcrvcQM2tBdrYu5pDK9y9U1NtnbKT3jwPf?= =?us-ascii?Q?LTjw0dwk4Mi2M1t4pPEdnrv6eAR2KmYiObkig8uZqSlR1uPY1Dg1rdC5KtNp?= =?us-ascii?Q?9snN0vDLSdAv0HtCtD1tsHKtN95j0voZOtCIXpmkrdmoxXwl0Y7HT23OjgnI?= =?us-ascii?Q?c3HM8MXfHKpHgrwfKdgyc8r04Zt/AbGDWv8gWPR+OPDu0KOT4vEWlq5jB83J?= =?us-ascii?Q?vXhCiBxCtAH7w7xvMHTWIsOWRnj5vGm+MChVpF6yrE+I6ThtaytmR1hJDXbT?= =?us-ascii?Q?TuoFcRRiXfB6dqENihDPQldbfHALh+E189gnbN3yQn/HEZMN2JanTO8mwV7X?= =?us-ascii?Q?QHD48BAzx2niSJpFhEWLDJX6p1bLHhLoV03X1Kz+mU99H/dTa9zxGQIOl/O/?= =?us-ascii?Q?AOtgCwNlZWvPl37zIeE41iyP9YBnp9L/zIAxk6wQ1Hpgk2tVJ4guvfmIGS3/?= =?us-ascii?Q?lJcN4HHZEHEB9BE9fWCfyPDFtty8z3uPRzOYh8uJiagToZ9hAoMf7aBjgeVN?= =?us-ascii?Q?gHt02RarbTwmjtA98NY3v7SD4qUJqHxEFua9Zg8I5Lk0UYPsgKkWy1gbOdW6?= =?us-ascii?Q?n8W70DkF9+jQAQUCUR2Y5UES5FALuS6jtCLZN9pk1nIUf9aAH3kqbZTlb6B6?= =?us-ascii?Q?mH/2tEW88qMOrVLb0m6nYPrJJi0zpo5H4O3yFiefMcbyQlDY5SxRP0HFY8zI?= =?us-ascii?Q?8AXya9cZuqJOGBhRFuTTfwJisSGHJcK/avgN6Si/SUCm+0WkWpVZH6G+Xsst?= =?us-ascii?Q?SLtTcefvbVLOb1QOYKpLv2SQtviAzH1sraREMZToRvMNXasDY+jYwakbjwZn?= =?us-ascii?Q?W6SjyPw4Vv7sZpbIOg1iR2ZjLfROJAs5uZCVuNS9++0ZKeWHrk2pbZWzlSK4?= =?us-ascii?Q?xttq2wWJzi5w//CqE0wLkvyVnv+LKz9P0hN9tqqfOiciu8bpGxmoJJ7R+Tn/?= =?us-ascii?Q?dkoVCub6iB5mGsMS+9+phDzBLGQVZBvEdDVq4mNe41WX864WJP09IXuekeC/?= =?us-ascii?Q?1NFFTlA5whf9vjIAjMaBtPE+O1v5gtbAccI0CdDDzi+VIb8zqv1Ixb1DoePO?= =?us-ascii?Q?JrzflmpxJXFeYKExEy58nizCiJ4oWsFQcwzaNpHukIqONJH/aypcOwiQd+ay?= =?us-ascii?Q?Tdlr5cThtUvqDfR4k6A1Bye6TNoTbIUBLR3IYnoqXZ2zALdeXP4d7Qto5dzX?= =?us-ascii?Q?D0S/921wA45zaG/WifkkfBuAZqxF1ndLCob1HSNlBMWjFTdnpx064sISUFuJ?= =?us-ascii?Q?hdd7LXF+l/LkLGPnU4MtQrq6cMiwxJ9aANLO57xYjzoBfrm1+8T1HIj0YbPq?= =?us-ascii?Q?vaGj0zFcUOXKfWL6RMrQWkFEq1h/6iE93ggEHqKrtpXLUXsAKtMQzEvT4FK0?= =?us-ascii?Q?i2pRgP/z+kPaBEy9rEX+52UmNQU30JIYoYzBWh1tG36vC2S4rUK4N49KMDPg?= =?us-ascii?Q?ayqdMDLn2QJvQA7VJm8=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR12MB6486.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(366016)(7416014)(376014);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?OIxYE2WNAGHf/QxYeGvQGKTv11OgJFadCLtyy6gDy0iIlvp7XFh1ZPwVI0ZB?= =?us-ascii?Q?jCxbWBUG92+reBZeL88Nrjj3aqW5SGll0Dt4Nwvjb+RIYNk/PAYTnebOrhsO?= =?us-ascii?Q?80XyOtojXe0hhReWLXAX20JQWl+NzeUEMWerJQRT6KF6Heb+udzQ/j8EKVzX?= =?us-ascii?Q?7c4jFudY5bV4sndBieqsGjMcy4+KGQ8APcaZb/3lfNEqFNNVfQINqL6fozLE?= =?us-ascii?Q?6o2GwEFW4odn2adRtJMXULUy7V23wLOx1mPCWuaEZysWLJlvcB5oENOBYLHo?= =?us-ascii?Q?1XViv93t1rgvYmlvu/yYiQiQrs+mAcqlsNcQCVTVeY868tE41ipYuIz1lGpr?= =?us-ascii?Q?t05j0APXMKLzeUHYp4DGBUjlu2UprH5hrL/w895lBbD/zsnxXdm/uNMiYH2+?= =?us-ascii?Q?efoSaqQhgTScvO7aJFLnCEqaMKZQG6nMuaCpFXQmTVV/AMGKpZ/ux0wpElV1?= =?us-ascii?Q?sHGbTsSr7dIKyrC18onZON7PYEE5etxED72FqTjo2J18EH4lfTq6/B9B1MS9?= =?us-ascii?Q?9wbnajx5L8dJMet6bqrNa5Bn8ID74EBdoFVgZY12UgJocgLuLKKbG7OUVfX/?= =?us-ascii?Q?cgrQMhIldrDWLDmc62pnS4BtKdMa2L0r2DYJnT5K259ar0D2pqsEyqC0MP3G?= =?us-ascii?Q?Zrlrh1mHlvcJhvFLgrGA+c/5ym6a2z53hhtF6QmstjrQmkob2g9IJ/DewP+d?= =?us-ascii?Q?+W67cHiPjiF2wYM0uhvNEwj7+uhGxheblaiRTWoTCID0maMHWP13bcQV7EDb?= =?us-ascii?Q?q8DHX2rKet/dIDMUQTeCtCM+YoIfxjNrqtPWsKKtSq6u8LtGmj+2yY29TSIx?= =?us-ascii?Q?8ADh2NuVrxYFTlD80nM8DsxXugzwNZwA6oYSwAMQNyPpMBTnvZpjKcOHayZD?= =?us-ascii?Q?Mzrjd0lE7TdgowJEAcOOXww5OHW1bArhH9JHAthE8vk5uA7OUjnV8DJ+MM+Z?= =?us-ascii?Q?2qdTEKMh9Lbtim5JKLzw41zCPun1fYUfTB+h0QogC8Rev7p7Hcd0Knisn00N?= =?us-ascii?Q?7Cr8ZRBJbG4vz+6D2jXg1gGwwnuQaA6MwoDfkdhjAqVhW/nmGYg4UnIoWVsT?= =?us-ascii?Q?+RHtaqFeiASHFOULVGIliTG26bceiIDzEeDv6PBo3lJFNSexNIdHSz78MmOR?= =?us-ascii?Q?msfJiXkXF9v/fipDXk69S47rS2DtmWFTSxdLRSwqZVPG8yOfALbnT/T5kGzW?= =?us-ascii?Q?qZqYh4a0KGExD3cjAJq8p0y2TO1YC2DNhWw3+qRPHb6jme7B8aO7E8dQwSRv?= =?us-ascii?Q?swPqEf8cs2D16o/bLZxx4IV4nuTVjncfB8fd3vT9Uruc8B5RE8GGG0EZboYF?= =?us-ascii?Q?l/jPuJw/CYRU/vF/A7hgZNTrGSlA698xcgbjX4nsyp9v7GdD3ML8VEWmjnx4?= =?us-ascii?Q?HoYFEUUUuSWKkz4XUJ52eHy+wUY2L+qqCms9sT0MAp/yd8E25aMeC9JtXqi7?= =?us-ascii?Q?p1LBRZSP1BirKqGbHkvShaZgLDuU1ZjiJ133BITHl6xIAw9pnC/gY8NKI80i?= =?us-ascii?Q?HFbDVOXTKYUM7BEAEye7iJ3bbbmFpbAs+DwTP4VlGf9+J+jqI8geO3z1uEkW?= =?us-ascii?Q?4Xte7CvbOumZTtXfRPKMmlx/XfWJSI/R+W9ei75aquAuDO+Cgv2+YO1dwyn3?= =?us-ascii?Q?4KmKxgXJ5GkNCPXat9MPEblCyTJfvxdszNQ47aEGkhgUf1nJ8WFPMISdUipW?= =?us-ascii?Q?WOijNIiFJukT0lyvps7TQ120oU/65Xkqe6UE9QkRpva5Ol3rAmM9K7EcqXwC?= =?us-ascii?Q?UmAgkSPPcg=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 59890a79-e509-448d-11e3-08de5864b262 X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB6486.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 20:44:24.8029 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ww+EmJl/fWsKzZdmDU1G1/iWD1GSViGcTM6wOzGUM6yNvPu0DflLw7zLhH3MM96+WnybY56T2CEaKWkoyG1bew== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR12MB9651 Content-Type: text/plain; charset="utf-8" Refactor the GSP boot function to return the GspStaticInfo and FbLayout. This enables access required for memory management initialization to: - bar1_pde_base: BAR1 page directory base. - bar2_pde_base: BAR2 page directory base. - usable memory regions in vidmem. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/gpu.rs | 9 +++++++-- drivers/gpu/nova-core/gsp/boot.rs | 15 ++++++++++++--- 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 572e6d4502bc..91ec7f7910e9 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -20,7 +20,10 @@ }, fb::SysmemFlush, gfw, - gsp::Gsp, + gsp::{ + commands::GetGspStaticInfoReply, + Gsp, // + }, mm::GpuMm, regs, }; @@ -257,6 +260,8 @@ pub(crate) struct Gpu { /// GSP runtime data. Temporarily an empty placeholder. #[pin] gsp: Gsp, + /// Static GPU information from GSP. + gsp_static_info: GetGspStaticInfoReply, } =20 impl Gpu { @@ -297,7 +302,7 @@ pub(crate) fn new<'a>( =20 gsp <- Gsp::new(pdev), =20 - _: { gsp.boot(pdev, bar, spec.chipset, gsp_falcon, sec2_falcon= )? }, + gsp_static_info: { gsp.boot(pdev, bar, spec.chipset, gsp_falco= n, sec2_falcon)?.0 }, =20 bar: devres_bar, }) diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/= boot.rs index 581b412554dc..75f949bc4864 100644 --- a/drivers/gpu/nova-core/gsp/boot.rs +++ b/drivers/gpu/nova-core/gsp/boot.rs @@ -32,7 +32,10 @@ }, gpu::Chipset, gsp::{ - commands, + commands::{ + self, + GetGspStaticInfoReply, // + }, sequencer::{ GspSequencer, GspSequencerParams, // @@ -127,6 +130,12 @@ fn run_fwsec_frts( /// structures that the GSP will use at runtime. /// /// Upon return, the GSP is up and running, and its runtime object giv= en as return value. + /// + /// Returns a tuple containing: + /// - [`GetGspStaticInfoReply`]: Static GPU information from GSP, incl= uding the BAR1 page + /// directory base address needed for memory management. + /// - [`FbLayout`]: Frame buffer layout computed during boot, containi= ng memory regions + /// required for [`GpuMm`] initialization. pub(crate) fn boot( mut self: Pin<&mut Self>, pdev: &pci::Device, @@ -134,7 +143,7 @@ pub(crate) fn boot( chipset: Chipset, gsp_falcon: &Falcon, sec2_falcon: &Falcon, - ) -> Result { + ) -> Result<(GetGspStaticInfoReply, FbLayout)> { let dev =3D pdev.as_ref(); =20 let bios =3D Vbios::new(dev, bar)?; @@ -243,6 +252,6 @@ pub(crate) fn boot( Err(e) =3D> dev_warn!(pdev.as_ref(), "GPU name unavailable: {:= ?}\n", e), } =20 - Ok(()) + Ok((info, fb_layout)) } } --=20 2.34.1 From nobody Sun Feb 8 09:32:51 2026 Received: from SN4PR2101CU001.outbound.protection.outlook.com (mail-southcentralusazon11012013.outbound.protection.outlook.com [40.93.195.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08F0E4418DC; Tue, 20 Jan 2026 20:44:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.195.13 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941884; cv=fail; b=EHgN9cEG4A1fMM69P0QzELCmokDfV32nU4st+gExHZjjj8S0hCmJ2/y2hNbRuAcQ8tLPCj0A1UOYMOl2YAFe21CNnDaWMZ2H6tJIAUGxakkb8owfgmgrBwAXiniVkZwhcNfQ4RrcA9D4zlVsBfGQfR21Q1o/Rq+uOOC7gZHtK4E= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941884; c=relaxed/simple; bh=BvKySZNsDc7QLbdq39745irzTvQhRaXMKYusrUqcmg0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=FhxF2jTAgzZ/6x9/amP74q+NRrBqq2kJK6cjO2NwCyub1CmMA2c45PJvowIpNVd4GxXVjU6BisTZvuolMEu+V5Ftuim4OP1ThLJ97F1blZN8JTpGQusjIigjK1CgJwrNIL/66UVbSJM0gTHJeJnNe5A6p574tGbPcN6GMiZFDio= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=gk2FYGpZ; arc=fail smtp.client-ip=40.93.195.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="gk2FYGpZ" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=jqw8l3QVEW/CqL3geQUW3l7pLJkQuU4XvNfofaUWSJp1exTrxl3AFDKOfk1zwaTrXoFKNGvL8QRImbVtCX2z3BD3j1o6g/3fFIK74McQKQ7kC0lYir1x/oN5BRrtINlyg44pfjmD1IM01zXtiCL+SbjpXjGM/NmwVrlzK7lt/P0yZOio4QCOhTx+BS1Lpnqqi0V31faUp58SNn9um8gYAzR077Zp6uj3iTxSj0dJp/4gv3o/47IYmGgcVwibJ4iEEUBiQ5jiSf1urKDE4BMzSsKk2JxM6Twyn9G89g19Aso7wF2MW4CDu/gnL7IU+B90In5xVDYaXbpWhO9wLpuSoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Yj3vA9psJcSaKDulHgpZPmwInF4j839R/DwTqlhUnh4=; b=P6trYYNnqxDYQprrjVAfOerxNMgoTmT9wE58/cScGG66GJa5+xVwZaVegWxG9+sbB5XKEImFLJDNFwWsWiPJzK0LEhkhrH+lur0ktiFE1wi5gtya2Qit9woIQzYPwjK8vp0x3DKnPJyroU3vRW/hQrDt1v6yS4W5wN54a6qZRA8GzBJAPv8aAFSJAIRi4I6nF8+Sj+W41XQfsRk70tkIW1DlC8247WQoUevEX8lG5Q6puGUgfkG1DkMEh1nnz2kr9IF4lm82Qlop3nP63D4AWiiU4ThirOyBN6SbXtJPibnf75hdQ+C1eu+izEoThLsoS/n8yvLlM79mtyhc8MaoRA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Yj3vA9psJcSaKDulHgpZPmwInF4j839R/DwTqlhUnh4=; b=gk2FYGpZDq/p4JWLvU6ymmWP/I6eqP/89kepwMMQ6v2maHqO2e7BWnYWM7R/jSlYaxh6qrREcsXiJ4PVrNlTyulMphiS4CDuD5G0Tx5o90CYy3nasx1BwtPpmMKH/vMpm5SPEXZSl9gL3CebNEtpKojgCedA/2EUe+k0WCYXfWTulRXIRWD0koYfv+TwJO/weUdm9rhn0scPcqNJDGbuJAyWovLDN6gFer/+sV4SaINiEO53s/AhtWMb+u0EeY+0px/rU1xW7S4EKAKcF6OX2eDFFgvHz0pDX7r5YvPuqU+x5Hu037h5yL7XVMZkB+zwXz51dSRvx3qKeZCoaD3iPQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by CY1PR12MB9651.namprd12.prod.outlook.com (2603:10b6:930:104::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.13; Tue, 20 Jan 2026 20:44:26 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9542.008; Tue, 20 Jan 2026 20:44:26 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jonathan Corbet , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Huang Rui , Matthew Auld , Matthew Brost , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Helge Deller , Danilo Krummrich , Alice Ryhl , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Alexey Ivanov , Balbir Singh , Philipp Stanner , Elle Rhumsaa , Daniel Almeida , joel@joelfernandes.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, linux-doc@vger.kernel.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-fbdev@vger.kernel.org, Joel Fernandes Subject: [PATCH RFC v6 21/26] nova-core: mm: Add memory management self-tests Date: Tue, 20 Jan 2026 15:42:58 -0500 Message-Id: <20260120204303.3229303-22-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120204303.3229303-1-joelagnelf@nvidia.com> References: <20260120204303.3229303-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MN2PR20CA0066.namprd20.prod.outlook.com (2603:10b6:208:235::35) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|CY1PR12MB9651:EE_ X-MS-Office365-Filtering-Correlation-Id: 57be3f57-2271-4964-f841-08de5864b363 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?NiNG7GUYUpGXD7Dji644zLw/00G9UAoGhBUWgClsUwkSUQxgP9TJSpDpxDGp?= =?us-ascii?Q?I1ViU6HT4yJkWkb7Ca7zINYd1hvH+y5G3jvAhqo2ODpCyPdv3FCWPUGJGzS5?= =?us-ascii?Q?HMRn0xp96H4vbr/B3JP6sI8tdobzoVviP07jdbHY/cyCZYug3EwCejezqGql?= =?us-ascii?Q?Wsd59JBuAnVemOxnQE4R+2/RB5FagHG7i17oHkkf+lWY5NEFnegy/yR52kSx?= =?us-ascii?Q?XAyXfnBDXKzaKMkIuuuJc5KUklRuFSFRaZxTSCYnH0a/V/Q0C5pNL3JcooS5?= =?us-ascii?Q?+zx5ojrND7lhlNWr0om4a3yQYPaVOAiM+ris8zBgfbS5EIngCTeGjoH3pDad?= =?us-ascii?Q?h1CLhBQJupwYF7nLxBvdV7qt2moi0cqCAYYRowDXhn/MOT3bMXl4kXFXKhqK?= =?us-ascii?Q?rr1Gp+FE3f9NodhvMetHZHBrq8KvdCwSczwQMhHF4FfHEVrq4z8XuEXrpAwY?= =?us-ascii?Q?BBuypCEaDsg8BxjcGSXjj8yy6cJqMg8bPOmK6/qwH7u1tIXRtSXWksSXbGj3?= =?us-ascii?Q?Py7cZA3//EpP5eg05e1f0opBt5rFEeHtic6lv16415MWxOmniKgQgg7aLO7C?= =?us-ascii?Q?mPayHykZQV0YlxdlCTUbRJAlyoFKqPWX3WuLJ7mxUsVfB+J+TyPmafeR9I27?= =?us-ascii?Q?WbZLEp/zx9L5dNr/Z2gMY+solmYsi1FYXrMAxiD2i6uFAqJVv0wUggS211DZ?= =?us-ascii?Q?UpnfqRKbjhAyrySCJ9/nrtC7jSwLEU6nexEOOMseODMhDNKHvtYSd2Q8I6TU?= =?us-ascii?Q?dm4hgg17RkoNOpsKMrJ6TxOx2FrJVZ6Sm0fV0Q9cefyXCSfaWig7CTBzaFoP?= =?us-ascii?Q?BELYdJtUcRC+oZ0HdUONS3fSgB5R1i0oHlCc4st7NwA8glWIQbfx425xJTna?= =?us-ascii?Q?6lIJq1V27wMl4YPrx7D8gOYTkS1mYe5PiphefXasZ8jaSLc8XLpRh2/JCWg9?= =?us-ascii?Q?j+GLsu4T1mHk3L+iHzVonAsqhBuxz1bEOexPnyWj+m32iBEaOvjVVSqlxCt4?= =?us-ascii?Q?+fEJ5gC+TBWDLoS5F9JRhEhve0AsyHZnJ+RILahLwU+FkQy1Ne+iAB6TBsPo?= =?us-ascii?Q?R1OvcXE27qbPzGDM9f/Yrf5Gycy360R59jhQ+47mBFnj3z+xOqdHK3Z1haWB?= =?us-ascii?Q?jp6bFgQJ6hBnV6YDWTA6lLVE+MrtYLOhq+4ybkOVE+Cx79KYUJnmmnyCVTQy?= =?us-ascii?Q?MK5cDD00Ii0a8zlf2QCSYO+koE8TVROzjZlyw3/mpadzuZzStgW7lxBuvelH?= =?us-ascii?Q?2Fr6Rv53CO4btA+Vqyc4LSnXKzaPQhPaidcnBroBKNy8QtF5K9V/6eFYGB/a?= =?us-ascii?Q?w3kK3/YkfjC2SCo28zk72Brr0l/xGyCPxW0+JrK3aDCv1EeZEG+i9Dxa1nQY?= =?us-ascii?Q?gpyQ/Wi/GWiCg7jyspHjjGjhcrVkMmmAKgGHPytFg8CWk+UQwqWEzQYtSjn2?= =?us-ascii?Q?65whLj58wqxJg/yXC0PmF42yo7NNXIejUxqrEbGwUSNTN2xsnMjir8IqvzHj?= =?us-ascii?Q?acjdfB1Gk/z+cMXrqG9lKaNp5ukOYKSG4TD/JAUnqjP1pf4ro7bIRPRVRDuT?= =?us-ascii?Q?X9oVMhUdrx0hs6zrpq0=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR12MB6486.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(366016)(7416014)(376014);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?mFpVSFboKug8TqNeZ96Uxa95wNfpxDEDV2KwfBVswqgcnPFLNApCJ7TozvZA?= =?us-ascii?Q?ymFfNknqpuerKogFlihgUQ/+txA9gpWrKCq01lCwAN45PRbPajGnKRjMVld6?= =?us-ascii?Q?bkGh7AnVGdXlgAyDzt1wGv/9LQuA4I5frGcatHjFR3UMHZ038KHkbpgVUTHU?= =?us-ascii?Q?sodWE63FDKFbstuSFIJuxJz9gZwVTQdIKmRMl1E5RzkKplLmBJVj0FzJt4li?= =?us-ascii?Q?ZFojG7xqQQxkT/Ri4tXiKmBq6ym68W38NrBx47uAdPlvAobpNOVZm9qUaQQ0?= =?us-ascii?Q?ChY0+zjh7KfzNSC28GkO6BJIlUxD44tT4GvlJnudrouONqFtdeNW/dNtz1e8?= =?us-ascii?Q?v9czWwZ0JAfaJVga9o6t33UjKx0UwXFPhfdvBr8EtmrKOVW7N3IalLHCQP5I?= =?us-ascii?Q?/S8ZXGjMUMlcFMbxfZyX6t0qkJtN4LgiRoiQEmRGiyoK59vdzvLJE8HZilz3?= =?us-ascii?Q?MYvCg/+lHBjCVfCrKQpEr8SHaP1ZVkl+jmT3YMqxFWv8/MILlR3hvfxaV80/?= =?us-ascii?Q?RzoD7NZXpmK3oslujd0CZd2+/JjCAwg/AhAOWGJiTqnn/cxMi6jahaTrusgr?= =?us-ascii?Q?A8WMrOn+82GAUjvU7XWZAfVhwHnA6mJyj1s7Z1B6H0cFOQxkdEOqWouNTS5w?= =?us-ascii?Q?mXAlQn5seOA3i8x63HXsSIJLWg6+UODxZB7JCSJKtivJHdX8rXjFpUz/oz99?= =?us-ascii?Q?lGIyvfDitQbJ+zLrdD/iKZ1ams1B8JgarY6zxB4vxECbedDyc+TJTOxZNGKm?= =?us-ascii?Q?PJ1LjABKBKNuuAkl0pcieXa8R/KbNMG6EdvdahyE6cgTMulaGQj9UphYUj/Y?= =?us-ascii?Q?AxXSYm8kKgPfGiiF90QDdOuWsSCmtSaEGIgYbY6A+x7NquE5WNFMdrm3pfVK?= =?us-ascii?Q?EXOkjkSla5dD/Gu0grVVziHjLPSv/WSHVSN/mrlmwFEJb1KDuCcH9u5JUjPd?= =?us-ascii?Q?HcraJbzCrbUhU36YYTBQ6Xtp2RrllnFm59wH0q/1Zy18wvtvSeV1jmyqyJkc?= =?us-ascii?Q?/Dbh29m4s+VPkaqiQXvc6GNa6QP/5JGT+xJb91Mb7+Y08N9qNrmuPMiMDOhB?= =?us-ascii?Q?ELq2NWC5V/zi8CyZr+zYWlCxNhYtF7SjFV62mjpTkI8JMRhYW2GWGDygU/JT?= =?us-ascii?Q?rXeYs2x5FzJYKPbNfFeDRKLs0R5nU2Ah6gIcgprTWFDFChnUxuxeisVyI2qR?= =?us-ascii?Q?kbViYW3HxAzvJTfD497CF7hM4AkzY7IR6hY3igAm6bEuNbrr1pjp1bBDvmTQ?= =?us-ascii?Q?6qZdWb1qooeY+zgqUaqq9pBOMTC3b8qbwiDlRK8fSTt7WlxC6HV7sGpFH6Gv?= =?us-ascii?Q?t5tugiWEs2k8UR7QuB7O2L1jFYhy6kylouPlAzlF75FQh6u/XjFNwAUdMy54?= =?us-ascii?Q?W+/j45EzWjn5GGQNnHhKkjJ7A3JvcNWoJwvNLhvEjMhhFPi80ntUiUK5fIdc?= =?us-ascii?Q?vbAHSlm7WTkyDMQuXtidBSOugHCDpjLTswRnA9xhUczO3aBLFpAvs6Vswf9i?= =?us-ascii?Q?ggI6OaCDk6oiEsO5pqnKASSpeoFbC1kZrS8gD9jQYI/+/ooCMKQ0xGWf5fsa?= =?us-ascii?Q?Ii5FO+l0UWJwMAhPyh+EjwLmFS8N7tF0On2+Pso3Bb9y/RQID8mW1f+7qI4y?= =?us-ascii?Q?ZXNW/KHt8ruwxpwbp5BLIWMvELHTsaUYPA0MSGWfCJcLyB7mWe2G7uubFwFC?= =?us-ascii?Q?4CNR4PCPfV2q8SnI+azISqLZ4NrDqwZs8wf2Z46wJrYSUt4B7da+N7TpuFbw?= =?us-ascii?Q?HxS9Vq71hA=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 57be3f57-2271-4964-f841-08de5864b363 X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB6486.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 20:44:26.5307 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 15B3EGlKPKU91G3wZWdeGxAvrzE0xU982H8F2Si2HlVp54w5yz0uRoHLQZxu67y++uILTmYHu+BGlsjw7Gv7ow== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR12MB9651 Content-Type: text/plain; charset="utf-8" Add comprehensive self-tests for the MM subsystem that run during driver probe when CONFIG_NOVA_MM_SELFTESTS is enabled (default disabled). These result in testing the Vmm, buddy, bar1 and pramin all of which should function correctly for the tests to pass. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/Kconfig | 10 ++ drivers/gpu/nova-core/driver.rs | 2 + drivers/gpu/nova-core/gpu.rs | 43 ++++++++ drivers/gpu/nova-core/gsp/commands.rs | 1 - drivers/gpu/nova-core/mm/bar_user.rs | 141 ++++++++++++++++++++++++++ 5 files changed, 196 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nova-core/Kconfig b/drivers/gpu/nova-core/Kconfig index 809485167aff..257bca5aa0ef 100644 --- a/drivers/gpu/nova-core/Kconfig +++ b/drivers/gpu/nova-core/Kconfig @@ -15,3 +15,13 @@ config NOVA_CORE This driver is work in progress and may not be functional. =20 If M is selected, the module will be called nova_core. + +config NOVA_MM_SELFTESTS + bool "Memory management self-tests" + depends on NOVA_CORE + help + Enable self-tests for the memory management subsystem. When enabled, + tests are run during GPU probe to verify page table walking and + BAR1 virtual memory mapping functionality. + + This is a testing option and is default-disabled. diff --git a/drivers/gpu/nova-core/driver.rs b/drivers/gpu/nova-core/driver= .rs index d8b2e967ba4c..7d0d09939835 100644 --- a/drivers/gpu/nova-core/driver.rs +++ b/drivers/gpu/nova-core/driver.rs @@ -92,6 +92,8 @@ fn probe(pdev: &pci::Device, _info: &Self::IdInfo) = -> impl PinInit) { .inspect(|bar| self.sysmem_flush.unregister(bar)) .is_err()); } + + /// Run selftests on the constructed [`Gpu`]. + pub(crate) fn run_selftests( + mut self: Pin<&mut Self>, + pdev: &pci::Device, + ) -> Result { + self.as_mut().run_mm_selftest(pdev)?; + Ok(()) + } + + fn run_mm_selftest(mut self: Pin<&mut Self>, pdev: &pci::Device) -> Result { + #[cfg(CONFIG_NOVA_MM_SELFTESTS)] + { + use crate::driver::BAR1_SIZE; + use crate::mm::pagetable::MmuVersion; + use kernel::c_str; + + let bar1 =3D Arc::pin_init( + pdev.iomap_region_sized::(1, c_str!("nova-core/= bar1")), + GFP_KERNEL, + )?; + let bar1_access =3D bar1.access(pdev.as_ref())?; + + // Use projection to access non-pinned fields. + let proj =3D self.as_mut().project(); + let bar1_pde_base =3D proj.gsp_static_info.bar1_pde_base(); + let mm =3D proj.mm; + let mmu_version =3D MmuVersion::from(proj.spec.chipset.arch()); + + crate::mm::bar_user::run_self_test( + pdev.as_ref(), + mm, + bar1_access, + bar1_pde_base, + mmu_version, + )?; + } + + // Suppress unused warnings when selftests disabled. + let _ =3D &mut self; + let _ =3D pdev; + Ok(()) + } } diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/= gsp/commands.rs index 7b5025cba106..311f65f8367b 100644 --- a/drivers/gpu/nova-core/gsp/commands.rs +++ b/drivers/gpu/nova-core/gsp/commands.rs @@ -232,7 +232,6 @@ pub(crate) fn gpu_name(&self) -> core::result::Result<&= str, GpuNameError> { } =20 /// Returns the BAR1 Page Directory Entry base address. - #[expect(dead_code)] pub(crate) fn bar1_pde_base(&self) -> u64 { self.bar1_pde_base } diff --git a/drivers/gpu/nova-core/mm/bar_user.rs b/drivers/gpu/nova-core/m= m/bar_user.rs index 288dec0ae920..e19906d5bcc6 100644 --- a/drivers/gpu/nova-core/mm/bar_user.rs +++ b/drivers/gpu/nova-core/mm/bar_user.rs @@ -193,3 +193,144 @@ fn drop(&mut self) { } } } + +/// Run MM subsystem self-tests during probe. +/// +/// Tests page table infrastructure and BAR1 MMIO access using the BAR1 +/// address space initialized by GSP-RM. Uses the GpuMm's buddy allocator +/// to allocate page tables and test pages as needed. +#[cfg(CONFIG_NOVA_MM_SELFTESTS)] +pub(crate) fn run_self_test( + dev: &kernel::device::Device, + mm: &mut GpuMm, + bar1: &crate::driver::Bar1, + bar1_pdb: u64, + mmu_version: MmuVersion, +) -> Result { + use crate::mm::vmm::Vmm; + use crate::mm::PAGE_SIZE; + use kernel::gpu::buddy::BuddyFlags; + use kernel::gpu::buddy::GpuBuddyAllocParams; + use kernel::sizes::{ + SZ_4K, + SZ_64K, // + }; + + // Self-tests only support MMU v2 (Turing/Ampere/Ada). + if mmu_version !=3D MmuVersion::V2 { + dev_info!( + dev, + "MM: Skipping self-tests for MMU {:?} (only V2 supported)\n", + mmu_version + ); + return Ok(()); + } + + // Test patterns - distinct values to detect stale reads. + const PATTERN_PRAMIN: u32 =3D 0xDEAD_BEEF; + const PATTERN_BAR1: u32 =3D 0xCAFE_BABE; + + dev_info!(dev, "MM: Starting self-test...\n"); + + let pdb_addr =3D VramAddress::new(bar1_pdb); + + // Phase 1: Check if page tables are in VRAM (accessible via PRAMIN). + { + use crate::mm::pagetable::ver2::Pde; + use crate::mm::pagetable::AperturePde; + + // Read PDB[0] to check the aperture of the first L1 pointer. + let pdb_entry_raw =3D mm.pramin().try_read64(pdb_addr.raw())?; + let pdb_entry =3D Pde::new(pdb_entry_raw); + + if !pdb_entry.is_valid() { + dev_info!(dev, "MM: Self-test SKIPPED - no valid page tables\n= "); + return Ok(()); + } + + if pdb_entry.aperture() !=3D AperturePde::VideoMemory { + dev_info!(dev, "MM: Self-test SKIPPED - requires VRAM-based pa= ge tables\n"); + return Ok(()); + } + } + + // Phase 2: Allocate a test page from the buddy allocator. + let alloc_params =3D GpuBuddyAllocParams { + start_range_address: 0, + end_range_address: 0, + size_bytes: SZ_4K as u64, + min_block_size_bytes: SZ_4K as u64, + buddy_flags: BuddyFlags::try_new(0)?, + }; + + let test_page_blocks =3D mm.buddy().alloc_blocks(alloc_params)?; + let test_vram_offset =3D test_page_blocks.iter().next().ok_or(ENOMEM)?= .offset(); + let test_vram =3D VramAddress::new(test_vram_offset); + let test_pfn =3D Pfn::from(test_vram); + + // Use VFN 8 (offset 0x8000) for the test mapping. + // This is within the BAR1 aperture and will trigger page table alloca= tion. + let test_vfn =3D Vfn::new(8u64); + + // Create a VMM of size 64K to track virtual memory mappings. + let mut vmm =3D Vmm::new(pdb_addr, MmuVersion::V2, SZ_64K as u64)?; + + // Phase 3+4: Create mapping using `GpuMm` and `Vmm`. + vmm.map_page(mm, test_vfn, test_pfn, true)?; + + // Phase 5: Test the mapping. + // Pre-compute test addresses for each access path. + // Use distinct offsets within the page for read (0x100) and write (0x= 200) tests. + let bar1_base_offset =3D test_vfn.raw() as usize * PAGE_SIZE; + let bar1_read_offset: usize =3D bar1_base_offset + 0x100; + let bar1_write_offset: usize =3D bar1_base_offset + 0x200; + let vram_read_addr: usize =3D test_vram.raw() + 0x100; + let vram_write_addr: usize =3D test_vram.raw() + 0x200; + + // Test 1: Write via PRAMIN, read via BAR1. + mm.pramin().try_write32(vram_read_addr, PATTERN_PRAMIN)?; + + // Read back via BAR1 aperture. + let bar1_value =3D bar1.try_read32(bar1_read_offset)?; + + let test1_passed =3D if bar1_value =3D=3D PATTERN_PRAMIN { + true + } else { + dev_err!( + dev, + "MM: Test 1 FAILED - Expected {:#010x}, got {:#010x}\n", + PATTERN_PRAMIN, + bar1_value + ); + false + }; + + // Test 2: Write via BAR1, read via PRAMIN. + bar1.try_write32(PATTERN_BAR1, bar1_write_offset)?; + + // Read back via PRAMIN. + let pramin_value =3D mm.pramin().try_read32(vram_write_addr)?; + + let test2_passed =3D if pramin_value =3D=3D PATTERN_BAR1 { + true + } else { + dev_err!( + dev, + "MM: Test 2 FAILED - Expected {:#010x}, got {:#010x}\n", + PATTERN_BAR1, + pramin_value + ); + false + }; + + // Phase 6: Cleanup - invalidate PTE. + vmm.unmap_page(mm, test_vfn)?; + + if test1_passed && test2_passed { + dev_info!(dev, "MM: All self-tests PASSED\n"); + Ok(()) + } else { + dev_err!(dev, "MM: Self-tests FAILED\n"); + Err(EIO) + } +} --=20 2.34.1 From nobody Sun Feb 8 09:32:51 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013061.outbound.protection.outlook.com [40.93.201.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97ABA44D005; Tue, 20 Jan 2026 20:44:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.201.61 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941887; cv=fail; b=dvQnKFPBg54514/r1bw0pfdtttRvaT0LtjPu+Kzncfv4ZGn2GufxFYwdri9GFs71/Xcgzt49MlJRE5FO/00oLA1+WcGjK4pDcH3krh2iezt6GFN87ivb99s36DiLRKO1RdhKSRGhXEkT60BbH2i6E3cmVEH6+2zqbkUCfCvUaVg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941887; c=relaxed/simple; bh=n84Wxur5RhF3dGKtXZohAG38OKUwYHMiNurPQha/f8E=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=lh91IQL3Wsffz5/8RSqYWz9/TpNQI8UdsIENem4k/RkVm765o7sPnWkD4wobsp6ovQwVzFVtb/sCnd4SUT787i5MzwQqntdTvQNy+IG+pmo7QaJC/jecl+Jj6QI6dgDMaGcE1Q9xpJ8FnwFm0qFLrjj94TWaIZznO7Fm8fxbQ3k= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=kjG74h7+; arc=fail smtp.client-ip=40.93.201.61 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="kjG74h7+" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=CpZhTczc54LBgZcUUShAXnIt24Jk/6aMNn6ejrbYxICw4WKl7eObMaaz+ghUCDpXBxh0YXdovXQjIfP2dLw9QxreqJwKCTW2cBJZF/5ztOFcI6BPHZBgtkIxhLEcRjwgaSWHRHon8xilAEF/NbjvGA+Qcyf4HaKhknkxwJX9IfmSl9ECVV4jsVkclMejDDJG7WuKMAD2n4xmd6DLTbWJ6ie93bBedDROsiJ0gBEaasHd+Ci/vqjkpXDRHppZ/VPrwDZgdtQAUB7/9qT6YFIC3RG3dWPE+m499fvJ5kwuISBm98Lo2hA+OqetHk830Ji9cjTyPZy0xrAL4fkloNqYXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=fNts2CmvatAyriteG+SRpJclNlHKGoF0tPzgCYqNO2o=; b=r4zLxg+hvIcaYq0VQ1Ra5pFbBbbVx3Eru8gG1DuCWRXAPdhdUM7APDVV6apIkGDPUxR2EAEf1xUkLSWItiHzPmfTecVukD9y+4i9gsFcPReThYjzFfoSgSfHl0nntIUB/8Lz+ZxyOVFXDS78C0MTZARjw9AGaM21+iiU65ErIEiX3R0moe5MsDEqWyjM135LpTHEsP2jeYc3sLY82sARTVr7MQDObzHtYRZWD6FFHg+Wjn//cLoEpBiAfDrNit9qHlKrpXQFqgl1rXXnNeEUQVO/l9Vc5zzrFyhu2aft5YsIBVtFg2vYICwqUa5UnKxVEdmCMTGOV24uiv8/hJqWdw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=fNts2CmvatAyriteG+SRpJclNlHKGoF0tPzgCYqNO2o=; b=kjG74h7+w0R+eCsy+zRmxTKKOpXizDeRsxnafrnfJZ2IehsZIm8DbDTWsKdXhfGOOBfvobVC/fB+cOHuKA2czOZUOnQSb/tKbDPrV48kPr+/SyIAjhlWba7qwVNeAB2XS5boCX/AXidYNmfm5YjMwUstRwZp/VjOAvd9CPQKef814b4SvIeJoipsr7/hkKIefS00/11q7lnLP6wMHdSPZT8MMk1TfUmxW0yq2FU0RwzVABLUvqRaFfwJF0+LO/a92ANtaH7G37TrEU8+P/RQy1nFBj2E/CiBv2XHXRn2KlpXqcpX2t55jQXw/tnySTJiHw98/Hl1gccVWCrS+2gntQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by CY1PR12MB9651.namprd12.prod.outlook.com (2603:10b6:930:104::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.13; Tue, 20 Jan 2026 20:44:28 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9542.008; Tue, 20 Jan 2026 20:44:28 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jonathan Corbet , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Huang Rui , Matthew Auld , Matthew Brost , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Helge Deller , Danilo Krummrich , Alice Ryhl , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Alexey Ivanov , Balbir Singh , Philipp Stanner , Elle Rhumsaa , Daniel Almeida , joel@joelfernandes.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, linux-doc@vger.kernel.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-fbdev@vger.kernel.org, Joel Fernandes Subject: [PATCH RFC v6 22/26] nova-core: mm: Add PRAMIN aperture self-tests Date: Tue, 20 Jan 2026 15:42:59 -0500 Message-Id: <20260120204303.3229303-23-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120204303.3229303-1-joelagnelf@nvidia.com> References: <20260120204303.3229303-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MN2PR20CA0057.namprd20.prod.outlook.com (2603:10b6:208:235::26) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|CY1PR12MB9651:EE_ X-MS-Office365-Filtering-Correlation-Id: 430b97a4-a43c-4ba1-dec1-08de5864b46f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?5Lpir1Q3pFdQMvUfJeVXUUFtfMjwoNNREsxEPtBA+eDzTQZtr/YrpRdg+dbz?= =?us-ascii?Q?WAEPAOGfi76+q1HUGesxLy27bLoZTLqDiylPjIl4Eku4vfHnshdlAkJ3GW2P?= =?us-ascii?Q?VFxSuJHkE+jTp6es/JgNMhNOp5zBOav7roZXYzRGxXfhGtoHukdn/ECEXtyh?= =?us-ascii?Q?OxNegu5d8TQgALpUPLcGSG87cUcwSOm5zIgZzfr6ZhgaxpUlCwLcIY3a0W+V?= =?us-ascii?Q?6K+gUjopTDPu29C3PCbE/9rLME0XKWg9Bz7Ik7FYPWZiOcEJ8oAucxwKylpN?= =?us-ascii?Q?+qhW5IZtlu9i+Dd7zVAUJ+Yrtr7qW5JfrgoukGWbV++ZypwoncK3ATsS9zGK?= =?us-ascii?Q?1eI1dt8C6pnC0Z/U4kwcB5dXJIqpxI0oz5icJAWzIiHLSI+Iro6m52HsCnN/?= =?us-ascii?Q?3hpcpXn0j0pi0+ePf+PcqHZvQfoL5rD4owXWhC6bft+tCEccRyM+9zjYnYZv?= =?us-ascii?Q?1YROxkH7REhjR+CPsk0iKdinzRAylQ7cIavKG96xX6/HJ23/Dv2LTfC8Ri9d?= =?us-ascii?Q?du+bKZMbUsn9JgpqWQW64i78MOLBw0Qn6yGDMVNnPXN/s+2BNXkU0KeQtZLT?= =?us-ascii?Q?lm2HA8SMNum+5+BEskM3FKkOnLRjEbympNDIN8grEHPzPUBNaxbz3nh0xrSA?= =?us-ascii?Q?9Yh6ZG35w6zXIVEljTQyoACg01PVhAu+xwsYXZ7CkHM0Uzbh7jTn5TRYXAIL?= =?us-ascii?Q?hvBHGRt8TPSGy+urbf7ngo1GY31wwAn/ca8RHzJg6qXwe9Y9CFSX6+kIPq8z?= =?us-ascii?Q?Es1VQZRqLEtCy+mRbySldKd3B8WIwahjr71wpYUnKfCJU8W75F2s6WG6BRGf?= =?us-ascii?Q?F75wGhsj7Rgrpne+KnkBuYk50CiZVjs6Yn0XQXtBL+cSGB3odpjgBiiS07iQ?= =?us-ascii?Q?nYMjARCt9SdJpj/BTO/g9I0V4JgFLmf0NQH5HkPNeW24+j0kky9jF+pLRhd2?= =?us-ascii?Q?oaIKrt25S6HkSEYGw/W2kzhQg9LlLnTNLgZnJp0NfSe5Q0B/XgnQw2JUNO/I?= =?us-ascii?Q?cuLbGyxecfOH5heiDyFs8Dgi16a7je5Q1ocgH0yoYd6FdonZhINZOrG1hXQY?= =?us-ascii?Q?SRQHQ4QLkFZqK3UaVJaLXN7TgDF6YY3ILDG2MUdHK+N57OniPiJrFsMA2us4?= =?us-ascii?Q?ezE8hfzYoGRIGpOaTFwnFNKKYc3to6CmYkHawcmL0h0cQ8nMlUlUoqqHYGFP?= =?us-ascii?Q?Cv/MzGCmApOodnUPIh+9F8PiljUCbQSfOacigpSebjjLtDwavYNdaITdWd/I?= =?us-ascii?Q?2mMrbAEiYb/rLRnkqNCbn8h2eWoNRJm3CXLydciN3API7a5oFXRsdn0Anvpo?= =?us-ascii?Q?rL1l3gBsyIeIs7HrmlBuAYMrgEQw7D3H9JPOvkJJJR5T5GmgqhEI6oVMgKJO?= =?us-ascii?Q?cDE4rTPP2NHwTmwpUtNGO+Qip6MMCa00yv4YF+t5/c4xaR/t6lN7Vetsfkl4?= =?us-ascii?Q?yErV27zgfFj21nibxqfBugtOWJ4DDcVSXMx5FTtUpGFAeI1NV5iQWTIRu3+M?= =?us-ascii?Q?16eXVzcja4hpBLy4zEi0wDZn3I520igXKHOlFxR10KGkdOGVJiFmz6kB6Tj0?= =?us-ascii?Q?3spkMrQWheGDoQGmFe8=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR12MB6486.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(366016)(7416014)(376014);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?uSKmWR2z0SPKSQMWbgSQ1N8L9Df0Loju/CuxWzvfrPaT3GRi7DPbAc4DgrU2?= =?us-ascii?Q?noOAaQphwpc4YhDzNqDF1FDjzkAmVhAKGz2lq1pZ1tM4mOzxzdDZaqlFC/Me?= =?us-ascii?Q?jd7QmIOQy1q0qb9/yX5b0gn9iEkfUzwq2e9i5GvI53EYti747t2NAYTtwWCM?= =?us-ascii?Q?+gc0qvoV9chnShVOIwukwUMrUqSiAt5S/dXWMU/tDs4PrIamkh+PeDRCbdri?= =?us-ascii?Q?76qh/AIOX1ZXGwJZMb9K9VF0B3mhmrK7KwhXk5XtoWVH0fcPZy0VWKQlOF+K?= =?us-ascii?Q?ReoCtGbdyx+KhtPksHjXTuhPeooE82/+BRo3qE71OEm3YHfv4aPvD4QCGZfd?= =?us-ascii?Q?mo7I98SV/f4THVhuMcG2TJ2WviTUOLHBWsJnAjkiK1IxPl6KXsrD4qT64iTU?= =?us-ascii?Q?H8YLi+zwGZ43TYx7nJr7DP+8KoJ0gvpN9sSKuA9e5aTR1OjEScVS7odcPOOy?= =?us-ascii?Q?It4S4iT72NRLzW4PeVHKEnr7RBm2b7WqFDgur2ivaTG9gtu7IY2qy0rf9d1Y?= =?us-ascii?Q?VwhmPI7cCa2IxMoVmQCwq5CbuMqjvtkVkxVwqAS/PQEwdY6OZ+Dc85A6D2gh?= =?us-ascii?Q?bIAHl9m8Mz6gbEuL81Biz7p7G1wsa3pFwc/WvioPEj9lfu0sdlCdYJzTKdyh?= =?us-ascii?Q?MFZhOq9+xfzxYXO+6DdKj6MnaTUiKR/gVb2MFBfYLLpoqj/VrJJDjUgh2rpF?= =?us-ascii?Q?d7R0fG3Yxa/vQ0KRmj+gtq5D3D1bDyA+LFPHN3/bPrMbaGDUaIizBDbkfzwX?= =?us-ascii?Q?CcJ3vL5Bu2VPD0GZdex2h3uEBGAmQ8fr+w/A1SH1egUvBQ2AAY9H9wOHV3A6?= =?us-ascii?Q?LYTVzFS9uTcbZKRYXMpTDZqW78btb04/l0/mHPj2bNnz2sln+HXkdQHs+IEa?= =?us-ascii?Q?EW9mq3I5pn4GHsZbOPqe90i8VQeebDQEVvmOBVY0dtCkZYcNuxO+A3meoKbf?= =?us-ascii?Q?0vRQH0QDrptyhoebI9fGMTyqwnAIi2gWsa3p1vV+2B0uVFzwqJSnkl2QOS2B?= =?us-ascii?Q?+5TQjTaUjn5PA8FFOCnD6+QIlcmn3iazV9sSKUFuKCBZQMdFcS4BcO9rd+aa?= =?us-ascii?Q?bNV6NEqsPcBSebgf2+d86X5hHoStHBLsVeL1epu81wI3hh6L0mQBEg55MNHB?= =?us-ascii?Q?p9VCY+P/K9XaLU4L3mq9QPlsW7RXhxfVsGF+lXpgg11vaRjwvWizQf5ZPNi8?= =?us-ascii?Q?KGBfsUKnnEXysY8lM7UBSnNA5m67554mWeC6KW1VfVZRTdVSOAtRcv3kjLff?= =?us-ascii?Q?uHCFvWbDWXFdbbzet6tTULZC2aJ6wJK1UpLbejhUiQcAGiFg8rULffAP0W0b?= =?us-ascii?Q?ziqsm+BZht3PWWGmaptcUvD7V5LR8m/RDcK7tYzbNAHz3vmDX0ZcaP/BJeo4?= =?us-ascii?Q?uxtCwc5ZVHFgY9p+SGXk/nkr5e1HGDi11PNS84w5IkmoC+rax61Bj90U9/3d?= =?us-ascii?Q?LBIMFpfSvNYHZym/6S7DvT8PDKAvGqqRVMRbi9Pab1YZNZ5GtbSmGPcDR1Fh?= =?us-ascii?Q?Oqc3fpHwCODnSmYRjuSb7xTJ0lCSzPsW3W9QMKpWx4swyp1cb21gs9zMwV9F?= =?us-ascii?Q?0nGZ6hnNQ7mdqiU1RlHpp59VMJUSrep32IeEi5oQonYD5J0khomvkl8oKrDr?= =?us-ascii?Q?HNlqNnVWRXQTd6w/xCg4ihk5UrtMFeebxFV1SJB0gPYnzpDBRHTNeHY505Fq?= =?us-ascii?Q?SRGpId6LBcV0bmUw9oEhj4XhZvS2hMWEfyTPqqgn4Vxtdx9wfMYY2g8MYuYV?= =?us-ascii?Q?bwRWhLtEJA=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 430b97a4-a43c-4ba1-dec1-08de5864b46f X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB6486.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 20:44:28.4558 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: z8S1/twqvH9hApD3w/5edTgb8i0rE/QA9+G/d1mgN9gRzOdy+S4s5RfgFhOf/TDuMP+h+fedi8hHLqWVxScT6Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR12MB9651 Content-Type: text/plain; charset="utf-8" Add self-tests for the PRAMIN aperture mechanism to verify correct operation during GPU probe. The tests validate various alignment requirements and corner cases. The tests are default disabled and behind CONFIG_NOVA_PRAMIN_SELFTESTS When enabled, tests run after GSP boot during probe. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/Kconfig | 11 ++ drivers/gpu/nova-core/gpu.rs | 14 +++ drivers/gpu/nova-core/mm/pramin.rs | 160 +++++++++++++++++++++++++++++ 3 files changed, 185 insertions(+) diff --git a/drivers/gpu/nova-core/Kconfig b/drivers/gpu/nova-core/Kconfig index 257bca5aa0ef..cbdbc1fb02b2 100644 --- a/drivers/gpu/nova-core/Kconfig +++ b/drivers/gpu/nova-core/Kconfig @@ -25,3 +25,14 @@ config NOVA_MM_SELFTESTS BAR1 virtual memory mapping functionality. =20 This is a testing option and is default-disabled. + +config NOVA_PRAMIN_SELFTESTS + bool "PRAMIN self-tests" + depends on NOVA_CORE + default n + help + Enable self-tests for the PRAMIN aperture mechanism. When enabled, + basic tests are run during GPU probe after GSP boot to + verify PRAMIN functionality. + + This is a testing option and is default-disabled. diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 938828508f2c..a1bcf6679e2a 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -324,10 +324,24 @@ pub(crate) fn run_selftests( mut self: Pin<&mut Self>, pdev: &pci::Device, ) -> Result { + self.as_mut().run_pramin_selftest(pdev)?; self.as_mut().run_mm_selftest(pdev)?; Ok(()) } =20 + fn run_pramin_selftest(self: Pin<&mut Self>, pdev: &pci::Device) -> Result { + #[cfg(CONFIG_NOVA_PRAMIN_SELFTESTS)] + { + use crate::mm::pagetable::MmuVersion; + + let mmu_version =3D MmuVersion::from(self.spec.chipset.arch()); + crate::mm::pramin::run_self_test(pdev.as_ref(), self.bar.clone= (), mmu_version)?; + } + + let _ =3D pdev; // Suppress unused warning when selftests disabled. + Ok(()) + } + fn run_mm_selftest(mut self: Pin<&mut Self>, pdev: &pci::Device) -> Result { #[cfg(CONFIG_NOVA_MM_SELFTESTS)] { diff --git a/drivers/gpu/nova-core/mm/pramin.rs b/drivers/gpu/nova-core/mm/= pramin.rs index 6a7ea2dc7d77..06384fb24841 100644 --- a/drivers/gpu/nova-core/mm/pramin.rs +++ b/drivers/gpu/nova-core/mm/pramin.rs @@ -242,3 +242,163 @@ unsafe impl Send for Window {} =20 // SAFETY: `Window` requires `&mut self` for all accessors. unsafe impl Sync for Window {} + +/// Run PRAMIN self-tests during boot if self-tests are enabled. +#[cfg(CONFIG_NOVA_PRAMIN_SELFTESTS)] +pub(crate) fn run_self_test( + dev: &kernel::device::Device, + bar: Arc>, + mmu_version: super::pagetable::MmuVersion, +) -> Result { + use super::pagetable::MmuVersion; + + // PRAMIN support is only for MMU v2 for now (Turing/Ampere/Ada). + if mmu_version !=3D MmuVersion::V2 { + dev_info!( + dev, + "PRAMIN: Skipping self-tests for MMU {:?} (only V2 supported)\= n", + mmu_version + ); + return Ok(()); + } + + dev_info!(dev, "PRAMIN: Starting self-test...\n"); + + let mut win =3D Window::new(bar)?; + + // Use offset 0x1000 as test area. + let base: usize =3D 0x1000; + + // Test 1: Read/write at byte-aligned locations. + for i in 0u8..4 { + let offset =3D base + 1 + usize::from(i); // Offsets 0x1001, 0x100= 2, 0x1003, 0x1004 + let val =3D 0xA0 + i; + win.try_write8(offset, val)?; + let read_val =3D win.try_read8(offset)?; + if read_val !=3D val { + dev_err!( + dev, + "PRAMIN: FAIL - offset {:#x}: wrote {:#x}, read {:#x}\n", + offset, + val, + read_val + ); + return Err(EIO); + } + } + + // Test 2: Write `u32` and read back as `u8`s. + let test2_offset =3D base + 0x10; + let test2_val: u32 =3D 0xDEADBEEF; + win.try_write32(test2_offset, test2_val)?; + + // Read back as individual bytes (little-endian: EF BE AD DE). + let expected_bytes: [u8; 4] =3D [0xEF, 0xBE, 0xAD, 0xDE]; + for (i, &expected) in expected_bytes.iter().enumerate() { + let read_val =3D win.try_read8(test2_offset + i)?; + if read_val !=3D expected { + dev_err!( + dev, + "PRAMIN: FAIL - offset {:#x}: expected {:#x}, read {:#x}\n= ", + test2_offset + i, + expected, + read_val + ); + return Err(EIO); + } + } + + // Test 3: Window repositioning across 1MB boundaries. + // Write to offset > 1MB to trigger window slide, then verify. + let test3_offset_a: usize =3D base; // First 1MB region. + let test3_offset_b: usize =3D 0x200000 + base; // 2MB + base (differen= t 1MB region). + let val_a: u32 =3D 0x11111111; + let val_b: u32 =3D 0x22222222; + + // Write to first region. + win.try_write32(test3_offset_a, val_a)?; + + // Write to second region (triggers window reposition). + win.try_write32(test3_offset_b, val_b)?; + + // Read back from second region. + let read_b =3D win.try_read32(test3_offset_b)?; + if read_b !=3D val_b { + dev_err!( + dev, + "PRAMIN: FAIL - offset {:#x}: expected {:#x}, read {:#x}\n", + test3_offset_b, + val_b, + read_b + ); + return Err(EIO); + } + + // Read back from first region (triggers window reposition again). + let read_a =3D win.try_read32(test3_offset_a)?; + if read_a !=3D val_a { + dev_err!( + dev, + "PRAMIN: FAIL - offset {:#x}: expected {:#x}, read {:#x}\n", + test3_offset_a, + val_a, + read_a + ); + return Err(EIO); + } + + // Test 4: Invalid offset rejection (beyond 40-bit address space). + { + // 40-bit address space limit check. + let invalid_offset: usize =3D MAX_VRAM_OFFSET + 1; + let result =3D win.try_read32(invalid_offset); + if result.is_ok() { + dev_err!( + dev, + "PRAMIN: FAIL - read at invalid offset {:#x} should have f= ailed\n", + invalid_offset + ); + return Err(EIO); + } + } + + // Test 5: Misaligned multi-byte access rejection. + // Verify that misaligned `u16`/`u32`/`u64` accesses are properly reje= cted. + { + // `u16` at odd offset (not 2-byte aligned). + let offset_u16 =3D base + 0x21; + if win.try_write16(offset_u16, 0xABCD).is_ok() { + dev_err!( + dev, + "PRAMIN: FAIL - misaligned u16 write at {:#x} should have = failed\n", + offset_u16 + ); + return Err(EIO); + } + + // `u32` at 2-byte-aligned (not 4-byte-aligned) offset. + let offset_u32 =3D base + 0x32; + if win.try_write32(offset_u32, 0x12345678).is_ok() { + dev_err!( + dev, + "PRAMIN: FAIL - misaligned u32 write at {:#x} should have = failed\n", + offset_u32 + ); + return Err(EIO); + } + + // `u64` read at 4-byte-aligned (not 8-byte-aligned) offset. + let offset_u64 =3D base + 0x44; + if win.try_read64(offset_u64).is_ok() { + dev_err!( + dev, + "PRAMIN: FAIL - misaligned u64 read at {:#x} should have f= ailed\n", + offset_u64 + ); + return Err(EIO); + } + } + + dev_info!(dev, "PRAMIN: All self-tests PASSED\n"); + Ok(()) +} --=20 2.34.1 From nobody Sun Feb 8 09:32:51 2026 Received: from SN4PR2101CU001.outbound.protection.outlook.com (mail-southcentralusazon11012013.outbound.protection.outlook.com [40.93.195.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76E1E47278B; Tue, 20 Jan 2026 20:44:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.195.13 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941888; cv=fail; b=cvVriXY//FR8M0ZuDzh8hk49h6s/AHJdnTETZNxb7aq9b5JjlGEZuNKp6ytwXbD9XUSXiGgtmE8YFQmkr9joJMc3G5X/sSD7j6ndxuG1FbUr3J4rnIGSze2YfRsppHbwrF6nJNCs1YfzAd58yfR/ISxEXAKz/CNv2rnbqSWzHhw= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941888; c=relaxed/simple; bh=6Safx74B/kEGIcvnSdeFI/PcH8Wo+4OmVJ/f6QPsIOQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=Fq8ynpZmrW02NiljY+m1qhLOasa+dlETuisLCzylrAaCuomQA2SPmvir71+OhTD1BX9e8wBMh4+vPj4wujWyUJAKZG5058LQG4JM90Sn7oGQyvsGoB59SwbDUCZajzDRsgSuasbrO4KLx/rCvDtIAbnJgWFHG/h6QU46bvzwGXU= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=BM2M06c5; arc=fail smtp.client-ip=40.93.195.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="BM2M06c5" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=nKAJKyDiAwR/28ewkIMF7n13R/76ZDXjMdNY6ygHo0Ln9qgZxwZQHQMYNuho6khmP9vhc3igJfdUoYfP7HUyM2KgShmHAwdYDEMPtCNwd1Ma8wkVhruI4XhIjhxo+ITJ7yDGLguKmWpFXpm6XaFtB9/RSbSNTYhhLudnCY1En8bNn66TkStI73mxKQah8pXfZ4ffoYHt2Z/UirrA+5sflLY7lYb2GQEYYFDgPxICcKSTmSwJcLZwLebNLSHuksxw4WCY4+LSnM9/yEWyRyYH4TOowFKkldCBPIz6RpfQC5Hsr1UkkjQ7MuTlmruywyBImA4vl8F6+uwm3TZEVyAv7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=0RMtF/D8S5J5kI93dJVCqOe3D5PszbnpUv1akdnavMY=; b=YzN9fkkptoE+1X7Zfal1ENt4eM4uBehcuUswgUR5xkPJOjC8+SWJugKELsL2RFv0TBVzP1TCok3hhZykQ0gMNlMnG0jrm70+mN0qTU7hYJsLLbJ7nMwr3HqsvPk7rM0K2JuSOYMSefPficoB2A+qk+cOcByB31lLlOWupweOGw9m94q1qxQHD5OEbASXsfLLTNNak+xnEc+8/PXrANGdBdmQJSYjJhUPjIiMNMeeP+LZ1g7ivBPtDi0OPgdnCpx6pv/hhA3sQVa08u6voED/3b9JYppZb/0T2ENzKlGpout7NotGX+ceJ+p5z3LB5zx6AUhBSCOECI1VVPYx+3iCyQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0RMtF/D8S5J5kI93dJVCqOe3D5PszbnpUv1akdnavMY=; b=BM2M06c5C6nUzDXHGpHjoqUGoCfYQdguwHojOnKhipv2tXg3hlBNuoov5JE0lS1AFo56DLHDnC1R4VTsHlxdmCeLt3z2ylew/2kfICrceDvC9f7h+9Q7TK0wPMSqz3fvsu5beXWpocqf6+sBDsBL1dMEEvjsmcniSKMGhoCYiTI/8StwVLDhwWFUipQAojDid4gGP1fCm6YQNPqS8D7C/aqobbrL+VuSAyM/zsfBlanoZO3+CnaH7D6fuNleq1bUx85GmXaKi/THpvDvxHT1fweupQVKU2Su7tJq25XXCZfwF5sP2eie0BCV/3jMLo138pv6/PNo/3g/R/DWiLrjiQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by CY1PR12MB9651.namprd12.prod.outlook.com (2603:10b6:930:104::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.13; Tue, 20 Jan 2026 20:44:30 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9542.008; Tue, 20 Jan 2026 20:44:30 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jonathan Corbet , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Huang Rui , Matthew Auld , Matthew Brost , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Helge Deller , Danilo Krummrich , Alice Ryhl , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Alexey Ivanov , Balbir Singh , Philipp Stanner , Elle Rhumsaa , Daniel Almeida , joel@joelfernandes.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, linux-doc@vger.kernel.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-fbdev@vger.kernel.org, Joel Fernandes Subject: [PATCH RFC v6 23/26] nova-core: gsp: Extract usable FB region from GSP Date: Tue, 20 Jan 2026 15:43:00 -0500 Message-Id: <20260120204303.3229303-24-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120204303.3229303-1-joelagnelf@nvidia.com> References: <20260120204303.3229303-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BL1PR13CA0110.namprd13.prod.outlook.com (2603:10b6:208:2b9::25) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|CY1PR12MB9651:EE_ X-MS-Office365-Filtering-Correlation-Id: a07fc773-eecf-4720-8462-08de5864b5b4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?2WVAjT5b5JwYmCHy00N8I4jLxMX1ohh8uFMk87RzE2FaqLjGVACAi/W2/8Z0?= =?us-ascii?Q?Vm0KwD5vT8Cdu9DiF92wYHC7G9zaoOd2iacFdh+Sh+0/jFBpihJTRLHRpGH9?= =?us-ascii?Q?wXivQomKWOSJGNrY90UvSAzPxSQpLBUg040v/YlR28ddjtVKMfOtEVEy7olR?= =?us-ascii?Q?Zks83dkP76XoXBh3HiRNJqED218f367MgNXGIh2GOzp8E+es02q0AvG3l/Pc?= =?us-ascii?Q?/jtrHhrR28AwONYLzNGYwW03tplQBtNW39ivVrI9gIMYmp5bH2Oz8pzaiXzb?= =?us-ascii?Q?dFEHI2IMMDS+nH0k1W3/54vxB8rwSYwip+FwCveB4gub1REHBe6BlZjW6Tnl?= =?us-ascii?Q?BdJ19hKnBAA7rT8nJjaFXdTAMc1/n+mfph4ywRwIYgjOa9yeAifgl+o4D4JN?= =?us-ascii?Q?vVwtMO0QKlRBFjh7G1Lz2LDOq0wPBuj5ghj4J5cu0J+O4bJegeMJI5v7i2Wp?= =?us-ascii?Q?lEJukFyUGSXWs+DIc2EpdcYYTUNToJmX3oO0p53P/KsT/Mcx4W6XqJOfy685?= =?us-ascii?Q?iga7lADyI8Z/nyc6LuNUWSk1jsdosO/B9Noe/Xv57kKxEhiFr//QpKkWeekA?= =?us-ascii?Q?mGbGl/vk03nxfzFm/LAi6t7OPPmJMHKt/eJ/imWcHpiDplUYMDYqM7R7yRN8?= =?us-ascii?Q?cMTKSrlZm3ZMmeFAfUvtb9xnrltTxQgN+jAcoj48aNGPJCtJaX+hgdx7Uqyd?= =?us-ascii?Q?lP3cmJOxhe9jQ6/rjep2MEUmzEEXvfeo/HSCRCC1YKKtibvV+EOe2jZSAzch?= =?us-ascii?Q?P5XNJ3pFRV5ZaFYENMaqiuLBoEYATqzpoyFaK5DzGtsfBZoK0NAxJwDQrd1T?= =?us-ascii?Q?TP9xdAfWNNA9ViUvq8YfSnYRqp+Uc358eNBIgED/nokN/naM16Y/2aiqEn25?= =?us-ascii?Q?6otIa4aVmHD/bB6gaSakt9QJF4Yn6OdYWzd63cltzDBoQncLZX4FsrJeF25J?= =?us-ascii?Q?CIt5sllqWgaaSwM/0wNbzjyYrHly9Jg/dZCi2TPRvCM9Nx7Sh302geCWyY4P?= =?us-ascii?Q?6OR1ZdUo56kOh3TQ1Zxtj25s/dPCRAfa0Kyav+iR3MUeXfSk/fFR/7cUQLdB?= =?us-ascii?Q?sFkTHp2ik4J1khqGxaorMZn9QN2YGwsUkYIbH5L+CKh/MqOlc9rg7dr+V/Cq?= =?us-ascii?Q?h1le/LSCA5GQPUbuSTRuELLL+vukGl0garDq40lEm2rIlrjpBCJjkSSa03RZ?= =?us-ascii?Q?svkdjEAt4gqp28HTkX9531vu99J2RylrhgAPF1pibCgaH+xkhtzItPYxBSRe?= =?us-ascii?Q?TEO/TAf4+0GDrwSn3UnHtkoTMdaoCM9gi/iQn83yhHW06vU6L2Bt8IBZXW6C?= =?us-ascii?Q?KvK3oxkXyd4e7rxc1xDMCw1A1v3uMeNFHF5Qp9W1E9ftORZ9MdewGeypQJyN?= =?us-ascii?Q?nwVnFgY8aS8YHRjU7XW6sK4lA2FqtHArMY9Dr06U/KxWbqCZ8N6Hbn50HZ6K?= =?us-ascii?Q?KbyiMU6CYK4StD5DPSI7quZjoC/ccUiw/jkA55mXLmyHgtHY5m3OS8OIlQBu?= =?us-ascii?Q?vmu6gZsfRjlXAYDCCHdAGjCGGaadwzR4qApHyMx3tXFasy1kGDMMeUrSDrfs?= =?us-ascii?Q?ExMzCEhxFSgDN8EMaFc=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR12MB6486.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(366016)(7416014)(376014);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?jDMAoKRUXDUG4g8R89XQKTeuQveTmrWsyEFKRPRET+qGdBfuUdxwYvchCI21?= =?us-ascii?Q?xpW+EzswzGGHvTLCBKjeodeoXSZlsxkdraOPL8UpOeuwnGmZKxQlFEzpit1b?= =?us-ascii?Q?arZxL9d9kln/VJ6CSGiA1/I1P4OHuMN38xqrPjQiA4HYYhgf6m7K2TFCucXp?= =?us-ascii?Q?/wjiQwkwjY9ONMneXlX4egaMALGRvIQX6d6+gn00jP5+2kYrXMZkK6DslvIw?= =?us-ascii?Q?PQby7zuHofxhYKgM1hBt4usVXBWuADgXq2Hfn//0GznCx3fjOykAwzIKLdoS?= =?us-ascii?Q?heeivtVdTumGdtUGLjz6JMAwvfyTzX+vXtLgD0bC6bIO+9rQFOixIJyHGXB1?= =?us-ascii?Q?skg3CuxzYqTxDPzp/hxS1FqiCE6/JvZUauXEdeV9Y1hQQvXtRwAd3xaJeSDJ?= =?us-ascii?Q?a9257Ybog0XyDcM0QkzfS16ETXKMR1iLSx4A7ZUUIvMg0iOgmoP5iv4ArLJI?= =?us-ascii?Q?HwvmiBNHdTLGisFDXeBmQm2TM/6DIWDrUsk4ZGcor16TlStZMmCHznCSAyHI?= =?us-ascii?Q?B4FxDgCS6L1uPlXeNsYdzCZdm6dUOpQDDLdVQKjNxwKjyXtMrmdHbAGrS89C?= =?us-ascii?Q?eBsUg/k9M0Rm/kjMW3mJUxy4/wGMTV1uzCualk4fm83394R+CZbVOmJYzMZx?= =?us-ascii?Q?iQsCZcQLL88YQ7d/Fj9r+mHfJXpzfzR0uzxGUmxDMIMcOIAUsgD1hHK0bkMW?= =?us-ascii?Q?1lhKtAFqsYq9/0hweK0AWYNdS1rB00GBgxTV7XJE+QcWkJB0fTapVcxLBI9I?= =?us-ascii?Q?CMGjHAO4w6f2eA0UNfQ16Ho9a1gZZyV5qqwPEs4DjMXdHElrtj9P34ZG5Pji?= =?us-ascii?Q?mjWwdxagB3ISgmk5zG/qFxE5ipPG52nfrfztOgpnJKFL52L1u+WyvvyvUdT1?= =?us-ascii?Q?Xm5jO/HUb+FV9aqsfNC3DlEvorP4rVmHcXqMeBH5MmXMaskrkYWvggypsiUj?= =?us-ascii?Q?UUVo/qhi0YWQZlGF94Boc6h9pw29qIuqgKUDSXjEoRERmnAzxv9RmMq8mPn+?= =?us-ascii?Q?OGlni7TBElaYaOa7HB2ftLW3OWjX9heuLifoRtg5sruCdsoJBzqHPmsBKtNB?= =?us-ascii?Q?ARTxWh5grsh7PiPPvdie7peknyKq4hhiEPraSvOgIxhE2viL/iUW1kVuvl/2?= =?us-ascii?Q?7FVsJZCIsqvu+vhAMPrimXzbjEatc6fM5HFMgoVJvk3ZaFrEaB3Bw9r762RR?= =?us-ascii?Q?lG+AT7y9UfK61gNc258hZ7CeK9D5lmd4qXJ245mgFCKiW+DEC6yaRTd523Rm?= =?us-ascii?Q?egBxoHLW0WqrMxmM4q/eduPtxuI7htHYGNzppSDJV4kUGOGP8h/zr82GrYGD?= =?us-ascii?Q?CUV8vkolQXNOkLIs+NX/TDPUt3fO89OmwAzJZErrJ7CRp9/3Z9m0C7+nMfwo?= =?us-ascii?Q?bALqjbE5qLYWx/+LuxoUWReN02DZdolWXuUK/2kvwfgOa8BR8sgmUCybB6I+?= =?us-ascii?Q?O0tqOYY4BC5j6zsyQfnJhfGjZGPGKnkDdwjJGEygWRpuuk0vskmV5t425eiq?= =?us-ascii?Q?KDk+WgiZVvL0dbUOuLYTgn5Mdw7QEjPObIBDvMNQCrPe+vUfR+SVVN9M+GTY?= =?us-ascii?Q?yCyaEQsKGRjCb56ImopoI5dDW9OYa79kg5YyeG3wi7YK3kol+d/Lp3Wu5/j9?= =?us-ascii?Q?y0TYzCU18BsIyp77k0f4cy2NJiVc2fhXyilu/baoXQbmzAHpxqjeS1bdeUtK?= =?us-ascii?Q?NvCO+uYk6G58SJactVEcbCIxWw9WKxfJS3RVbjLxcQY+2fRhzrTq7M0ZaZVA?= =?us-ascii?Q?6KJEFqwEXQ=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: a07fc773-eecf-4720-8462-08de5864b5b4 X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB6486.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 20:44:30.5398 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: YiLIInnqRe+b7FzP0824dA8EkyeXk2RtO1PmelwtytUxP6qqievOSs8X6ZHwVHCilaR333WEHTw9SZibOedr3A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR12MB9651 Content-Type: text/plain; charset="utf-8" Add first_usable_fb_region() to GspStaticConfigInfo to extract the first usable FB region from GSP's fbRegionInfoParams. Usable regions are those that are not reserved or protected. The extracted region is stored in GetGspStaticInfoReply and exposed via usable_fb_region() API for use by the memory subsystem. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/gsp/commands.rs | 13 +++++++++- drivers/gpu/nova-core/gsp/fw/commands.rs | 30 ++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/= gsp/commands.rs index 311f65f8367b..d619cf294b9c 100644 --- a/drivers/gpu/nova-core/gsp/commands.rs +++ b/drivers/gpu/nova-core/gsp/commands.rs @@ -186,10 +186,13 @@ fn init(&self) -> impl Init { } } =20 -/// The reply from the GSP to the [`GetGspInfo`] command. +/// The reply from the GSP to the [`GetGspStaticInfo`] command. pub(crate) struct GetGspStaticInfoReply { gpu_name: [u8; 64], bar1_pde_base: u64, + /// First usable FB region (base, size) for memory allocation. + #[expect(dead_code)] + usable_fb_region: Option<(u64, u64)>, } =20 impl MessageFromGsp for GetGspStaticInfoReply { @@ -204,6 +207,7 @@ fn read( Ok(GetGspStaticInfoReply { gpu_name: msg.gpu_name_str(), bar1_pde_base: msg.bar1_pde_base(), + usable_fb_region: msg.first_usable_fb_region(), }) } } @@ -235,6 +239,13 @@ pub(crate) fn gpu_name(&self) -> core::result::Result<= &str, GpuNameError> { pub(crate) fn bar1_pde_base(&self) -> u64 { self.bar1_pde_base } + + /// Returns the usable FB region (base, size) for driver allocation wh= ich is + /// already retrieved from the GSP. + #[expect(dead_code)] + pub(crate) fn usable_fb_region(&self) -> Option<(u64, u64)> { + self.usable_fb_region + } } =20 /// Send the [`GetGspInfo`] command and awaits for its reply. diff --git a/drivers/gpu/nova-core/gsp/fw/commands.rs b/drivers/gpu/nova-co= re/gsp/fw/commands.rs index f069f4092911..cc1cf4bd52ea 100644 --- a/drivers/gpu/nova-core/gsp/fw/commands.rs +++ b/drivers/gpu/nova-core/gsp/fw/commands.rs @@ -122,6 +122,36 @@ impl GspStaticConfigInfo { pub(crate) fn bar1_pde_base(&self) -> u64 { self.0.bar1PdeBase } + + /// Extract the first usable FB region from GSP firmware data. + /// + /// Returns the first region suitable for driver memory allocation as = a base,size tuple. + /// Usable regions are those that: + /// - Are not reserved for firmware internal use. + /// - Are not protected (hardware-enforced access restrictions). + /// - Support compression (can use GPU memory compression for bandwidt= h). + /// - Support ISO (isochronous memory for display requiring guaranteed= bandwidth). + pub(crate) fn first_usable_fb_region(&self) -> Option<(u64, u64)> { + let fb_info =3D &self.0.fbRegionInfoParams; + for i in 0..fb_info.numFBRegions as usize { + if let Some(reg) =3D fb_info.fbRegion.get(i) { + // Skip malformed regions where limit < base. + if reg.limit < reg.base { + continue; + } + // Filter: not reserved, not protected, supports compressi= on and ISO. + if reg.reserved =3D=3D 0 + && reg.bProtected =3D=3D 0 + && reg.supportCompressed !=3D 0 + && reg.supportISO !=3D 0 + { + let size =3D reg.limit - reg.base + 1; + return Some((reg.base, size)); + } + } + } + None + } } =20 // SAFETY: Padding is explicit and will not contain uninitialized data. --=20 2.34.1 From nobody Sun Feb 8 09:32:51 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013061.outbound.protection.outlook.com [40.93.201.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B529F478E32; Tue, 20 Jan 2026 20:44:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.201.61 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941892; cv=fail; b=crXQIwbF14GPYjg6fiZQELVxRIxPwIf0m9qrpZbzuLemGjqepBRpHSHpNW5c2C7QlnI2YiSIsbvNByS10ttPeiMcFnujiEXk6yBtxspIfx5ISdUTEPGs9at0feHJkTbx1Mzd5RAprvleWVrGHv6CPbbaLjrhlWfHwCixYVYFLds= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941892; c=relaxed/simple; bh=Z5nVrtdQoHTmT4xF/VdjrFhB+clrS03UZp6np+a0k78=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=CkVp/xXT2KNq/WayeCckhT4WNB8zTeOeKpcnUmHJOy4m4ecw06QZRk6NXNN70KTzaicymkE0JCO86U1nvIccZtSQPeMjvlhD3QR97/fNvMg9Sw8wdS7HQ139ynmz+hWRetju7wNm35Ok9jupMpkheIodX4eu6nq79ZEocDvRT8w= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=NydVoLgG; arc=fail smtp.client-ip=40.93.201.61 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="NydVoLgG" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=QiXh/hIfuVXjl0/bB3Di49zx2npXJ3f2E9DvG56W5Z0xmdjSr/CvIFoe9AIFBxGZPSL70/vbTIVKRz51RcrC1feiCjNSfXCQixoeL5iE86OfBQbJKfrxMAH0xCdt3IwZF9SSbRycgSbTOm8TxuRwBD5L+WkEYIDCBtge61Sv98h5d6pW7IOZhO35tFPfEjJOEO0Af/wsxUn0Hhw3bxSbSNS52Pv+iXUA2TKwqwkJDeCuONuGFzKUCYMj2Vv8KXnt0zrPBS3VlHq53bCmnK2o9sd5jQRuMr7o62GDN2vUVi1LnalyeBDcySGTxFxOKEyq4CD2mSv8Z+Basr6LjaeRpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=nulEOsZpSeXJ7Y5H4Pmyy0krRZ8hN+O1WrImhGyRv9k=; b=oZfemtkj6Y8y1pIdRDzYX4mjqvFfeWdpHb5BFpKlALyyTn/d0QbdG1atDgO0ihDrjp4rGaMyS4A2/cQ0PVgV3RAne8GW+pxQkGwPO1a8f8Efh2P/82wAejIBtgHY4oX2yuAR3eReteQxiM/rto0oHM+rkxfpNkvO4GpSJhIxQjMNXO3vE/wYWy9XDhJluAs6DgJ8ycyu7CWZM+WPcvhkGGz81Mhe9fw74TeIYMPhnnNg6BLH9uVSOueM8wwA35da5I+SdmYI0DS/4mieJBW1PT+A820bA9wXNSFZ+YUfqL/xEAVkXodQN3ktugP6f01F+pAT8YBBA13xeLg4//Amlw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=nulEOsZpSeXJ7Y5H4Pmyy0krRZ8hN+O1WrImhGyRv9k=; b=NydVoLgGfZ8oQ7xYLmZvQdNBjKweF6uTnLlyXoIpjuKUUOkX5QKoHReBt2MIPe3mP+72QMuLqGP5uAuCAqtqasVqf4w5yvX2DkW3Rai9Zayw+4Ic4D23aQHPUdnG5GJFjjig6mhOBQemxgfnGCO+SpBJmiJNUJIUUobu8C1AkUBmy9InIOUDI61a8AFhlAk2AWKwS9qSRkBwzwzRARq3gTqswmheQnhCYZcn6w5y4d8Otbu/7rJJGsclpHFZO9nViw+Nz8cb7F9RyTg+xpMrXbOJ+8kTMFBfFtc0r+CKRqdGjpT/YZqdRaNkwwUJ2SXGk7eQqPryqJ855nw7gjIq4A== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by CY1PR12MB9651.namprd12.prod.outlook.com (2603:10b6:930:104::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.13; Tue, 20 Jan 2026 20:44:32 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9542.008; Tue, 20 Jan 2026 20:44:32 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jonathan Corbet , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Huang Rui , Matthew Auld , Matthew Brost , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Helge Deller , Danilo Krummrich , Alice Ryhl , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Alexey Ivanov , Balbir Singh , Philipp Stanner , Elle Rhumsaa , Daniel Almeida , joel@joelfernandes.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, linux-doc@vger.kernel.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-fbdev@vger.kernel.org, Joel Fernandes Subject: [PATCH RFC v6 24/26] nova-core: fb: Add usable_vram field to FbLayout Date: Tue, 20 Jan 2026 15:43:01 -0500 Message-Id: <20260120204303.3229303-25-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120204303.3229303-1-joelagnelf@nvidia.com> References: <20260120204303.3229303-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BL1PR13CA0097.namprd13.prod.outlook.com (2603:10b6:208:2b9::12) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|CY1PR12MB9651:EE_ X-MS-Office365-Filtering-Correlation-Id: 923f5975-b2f0-4087-889f-08de5864b6e2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?MyLVl2DzY00W+YqekWO3Zyh3RWpVxF7y5FcX9zyfHOyB15CCH/M5WVYZIpiP?= =?us-ascii?Q?+tL4o8OZpdwIwTtUSaQl1E4gIDwB7Fqs5QgObQ9y7YXJU+D4PBnfSKPO9v/u?= =?us-ascii?Q?GFRrirfUJtKQ4lorn82YXq6vKna5QbTOASL/Hvi5sEhVwYynQc4OgzY70vns?= =?us-ascii?Q?i3q6xnnDtwwA5Voj+7pzQun22pVOhBKqNYwuAfjVvrBkj/htuNGPTE0USIFB?= =?us-ascii?Q?Qe7+2sYLCI0ywMNJR5rpZqvDLAybRmo1KJG/a5ND9MMvBhOfIhTMvg3FQ9Tt?= =?us-ascii?Q?r8FxrYhfqJGLT9jnUFX2vdXAt4azfU52/Q2J3Pnlhtrptc9sbZlaRCP7ZoFc?= =?us-ascii?Q?cSyYMZqlIEwAC9hANiB7vzCbD9HXLwyWexAlASrwhz9yo1/5jJHbOvpzRJrC?= =?us-ascii?Q?FFKadBh7HpHvmtnGhT8qiUHwvgZiaDSxsWS8q99t9u8J4MgRlCIYOazFMjBq?= =?us-ascii?Q?kA6j62GN5qI+onLngHDjuVOo4oppzIFXqmBFKoLJg0tpeADaCHx9j58hRQ2a?= =?us-ascii?Q?7jqRdZ/p2gTEP2ITb44+xpQ1F9dGzcnYuHCi+cUujg7IVh0JsEgonWMviDmX?= =?us-ascii?Q?7moxCHxK1hmcwSDbaSo1AMnW8enIuBvpL3pixhL2MCKDu0KoEYzV+iABHPt/?= =?us-ascii?Q?DI7YQ39tdC75aCf9L5y3WyZIRxNZS2oeUMSk34gEIRhdicR9vApuDIkzmbx2?= =?us-ascii?Q?/kzZnJ0fXt6OSihh89bx9BxpSN8Q0rXdz2Du9Jx/ChZEKoLE2xyeb19R+hDr?= =?us-ascii?Q?u0WFZ57bhaalDMSAD4shydIUio67PEtH5rDQieecE+cxdakhpTXf2IwKfeiP?= =?us-ascii?Q?VzrZ/sMjG4DKXH0XPjd6BM2Mdi5JGwuutaVMtGvJU1U0+ENKweK7OX7NMSqb?= =?us-ascii?Q?3IfxPus9sX3ZBCcm0W2yERGl22UZcPPL+DGzE7QQUSsLg3qkcs3kwxhJcaT8?= =?us-ascii?Q?j1yKG51z6bIuwpufXDLMXxNdC/ft3UxSAfugXtnUvuzTrt9eSyjFAIp0xiV9?= =?us-ascii?Q?xksv74FBLmUMgLQvKMCDKtmLwjN2QyGEy7JwPd4w5+GRHfiE4hFkjOsdt68Z?= =?us-ascii?Q?SUBvjw3wfBYvLRapmlY2xQKHUah8OtoIl8zfi5ESbfChY0HurXqb05lwgtmp?= =?us-ascii?Q?Xl/thFY7yQrBhxULp/Uno6H74bqAxNVSmC9CVQyVXMx1BdRoRFi+NHogESVG?= =?us-ascii?Q?opeRFogM/M6noL01yTSsVZFdEdTMZAI9nETGikAJQxHLFSFXMNzxwLmWz9Zp?= =?us-ascii?Q?jl6ZCnZ06FqatKpgIinaqeNPYnCshFjGUGb5JcjU5e7oIaFCDudIKycDr1r/?= =?us-ascii?Q?67TARJjHrzOSlzCSWLyjzuRJ1GmEQ2hA5yPpRkkQSbvOclOO1aufuKB4UcoZ?= =?us-ascii?Q?9aq9MxzHcBv9ARSa7rcKFmPS/F/TzfQ2vNDCM8scYCuLGY2to62+wpyf57Xw?= =?us-ascii?Q?WJ5/gQZMUtUhbXEhK1g6frb2wNzjovwt8zd4b0OlIsock83fiytIZIEuzeyJ?= =?us-ascii?Q?TyaGGrw/7+9Bnwc4LZkNb9/dUGzHEU/4FtJOlcyu7RiE2BUmKqMZwR5ZM2+5?= =?us-ascii?Q?JYYiB9xT8ZWQIqE40yU=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR12MB6486.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(366016)(7416014)(376014);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?dX9lmpa0iuV3uA4IBHFB9Ls1rJR6fpnr+MIWVaGidgfsaoYlA5JfWbiWTLob?= =?us-ascii?Q?fRKup65M+Up4p+XRr7zoA8Dtl+NEqM6GCi/oVu4BGczQnDry5yfNtY5cR76M?= =?us-ascii?Q?+8PemTPtavonlalXT+p4WBF3yxNcE7rT1Tvhfx7HCr2lf4mNKTcjQMEQpJY9?= =?us-ascii?Q?B7setFPU7vbIKidKQQDRq5WsiSdQxpCX352HIn6ojfA1c1szY53SqDiw0IRE?= =?us-ascii?Q?TIc7cuCTW6Fvq2ye5i+p891gClsrGFMFFmkqgqxrPJLM6d5fuz/iJZgGQKnP?= =?us-ascii?Q?CaCaGd3bPkra5bs8tn+1EXQPQoFM/fIzF8O2RTtar3mcPngYF8aBrTbIIYhC?= =?us-ascii?Q?99VrlNvWYIle4qrqYALI9u/FkWauKuOHsKAcl8QiKBf4dqh6S5QmTbj4O/Hs?= =?us-ascii?Q?7fYRSTgTkpJ17dERvrkn9zt2hjunpi7fUqEwJSb3yVousi/9fZNgxIdR4Ljn?= =?us-ascii?Q?TBe/nECfAIISnJL9j5uSWhrUdvWqBtMj6MT5cICJ0xSOhJnqFeiqhMvHGL6Q?= =?us-ascii?Q?8ch7qIN++O+Zo1xqm3nWqexsijrkggYm2dHuLPHoG3AJpQs/yF+72mjtGQKm?= =?us-ascii?Q?FQbI0rn6A8L4RbmW990WVxMkvja3fsvwaPb+GhMvhRgxbqR8wAKJ5ln1PV/Y?= =?us-ascii?Q?jZSkegjpwcwO0L0xa9ptPWjS/nq/Mje4qB3np4cDaTbShOZWlBqOSSFUNgYM?= =?us-ascii?Q?9BB/mK5uqXISThq24RV6b//lg5hbdP6Tb9ORyeMbGWRIDRS465f4QweMOSg4?= =?us-ascii?Q?s4lIu8jy4SXdXcytg2O3WalFqxgv3hz9bzWQc/X+gQeCDM5NVaZIncK0y6Wv?= =?us-ascii?Q?q56lAq2cgHmK8D/bIBbXPaQk/40G+QENnr43htc/dwazHoDftY8o1Oq5gCXC?= =?us-ascii?Q?2cTIXgq/aPXnQSNaTnnKhJfjLjJ7sx2ajQhssAwNgX0Nk8WGU+UBa6jAgKjo?= =?us-ascii?Q?ZjGzBnblrhMlh+PdF/JYpmvTMoP8S8pF2M+8jtjOfhLEErM4vOnhQOben2QZ?= =?us-ascii?Q?fAMuiJunFrNJPBB9LfxMzxHRBd772WOHSjQ32uL+SbPN0JHWM8zHeAhlVcnq?= =?us-ascii?Q?vc3TE3uv26hHK89jOc8r/kLxUMzx+wvwfvVg91CH618Hdg6mDbAI0Y9WJp19?= =?us-ascii?Q?NoAybl2nmPGh301zUu9t4L9zIf3u20HhOQE79Zr1ke0BIUF+37/4jzP0z8/3?= =?us-ascii?Q?e4dXOJ6sN9vVgGmedwuZC6P4yIFFd7WO1YJdvmzrQ9qYAlQUFBgmla3fHP2X?= =?us-ascii?Q?N0CYE6Dy6Fy1Gm8X0r90Em3gbNHN10XdNXtCXBmVylw7JBAyOml5jYbR1Vzq?= =?us-ascii?Q?i87bzyMA/a9E11ApAzRNVbkXnSuGVhJcw+TYFuObFJFLnxFbcymz+yemRBZp?= =?us-ascii?Q?9F+OdX+Pcd0jCW7kaDO+BZ8aHPuIt2t4abf0wBbcci+viA5V10Q0x8dC7vEl?= =?us-ascii?Q?3+J/+c+vSbd0NVIZtbKjM78u8BYPvONI0pSOKgLYVeFuL94tuVfNLVSIF7UR?= =?us-ascii?Q?dbfBmrh8jbh405mNBNN2fDqfo8EttDZ6T40wGLIdcPkNgTPtrIpwpXSBPCbF?= =?us-ascii?Q?VU7jIKtuRRakcNyO9WSgG2EYoCxmUPuf5/9L2zAxnooYi/KlYUV//ha/+sKg?= =?us-ascii?Q?GHbrJqeBmmU8zFXW5n5Wdj+BZbSl3UCmE/ZprMyJShLsMtf040/4Mn1hsJ4q?= =?us-ascii?Q?FZCE6XZdbsyfcJ+CqNX/68ijzEcTXgUYvxl51rP2/FRGlLib4hsisw6CReal?= =?us-ascii?Q?EMTMHuY4tg=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 923f5975-b2f0-4087-889f-08de5864b6e2 X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB6486.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 20:44:32.3394 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 2a7NoyYxJw8a5rEhbUmX4+c0dKj+QYWpNOje01600O43glKtA2sTrJiPKdzpGc4WiB/PeFEyYaHA7Sj4N3ix0w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR12MB9651 Content-Type: text/plain; charset="utf-8" Add usable_vram field to FbLayout to store the usable VRAM region for driver allocations. This is populated after GSP boot with the region extracted from GSP's fbRegionInfoParams. FbLayout is now a two-phase structure: 1. new() computes firmware layout from hardware 2. set_usable_vram() populates usable region from GSP The new usable_vram field represents the actual usable VRAM region (~23.7GB on a 24GB GPU GA102 Ampere GPU). Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/fb.rs | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs index c62abcaed547..779447952b19 100644 --- a/drivers/gpu/nova-core/fb.rs +++ b/drivers/gpu/nova-core/fb.rs @@ -97,6 +97,10 @@ pub(crate) fn unregister(&self, bar: &Bar0) { /// Layout of the GPU framebuffer memory. /// /// Contains ranges of GPU memory reserved for a given purpose during the = GSP boot process. +/// +/// This structure is populated in 2 steps: +/// 1. [`FbLayout::new()`] computes firmware layout from hardware. +/// 2. [`FbLayout::set_usable_vram()`] populates usable region from GSP re= sponse. #[derive(Debug)] pub(crate) struct FbLayout { /// Range of the framebuffer. Starts at `0`. @@ -111,10 +115,14 @@ pub(crate) struct FbLayout { pub(crate) elf: Range, /// WPR2 heap. pub(crate) wpr2_heap: Range, - /// WPR2 region range, starting with an instance of `GspFwWprMeta`. + /// WPR2 region range, starting with an instance of [`GspFwWprMeta`]. pub(crate) wpr2: Range, + /// Non-WPR heap carved before WPR2, used by GSP firmware. pub(crate) heap: Range, pub(crate) vf_partition_count: u8, + /// Usable VRAM region for driver allocations (from GSP `fbRegionInfoP= arams`). + /// Initially [`None`], populated after GSP boot with usable region in= fo. + pub(crate) usable_vram: Option>, } =20 impl FbLayout { @@ -212,6 +220,19 @@ pub(crate) fn new(chipset: Chipset, bar: &Bar0, gsp_fw= : &GspFirmware) -> Result< wpr2, heap, vf_partition_count: 0, + usable_vram: None, }) } + + /// Set the usable VRAM region from GSP response. + /// + /// Called after GSP boot with the first usable region extracted from + /// GSP's `fbRegionInfoParams`. Usable regions are those that: + /// - Are not reserved for firmware internal use. + /// - Are not protected (hardware-enforced access restrictions). + /// - Support compression (can use GPU memory compression for bandwidt= h). + /// - Support ISO (isochronous memory for display requiring guaranteed= bandwidth). + pub(crate) fn set_usable_vram(&mut self, base: u64, size: u64) { + self.usable_vram =3D Some(base..base.saturating_add(size)); + } } --=20 2.34.1 From nobody Sun Feb 8 09:32:51 2026 Received: from SN4PR2101CU001.outbound.protection.outlook.com (mail-southcentralusazon11012013.outbound.protection.outlook.com [40.93.195.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5903A3D34BC; Tue, 20 Jan 2026 20:44:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.195.13 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941898; cv=fail; b=SRkkGHdsxnYw7B24FpRljY02stPFCZ/Bd9ef8tRmfTXU6wp/fGiqo5n0baDb4/cEEBekfhfFzoSrjtpvQgyGtqsMSALq1gmKkp34Lha+ndY3jfgwr1V4Yi/e8N/odbWo55xvnM8TW2ENjHOzoSdDn471p6XPHadQpWcT1pNWdnU= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941898; c=relaxed/simple; bh=uWeyARMwX0lyalYwj9wkbsYDIWuzaCsHP+NQmUZQrYM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=dBhQ66sO70J+iPffbuNBBjfG2+SGYrzTkErOBIi++Uz0S9A7F6cgy6x3XQjXWCOOx05NdLJ5IeJg3dAexZj00ygyj/UWFFosCD6LgkVUXoAtxkPbqkT93aPsPt0BhKZIARP3lmo+sIK8g56AYQ6M2jIOKL+AFPwslmtHVjWeRlM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=blT8Xdvh; arc=fail smtp.client-ip=40.93.195.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="blT8Xdvh" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ZA1DHHPQhVrRe3yiT8s7YeG8obRtVQyh3czPNmtRuZTw32V1XGsFfyp9bE76raBGNgdM7lBtKY5lGUwLB9uKq0wILFX3nXIiJ23/h88ci6spgJuNuJTDudNCxMVniTZ/djlpaFr7FBApywJSFkurX8jkQFPwxWmclBiiTcNsldzyKSlxv5ErKaBKc/M5OeD9H4NBZGzhbn3/b5N6/RNDwprf/7WWHSIuTRh6cYVrNQr3axqvNCzn/uq0KPrKOYOlJdeCGi2/xIPQZ5vL56RT8/RyLzbZ/uZQu+VHY0Ww5ubu1U0uSl9NaIWaucYFiSG2mpA0rMWXwCTtOD5XAfiMvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=PomTm1iOEgO20nycd1szNoCYqeZgpfISaUbKMSUnqLw=; b=rqwkgcxVLZCAi59DPoMTkcaLJSUW8chau5VkiiFYwuQFSUZX0ydjCeYS9Wen3j+U9XmT28mOP2KtLR1yFYvvkGsAgW55bJUg/hKsyh/GbM6oCBOX9jOiv+2daNqC2xdAc3yOcgXbl/itrwYYQVjpJ0fWxzb09r2hJExvPTyX8oIRtRM+lVs9a1jm1m+zsreNQYtjUt+raNOu1dIsadrg5WLg//AFhCuoNBJsfs8vfjs4blRZLI9zS+CXUUaH/XOaEheYqdVY1STM28C+Fj74uINmxKPli79uNBScAWD9yS/l4uVnB42QsIkQEfO1hiic6EpmasaZCzDnb6TBJv0EMw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=PomTm1iOEgO20nycd1szNoCYqeZgpfISaUbKMSUnqLw=; b=blT8XdvhVBggSaIYaDtjqsNqnyKDXpdJncEew4qWAfaTH2wsLFrHIa1McEofwzMCua15mMSsnVdPkoXMYmnMdAxdPZuR0sfXqvpwDMOfxD1SagEUwZhuP/lioSh0jytnZtYirYgPpsrdO9jerG3jzz7HdtcwUFg+MxnJrGdehrNYR4T7Ab0WB/5PQDErWLvS94e/OO81D2SZNuT6i80mJbTos/J52jaApTTlx/BiLRfwDwSHU843FwK0451+CtvLQYnT4LxFbUxVgaxFiGKF9PzfeRn4xaGTYTXkYDiF2yrzJreMf7njHM/XQzZmW7P8/pQGGqV9qmY1jFnAvRNq0w== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by CY1PR12MB9651.namprd12.prod.outlook.com (2603:10b6:930:104::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.13; Tue, 20 Jan 2026 20:44:34 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9542.008; Tue, 20 Jan 2026 20:44:34 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jonathan Corbet , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Huang Rui , Matthew Auld , Matthew Brost , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Helge Deller , Danilo Krummrich , Alice Ryhl , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Alexey Ivanov , Balbir Singh , Philipp Stanner , Elle Rhumsaa , Daniel Almeida , joel@joelfernandes.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, linux-doc@vger.kernel.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-fbdev@vger.kernel.org, Joel Fernandes Subject: [PATCH RFC v6 25/26] nova-core: mm: Use usable VRAM region for buddy allocator Date: Tue, 20 Jan 2026 15:43:02 -0500 Message-Id: <20260120204303.3229303-26-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120204303.3229303-1-joelagnelf@nvidia.com> References: <20260120204303.3229303-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MN2PR12CA0019.namprd12.prod.outlook.com (2603:10b6:208:a8::32) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|CY1PR12MB9651:EE_ X-MS-Office365-Filtering-Correlation-Id: a9a611a1-a55b-4abf-89b2-08de5864b7cd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?6m3x5IBQPfADy9nFW4J1NJ0JuoI76F9S/OVVg/r3FKY20OvxLP6+TxEPaeTt?= =?us-ascii?Q?U3r0ozfF9JST+WqH+pR//XCjB4oJ6MeDRIF6U7zAZMic6o0mu2Dnjyw25UOq?= =?us-ascii?Q?i0lLx8YAprYhf7uRArNydDWGDRnz+dWNOyKUeYxFLj5cxyFsjzrehOO4Ni2o?= =?us-ascii?Q?arb5NyfL068XoMV1RKNNrgfNBJf48SYtJMZxyw+HadoM0W3fTIQGzVegNf4B?= =?us-ascii?Q?ZNyIlWkMeNqxTZYx+gt3yTOi+g64yIRUtZqyqto4TLosFoOCmmas3NfxNPM9?= =?us-ascii?Q?b8fPrC2g2BwC9jeND0rtLgo2l/G6iIwmsGMKZp5bJmTSmOcFCBMv25oW0kVM?= =?us-ascii?Q?p21XKId5jTGrhPlA0TomcFo5tDjd+MzjKTV2snqA5kL8SGLDsqbcJHl1J4kZ?= =?us-ascii?Q?XemxIOrvOayZWShkqXJP072903akw0eHaaL94mIv0EAHISY7GadJLpLb/oWO?= =?us-ascii?Q?EGmyaUFytRJ9vlUGIHh2Xr8mQjzooMO39u86Lx4Y31fP0lp++QxhVqHoou96?= =?us-ascii?Q?KubgnepnLeYjHqPT+pgUS8+ZGiIqQeoEpFBfzOlnLMVUHGKykKE16c21bz4g?= =?us-ascii?Q?kPELbeGSmf2Vcx0XSYIBjaBavuNLsn//F5LgNgAbK36tTAZQZ+aSphVZz+SX?= =?us-ascii?Q?f/MDRKQRdl5od85HZ7M2BQd3eRuwRYX1gFG8LwZWTlDvGlgw8bsLo/en72Py?= =?us-ascii?Q?OW8Xgdwx9XY0OkSt/e/3LdE3OFCrZKyHszx6mAcaqzX665654AymZFKYQuo4?= =?us-ascii?Q?UCk0h05qsm1GeiYNnj9TX6plKBbG+G8JWSuvFxLqZqqbtlF74EqdIbdZwOB2?= =?us-ascii?Q?byMZroUPGTSoszdi5REfkO56mcaPnJSHfUt87LFowqfEEejtYpZATm0TkSCa?= =?us-ascii?Q?jVzeW/UHqbyiTUIktNLMOlSN3ncFk5AU+XypKtuzRU+7IhIhAnu2ZASlkgtP?= =?us-ascii?Q?fLkDAqiIxo+9+s1GwUUuYpNAx+oEhGGGhYhyTemSwckMN45QEYaI8UWfRC7O?= =?us-ascii?Q?rd0DWgj3WoJ8Yxj1zYE91lkWOs15XXNd505DC7FvOlux9bqGFoigsxoPk0c9?= =?us-ascii?Q?3nIOygAITPBdMvMRebyTzI+PdbAPeo99hfzIovQLBIrt7y2wQeXaaYVQ/Xec?= =?us-ascii?Q?GbSsMOBQ75WtM1cFqSa7HtyR8tZSRsFDlm/AtnYqKpBr03qUg2kq7IXLDX/c?= =?us-ascii?Q?SGuK/BP32PT8gwEWUJJKt7L5vUde5UVVue2CXSjYbaDqMSVG2+NmINKylyav?= =?us-ascii?Q?OYdq4mMsVCZOjbI5RAzc0tmnCGlUJlzJnvEzuAGkXrZX2OC6sAJrsTBxnu83?= =?us-ascii?Q?JamPAFvt7THnIBHcVeVgYfmB+wDzUg4rDq4MimcuwkmQ3bLajJr84UyClcLW?= =?us-ascii?Q?E/EIHgMxZm9Zn2aszObVCkMRFdApuxtLQkraKcQ+8BUseGuXhFeAVIDew3ok?= =?us-ascii?Q?XQ43JITqNuona8yP3rDCQGYoRITlDrxBeZ7e4cYUNYKEXOn635uoLU/ucWHe?= =?us-ascii?Q?3/HG6bJxr7OO7WcMLTjtKAASBxIHudipF2VTeFa+QikvIOrM9RZcSWJr+uTT?= =?us-ascii?Q?ssxER53iHGVDwJRg2K0=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR12MB6486.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(366016)(7416014)(376014);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?9lj9cc4pFVOGfbMy6n4l4hm/ShXpl7PZONOWTfBRnvyeiSmyt2T4rWG8CQSN?= =?us-ascii?Q?aTveLP0bBb0COOquy+sRTC2F5026J81UUX6ZwEZDkf6o3XkPTIm3cUHnICoK?= =?us-ascii?Q?K+/DAU3MwEQ5oYAXMs41yZv6lgyFva6foKZlfa+8pOOrRhc5aiERD87KuGii?= =?us-ascii?Q?7v0L6abf5dhlkOaVcjjkOp+GlecDndhqBZmvZRZHGefZ4limnso9p1wfSox6?= =?us-ascii?Q?PSqNMY8Tn1ZvzhzW1kSeW6b8PmEiddMRmNm/ahkcGn7el4Gl68EwWwH2jq3M?= =?us-ascii?Q?VE6D7UzoGV8RSNhr1DPC+1HfREgfDn6xBK5flJWJI2fX5ARCxq7ZY8xa6CPf?= =?us-ascii?Q?lBb9XdYAmfrDiz36IePflC7/Y8I7nQSseMZsC3CGncnnhmRG3oBJugOaewzK?= =?us-ascii?Q?jhSSWt/25ICBBYGAsivYIiwfUt2RHMrY37ApvvLWVcIIoslBkBZNomF0CQ7I?= =?us-ascii?Q?nvhtmErtkdGgD1BidOZFIRF5qHJIQ33IFyvFH+fkso9eIQVdJbBA3PZU3Jg+?= =?us-ascii?Q?JMa0cnlFm31quBsKLMIZwHrL1mxtSzhNrHtGCgSzT0+4GWdahpeTqX4IS8PM?= =?us-ascii?Q?REAjfJ8Qu4xalocESN66Y6wExxuSkji+2P/tm2SyTlnXZ/N8c8RloNPlCQ0p?= =?us-ascii?Q?+X/LJhJO1a17ghE/IISnGXL37xRTJwoM4RkfMGunTDpQQHk8mx4lf47dUfsl?= =?us-ascii?Q?F2wqP3NiLCJYuNq+9d+39R2SMImNKXViAPuwyORUyfLdNmctjqhMJZT2ios/?= =?us-ascii?Q?3PqC6wV1zZHczk1dWTFoRyxFXguH1KEQ8PQoxpFI59xUFsMWCY7mzRi//9Qv?= =?us-ascii?Q?8keeI7WYvdTn8ifARFEAjA2BxtuxoMv6cRgQI40vmd8/aB/bkp6AQad7LXDH?= =?us-ascii?Q?0S/LtTvm+xnZfT8jdFbTnr5YUoFANIE07ijzKPh/DUo/pYoaI15saVxfouMq?= =?us-ascii?Q?4jrNSA1wbVJ/cJ59Wpr64VIl8nYwMH9oG/B6OrlqHhWk5E5GxmiJQT2p66Rx?= =?us-ascii?Q?zPRGWFUNo6u/jefpYXiY46n5xTUFMbcwshcLc5nDwl+fjGpe5Qp1Z1tCRXwX?= =?us-ascii?Q?vHEa49yHIuhMQV95N0W9MtiBgo3DSOKTWXehn5VSpEIStjKe7wH4Y4wPuN0d?= =?us-ascii?Q?8Dfr1YDV5c5ysHrL5Ts+QgoB6MRUvHycopl5ara1RtcQQnp2jMExsmWxRoVg?= =?us-ascii?Q?40R4xowmv/AjM2oOK+1IJW9AH8QvuHfDtCTJXn8qouc8A5MP9eqSIZmNWqEL?= =?us-ascii?Q?YBaRb4KA1gCQUZcBsfaasylGx1+Dcn1SSzvrWAR6jPM6nHcwbFQv5N100qZ5?= =?us-ascii?Q?ePoo1qbtRwv5b6/wKzQkSMtw7ikOzAFGjjQhYc8YlzQEOZxpWep3Le3wyiO+?= =?us-ascii?Q?3GTNrt4r4MMckQMQovqdl1s+yd9LXrKNvbh9q4h0JFRRLmr8t6o7Fp5yw+zl?= =?us-ascii?Q?vHfhY3gwi948+trpa1EkJ6vfNlVQvDywgwUoc7ETiBaVMjtg50v+fC0bNtub?= =?us-ascii?Q?auXXyDWPZk2dOV7CuehVe6B+AqeGGG72b4sAcuivjII0KNtGrMbi8zxCQAwm?= =?us-ascii?Q?L957ZgHGBDqybWP7R+lmvL9WQscybbkPb2CsXhy3bzgiID/cveXXZbZIm+7D?= =?us-ascii?Q?0chNUQW/Chak7hUFBnPlmSxK1EZk++FUikhozmTjdTiXUPvcdqRI0e/fF2V6?= =?us-ascii?Q?nNSvh1RSmRsHYsRoQecIXOoAv/PxzdlzH3JDc8dVMl6YEjyU08yWO7lRjCBy?= =?us-ascii?Q?ZvClK+9evA=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: a9a611a1-a55b-4abf-89b2-08de5864b7cd X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB6486.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 20:44:33.9787 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: BqFll4Hr7pfrljO+amAX8Ws+k8kpmnwYpM6bhvuWCTQkWrZPcSO0bEDBRWyPvQNulxZiiLcHnwYZKHSGZNndPA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR12MB9651 Content-Type: text/plain; charset="utf-8" The buddy allocator manages the actual usable VRAM. On my GA102 Ampere with 24GB video memory, that is ~23.7GB on a 24GB GPU enabling proper GPU memory allocation for driver use. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/gpu.rs | 62 ++++++++++++++++++++++----- drivers/gpu/nova-core/gsp/boot.rs | 7 ++- drivers/gpu/nova-core/gsp/commands.rs | 2 - 3 files changed, 57 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index a1bcf6679e2a..dd05ad23f763 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 =20 +use core::cell::Cell; + use kernel::{ device, devres::Devres, @@ -7,7 +9,7 @@ gpu::buddy::GpuBuddyParams, pci, prelude::*, - sizes::{SZ_1M, SZ_4K}, + sizes::SZ_4K, sync::Arc, // }; =20 @@ -28,6 +30,13 @@ regs, }; =20 +/// Parameters extracted from GSP boot for initializing memory subsystems. +#[derive(Clone, Copy)] +struct BootParams { + usable_vram_start: u64, + usable_vram_size: u64, +} + macro_rules! define_chipset { ({ $($variant:ident =3D $value:expr),* $(,)* }) =3D> { @@ -270,6 +279,13 @@ pub(crate) fn new<'a>( devres_bar: Arc>, bar: &'a Bar0, ) -> impl PinInit + 'a { + // Cell to share boot parameters between GSP boot and subsequent i= nitializations. + // Contains usable VRAM region from FbLayout and BAR1 PDE base fro= m GSP info. + let boot_params: Cell =3D Cell::new(BootParams { + usable_vram_start: 0, + usable_vram_size: 0, + }); + try_pin_init!(Self { spec: Spec::new(pdev.as_ref(), bar).inspect(|spec| { dev_info!(pdev.as_ref(),"NVIDIA ({})\n", spec); @@ -291,18 +307,42 @@ pub(crate) fn new<'a>( =20 sec2_falcon: Falcon::new(pdev.as_ref(), spec.chipset)?, =20 - // Create GPU memory manager owning memory management resource= s. - // This will be initialized with the usable VRAM region from G= SP in a later - // patch. For now, we use a placeholder of 1MB. - mm: GpuMm::new(devres_bar.clone(), GpuBuddyParams { - base_offset_bytes: 0, - physical_memory_size_bytes: SZ_1M as u64, - chunk_size_bytes: SZ_4K as u64, - })?, - gsp <- Gsp::new(pdev), =20 - gsp_static_info: { gsp.boot(pdev, bar, spec.chipset, gsp_falco= n, sec2_falcon)?.0 }, + // Boot GSP and extract usable VRAM region for buddy allocator. + gsp_static_info: { + let (info, fb_layout) =3D gsp.boot(pdev, bar, spec.chipset= , gsp_falcon, sec2_falcon)?; + + let usable_vram =3D fb_layout.usable_vram.as_ref().ok_or_e= lse(|| { + dev_err!(pdev.as_ref(), "No usable FB regions found fr= om GSP\n"); + ENODEV + })?; + + dev_info!( + pdev.as_ref(), + "Using FB region: {:#x}..{:#x}\n", + usable_vram.start, + usable_vram.end + ); + + boot_params.set(BootParams { + usable_vram_start: usable_vram.start, + usable_vram_size: usable_vram.end - usable_vram.start, + }); + + info + }, + + // Create GPU memory manager owning memory management resource= s. + // Uses the usable VRAM region from GSP for buddy allocator. + mm: { + let params =3D boot_params.get(); + GpuMm::new(devres_bar.clone(), GpuBuddyParams { + base_offset_bytes: params.usable_vram_start, + physical_memory_size_bytes: params.usable_vram_size, + chunk_size_bytes: SZ_4K as u64, + })? + }, =20 bar: devres_bar, }) diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/= boot.rs index 75f949bc4864..a034e2e80a4b 100644 --- a/drivers/gpu/nova-core/gsp/boot.rs +++ b/drivers/gpu/nova-core/gsp/boot.rs @@ -150,7 +150,7 @@ pub(crate) fn boot( =20 let gsp_fw =3D KBox::pin_init(GspFirmware::new(dev, chipset, FIRMW= ARE_VERSION), GFP_KERNEL)?; =20 - let fb_layout =3D FbLayout::new(chipset, bar, &gsp_fw)?; + let mut fb_layout =3D FbLayout::new(chipset, bar, &gsp_fw)?; dev_dbg!(dev, "{:#x?}\n", fb_layout); =20 Self::run_fwsec_frts(dev, gsp_falcon, bar, &bios, &fb_layout)?; @@ -252,6 +252,11 @@ pub(crate) fn boot( Err(e) =3D> dev_warn!(pdev.as_ref(), "GPU name unavailable: {:= ?}\n", e), } =20 + // Populate usable VRAM from GSP response. + if let Some((base, size)) =3D info.usable_fb_region() { + fb_layout.set_usable_vram(base, size); + } + Ok((info, fb_layout)) } } diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/= gsp/commands.rs index d619cf294b9c..4a7eda512789 100644 --- a/drivers/gpu/nova-core/gsp/commands.rs +++ b/drivers/gpu/nova-core/gsp/commands.rs @@ -191,7 +191,6 @@ pub(crate) struct GetGspStaticInfoReply { gpu_name: [u8; 64], bar1_pde_base: u64, /// First usable FB region (base, size) for memory allocation. - #[expect(dead_code)] usable_fb_region: Option<(u64, u64)>, } =20 @@ -242,7 +241,6 @@ pub(crate) fn bar1_pde_base(&self) -> u64 { =20 /// Returns the usable FB region (base, size) for driver allocation wh= ich is /// already retrieved from the GSP. - #[expect(dead_code)] pub(crate) fn usable_fb_region(&self) -> Option<(u64, u64)> { self.usable_fb_region } --=20 2.34.1 From nobody Sun Feb 8 09:32:51 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013061.outbound.protection.outlook.com [40.93.201.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D5AC47AF76; Tue, 20 Jan 2026 20:44:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.201.61 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941898; cv=fail; b=K/150uLsdqG7qsF9mSo0ZZzbdb21fABENQurudfMODHarzDFg86pWW+eZBokkrG7BToaZU6ki9hPr3aDNJn3QOJORgIpJLWbEDcIuIaOAl+jkhXT+WdHdlBWzoDWA87Pnt57hk3UV69u9HwUaIZ+l3ZX0p1gSXfOr9MZvENGqDQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768941898; c=relaxed/simple; bh=6WPKSzEeOBIe6Ws+ORfmGjwYBVDjO6t2YAT6tofQnno=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=Ukcxw4ouWd/5SVMjfahJCT/8Igna2Nc/aEIZwBz7Yb98v/gsgJQZCeDWZ3tqtydCLyh9fUCa+sCp2XEZzPjCHHHRmpSYuiX94oSfM+A7ntvY8/m+XEjPE/Dn5YRKpxbtfsmzL+D11QAbliuzQaG/pvL/P6sazrjJG5lyeTP0peE= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=mYJLNEo0; arc=fail smtp.client-ip=40.93.201.61 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="mYJLNEo0" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=oIdt4AMouvdBqWFtPo+qf7goefXpu40PqPC+bTkQeG95rpRa+KL5boCNbMdBD6lWhRMXNUILnrTUgYrOSxmYcUJ6PMwkQNrtf+O7Fw5jRcBeSmG2I7HDMEXqtrhOemB+vlkoKsSomD+qNfXB4u2J47dlPxQP9s2xt9C9VLkQ0CyFMppFVoRpW/tvJ3gNARDLezey3Otr6yGHJklbhJP89O3pnQ6mQtrQ4X2Qyb01SYU6LAtG9yhECrQv3UT62j3HYmTLGflBeBKDkhKRAh7aUOPoUA5DzmZipyLKPDy2VxiYc3CwrQhj6wz6k1eKqy6XbHZnMCuWfCWTu2Z/zSmcAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Jsv1e8brNR4vRcNmqW8W+18B6YXhLsOcJX3aAlSFAAo=; b=tewqwABnVlI+YH+l1lii7MLvIFr+2lscwfm0vDM/q/E4DNHMbolTsLE201zRCuohNRBzbeDm64ugqLHwWqzB5I6IVI7lJs45Wwc6Dt29yxWDs54NfUs31RdUr2jB6DLtL51/y4isDvYQInyz3z9igMITEa2uBe1RlZjPaJelSEw+2rwwWGFPIAKya3Q6WNmHbhr7CgKyPPpFKeTHx6Xaf60WZ5Tc8wPt+VPZ1tWLwR4RUA7OfgzCEfJkKswoj1FUiEfyK+5UwFRjO6mIGN5C8WSFE736zumAXO1RogDZ3BLTbssGA1b8zS7ERVDTlFWXg8+bbGVq3iBMEj7w/eVEyg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Jsv1e8brNR4vRcNmqW8W+18B6YXhLsOcJX3aAlSFAAo=; b=mYJLNEo0LWrSNHrNr869MhSvSH66M6aXuTSlVQY2vZDpjo/Ll58ZLgtmPuDLqvD98LG4jaC7Wnran4+JZVMlra5tejd0m9Ci9UUtJJ6ZN6p0RO/NOkD4jVD3PoJfuwfrLom0rB0UggwtLrMKLFTvlcXQ4bZIvqI89XIKFt/ZbwcP3Y4m8dc6SEzVpOXOtYaOVQtZxKw5+tbajGyOoXui/Vzwl+nNNnRjXcjt29igWNPZuYn9Opcjob9ZTTroGLnCqlK5rI0ikDrBhatredDkrpQo6dx0nlaXqxnpdEAM3XLyNwxZprPSpoLQKdTkV/QzJt5a6YHpBMciRw4zH0uMGw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) by CY1PR12MB9651.namprd12.prod.outlook.com (2603:10b6:930:104::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.13; Tue, 20 Jan 2026 20:44:35 +0000 Received: from DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33]) by DS0PR12MB6486.namprd12.prod.outlook.com ([fe80::88a9:f314:c95f:8b33%4]) with mapi id 15.20.9542.008; Tue, 20 Jan 2026 20:44:35 +0000 From: Joel Fernandes To: linux-kernel@vger.kernel.org Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jonathan Corbet , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin , Huang Rui , Matthew Auld , Matthew Brost , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Helge Deller , Danilo Krummrich , Alice Ryhl , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Alexey Ivanov , Balbir Singh , Philipp Stanner , Elle Rhumsaa , Daniel Almeida , joel@joelfernandes.org, nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, linux-doc@vger.kernel.org, amd-gfx@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-fbdev@vger.kernel.org, Joel Fernandes Subject: [PATCH RFC v6 26/26] nova-core: mm: Add BarUser to struct Gpu and create at boot Date: Tue, 20 Jan 2026 15:43:03 -0500 Message-Id: <20260120204303.3229303-27-joelagnelf@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120204303.3229303-1-joelagnelf@nvidia.com> References: <20260120204303.3229303-1-joelagnelf@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MN2PR12CA0026.namprd12.prod.outlook.com (2603:10b6:208:a8::39) To DS0PR12MB6486.namprd12.prod.outlook.com (2603:10b6:8:c5::21) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR12MB6486:EE_|CY1PR12MB9651:EE_ X-MS-Office365-Filtering-Correlation-Id: f35792fe-f5ac-42ed-70ab-08de5864b8c7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?wJ9qVTEp+tLm0w6mG0nh6k70zse8tNsYAonZi9n7QTBVw9h91XU6tc+sJ6tS?= =?us-ascii?Q?PKTiKNlkj3I5hPyklQgyYKF3w6bZf1KYC6Z/HEa4n4VYtFW9n7rB6QmjtdoW?= =?us-ascii?Q?Pm3fPLwSmBFCAj22U4QnZlWElED11CGYPqQMhAhSMoPwNW/qRIuxLJ+UMI+I?= =?us-ascii?Q?kyEaN2yPmW+RFIMCCoBf/MXMytFiLz9TbC5GwERIk3LNYePsZWrsoGU625Ny?= =?us-ascii?Q?n1yP1/xMxeNg5gyByZSnqY+pBrYRphO8I9oncF3oIkErAvk3EqO2ZtXe6DTq?= =?us-ascii?Q?9zpyuwq8WO7HeQonX7TAeuSbBeRKXYc/lzwPvxJbRMbItdXfLnLIUfwNeDwx?= =?us-ascii?Q?TukYK/VUt0c9BI6SfmnUiQpkmDzz5UCKppWus/LIpRfPQOVrcnGg4YIYYJkd?= =?us-ascii?Q?XtZzHwWPUF8g3FkqYMrxRhoFtsn+UEND4Oax4thpvN55WY6dQfrxLEiKorR7?= =?us-ascii?Q?dZ2HxTXjGUzLEh7wv4NjaBV7ClAfH6KR4zOYEhpzNuXkc8wslO3vCRBC9rLT?= =?us-ascii?Q?FtxZmM/tYenZBwe5Fkp0m6jjHDpNaQootkF9fbgzKjXSyT7ZDysr5Wx5rvY/?= =?us-ascii?Q?A2H8NjAglm1241fUnyAMNn/UlfZqTeihqvwpStqhr0Qer31oEYKyMmSGtdgC?= =?us-ascii?Q?g+GFSUh5JT5m7lMRNMR5ykW9tRihFnp7GgwhTXYH8cHX//XGW8XpTRuYCQMc?= =?us-ascii?Q?vwTRSTG+SHcKf8LD0vcZQqMyVXAiBssdI9h4oDgdeY6A2K/npGYTetawe53G?= =?us-ascii?Q?NI6AQTkQGvCCu0S1Ogfi7iArOP3T4Hbd989nSdxlD0a4Wi7IzqaZ978YlgD4?= =?us-ascii?Q?nPV0f1HDo9Ne81Cy5IEInvF+XmkiwuML8SM8fXVVMw0NSNUOYmbH5eAoA7bH?= =?us-ascii?Q?16vpNlVcsc3qXIqNd026bNucCEJXC/fKoiN6O+P0gLCOXivk800U8i5U4DND?= =?us-ascii?Q?PP8uO1AjkVvHlJAWo9OjGFqQ72iE97OPKPb+kx8wmu7ersmBZjTZ0kZPC32s?= =?us-ascii?Q?3CAE7f3/QnOJAbvwv/bOASUKrxHBQ6+ObFDDUsZRddq9OEET/8SPOSCbKRYe?= =?us-ascii?Q?b1wbU4x/etImYNyiJVmIpFs04IxYJY7BZ0BJVVGlyqTbeo8q9OlvGtSkLqeI?= =?us-ascii?Q?eZGuG6BxKEz+04lcf68Xqs268KcmLHH53NgjgHspZfgtnJIAr9fKZq6ZtkeH?= =?us-ascii?Q?YTT2lnIM+/t4HJLkPhQ6enWhm6Spn7/QIACaAnpio8nA3fwgriJCM2m4TMUa?= =?us-ascii?Q?olHrFGOFnDdYXSEIsEGMtkIB7RUThfiSF17KQMphnn4+qxuHzW6ScAX/hQkc?= =?us-ascii?Q?z3l7wnQBm0ExqNAiUWoF/fREfXLZsC0wOYnQ2bd6w4pBrffPH/WK6inpgh2D?= =?us-ascii?Q?k6ZuIuJqEZIumwpbTVM5EMXoLP3cDbPPVYuLIT9zs8Z/3PM+RXL3N/vL4OFX?= =?us-ascii?Q?aMfLSS5FmzkwBeG7GhJ/LHawvpC/M0z+qQie5Jon+9VWXMua/eyV03bYL5rU?= =?us-ascii?Q?0lLyXWB9PSNZsjgA10AvoQCV+D34AqGdh2AxDyVN7bqAt4kJnrZrL2nIZWyb?= =?us-ascii?Q?VuigMb63ufioQ6sr2fU=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR12MB6486.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(366016)(7416014)(376014);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?+midhUHRyjfDD0STAL7z94X16xh88xbqNDauodS/8wFXmNOPJZfCwAbMmFGZ?= =?us-ascii?Q?eonZhmGmN0xjnbHYcDH3X3jqU00QApV7L7uXqOEHOktZUMFYRORIcMVSxc3q?= =?us-ascii?Q?yGj/9mxL3yJnDKdjijrEA5pEcUDZs6dgAQq5rmfHFiDb7OTRQzzl/YNDolUc?= =?us-ascii?Q?+CiIPqR8A1BK3z0XknnqifNSxe3I2eHMrL/qnRUDVKE+syBsSV6umZXWVM/t?= =?us-ascii?Q?tqfZiAfo3isZxvNLwKwBAR+s4VQG0YfOXpzkA5Z8iv5gVuetOVUEjnDMGnP0?= =?us-ascii?Q?6H5BQCOXsyqOenPoACd+GIhFm/0KpIKhzA/Km7TKLczPwhaNEO07wYKFAe1h?= =?us-ascii?Q?8chp2FwY+K+OHWmWMFho6hry82xh0/Z5PhRvMBkmxurn5SzRm60km7t+AIuh?= =?us-ascii?Q?Le91PLHIOJ6h9Du/be2acRC1mC9kr5mli1i1rphuuS9XpTWORih7jEZpXvHS?= =?us-ascii?Q?wVis/DjqbnxB9j7lhNopXaScROCQ8wdrxoES5gmFEwwBVYJmPEt5MCOUGkOM?= =?us-ascii?Q?gNOL7ctfowIYFDQCwxQLH1STq2aC4WP7dCZTaCiaBfwh1wmg8U7yrHe9r0mS?= =?us-ascii?Q?eMCnADTcvPdizcJOW9iY396jyJnBo0aTi2uoZkQQOI1MDTto7d+Ars4+8Ctf?= =?us-ascii?Q?fhNwYv8Fg1UlW4rUWnvEZ0HUc6sg2yXg0sAMTcIU8OZPRBuuH7R4ZcEEFpl7?= =?us-ascii?Q?3CpWrIl2XcRpfhyoDxGxlP42JoUAKO8l9wWAL1oimm+Yayax7JnSHazl+Ifx?= =?us-ascii?Q?tCIL8V1GtrVxDv6rwklDk0fZ/o+7hwA8r7ywZa9d2nM2xrOzagKokHwHQ27v?= =?us-ascii?Q?3k8uEGEz8JANZ2u/oxRo0LBzWw/+R/wSO+yISL7DCHK1HAOE1GiB8mONelfd?= =?us-ascii?Q?MXPrXDwQj/CF68G4zBgjEGPtcj/cKJ6cjqwSXaIdwx4mZnnRqAgGiJrNBQ1j?= =?us-ascii?Q?mp3ouu6y20iHM7+q+16R3OMWxpU06uDcnw4ZX+ZxcU8aq20DD1ScxhCVTvi2?= =?us-ascii?Q?8PMHlKmcmZMizQKYAecLbFHGxKZWGS7TJAtXjKHEtSvu1SDXo4QHkCRE4u4n?= =?us-ascii?Q?3ip51+8jT9VniRB0DMdOkL8z7TzsBMpT54zweB6ifekSy17dOy+N56q4ReW8?= =?us-ascii?Q?2gqwHVSBYGgbTRUVdyDprIYZCVPaYWMoNWNjm1kkJLIPYb/eqsz6UJNIvvZ6?= =?us-ascii?Q?KOXtg4JsqGlCXT5hEX/WfvlUDNYcxnJ0eoE0Q1gVVrMBkWLbFuukgKY/PN4V?= =?us-ascii?Q?7AV2SQYgBs4jZJkIKOmL+/E7+RsC1EIrWa7Xt1xIRkYS61mXFNxZH53hcjiq?= =?us-ascii?Q?2krrbgnmCqE6TaZgs+i6g4gi5AFhEklnWo4jAqBjb5MAvVT4grNRALgdnyrf?= =?us-ascii?Q?ddCgzc+pZWGNdc2oHU3HQixWFzf9lpSrblw3y5miBPsxOau/UFw9QB0RwaZd?= =?us-ascii?Q?cKSFXiapIbrto7XeTu3/i5v8KlSMtJbM4e69ipsfM9Kmc+pkJiSXGEISMtSg?= =?us-ascii?Q?5B6yxNfyY5s6cS67LxR6m+Da5dZhAPMKu2tf/t0PwtOwPD3AWd6VyYQAWbY9?= =?us-ascii?Q?xVMduQ1K9MeTECCrUzEsYrojMiw4OWVQ4zvaltsWv52cVTukh3IvGj4+Ty7T?= =?us-ascii?Q?BIjROHm/SvJWyTk4KcAEy3GVhQK24UaKIGVclzJQa5h7J3s6Laz354nZFmiV?= =?us-ascii?Q?lTIob90AEXcJs4Xp4fkaIC6KPlRofpbgTjxz5zhNCZRBypoLCuCEQA8xgb/f?= =?us-ascii?Q?dY9JNKnS/Q=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: f35792fe-f5ac-42ed-70ab-08de5864b8c7 X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB6486.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 20:44:35.5096 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 3Ig643zkLuC7LXCBSY/i9lX77fhcBupmWFSEMQPNE5LQG/1otdQPuXyQ4NEVK5XaB1ss3KJst2+9wxVrOwFFDw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR12MB9651 Content-Type: text/plain; charset="utf-8" Add a BarUser field to struct Gpu and eagerly create it during GPU initialization. The BarUser provides the BAR1 user interface for CPU access to GPU virtual memory through the GPU's MMU. The BarUser is initialized using BAR1 PDE base address from GSP static info, MMU version and BAR1 size obtained from platform device. Signed-off-by: Joel Fernandes --- drivers/gpu/nova-core/gpu.rs | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index dd05ad23f763..15d8d42ecfa8 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -26,7 +26,12 @@ commands::GetGspStaticInfoReply, Gsp, // }, - mm::GpuMm, + mm::{ + bar_user::BarUser, + pagetable::MmuVersion, + GpuMm, + VramAddress, // + }, regs, }; =20 @@ -35,6 +40,7 @@ struct BootParams { usable_vram_start: u64, usable_vram_size: u64, + bar1_pde_base: u64, } =20 macro_rules! define_chipset { @@ -271,6 +277,8 @@ pub(crate) struct Gpu { gsp: Gsp, /// Static GPU information from GSP. gsp_static_info: GetGspStaticInfoReply, + /// BAR1 user interface for CPU access to GPU virtual memory. + bar_user: BarUser, } =20 impl Gpu { @@ -284,6 +292,7 @@ pub(crate) fn new<'a>( let boot_params: Cell =3D Cell::new(BootParams { usable_vram_start: 0, usable_vram_size: 0, + bar1_pde_base: 0, }); =20 try_pin_init!(Self { @@ -328,6 +337,7 @@ pub(crate) fn new<'a>( boot_params.set(BootParams { usable_vram_start: usable_vram.start, usable_vram_size: usable_vram.end - usable_vram.start, + bar1_pde_base: info.bar1_pde_base(), }); =20 info @@ -344,6 +354,16 @@ pub(crate) fn new<'a>( })? }, =20 + // Create BAR1 user interface for CPU access to GPU virtual me= mory. + // Uses the BAR1 PDE base from GSP and full BAR1 size for VA s= pace. + bar_user: { + let params =3D boot_params.get(); + let pdb_addr =3D VramAddress::new(params.bar1_pde_base); + let mmu_version =3D MmuVersion::from(spec.chipset.arch()); + let bar1_size =3D pdev.resource_len(1)?; + BarUser::new(pdb_addr, mmu_version, bar1_size)? + }, + bar: devres_bar, }) } --=20 2.34.1