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Tue, 20 Jan 2026 06:56:41 -0800 From: Sumit Gupta To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v6 1/9] cpufreq: CPPC: Add generic helpers for sysfs show/store Date: Tue, 20 Jan 2026 20:26:15 +0530 Message-ID: <20260120145623.2959636-2-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120145623.2959636-1-sumitg@nvidia.com> References: <20260120145623.2959636-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9DC:EE_|IA0PR12MB7529:EE_ X-MS-Office365-Filtering-Correlation-Id: 313bc7cf-b594-4e59-905a-08de58343550 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|376014|82310400026|1800799024|921020; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 14:57:18.7894 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 313bc7cf-b594-4e59-905a-08de58343550 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9DC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7529 Content-Type: text/plain; charset="utf-8" Add generic helper functions for u64 sysfs attributes that follow the common pattern of calling CPPC get/set APIs: - cppc_cpufreq_sysfs_show_u64(): reads value and handles -EOPNOTSUPP - cppc_cpufreq_sysfs_store_u64(): parses input and calls set function Add CPPC_CPUFREQ_ATTR_RW_U64() macro to generate show/store functions using these helpers, reducing boilerplate for simple attributes. Convert auto_act_window and energy_performance_preference_val to use the new macro. No functional changes. Signed-off-by: Sumit Gupta Reviewed-by: Lifeng Zheng --- drivers/cpufreq/cppc_cpufreq.c | 69 ++++++++++++---------------------- 1 file changed, 25 insertions(+), 44 deletions(-) diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index 36e8a75a37f1..c95dcd7719c3 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -863,73 +863,54 @@ static ssize_t store_auto_select(struct cpufreq_polic= y *policy, return count; } =20 -static ssize_t show_auto_act_window(struct cpufreq_policy *policy, char *b= uf) +static ssize_t cppc_cpufreq_sysfs_show_u64(unsigned int cpu, + int (*get_func)(int, u64 *), + char *buf) { u64 val; - int ret; - - ret =3D cppc_get_auto_act_window(policy->cpu, &val); + int ret =3D get_func((int)cpu, &val); =20 - /* show "" when this register is not supported by cpc */ if (ret =3D=3D -EOPNOTSUPP) return sysfs_emit(buf, "\n"); - if (ret) return ret; =20 return sysfs_emit(buf, "%llu\n", val); } =20 -static ssize_t store_auto_act_window(struct cpufreq_policy *policy, - const char *buf, size_t count) +static ssize_t cppc_cpufreq_sysfs_store_u64(unsigned int cpu, + int (*set_func)(int, u64), + const char *buf, size_t count) { - u64 usec; + u64 val; int ret; =20 - ret =3D kstrtou64(buf, 0, &usec); + ret =3D kstrtou64(buf, 0, &val); if (ret) return ret; =20 - ret =3D cppc_set_auto_act_window(policy->cpu, usec); - if (ret) - return ret; + ret =3D set_func((int)cpu, val); =20 - return count; + return ret ? ret : count; } =20 -static ssize_t show_energy_performance_preference_val(struct cpufreq_polic= y *policy, char *buf) -{ - u64 val; - int ret; - - ret =3D cppc_get_epp_perf(policy->cpu, &val); - - /* show "" when this register is not supported by cpc */ - if (ret =3D=3D -EOPNOTSUPP) - return sysfs_emit(buf, "\n"); - - if (ret) - return ret; - - return sysfs_emit(buf, "%llu\n", val); +#define CPPC_CPUFREQ_ATTR_RW_U64(_name, _get_func, _set_func) \ +static ssize_t show_##_name(struct cpufreq_policy *policy, char *buf) \ +{ \ + return cppc_cpufreq_sysfs_show_u64(policy->cpu, _get_func, buf);\ +} \ +static ssize_t store_##_name(struct cpufreq_policy *policy, \ + const char *buf, size_t count) \ +{ \ + return cppc_cpufreq_sysfs_store_u64(policy->cpu, _set_func, \ + buf, count); \ } =20 -static ssize_t store_energy_performance_preference_val(struct cpufreq_poli= cy *policy, - const char *buf, size_t count) -{ - u64 val; - int ret; +CPPC_CPUFREQ_ATTR_RW_U64(auto_act_window, cppc_get_auto_act_window, + cppc_set_auto_act_window) =20 - ret =3D kstrtou64(buf, 0, &val); - if (ret) - return ret; - - ret =3D cppc_set_epp(policy->cpu, val); - if (ret) - return ret; - - return count; -} +CPPC_CPUFREQ_ATTR_RW_U64(energy_performance_preference_val, + cppc_get_epp_perf, cppc_set_epp) =20 cpufreq_freq_attr_ro(freqdomain_cpus); cpufreq_freq_attr_rw(auto_select); --=20 2.34.1 From nobody Sat Feb 7 19:08:29 2026 Received: from CO1PR03CU002.outbound.protection.outlook.com (mail-westus2azon11010067.outbound.protection.outlook.com [52.101.46.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B80C343DA2F; Tue, 20 Jan 2026 14:57:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 14:57:17.3693 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4bbe3ec6-c4eb-4dc8-e136-08de5834347d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000145.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7000 Content-Type: text/plain; charset="utf-8" - Remove redundant energy_perf field from 'struct cppc_perf_caps' as the same is available in 'struct cppc_perf_ctrls' which is used. - Move the 'auto_sel' field from 'struct cppc_perf_caps' to 'struct cppc_perf_ctrls' as it represents a control register. Reviewed-by: Pierre Gondois Signed-off-by: Sumit Gupta Reviewed-by: Lifeng Zheng --- include/acpi/cppc_acpi.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index 4bcdcaf8bf2c..6573a759eb8d 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -119,8 +119,6 @@ struct cppc_perf_caps { u32 lowest_nonlinear_perf; u32 lowest_freq; u32 nominal_freq; - u32 energy_perf; - bool auto_sel; }; =20 struct cppc_perf_ctrls { @@ -128,6 +126,7 @@ struct cppc_perf_ctrls { u32 min_perf; u32 desired_perf; u32 energy_perf; + bool auto_sel; }; =20 struct cppc_perf_fb_ctrs { --=20 2.34.1 From nobody Sat Feb 7 19:08:29 2026 Received: from DM1PR04CU001.outbound.protection.outlook.com (mail-centralusazon11010062.outbound.protection.outlook.com [52.101.61.62]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58B6943D508; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 14:57:34.2470 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4b86da8a-cc99-48d7-e2fd-08de58343e86 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9DB.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7032 Content-Type: text/plain; charset="utf-8" Update EPP (Energy Performance Preference) constants for better clarity: - Add CPPC_EPP_PERFORMANCE_PREF (0x00) for performance preference - Rename CPPC_ENERGY_PERF_MAX to CPPC_EPP_ENERGY_EFFICIENCY_PREF (0xFF) for energy efficiency Signed-off-by: Sumit Gupta Reviewed-by: Lifeng Zheng --- drivers/acpi/cppc_acpi.c | 2 +- include/acpi/cppc_acpi.h | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 22d7fd669a6c..a09bdabaa804 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1615,7 +1615,7 @@ EXPORT_SYMBOL_GPL(cppc_set_epp_perf); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 14:57:31.5638 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: da2754a1-3adc-48c6-62ba-08de58343cf3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000149.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5920 Content-Type: text/plain; charset="utf-8" Add cppc_get_perf() function to read values of performance control registers including desired_perf, min_perf, max_perf, energy_perf, and auto_sel. This provides a read interface to complement the existing cppc_set_perf() write interface for performance control registers. Note that auto_sel is read by cppc_get_perf() but not written by cppc_set_perf() to avoid unintended mode changes during performance updates. It can be updated with existing dedicated cppc_set_auto_sel() API. Use cppc_get_perf() in cppc_cpufreq_get_cpu_data() to initialize perf_ctrls with current hardware register values during cpufreq policy initialization. Signed-off-by: Sumit Gupta --- drivers/acpi/cppc_acpi.c | 80 ++++++++++++++++++++++++++++++++++ drivers/cpufreq/cppc_cpufreq.c | 6 +++ include/acpi/cppc_acpi.h | 5 +++ 3 files changed, 91 insertions(+) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index a09bdabaa804..de35aeb07833 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1739,6 +1739,86 @@ int cppc_set_enable(int cpu, bool enable) } EXPORT_SYMBOL_GPL(cppc_set_enable); =20 +/** + * cppc_get_perf - Get a CPU's performance controls. + * @cpu: CPU for which to get performance controls. + * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h + * + * Return: 0 for success with perf_ctrls, -ERRNO otherwise. + */ +int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) +{ + struct cpc_desc *cpc_desc =3D per_cpu(cpc_desc_ptr, cpu); + struct cpc_register_resource *desired_perf_reg, + *min_perf_reg, *max_perf_reg, + *energy_perf_reg, *auto_sel_reg; + u64 desired_perf =3D 0, min =3D 0, max =3D 0, energy_perf =3D 0, auto_sel= =3D 0; + int pcc_ss_id =3D per_cpu(cpu_pcc_subspace_idx, cpu); + struct cppc_pcc_data *pcc_ss_data =3D NULL; + int ret =3D 0, regs_in_pcc =3D 0; + + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU:%d\n", cpu); + return -ENODEV; + } + + if (!perf_ctrls) { + pr_debug("Invalid perf_ctrls pointer\n"); + return -EINVAL; + } + + desired_perf_reg =3D &cpc_desc->cpc_regs[DESIRED_PERF]; + min_perf_reg =3D &cpc_desc->cpc_regs[MIN_PERF]; + max_perf_reg =3D &cpc_desc->cpc_regs[MAX_PERF]; + energy_perf_reg =3D &cpc_desc->cpc_regs[ENERGY_PERF]; + auto_sel_reg =3D &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; + + /* Are any of the regs PCC ?*/ + if (CPC_IN_PCC(desired_perf_reg) || CPC_IN_PCC(min_perf_reg) || + CPC_IN_PCC(max_perf_reg) || CPC_IN_PCC(energy_perf_reg) || + CPC_IN_PCC(auto_sel_reg)) { + if (pcc_ss_id < 0) { + pr_debug("Invalid pcc_ss_id for CPU:%d\n", cpu); + return -ENODEV; + } + pcc_ss_data =3D pcc_data[pcc_ss_id]; + regs_in_pcc =3D 1; + down_write(&pcc_ss_data->pcc_lock); + /* Ring doorbell once to update PCC subspace */ + if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) { + ret =3D -EIO; + goto out_err; + } + } + + /* Read optional elements if present */ + if (CPC_SUPPORTED(max_perf_reg)) + cpc_read(cpu, max_perf_reg, &max); + perf_ctrls->max_perf =3D max; + + if (CPC_SUPPORTED(min_perf_reg)) + cpc_read(cpu, min_perf_reg, &min); + perf_ctrls->min_perf =3D min; + + if (CPC_SUPPORTED(desired_perf_reg)) + cpc_read(cpu, desired_perf_reg, &desired_perf); + perf_ctrls->desired_perf =3D desired_perf; + + if (CPC_SUPPORTED(energy_perf_reg)) + cpc_read(cpu, energy_perf_reg, &energy_perf); + perf_ctrls->energy_perf =3D energy_perf; + + if (CPC_SUPPORTED(auto_sel_reg)) + cpc_read(cpu, auto_sel_reg, &auto_sel); + perf_ctrls->auto_sel =3D (bool)auto_sel; + +out_err: + if (regs_in_pcc) + up_write(&pcc_ss_data->pcc_lock); + return ret; +} +EXPORT_SYMBOL_GPL(cppc_get_perf); + /** * cppc_set_perf - Set a CPU's performance controls. * @cpu: CPU for which to set performance controls. diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index c95dcd7719c3..229880c4eedb 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -594,6 +594,12 @@ static struct cppc_cpudata *cppc_cpufreq_get_cpu_data(= unsigned int cpu) goto free_mask; } =20 + ret =3D cppc_get_perf(cpu, &cpu_data->perf_ctrls); + if (ret) { + pr_debug("Err reading CPU%d perf ctrls: ret:%d\n", cpu, ret); + goto free_mask; + } + return cpu_data; =20 free_mask: diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index 4d644f03098e..3fc796c0d902 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -151,6 +151,7 @@ extern int cppc_get_desired_perf(int cpunum, u64 *desir= ed_perf); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 14:57:50.0455 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a0321ad1-55a7-41d3-d8ae-08de583447f2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6483 Content-Type: text/plain; charset="utf-8" Extend cppc_set_epp_perf() to write both auto_sel and energy_perf registers when they are in FFH or SystemMemory address space. This keeps the behavior consistent with PCC case where both registers are already updated together, but was missing for FFH/SystemMemory. Signed-off-by: Sumit Gupta --- drivers/acpi/cppc_acpi.c | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index de35aeb07833..45c6bd6ec24b 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1562,6 +1562,8 @@ int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls= *perf_ctrls, bool enable) struct cpc_register_resource *auto_sel_reg; struct cpc_desc *cpc_desc =3D per_cpu(cpc_desc_ptr, cpu); struct cppc_pcc_data *pcc_ss_data =3D NULL; + bool autosel_ffh_sysmem; + bool epp_ffh_sysmem; int ret; =20 if (!cpc_desc) { @@ -1572,6 +1574,11 @@ int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrl= s *perf_ctrls, bool enable) auto_sel_reg =3D &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; epp_set_reg =3D &cpc_desc->cpc_regs[ENERGY_PERF]; =20 + epp_ffh_sysmem =3D CPC_SUPPORTED(epp_set_reg) && + (CPC_IN_FFH(epp_set_reg) || CPC_IN_SYSTEM_MEMORY(epp_set_reg)); + autosel_ffh_sysmem =3D CPC_SUPPORTED(auto_sel_reg) && + (CPC_IN_FFH(auto_sel_reg) || CPC_IN_SYSTEM_MEMORY(auto_sel_reg)); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 14:58:17.3087 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d0f5c705-cab0-43af-567c-08de58345832 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9DA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PPF9507C739C Content-Type: text/plain; charset="utf-8" Add cppc_get/set_min_perf() and cppc_get/set_max_perf() APIs to read and write the MIN_PERF and MAX_PERF registers. Also add sysfs interfaces (min_perf, max_perf) in cppc_cpufreq driver to expose these controls to userspace. The sysfs values are in frequency (kHz) for consistency with other cpufreq sysfs files. A mutex is used to serialize sysfs store operations to ensure hardware register writes and perf_ctrls updates are atomic. Signed-off-by: Sumit Gupta --- drivers/acpi/cppc_acpi.c | 44 +++++++++ drivers/cpufreq/cppc_cpufreq.c | 157 +++++++++++++++++++++++++++++++++ include/acpi/cppc_acpi.h | 20 +++++ 3 files changed, 221 insertions(+) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 45c6bd6ec24b..46bf45f8b0f3 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1743,6 +1743,50 @@ int cppc_set_auto_sel(int cpu, bool enable) } EXPORT_SYMBOL_GPL(cppc_set_auto_sel); =20 +/** + * cppc_get_min_perf - Read minimum performance register. + * @cpu: CPU from which to read register. + * @min_perf: Return address. + */ +int cppc_get_min_perf(int cpu, u64 *min_perf) +{ + return cppc_get_reg_val(cpu, MIN_PERF, min_perf); +} +EXPORT_SYMBOL_GPL(cppc_get_min_perf); + +/** + * cppc_set_min_perf - Write minimum performance register. + * @cpu: CPU to which to write register. + * @min_perf: the desired minimum performance value to be updated. + */ +int cppc_set_min_perf(int cpu, u32 min_perf) +{ + return cppc_set_reg_val(cpu, MIN_PERF, min_perf); +} +EXPORT_SYMBOL_GPL(cppc_set_min_perf); + +/** + * cppc_get_max_perf - Read maximum performance register. + * @cpu: CPU from which to read register. + * @max_perf: Return address. + */ +int cppc_get_max_perf(int cpu, u64 *max_perf) +{ + return cppc_get_reg_val(cpu, MAX_PERF, max_perf); +} +EXPORT_SYMBOL_GPL(cppc_get_max_perf); + +/** + * cppc_set_max_perf - Write maximum performance register. + * @cpu: CPU to which to write register. + * @max_perf: the desired maximum performance value to be updated. + */ +int cppc_set_max_perf(int cpu, u32 max_perf) +{ + return cppc_set_reg_val(cpu, MAX_PERF, max_perf); +} +EXPORT_SYMBOL_GPL(cppc_set_max_perf); + /** * cppc_set_enable - Set to enable CPPC on the processor by writing the * Continuous Performance Control package EnableRegister field. diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index 229880c4eedb..66e183b45fb0 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -28,6 +28,8 @@ =20 static struct cpufreq_driver cppc_cpufreq_driver; =20 +static DEFINE_MUTEX(cppc_cpufreq_autonomous_lock); + #ifdef CONFIG_ACPI_CPPC_CPUFREQ_FIE static enum { FIE_UNSET =3D -1, @@ -570,6 +572,35 @@ static void populate_efficiency_class(void) } #endif =20 +/* Set min/max performance HW register and cache the value */ +static int cppc_cpufreq_set_mperf_reg(struct cpufreq_policy *policy, + u64 val, bool is_min) +{ + struct cppc_cpudata *cpu_data =3D policy->driver_data; + struct cppc_perf_caps *caps =3D &cpu_data->perf_caps; + unsigned int cpu =3D policy->cpu; + u32 perf; + int ret; + + perf =3D clamp(val, caps->lowest_perf, caps->highest_perf); + + ret =3D is_min ? cppc_set_min_perf(cpu, perf) : + cppc_set_max_perf(cpu, perf); + if (ret) { + if (ret !=3D -EOPNOTSUPP) + pr_warn("CPU%d: set %s_perf=3D%u failed (%d)\n", + cpu, is_min ? "min" : "max", perf, ret); + return ret; + } + + if (is_min) + cpu_data->perf_ctrls.min_perf =3D perf; + else + cpu_data->perf_ctrls.max_perf =3D perf; + + return 0; +} + static struct cppc_cpudata *cppc_cpufreq_get_cpu_data(unsigned int cpu) { struct cppc_cpudata *cpu_data; @@ -918,16 +949,142 @@ CPPC_CPUFREQ_ATTR_RW_U64(auto_act_window, cppc_get_a= uto_act_window, CPPC_CPUFREQ_ATTR_RW_U64(energy_performance_preference_val, cppc_get_epp_perf, cppc_set_epp) =20 +/** + * show_min_perf - Show minimum performance as frequency (kHz) + * @policy: cpufreq policy + * @buf: buffer to write the frequency value to + * + * Reads the MIN_PERF register and converts the performance value to + * frequency (kHz). + */ +static ssize_t show_min_perf(struct cpufreq_policy *policy, char *buf) +{ + struct cppc_cpudata *cpu_data =3D policy->driver_data; + struct cppc_perf_caps *caps =3D &cpu_data->perf_caps; + u64 perf; + int ret; + + ret =3D cppc_get_min_perf(policy->cpu, &perf); + if (ret =3D=3D -EOPNOTSUPP) + return sysfs_emit(buf, "\n"); + if (ret) + return ret; + + /* Use lowest_perf if register is uninitialized (0) */ + if (perf =3D=3D 0) + perf =3D caps->lowest_perf; + + /* Convert performance to frequency (kHz) for user */ + return sysfs_emit(buf, "%u\n", cppc_perf_to_khz(caps, perf)); +} + +/** + * store_min_perf - Set minimum performance from frequency (kHz) + * @policy: cpufreq policy + * @buf: buffer containing the frequency value + * @count: size of @buf + * + * Converts the user-provided frequency (kHz) to a performance value + * and writes it to the MIN_PERF register. + */ +static ssize_t store_min_perf(struct cpufreq_policy *policy, const char *b= uf, + size_t count) +{ + struct cppc_cpudata *cpu_data =3D policy->driver_data; + unsigned int freq_khz; + u64 perf; + int ret; + + ret =3D kstrtouint(buf, 0, &freq_khz); + if (ret) + return ret; + + /* Convert frequency (kHz) to performance value */ + perf =3D cppc_khz_to_perf(&cpu_data->perf_caps, freq_khz); + + guard(mutex)(&cppc_cpufreq_autonomous_lock); + ret =3D cppc_cpufreq_set_mperf_reg(policy, perf, true); + if (ret) + return ret; + + return count; +} + +/** + * show_max_perf - Show maximum performance as frequency (kHz) + * @policy: cpufreq policy + * @buf: buffer to write the frequency value to + * + * Reads the MAX_PERF register and converts the performance value to + * frequency (kHz). + */ +static ssize_t show_max_perf(struct cpufreq_policy *policy, char *buf) +{ + struct cppc_cpudata *cpu_data =3D policy->driver_data; + struct cppc_perf_caps *caps =3D &cpu_data->perf_caps; + u64 perf; + int ret; + + ret =3D cppc_get_max_perf(policy->cpu, &perf); + if (ret =3D=3D -EOPNOTSUPP) + return sysfs_emit(buf, "\n"); + if (ret) + return ret; + + /* Use highest_perf if register is uninitialized or out of range */ + if (perf =3D=3D 0 || perf > caps->highest_perf) + perf =3D caps->highest_perf; + + /* Convert performance to frequency (kHz) for user */ + return sysfs_emit(buf, "%u\n", cppc_perf_to_khz(caps, perf)); +} + +/** + * store_max_perf - Set maximum performance from frequency (kHz) + * @policy: cpufreq policy + * @buf: buffer containing the frequency value + * @count: size of @buf + * + * Converts the user-provided frequency (kHz) to a performance value + * and writes it to the MAX_PERF register. + */ +static ssize_t store_max_perf(struct cpufreq_policy *policy, const char *b= uf, + size_t count) +{ + struct cppc_cpudata *cpu_data =3D policy->driver_data; + unsigned int freq_khz; + u64 perf; + int ret; + + ret =3D kstrtouint(buf, 0, &freq_khz); + if (ret) + return ret; + + /* Convert frequency (kHz) to performance value */ + perf =3D cppc_khz_to_perf(&cpu_data->perf_caps, freq_khz); + + guard(mutex)(&cppc_cpufreq_autonomous_lock); + ret =3D cppc_cpufreq_set_mperf_reg(policy, perf, false); + if (ret) + return ret; + + return count; +} + cpufreq_freq_attr_ro(freqdomain_cpus); cpufreq_freq_attr_rw(auto_select); cpufreq_freq_attr_rw(auto_act_window); cpufreq_freq_attr_rw(energy_performance_preference_val); +cpufreq_freq_attr_rw(min_perf); +cpufreq_freq_attr_rw(max_perf); =20 static struct freq_attr *cppc_cpufreq_attr[] =3D { &freqdomain_cpus, &auto_select, &auto_act_window, &energy_performance_preference_val, + &min_perf, + &max_perf, NULL, }; =20 diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index 3fc796c0d902..b358440cd0e2 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -174,6 +174,10 @@ extern int cppc_get_auto_act_window(int cpu, u64 *auto= _act_window); extern int cppc_set_auto_act_window(int cpu, u64 auto_act_window); extern int cppc_get_auto_sel(int cpu, bool *enable); extern int cppc_set_auto_sel(int cpu, bool enable); +extern int cppc_get_min_perf(int cpu, u64 *min_perf); +extern int cppc_set_min_perf(int cpu, u32 min_perf); +extern int cppc_get_max_perf(int cpu, u64 *max_perf); +extern int cppc_set_max_perf(int cpu, u32 max_perf); extern int amd_get_highest_perf(unsigned int cpu, u32 *highest_perf); extern int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator); extern int amd_detect_prefcore(bool *detected); @@ -270,6 +274,22 @@ static inline int cppc_set_auto_sel(int cpu, bool enab= le) { return -EOPNOTSUPP; } +static inline int cppc_get_min_perf(int cpu, u64 *min_perf) +{ + return -EOPNOTSUPP; +} +static inline int cppc_set_min_perf(int cpu, u32 min_perf) +{ + return -EOPNOTSUPP; +} +static inline int cppc_get_max_perf(int cpu, u64 *max_perf) +{ + return -EOPNOTSUPP; +} +static inline int cppc_set_max_perf(int cpu, u32 max_perf) +{ + return -EOPNOTSUPP; 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Tue, 20 Jan 2026 06:57:54 -0800 From: Sumit Gupta To: , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v6 7/9] ACPI: CPPC: add APIs and sysfs interface for perf_limited Date: Tue, 20 Jan 2026 20:26:21 +0530 Message-ID: <20260120145623.2959636-8-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260120145623.2959636-1-sumitg@nvidia.com> References: <20260120145623.2959636-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D6:EE_|DS0PR12MB8293:EE_ X-MS-Office365-Filtering-Correlation-Id: 3502bd1d-014b-4653-23c7-08de58345ff7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700013|1800799024|82310400026|921020; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 14:58:30.3440 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3502bd1d-014b-4653-23c7-08de58345ff7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8293 Content-Type: text/plain; charset="utf-8" Add sysfs interface to read/write the Performance Limited register. The Performance Limited register indicates to the OS that an unpredictable event (like thermal throttling) has limited processor performance. It contains two sticky bits set by the platform: - Bit 0 (Desired_Excursion): Set when delivered performance is constrained below desired performance. Not used when Autonomous Selection is enabled. - Bit 1 (Minimum_Excursion): Set when delivered performance is constrained below minimum performance. These bits remain set until OSPM explicitly clears them. The write operation accepts a bitmask of bits to clear: - Write 0x1 to clear bit 0 - Write 0x2 to clear bit 1 - Write 0x3 to clear both bits This enables users to detect if platform throttling impacted a workload. Users clear the register before execution, run the workload, then check afterward - if set, hardware throttling occurred during that time window. The interface is exposed as: /sys/devices/system/cpu/cpuX/cpufreq/perf_limited Signed-off-by: Sumit Gupta --- drivers/acpi/cppc_acpi.c | 56 ++++++++++++++++++++++++++++++++++ drivers/cpufreq/cppc_cpufreq.c | 5 +++ include/acpi/cppc_acpi.h | 15 +++++++++ 3 files changed, 76 insertions(+) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 46bf45f8b0f3..b46f22f58f56 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1787,6 +1787,62 @@ int cppc_set_max_perf(int cpu, u32 max_perf) } EXPORT_SYMBOL_GPL(cppc_set_max_perf); =20 +/** + * cppc_get_perf_limited - Get the Performance Limited register value. + * @cpu: CPU from which to get Performance Limited register. + * @perf_limited: Pointer to store the Performance Limited value. + * + * The returned value contains sticky status bits indicating platform-impo= sed + * performance limitations. + * + * Return: 0 for success, -EIO on failure, -EOPNOTSUPP if not supported. + */ +int cppc_get_perf_limited(int cpu, u64 *perf_limited) +{ + return cppc_get_reg_val(cpu, PERF_LIMITED, perf_limited); +} +EXPORT_SYMBOL_GPL(cppc_get_perf_limited); + +/** + * cppc_set_perf_limited() - Clear bits in the Performance Limited registe= r. + * @cpu: CPU on which to write register. + * @bits_to_clear: Bitmask of bits to clear in the perf_limited register. + * + * The Performance Limited register contains two sticky bits set by platfo= rm: + * - Bit 0 (Desired_Excursion): Set when delivered performance is constr= ained + * below desired performance. Not used when Autonomous Selection is en= abled. + * - Bit 1 (Minimum_Excursion): Set when delivered performance is constr= ained + * below minimum performance. + * + * These bits are sticky and remain set until OSPM explicitly clears them. + * This function only allows clearing bits (the platform sets them). + * + * Return: 0 for success, -EINVAL for invalid bits, -EIO on register + * access failure, -EOPNOTSUPP if not supported. + */ +int cppc_set_perf_limited(int cpu, u64 bits_to_clear) +{ + u64 current_val, new_val; + int ret; + + /* Only bits 0 and 1 are valid */ + if (bits_to_clear & ~CPPC_PERF_LIMITED_MASK) + return -EINVAL; + + if (!bits_to_clear) + return 0; + + ret =3D cppc_get_perf_limited(cpu, ¤t_val); + if (ret) + return ret; + + /* Clear the specified bits */ + new_val =3D current_val & ~bits_to_clear; + + return cppc_set_reg_val(cpu, PERF_LIMITED, new_val); +} +EXPORT_SYMBOL_GPL(cppc_set_perf_limited); + /** * cppc_set_enable - Set to enable CPPC on the processor by writing the * Continuous Performance Control package EnableRegister field. diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index 66e183b45fb0..afb2cdb67a2f 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -1071,12 +1071,16 @@ static ssize_t store_max_perf(struct cpufreq_policy= *policy, const char *buf, return count; } =20 +CPPC_CPUFREQ_ATTR_RW_U64(perf_limited, cppc_get_perf_limited, + cppc_set_perf_limited) + cpufreq_freq_attr_ro(freqdomain_cpus); cpufreq_freq_attr_rw(auto_select); cpufreq_freq_attr_rw(auto_act_window); cpufreq_freq_attr_rw(energy_performance_preference_val); cpufreq_freq_attr_rw(min_perf); cpufreq_freq_attr_rw(max_perf); +cpufreq_freq_attr_rw(perf_limited); =20 static struct freq_attr *cppc_cpufreq_attr[] =3D { &freqdomain_cpus, @@ -1085,6 +1089,7 @@ static struct freq_attr *cppc_cpufreq_attr[] =3D { &energy_performance_preference_val, &min_perf, &max_perf, + &perf_limited, NULL, }; =20 diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index b358440cd0e2..f3a04ccd10b7 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -42,6 +42,11 @@ #define CPPC_EPP_PERFORMANCE_PREF 0x00 #define CPPC_EPP_ENERGY_EFFICIENCY_PREF 0xFF =20 +#define CPPC_PERF_LIMITED_DESIRED_EXCURSION BIT(0) +#define CPPC_PERF_LIMITED_MINIMUM_EXCURSION BIT(1) +#define CPPC_PERF_LIMITED_MASK (CPPC_PERF_LIMITED_DESIRED_EXCURSION | \ + CPPC_PERF_LIMITED_MINIMUM_EXCURSION) + /* Each register has the folowing format. */ struct cpc_reg { u8 descriptor; @@ -178,6 +183,8 @@ extern int cppc_get_min_perf(int cpu, u64 *min_perf); extern int cppc_set_min_perf(int cpu, u32 min_perf); extern int cppc_get_max_perf(int cpu, u64 *max_perf); extern int cppc_set_max_perf(int cpu, u32 max_perf); +extern int cppc_get_perf_limited(int cpu, u64 *perf_limited); +extern int cppc_set_perf_limited(int cpu, u64 perf_limited); extern int amd_get_highest_perf(unsigned int cpu, u32 *highest_perf); extern int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator); extern int amd_detect_prefcore(bool *detected); @@ -290,6 +297,14 @@ static inline int cppc_set_max_perf(int cpu, u32 max_p= erf) { return -EOPNOTSUPP; } +static inline int cppc_get_perf_limited(int cpu, u64 *perf_limited) +{ + return -EOPNOTSUPP; +} +static inline int cppc_set_perf_limited(int cpu, u64 perf_limited) +{ + return -EOPNOTSUPP; +} static inline int amd_get_highest_perf(unsigned int cpu, u32 *highest_perf) { return -ENODEV; --=20 2.34.1 From nobody Sat Feb 7 19:08:29 2026 Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazon11013069.outbound.protection.outlook.com [40.107.201.69]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B46F64611FB; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 14:58:40.9369 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fbc32a74-ae09-4741-4d20-08de58346647 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8407 Content-Type: text/plain; charset="utf-8" Add sysfs interfaces for Minimum Performance, Maximum Performance and Performance Limited Register in the cppc_cpufreq driver. Reviewed-by: Randy Dunlap Signed-off-by: Sumit Gupta --- .../ABI/testing/sysfs-devices-system-cpu | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documenta= tion/ABI/testing/sysfs-devices-system-cpu index 3a05604c21bf..0b0c07c074bf 100644 --- a/Documentation/ABI/testing/sysfs-devices-system-cpu +++ b/Documentation/ABI/testing/sysfs-devices-system-cpu @@ -327,6 +327,50 @@ Description: Energy performance preference =20 This file is only present if the cppc-cpufreq driver is in use. =20 +What: /sys/devices/system/cpu/cpuX/cpufreq/min_perf +Date: February 2026 +Contact: linux-pm@vger.kernel.org +Description: Minimum Performance Frequency + + Read/write a frequency value in kHz from/to this file. This + file sets the minimum performance level (as frequency) at + which the platform may run. The frequency value is internally + converted to a performance value and must be in the range + [cpuinfo_min_freq, cpuinfo_max_freq], inclusive. + + This file is only present if the cppc-cpufreq driver is in use. + +What: /sys/devices/system/cpu/cpuX/cpufreq/max_perf +Date: February 2026 +Contact: linux-pm@vger.kernel.org +Description: Maximum Performance Frequency + + Read/write a frequency value in kHz from/to this file. This + file sets the maximum performance level (as frequency) at + which the platform may run. The frequency value is internally + converted to a performance value and must be in the range + [cpuinfo_min_freq, cpuinfo_max_freq], inclusive. + + This file is only present if the cppc-cpufreq driver is in use. + +What: /sys/devices/system/cpu/cpuX/cpufreq/perf_limited +Date: February 2026 +Contact: linux-pm@vger.kernel.org +Description: Performance Limited + + Read to check if platform throttling (thermal/power/current + limits) caused delivered performance to fall below the + requested level. A non-zero value indicates throttling occurred. + + Write the bitmask of bits to clear: + + - 0x1 =3D clear bit 0 (desired performance excursion) + - 0x2 =3D clear bit 1 (minimum performance excursion) + - 0x3 =3D clear both bits + + The platform sets these bits; OSPM can only clear them. + + This file is only present if the cppc-cpufreq driver is in use. =20 What: /sys/devices/system/cpu/cpu*/cache/index3/cache_disable_{0,1} Date: August 2008 --=20 2.34.1 From nobody Sat Feb 7 19:08:29 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013058.outbound.protection.outlook.com [40.93.201.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D87FD438FED; Tue, 20 Jan 2026 14:58:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.201.58 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 14:58:45.1568 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 71956172-93b4-428f-648e-08de583468c8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000014A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS5PPFB8FBD73EA Content-Type: text/plain; charset="utf-8" Update the cached perf_ctrls values when writing via sysfs to keep them in sync with hardware registers: - store_auto_select(): update perf_ctrls.auto_sel - store_energy_performance_preference_val(): update perf_ctrls.energy_perf Add mutex protection to these functions to ensure hardware register writes and cache updates are atomic. This ensures consistent cached values after sysfs writes, which complements the cppc_get_perf() initialization during policy setup. Signed-off-by: Sumit Gupta --- drivers/cpufreq/cppc_cpufreq.c | 35 ++++++++++++++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index afb2cdb67a2f..946fb93179d7 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -886,6 +886,7 @@ static ssize_t show_auto_select(struct cpufreq_policy *= policy, char *buf) static ssize_t store_auto_select(struct cpufreq_policy *policy, const char *buf, size_t count) { + struct cppc_cpudata *cpu_data =3D policy->driver_data; bool val; int ret; =20 @@ -893,10 +894,14 @@ static ssize_t store_auto_select(struct cpufreq_polic= y *policy, if (ret) return ret; =20 + guard(mutex)(&cppc_cpufreq_autonomous_lock); + ret =3D cppc_set_auto_sel(policy->cpu, val); if (ret) return ret; =20 + cpu_data->perf_ctrls.auto_sel =3D val; + return count; } =20 @@ -946,8 +951,34 @@ static ssize_t store_##_name(struct cpufreq_policy *po= licy, \ CPPC_CPUFREQ_ATTR_RW_U64(auto_act_window, cppc_get_auto_act_window, cppc_set_auto_act_window) =20 -CPPC_CPUFREQ_ATTR_RW_U64(energy_performance_preference_val, - cppc_get_epp_perf, cppc_set_epp) +static ssize_t +show_energy_performance_preference_val(struct cpufreq_policy *policy, char= *buf) +{ + return cppc_cpufreq_sysfs_show_u64(policy->cpu, cppc_get_epp_perf, buf); +} + +static ssize_t +store_energy_performance_preference_val(struct cpufreq_policy *policy, + const char *buf, size_t count) +{ + struct cppc_cpudata *cpu_data =3D policy->driver_data; + u64 val; + int ret; + + ret =3D kstrtou64(buf, 0, &val); + if (ret) + return ret; + + guard(mutex)(&cppc_cpufreq_autonomous_lock); + + ret =3D cppc_set_epp(policy->cpu, val); + if (ret) + return ret; + + cpu_data->perf_ctrls.energy_perf =3D val; + + return count; +} =20 /** * show_min_perf - Show minimum performance as frequency (kHz) --=20 2.34.1