From nobody Sat Feb 7 05:44:19 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A709C421F08; Tue, 20 Jan 2026 13:07:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768914457; cv=none; b=NfvLKzaICL5mbtqB02X3QMGmyoActrfnWSV9WpP2C1WMZl6aTQiGuMHUAF1/JMl3Gvqk1gBRBs7Aawt6lobTKHCFz9B+RU1NDfIS94fumjQqjsXIRwgxxA6i7tnWoRF0oRey2crQojygKZNDlnWsqzchFzJ02WpJmz0yelEhRwg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768914457; c=relaxed/simple; bh=BtM9/5m1xBxZS9vSPl1vQCMLAzqJOaif0KkuGXck9aM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PTj/Gtcwj4CpwbuJY2vIEiq44KUVmWI/VnAFHrga9E0v4QVjlZEYZQtu8oHASdCKIAfCDCqpKPUXcjsCKuZ/P9WS29WVqT0tGjYkJ88QjKhnxSZYFrWPcjh9/n8nxglOK5Ox4npIcNFOBOxPZ7/A+v9rq31yoq6cTGzOXfwAQVk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=HW2qGZo+; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="HW2qGZo+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768914455; x=1800450455; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BtM9/5m1xBxZS9vSPl1vQCMLAzqJOaif0KkuGXck9aM=; b=HW2qGZo+MM55L3a7/DkUltTqdUSzVt1IQJNiocnZmC8yIDYGXrGq9EiQ yJyxD4uR3wTlEEwRv/cGbleqkO6P8Yb8AOgm6ehNG9JNBoRk8BRyha9LU YQ0ikHgUttrOE/cAKdmzxnUXjV+mPj83+kwj5R5DriSiE4VB+1beSR5EH Y7uX+bfwn/WhvV5sLOJ4deolgd4bK1ng1aZX1MWNsMHSy6qLGTAb7mf0Z uE5xTGI5SjXpLQwBXnYe9zVlKEIPVBSwZ9oQbaUo4AGZEqAJxddNNU2EU lfIVymKbgq6xxqc2arNbczOZm9go/tsJ8vcO4OPHxmoJb4HDm0XJV2pNb Q==; X-CSE-ConnectionGUID: sxdTr3Y5SEqbZwbmtCMxSQ== X-CSE-MsgGUID: lx9RWfQGTlePycOVqdbvjw== X-IronPort-AV: E=McAfee;i="6800,10657,11676"; a="73748519" X-IronPort-AV: E=Sophos;i="6.21,240,1763452800"; d="scan'208";a="73748519" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2026 05:07:34 -0800 X-CSE-ConnectionGUID: SAesiFEjQqSGFrvrRWz8Kw== X-CSE-MsgGUID: xXh5M/FNRUiyeVUEKHmqwg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,240,1763452800"; d="scan'208";a="229053340" Received: from black.igk.intel.com ([10.91.253.5]) by fmviesa002.fm.intel.com with ESMTP; 20 Jan 2026 05:07:32 -0800 From: Heikki Krogerus To: Andi Shyti , Mika Westerberg Cc: Andy Shevchenko , Jan Dabros , Raag Jadav , linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/4] i2c: designware: Combine some of the common functions Date: Tue, 20 Jan 2026 14:07:25 +0100 Message-ID: <20260120130729.1679560-2-heikki.krogerus@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260120130729.1679560-1-heikki.krogerus@linux.intel.com> References: <20260120130729.1679560-1-heikki.krogerus@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The adapter can be registered just in the core instead of separately in the master and slave drivers. The same applies to the interrupt. The dedicated "target only" (slave only) configuration for this controller will be removed so that host mode (master mode) will always be supported together with the target mode. Therefore the descrption for the "target only" configuration that appears in the "name" sysfs attribute file is also dropped while at it. Signed-off-by: Heikki Krogerus Acked-by: Mika Westerberg --- drivers/i2c/busses/i2c-designware-common.c | 108 +++++++++++++++++++-- drivers/i2c/busses/i2c-designware-core.h | 11 ++- drivers/i2c/busses/i2c-designware-master.c | 97 +++--------------- drivers/i2c/busses/i2c-designware-slave.c | 53 ++-------- 4 files changed, 126 insertions(+), 143 deletions(-) diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busse= s/i2c-designware-common.c index 6671e98691ee..547ccf600b53 100644 --- a/drivers/i2c/busses/i2c-designware-common.c +++ b/drivers/i2c/busses/i2c-designware-common.c @@ -136,7 +136,7 @@ static int dw_reg_write_word(void *context, unsigned in= t reg, unsigned int val) * * Return: 0 on success, or negative errno otherwise. */ -int i2c_dw_init_regmap(struct dw_i2c_dev *dev) +static int i2c_dw_init_regmap(struct dw_i2c_dev *dev) { struct regmap_config map_cfg =3D { .reg_bits =3D 32, @@ -462,7 +462,7 @@ u32 i2c_dw_scl_lcnt(struct dw_i2c_dev *dev, unsigned in= t reg, u32 ic_clk, return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tLOW + tf), MICRO) - 1 + offs= et; } =20 -int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev) +static int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev) { unsigned int reg; int ret; @@ -679,7 +679,7 @@ int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev) return -EIO; } =20 -int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev) +static int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev) { u32 tx_fifo_depth, rx_fifo_depth; unsigned int param; @@ -748,19 +748,113 @@ void i2c_dw_disable(struct dw_i2c_dev *dev) } EXPORT_SYMBOL_GPL(i2c_dw_disable); =20 +static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) +{ + struct dw_i2c_dev *dev =3D dev_id; + + if (dev->mode =3D=3D DW_IC_SLAVE) + return i2c_dw_isr_slave(dev); + + return i2c_dw_isr_master(dev); +} + +static const struct i2c_algorithm i2c_dw_algo =3D { + .xfer =3D i2c_dw_xfer, + .functionality =3D i2c_dw_func, +#if IS_ENABLED(CONFIG_I2C_SLAVE) + .reg_slave =3D i2c_dw_reg_slave, + .unreg_slave =3D i2c_dw_unreg_slave, +#endif +}; + +static const struct i2c_adapter_quirks i2c_dw_quirks =3D { + .flags =3D I2C_AQ_NO_ZERO_LEN, +}; + int i2c_dw_probe(struct dw_i2c_dev *dev) { + struct i2c_adapter *adap =3D &dev->adapter; + unsigned long irq_flags; + int ret; + device_set_node(&dev->adapter.dev, dev_fwnode(dev->dev)); =20 + ret =3D i2c_dw_init_regmap(dev); + if (ret) + return ret; + + ret =3D i2c_dw_set_sda_hold(dev); + if (ret) + return ret; + + ret =3D i2c_dw_set_fifo_size(dev); + if (ret) + return ret; + switch (dev->mode) { case DW_IC_SLAVE: - return i2c_dw_probe_slave(dev); + ret =3D i2c_dw_probe_slave(dev); + break; case DW_IC_MASTER: - return i2c_dw_probe_master(dev); + ret =3D i2c_dw_probe_master(dev); + break; default: - dev_err(dev->dev, "Wrong operation mode: %d\n", dev->mode); - return -EINVAL; + ret =3D -EINVAL; + break; } + if (ret) + return ret; + + ret =3D dev->init(dev); + if (ret) + return ret; + + if (!adap->name[0]) + strscpy(adap->name, "Synopsys DesignWare I2C adapter"); + + adap->retries =3D 3; + adap->algo =3D &i2c_dw_algo; + adap->quirks =3D &i2c_dw_quirks; + adap->dev.parent =3D dev->dev; + i2c_set_adapdata(adap, dev); + + /* + * REVISIT: The mode check may not be necessary. + * For now keeping the flags as they were originally. + */ + if (dev->mode =3D=3D DW_IC_SLAVE) + irq_flags =3D IRQF_SHARED; + else if (dev->flags & ACCESS_NO_IRQ_SUSPEND) + irq_flags =3D IRQF_NO_SUSPEND; + else + irq_flags =3D IRQF_SHARED | IRQF_COND_SUSPEND; + + ret =3D i2c_dw_acquire_lock(dev); + if (ret) + return ret; + + __i2c_dw_write_intr_mask(dev, 0); + i2c_dw_release_lock(dev); + + if (!(dev->flags & ACCESS_POLLING)) { + ret =3D devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, + irq_flags, dev_name(dev->dev), dev); + if (ret) + return ret; + } + + /* + * Increment PM usage count during adapter registration in order to + * avoid possible spurious runtime suspend when adapter device is + * registered to the device core and immediate resume in case bus has + * registered I2C slaves that do I2C transfers in their probe. + */ + ACQUIRE(pm_runtime_noresume, pm)(dev->dev); + ret =3D ACQUIRE_ERR(pm_runtime_noresume, &pm); + if (ret) + return ret; + + return i2c_add_numbered_adapter(adap); } EXPORT_SYMBOL_GPL(i2c_dw_probe); =20 diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/= i2c-designware-core.h index ba7e307f0791..1fc16a2d5fc5 100644 --- a/drivers/i2c/busses/i2c-designware-core.h +++ b/drivers/i2c/busses/i2c-designware-core.h @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -345,20 +346,18 @@ struct i2c_dw_semaphore_callbacks { int (*probe)(struct dw_i2c_dev *dev); }; =20 -int i2c_dw_init_regmap(struct dw_i2c_dev *dev); u32 i2c_dw_scl_hcnt(struct dw_i2c_dev *dev, unsigned int reg, u32 ic_clk, u32 tSYMBOL, u32 tf, int offset); u32 i2c_dw_scl_lcnt(struct dw_i2c_dev *dev, unsigned int reg, u32 ic_clk, u32 tLOW, u32 tf, int offset); -int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev); u32 i2c_dw_clk_rate(struct dw_i2c_dev *dev); int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare); int i2c_dw_acquire_lock(struct dw_i2c_dev *dev); void i2c_dw_release_lock(struct dw_i2c_dev *dev); int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev); int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev); -int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev); u32 i2c_dw_func(struct i2c_adapter *adap); +irqreturn_t i2c_dw_isr_master(struct dw_i2c_dev *dev); =20 extern const struct dev_pm_ops i2c_dw_dev_pm_ops; =20 @@ -398,12 +397,18 @@ void i2c_dw_disable(struct dw_i2c_dev *dev); extern void i2c_dw_configure_master(struct dw_i2c_dev *dev); extern int i2c_dw_probe_master(struct dw_i2c_dev *dev); =20 +int i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num); + #if IS_ENABLED(CONFIG_I2C_SLAVE) extern void i2c_dw_configure_slave(struct dw_i2c_dev *dev); extern int i2c_dw_probe_slave(struct dw_i2c_dev *dev); +irqreturn_t i2c_dw_isr_slave(struct dw_i2c_dev *dev); +int i2c_dw_reg_slave(struct i2c_client *client); +int i2c_dw_unreg_slave(struct i2c_client *client); #else static inline void i2c_dw_configure_slave(struct dw_i2c_dev *dev) { } static inline int i2c_dw_probe_slave(struct dw_i2c_dev *dev) { return -EIN= VAL; } +static inline irqreturn_t i2c_dw_isr_slave(struct dw_i2c_dev *dev) { retur= n IRQ_NONE; } #endif =20 static inline void i2c_dw_configure(struct dw_i2c_dev *dev) diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busse= s/i2c-designware-master.c index 15b3a46f0132..91540a4520a3 100644 --- a/drivers/i2c/busses/i2c-designware-master.c +++ b/drivers/i2c/busses/i2c-designware-master.c @@ -191,10 +191,6 @@ static int i2c_dw_set_timings_master(struct dw_i2c_dev= *dev) dev->hs_hcnt, dev->hs_lcnt); } =20 - ret =3D i2c_dw_set_sda_hold(dev); - if (ret) - return ret; - dev_dbg(dev->dev, "Bus speed: %s\n", i2c_freq_mode_string(t->bus_freq_hz)= ); return 0; } @@ -353,9 +349,8 @@ static int i2c_dw_status(struct dw_i2c_dev *dev) * Initiate and continue master read/write transaction with polling * based transfer routine afterward write messages into the Tx buffer. */ -static int amd_i2c_dw_xfer_quirk(struct i2c_adapter *adap, struct i2c_msg = *msgs, int num_msgs) +static int amd_i2c_dw_xfer_quirk(struct dw_i2c_dev *dev, struct i2c_msg *m= sgs, int num_msgs) { - struct dw_i2c_dev *dev =3D i2c_get_adapdata(adap); int msg_wrt_idx, msg_itr_lmt, buf_len, data_idx; int cmd =3D 0, status; u8 *tx_buf; @@ -752,9 +747,8 @@ static void i2c_dw_process_transfer(struct dw_i2c_dev *= dev, unsigned int stat) * Interrupt service routine. This gets called whenever an I2C master inte= rrupt * occurs. */ -static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) +irqreturn_t i2c_dw_isr_master(struct dw_i2c_dev *dev) { - struct dw_i2c_dev *dev =3D dev_id; unsigned int stat, enabled; =20 regmap_read(dev->map, DW_IC_ENABLE, &enabled); @@ -815,9 +809,8 @@ static int i2c_dw_wait_transfer(struct dw_i2c_dev *dev) * Prepare controller for a transaction and call i2c_dw_xfer_msg. */ static int -i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) +i2c_dw_xfer_common(struct dw_i2c_dev *dev, struct i2c_msg msgs[], int num) { - struct dw_i2c_dev *dev =3D i2c_get_adapdata(adap); int ret; =20 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); @@ -908,19 +901,15 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg = msgs[], int num) return ret; } =20 -static const struct i2c_algorithm i2c_dw_algo =3D { - .xfer =3D i2c_dw_xfer, - .functionality =3D i2c_dw_func, -}; +int i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) +{ + struct dw_i2c_dev *dev =3D i2c_get_adapdata(adap); =20 -static const struct i2c_algorithm amd_i2c_dw_algo =3D { - .xfer =3D amd_i2c_dw_xfer_quirk, - .functionality =3D i2c_dw_func, -}; + if ((dev->flags & MODEL_MASK) =3D=3D MODEL_AMD_NAVI_GPU) + return amd_i2c_dw_xfer_quirk(dev, msgs, num); =20 -static const struct i2c_adapter_quirks i2c_dw_quirks =3D { - .flags =3D I2C_AQ_NO_ZERO_LEN, -}; + return i2c_dw_xfer_common(dev, msgs, num); +} =20 void i2c_dw_configure_master(struct dw_i2c_dev *dev) { @@ -1005,8 +994,6 @@ static int i2c_dw_init_recovery_info(struct dw_i2c_dev= *dev) =20 int i2c_dw_probe_master(struct dw_i2c_dev *dev) { - struct i2c_adapter *adap =3D &dev->adapter; - unsigned long irq_flags; unsigned int ic_con; int ret; =20 @@ -1014,18 +1001,10 @@ int i2c_dw_probe_master(struct dw_i2c_dev *dev) =20 dev->init =3D i2c_dw_init_master; =20 - ret =3D i2c_dw_init_regmap(dev); - if (ret) - return ret; - ret =3D i2c_dw_set_timings_master(dev); if (ret) return ret; =20 - ret =3D i2c_dw_set_fifo_size(dev); - if (ret) - return ret; - /* Lock the bus for accessing DW_IC_CON */ ret =3D i2c_dw_acquire_lock(dev); if (ret) @@ -1045,61 +1024,7 @@ int i2c_dw_probe_master(struct dw_i2c_dev *dev) if (ic_con & DW_IC_CON_BUS_CLEAR_CTRL) dev->master_cfg |=3D DW_IC_CON_BUS_CLEAR_CTRL; =20 - ret =3D dev->init(dev); - if (ret) - return ret; - - if (!adap->name[0]) - scnprintf(adap->name, sizeof(adap->name), - "Synopsys DesignWare I2C adapter"); - adap->retries =3D 3; - if ((dev->flags & MODEL_MASK) =3D=3D MODEL_AMD_NAVI_GPU) - adap->algo =3D &amd_i2c_dw_algo; - else - adap->algo =3D &i2c_dw_algo; - adap->quirks =3D &i2c_dw_quirks; - adap->dev.parent =3D dev->dev; - i2c_set_adapdata(adap, dev); - - if (dev->flags & ACCESS_NO_IRQ_SUSPEND) { - irq_flags =3D IRQF_NO_SUSPEND; - } else { - irq_flags =3D IRQF_SHARED | IRQF_COND_SUSPEND; - } - - ret =3D i2c_dw_acquire_lock(dev); - if (ret) - return ret; - - __i2c_dw_write_intr_mask(dev, 0); - i2c_dw_release_lock(dev); - - if (!(dev->flags & ACCESS_POLLING)) { - ret =3D devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, - irq_flags, dev_name(dev->dev), dev); - if (ret) - return dev_err_probe(dev->dev, ret, - "failure requesting irq %i: %d\n", - dev->irq, ret); - } - - ret =3D i2c_dw_init_recovery_info(dev); - if (ret) - return ret; - - /* - * Increment PM usage count during adapter registration in order to - * avoid possible spurious runtime suspend when adapter device is - * registered to the device core and immediate resume in case bus has - * registered I2C slaves that do I2C transfers in their probe. - */ - pm_runtime_get_noresume(dev->dev); - ret =3D i2c_add_numbered_adapter(adap); - if (ret) - dev_err(dev->dev, "failure adding adapter: %d\n", ret); - pm_runtime_put_noidle(dev->dev); - - return ret; + return i2c_dw_init_recovery_info(dev); } =20 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter"); diff --git a/drivers/i2c/busses/i2c-designware-slave.c b/drivers/i2c/busses= /i2c-designware-slave.c index 1995be79544d..c0baf53e97d8 100644 --- a/drivers/i2c/busses/i2c-designware-slave.c +++ b/drivers/i2c/busses/i2c-designware-slave.c @@ -63,7 +63,7 @@ static int i2c_dw_init_slave(struct dw_i2c_dev *dev) return 0; } =20 -static int i2c_dw_reg_slave(struct i2c_client *slave) +int i2c_dw_reg_slave(struct i2c_client *slave) { struct dw_i2c_dev *dev =3D i2c_get_adapdata(slave->adapter); =20 @@ -88,7 +88,7 @@ static int i2c_dw_reg_slave(struct i2c_client *slave) return 0; } =20 -static int i2c_dw_unreg_slave(struct i2c_client *slave) +int i2c_dw_unreg_slave(struct i2c_client *slave) { struct dw_i2c_dev *dev =3D i2c_get_adapdata(slave->adapter); =20 @@ -152,9 +152,8 @@ static u32 i2c_dw_read_clear_intrbits_slave(struct dw_i= 2c_dev *dev) * Interrupt service routine. This gets called whenever an I2C slave inter= rupt * occurs. */ -static irqreturn_t i2c_dw_isr_slave(int this_irq, void *dev_id) +irqreturn_t i2c_dw_isr_slave(struct dw_i2c_dev *dev) { - struct dw_i2c_dev *dev =3D dev_id; unsigned int raw_stat, stat, enabled, tmp; u8 val =3D 0, slave_activity; =20 @@ -217,12 +216,6 @@ static irqreturn_t i2c_dw_isr_slave(int this_irq, void= *dev_id) return IRQ_HANDLED; } =20 -static const struct i2c_algorithm i2c_dw_algo =3D { - .functionality =3D i2c_dw_func, - .reg_slave =3D i2c_dw_reg_slave, - .unreg_slave =3D i2c_dw_unreg_slave, -}; - void i2c_dw_configure_slave(struct dw_i2c_dev *dev) { dev->functionality =3D I2C_FUNC_SLAVE; @@ -236,46 +229,12 @@ EXPORT_SYMBOL_GPL(i2c_dw_configure_slave); =20 int i2c_dw_probe_slave(struct dw_i2c_dev *dev) { - struct i2c_adapter *adap =3D &dev->adapter; - int ret; + if (dev->flags & ACCESS_POLLING) + return -EOPNOTSUPP; =20 dev->init =3D i2c_dw_init_slave; =20 - ret =3D i2c_dw_init_regmap(dev); - if (ret) - return ret; - - ret =3D i2c_dw_set_sda_hold(dev); - if (ret) - return ret; - - ret =3D i2c_dw_set_fifo_size(dev); - if (ret) - return ret; - - ret =3D dev->init(dev); - if (ret) - return ret; - - snprintf(adap->name, sizeof(adap->name), - "Synopsys DesignWare I2C Slave adapter"); - adap->retries =3D 3; - adap->algo =3D &i2c_dw_algo; - adap->dev.parent =3D dev->dev; - i2c_set_adapdata(adap, dev); - - ret =3D devm_request_irq(dev->dev, dev->irq, i2c_dw_isr_slave, - IRQF_SHARED, dev_name(dev->dev), dev); - if (ret) - return dev_err_probe(dev->dev, ret, - "failure requesting IRQ %i: %d\n", - dev->irq, ret); - - ret =3D i2c_add_numbered_adapter(adap); - if (ret) - dev_err(dev->dev, "failure adding adapter: %d\n", ret); - - return ret; + return 0; } =20 MODULE_AUTHOR("Luis Oliveira "); --=20 2.50.1 From nobody Sat Feb 7 05:44:19 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63AC63D3015; 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X-CSE-ConnectionGUID: ZR1zLKGmSz+vrTQPUZav9A== X-CSE-MsgGUID: jpUs/zb5SJq6C4f44+v/8w== X-IronPort-AV: E=McAfee;i="6800,10657,11676"; a="73748524" X-IronPort-AV: E=Sophos;i="6.21,240,1763452800"; d="scan'208";a="73748524" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2026 05:07:36 -0800 X-CSE-ConnectionGUID: f5DdkXNWSpKRleKgaPbHCw== X-CSE-MsgGUID: QLQloiJ4Qs+DPknrmErggg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,240,1763452800"; d="scan'208";a="229053346" Received: from black.igk.intel.com ([10.91.253.5]) by fmviesa002.fm.intel.com with ESMTP; 20 Jan 2026 05:07:34 -0800 From: Heikki Krogerus To: Andi Shyti , Mika Westerberg Cc: Andy Shevchenko , Jan Dabros , Raag Jadav , linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/4] i2c: designware: Combine the init functions Date: Tue, 20 Jan 2026 14:07:26 +0100 Message-ID: <20260120130729.1679560-3-heikki.krogerus@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260120130729.1679560-1-heikki.krogerus@linux.intel.com> References: <20260120130729.1679560-1-heikki.krogerus@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Providing a single function for controller initialisation. The controller initialisation has the same steps for master and slave modes, except the timing parameters are only needed in master mode. Signed-off-by: Heikki Krogerus Acked-by: Mika Westerberg Reviewed-by: Andy Shevchenko --- drivers/i2c/busses/i2c-designware-amdisp.c | 4 +- drivers/i2c/busses/i2c-designware-common.c | 81 +++++++++++++++++++++- drivers/i2c/busses/i2c-designware-core.h | 3 +- drivers/i2c/busses/i2c-designware-master.c | 70 +------------------ drivers/i2c/busses/i2c-designware-slave.c | 44 ------------ 5 files changed, 85 insertions(+), 117 deletions(-) diff --git a/drivers/i2c/busses/i2c-designware-amdisp.c b/drivers/i2c/busse= s/i2c-designware-amdisp.c index 450793d5f839..ec9259dd2a4f 100644 --- a/drivers/i2c/busses/i2c-designware-amdisp.c +++ b/drivers/i2c/busses/i2c-designware-amdisp.c @@ -163,8 +163,8 @@ static int amd_isp_dw_i2c_plat_runtime_resume(struct de= vice *dev) =20 if (!i_dev->shared_with_punit) i2c_dw_prepare_clk(i_dev, true); - if (i_dev->init) - i_dev->init(i_dev); + + i2c_dw_init(i_dev); =20 return 0; } diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busse= s/i2c-designware-common.c index 547ccf600b53..4668898b031d 100644 --- a/drivers/i2c/busses/i2c-designware-common.c +++ b/drivers/i2c/busses/i2c-designware-common.c @@ -363,6 +363,83 @@ static inline u32 i2c_dw_acpi_round_bus_speed(struct d= evice *device) { return 0; =20 #endif /* CONFIG_ACPI */ =20 +static void i2c_dw_configure_mode(struct dw_i2c_dev *dev) +{ + switch (dev->mode) { + case DW_IC_MASTER: + regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2); + regmap_write(dev->map, DW_IC_RX_TL, 0); + regmap_write(dev->map, DW_IC_CON, dev->master_cfg); + break; + case DW_IC_SLAVE: + regmap_write(dev->map, DW_IC_TX_TL, 0); + regmap_write(dev->map, DW_IC_RX_TL, 0); + regmap_write(dev->map, DW_IC_CON, dev->slave_cfg); + regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_SLAVE_MASK); + break; + default: + return; + } +} + +static void i2c_dw_write_timings(struct dw_i2c_dev *dev) +{ + /* Write standard speed timing parameters */ + regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt); + regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt); + + /* Write fast mode/fast mode plus timing parameters */ + regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt); + regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt); + + /* Write high speed timing parameters if supported */ + if (dev->hs_hcnt && dev->hs_lcnt) { + regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt); + regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt); + } +} + +/** + * i2c_dw_init() - Initialize the DesignWare I2C hardware + * @dev: device private data + * + * This functions configures and enables the DesigWare I2C hardware. + * + * Return: 0 on success, or negative errno otherwise. + */ +int i2c_dw_init(struct dw_i2c_dev *dev) +{ + int ret; + + ret =3D i2c_dw_acquire_lock(dev); + if (ret) + return ret; + + /* Disable the adapter */ + __i2c_dw_disable(dev); + + /* + * Mask SMBus interrupts to block storms from broken + * firmware that leaves IC_SMBUS=3D1; the handler never + * services them. + */ + regmap_write(dev->map, DW_IC_SMBUS_INTR_MASK, 0); + + if (dev->mode =3D=3D DW_IC_MASTER) + i2c_dw_write_timings(dev); + + /* Write SDA hold time if supported */ + if (dev->sda_hold_time) + regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time); + + i2c_dw_configure_mode(dev); + + i2c_dw_release_lock(dev); + + return 0; +} +EXPORT_SYMBOL_GPL(i2c_dw_init); + static void i2c_dw_adjust_bus_speed(struct dw_i2c_dev *dev) { u32 acpi_speed =3D i2c_dw_acpi_round_bus_speed(dev->dev); @@ -805,7 +882,7 @@ int i2c_dw_probe(struct dw_i2c_dev *dev) if (ret) return ret; =20 - ret =3D dev->init(dev); + ret =3D i2c_dw_init(dev); if (ret) return ret; =20 @@ -898,7 +975,7 @@ static int i2c_dw_runtime_resume(struct device *device) if (!dev->shared_with_punit) i2c_dw_prepare_clk(dev, true); =20 - dev->init(dev); + i2c_dw_init(dev); =20 return 0; } diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/= i2c-designware-core.h index 1fc16a2d5fc5..a831595b199c 100644 --- a/drivers/i2c/busses/i2c-designware-core.h +++ b/drivers/i2c/busses/i2c-designware-core.h @@ -253,7 +253,6 @@ struct reset_control; * @semaphore_idx: Index of table with semaphore type attached to the bus.= It's * -1 if there is no semaphore. * @shared_with_punit: true if this bus is shared with the SoC's PUNIT - * @init: function to initialize the I2C hardware * @set_sda_hold_time: callback to retrieve IP specific SDA hold timing * @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE * @rinfo: I=C2=B2C GPIO recovery information @@ -314,7 +313,6 @@ struct dw_i2c_dev { void (*release_lock)(void); int semaphore_idx; bool shared_with_punit; - int (*init)(struct dw_i2c_dev *dev); int (*set_sda_hold_time)(struct dw_i2c_dev *dev); int mode; struct i2c_bus_recovery_info rinfo; @@ -420,6 +418,7 @@ static inline void i2c_dw_configure(struct dw_i2c_dev *= dev) } =20 int i2c_dw_probe(struct dw_i2c_dev *dev); +int i2c_dw_init(struct dw_i2c_dev *dev); =20 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL) int i2c_dw_baytrail_probe_lock_support(struct dw_i2c_dev *dev); diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busse= s/i2c-designware-master.c index 91540a4520a3..33432bbaec1f 100644 --- a/drivers/i2c/busses/i2c-designware-master.c +++ b/drivers/i2c/busses/i2c-designware-master.c @@ -31,16 +31,6 @@ #define AMD_TIMEOUT_MAX_US 250 #define AMD_MASTERCFG_MASK GENMASK(15, 0) =20 -static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev) -{ - /* Configure Tx/Rx FIFO threshold levels */ - regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2); - regmap_write(dev->map, DW_IC_RX_TL, 0); - - /* Configure the I2C master */ - regmap_write(dev->map, DW_IC_CON, dev->master_cfg); -} - static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev) { unsigned int comp_param1; @@ -195,58 +185,6 @@ static int i2c_dw_set_timings_master(struct dw_i2c_dev= *dev) return 0; } =20 -/** - * i2c_dw_init_master() - Initialize the DesignWare I2C master hardware - * @dev: device private data - * - * This functions configures and enables the I2C master. - * This function is called during I2C init function, and in case of timeou= t at - * run time. - * - * Return: 0 on success, or negative errno otherwise. - */ -static int i2c_dw_init_master(struct dw_i2c_dev *dev) -{ - int ret; - - ret =3D i2c_dw_acquire_lock(dev); - if (ret) - return ret; - - /* Disable the adapter */ - __i2c_dw_disable(dev); - - /* - * Mask SMBus interrupts to block storms from broken - * firmware that leaves IC_SMBUS=3D1; the handler never - * services them. - */ - regmap_write(dev->map, DW_IC_SMBUS_INTR_MASK, 0); - - /* Write standard speed timing parameters */ - regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt); - regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt); - - /* Write fast mode/fast mode plus timing parameters */ - regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt); - regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt); - - /* Write high speed timing parameters if supported */ - if (dev->hs_hcnt && dev->hs_lcnt) { - regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt); - regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt); - } - - /* Write SDA hold time if supported */ - if (dev->sda_hold_time) - regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time); - - i2c_dw_configure_fifo_master(dev); - i2c_dw_release_lock(dev); - - return 0; -} - static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) { struct i2c_msg *msgs =3D dev->msgs; @@ -843,9 +781,9 @@ i2c_dw_xfer_common(struct dw_i2c_dev *dev, struct i2c_m= sg msgs[], int num) ret =3D i2c_dw_wait_transfer(dev); if (ret) { dev_err(dev->dev, "controller timed out\n"); - /* i2c_dw_init_master() implicitly disables the adapter */ + /* i2c_dw_init() implicitly disables the adapter */ i2c_recover_bus(&dev->adapter); - i2c_dw_init_master(dev); + i2c_dw_init(dev); goto done; } =20 @@ -950,7 +888,7 @@ static void i2c_dw_unprepare_recovery(struct i2c_adapte= r *adap) =20 i2c_dw_prepare_clk(dev, true); reset_control_deassert(dev->rst); - i2c_dw_init_master(dev); + i2c_dw_init(dev); } =20 static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev) @@ -999,8 +937,6 @@ int i2c_dw_probe_master(struct dw_i2c_dev *dev) =20 init_completion(&dev->cmd_complete); =20 - dev->init =3D i2c_dw_init_master; - ret =3D i2c_dw_set_timings_master(dev); if (ret) return ret; diff --git a/drivers/i2c/busses/i2c-designware-slave.c b/drivers/i2c/busses= /i2c-designware-slave.c index c0baf53e97d8..9fc8faa33735 100644 --- a/drivers/i2c/busses/i2c-designware-slave.c +++ b/drivers/i2c/busses/i2c-designware-slave.c @@ -21,48 +21,6 @@ =20 #include "i2c-designware-core.h" =20 -static void i2c_dw_configure_fifo_slave(struct dw_i2c_dev *dev) -{ - /* Configure Tx/Rx FIFO threshold levels. */ - regmap_write(dev->map, DW_IC_TX_TL, 0); - regmap_write(dev->map, DW_IC_RX_TL, 0); - - /* Configure the I2C slave. */ - regmap_write(dev->map, DW_IC_CON, dev->slave_cfg); - regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_SLAVE_MASK); -} - -/** - * i2c_dw_init_slave() - Initialize the DesignWare i2c slave hardware - * @dev: device private data - * - * This function configures and enables the I2C in slave mode. - * This function is called during I2C init function, and in case of timeou= t at - * run time. - * - * Return: 0 on success, or negative errno otherwise. - */ -static int i2c_dw_init_slave(struct dw_i2c_dev *dev) -{ - int ret; - - ret =3D i2c_dw_acquire_lock(dev); - if (ret) - return ret; - - /* Disable the adapter. */ - __i2c_dw_disable(dev); - - /* Write SDA hold time if supported */ - if (dev->sda_hold_time) - regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time); - - i2c_dw_configure_fifo_slave(dev); - i2c_dw_release_lock(dev); - - return 0; -} - int i2c_dw_reg_slave(struct i2c_client *slave) { struct dw_i2c_dev *dev =3D i2c_get_adapdata(slave->adapter); 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20 Jan 2026 05:07:36 -0800 From: Heikki Krogerus To: Andi Shyti , Mika Westerberg Cc: Andy Shevchenko , Jan Dabros , Raag Jadav , linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/4] i2c: designware: Enable mode swapping Date: Tue, 20 Jan 2026 14:07:27 +0100 Message-ID: <20260120130729.1679560-4-heikki.krogerus@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260120130729.1679560-1-heikki.krogerus@linux.intel.com> References: <20260120130729.1679560-1-heikki.krogerus@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The DesignWare I2C can not be operated as I2C master and I2C slave simultaneously, but that does not actually mean master and slave modes can not be supported at the same time. It just means an explicit mode swap needs to be executed when the mode is changed. The DesignWare I2C documentation actually describes a couple of cases where the mode is excepted to be changed. The I2C master will now always be supported. Both modes are now always configured in i2c_dw_configure(), but the slave mode will continue to be available only when the Kconfig option I2C_SLAVE is enabled. The driver will now start in master mode and then swap to slave mode when a slave device is registered. After a slave device is registered, the controller is swapped to master mode when a transfer in master mode is started and then back to slave mode again after the transfer is completed. The DesignWare I2C can now be used with protocols such as MCTP (drivers/net/mctp/mctp-i2c.c) and IPMI (drivers/char/ipmi/) that require support for both I2C master and I2C slave. It is now also possible to support the SMBus Host Notification Protocol as I2C master if needed. Signed-off-by: Heikki Krogerus Acked-by: Mika Westerberg --- drivers/i2c/busses/i2c-designware-common.c | 50 +++++++++++++++------- drivers/i2c/busses/i2c-designware-core.h | 9 ++-- drivers/i2c/busses/i2c-designware-master.c | 6 ++- drivers/i2c/busses/i2c-designware-slave.c | 35 +++++++-------- 4 files changed, 57 insertions(+), 43 deletions(-) diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busse= s/i2c-designware-common.c index 4668898b031d..1a934283f650 100644 --- a/drivers/i2c/busses/i2c-designware-common.c +++ b/drivers/i2c/busses/i2c-designware-common.c @@ -363,21 +363,25 @@ static inline u32 i2c_dw_acpi_round_bus_speed(struct = device *device) { return 0; =20 #endif /* CONFIG_ACPI */ =20 -static void i2c_dw_configure_mode(struct dw_i2c_dev *dev) +static void i2c_dw_configure_mode(struct dw_i2c_dev *dev, int mode) { - switch (dev->mode) { + switch (mode) { case DW_IC_MASTER: regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2); regmap_write(dev->map, DW_IC_RX_TL, 0); regmap_write(dev->map, DW_IC_CON, dev->master_cfg); break; case DW_IC_SLAVE: + dev->status =3D 0; regmap_write(dev->map, DW_IC_TX_TL, 0); regmap_write(dev->map, DW_IC_RX_TL, 0); regmap_write(dev->map, DW_IC_CON, dev->slave_cfg); + regmap_write(dev->map, DW_IC_SAR, dev->slave->addr); regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_SLAVE_MASK); + __i2c_dw_enable(dev); break; default: + WARN(1, "Invalid mode %d\n", mode); return; } } @@ -399,6 +403,31 @@ static void i2c_dw_write_timings(struct dw_i2c_dev *de= v) } } =20 +/** + * i2c_dw_set_mode() - Select the controller mode of operation - master or= slave + * @dev: device private data + * @mode: I2C mode of operation + * + * Configures the controller to operate in @mode. This function needs to be + * called when ever a mode swap is required. + * + * Setting the slave mode does not have an effect before a slave device is + * registered. So before the slave device is registered, the controller is= kept + * in master mode regardless of @mode. + * + * The controller must be disabled before this function is called. + */ +void i2c_dw_set_mode(struct dw_i2c_dev *dev, int mode) +{ + if (mode =3D=3D DW_IC_SLAVE && !dev->slave) + mode =3D DW_IC_MASTER; + if (dev->mode =3D=3D mode) + return; + + i2c_dw_configure_mode(dev, mode); + dev->mode =3D mode; +} + /** * i2c_dw_init() - Initialize the DesignWare I2C hardware * @dev: device private data @@ -425,14 +454,13 @@ int i2c_dw_init(struct dw_i2c_dev *dev) */ regmap_write(dev->map, DW_IC_SMBUS_INTR_MASK, 0); =20 - if (dev->mode =3D=3D DW_IC_MASTER) - i2c_dw_write_timings(dev); + i2c_dw_write_timings(dev); =20 /* Write SDA hold time if supported */ if (dev->sda_hold_time) regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time); =20 - i2c_dw_configure_mode(dev); + i2c_dw_configure_mode(dev, dev->mode); =20 i2c_dw_release_lock(dev); =20 @@ -868,17 +896,7 @@ int i2c_dw_probe(struct dw_i2c_dev *dev) if (ret) return ret; =20 - switch (dev->mode) { - case DW_IC_SLAVE: - ret =3D i2c_dw_probe_slave(dev); - break; - case DW_IC_MASTER: - ret =3D i2c_dw_probe_master(dev); - break; - default: - ret =3D -EINVAL; - break; - } + ret =3D i2c_dw_probe_master(dev); if (ret) return ret; =20 diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/= i2c-designware-core.h index a831595b199c..853a8a4ed2c1 100644 --- a/drivers/i2c/busses/i2c-designware-core.h +++ b/drivers/i2c/busses/i2c-designware-core.h @@ -399,26 +399,23 @@ int i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_= msg *msgs, int num); =20 #if IS_ENABLED(CONFIG_I2C_SLAVE) extern void i2c_dw_configure_slave(struct dw_i2c_dev *dev); -extern int i2c_dw_probe_slave(struct dw_i2c_dev *dev); irqreturn_t i2c_dw_isr_slave(struct dw_i2c_dev *dev); int i2c_dw_reg_slave(struct i2c_client *client); int i2c_dw_unreg_slave(struct i2c_client *client); #else static inline void i2c_dw_configure_slave(struct dw_i2c_dev *dev) { } -static inline int i2c_dw_probe_slave(struct dw_i2c_dev *dev) { return -EIN= VAL; } static inline irqreturn_t i2c_dw_isr_slave(struct dw_i2c_dev *dev) { retur= n IRQ_NONE; } #endif =20 static inline void i2c_dw_configure(struct dw_i2c_dev *dev) { - if (i2c_detect_slave_mode(dev->dev)) - i2c_dw_configure_slave(dev); - else - i2c_dw_configure_master(dev); + i2c_dw_configure_slave(dev); + i2c_dw_configure_master(dev); } =20 int i2c_dw_probe(struct dw_i2c_dev *dev); int i2c_dw_init(struct dw_i2c_dev *dev); +void i2c_dw_set_mode(struct dw_i2c_dev *dev, int mode); =20 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL) int i2c_dw_baytrail_probe_lock_support(struct dw_i2c_dev *dev); diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busse= s/i2c-designware-master.c index 33432bbaec1f..ba2ee526ecc6 100644 --- a/drivers/i2c/busses/i2c-designware-master.c +++ b/drivers/i2c/busses/i2c-designware-master.c @@ -194,6 +194,8 @@ static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) /* Disable the adapter */ __i2c_dw_disable(dev); =20 + i2c_dw_set_mode(dev, DW_IC_MASTER); + /* If the slave address is ten bit address, enable 10BITADDR */ if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) { ic_con =3D DW_IC_CON_10BITADDR_MASTER; @@ -831,6 +833,8 @@ i2c_dw_xfer_common(struct dw_i2c_dev *dev, struct i2c_m= sg msgs[], int num) ret =3D -EIO; =20 done: + i2c_dw_set_mode(dev, DW_IC_SLAVE); + i2c_dw_release_lock(dev); =20 done_nolock: @@ -853,7 +857,7 @@ void i2c_dw_configure_master(struct dw_i2c_dev *dev) { struct i2c_timings *t =3D &dev->timings; =20 - dev->functionality =3D I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY; + dev->functionality |=3D I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY; =20 dev->master_cfg =3D DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | DW_IC_CON_RESTART_EN; diff --git a/drivers/i2c/busses/i2c-designware-slave.c b/drivers/i2c/busses= /i2c-designware-slave.c index 9fc8faa33735..ad0d5fbfa6d5 100644 --- a/drivers/i2c/busses/i2c-designware-slave.c +++ b/drivers/i2c/busses/i2c-designware-slave.c @@ -24,24 +24,25 @@ int i2c_dw_reg_slave(struct i2c_client *slave) { struct dw_i2c_dev *dev =3D i2c_get_adapdata(slave->adapter); + int ret; =20 + if (!i2c_check_functionality(slave->adapter, I2C_FUNC_SLAVE)) + return -EOPNOTSUPP; if (dev->slave) return -EBUSY; if (slave->flags & I2C_CLIENT_TEN) return -EAFNOSUPPORT; - pm_runtime_get_sync(dev->dev); =20 - /* - * Set slave address in the IC_SAR register, - * the address to which the DW_apb_i2c responds. - */ + ret =3D i2c_dw_acquire_lock(dev); + if (ret) + return ret; + + pm_runtime_get_sync(dev->dev); __i2c_dw_disable_nowait(dev); - regmap_write(dev->map, DW_IC_SAR, slave->addr); dev->slave =3D slave; + i2c_dw_set_mode(dev, DW_IC_SLAVE); =20 - __i2c_dw_enable(dev); - - dev->status =3D 0; + i2c_dw_release_lock(dev); =20 return 0; } @@ -54,6 +55,7 @@ int i2c_dw_unreg_slave(struct i2c_client *slave) i2c_dw_disable(dev); synchronize_irq(dev->irq); dev->slave =3D NULL; + i2c_dw_set_mode(dev, DW_IC_MASTER); pm_runtime_put_sync_suspend(dev->dev); =20 return 0; @@ -176,23 +178,16 @@ irqreturn_t i2c_dw_isr_slave(struct dw_i2c_dev *dev) =20 void i2c_dw_configure_slave(struct dw_i2c_dev *dev) { - dev->functionality =3D I2C_FUNC_SLAVE; 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d="scan'208";a="73748534" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2026 05:07:40 -0800 X-CSE-ConnectionGUID: gVbkaxPiT9m/CpesJZyJJg== X-CSE-MsgGUID: +wK6q3rVSmeXMvkoC4f6Cg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,240,1763452800"; d="scan'208";a="229053360" Received: from black.igk.intel.com ([10.91.253.5]) by fmviesa002.fm.intel.com with ESMTP; 20 Jan 2026 05:07:38 -0800 From: Heikki Krogerus To: Andi Shyti , Mika Westerberg Cc: Andy Shevchenko , Jan Dabros , Raag Jadav , linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 4/4] i2c: designware: Remove an unnecessary condition Date: Tue, 20 Jan 2026 14:07:28 +0100 Message-ID: <20260120130729.1679560-5-heikki.krogerus@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260120130729.1679560-1-heikki.krogerus@linux.intel.com> References: <20260120130729.1679560-1-heikki.krogerus@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Writing also the high speed timing registers unconditionally. The reset value for these registers is 0, so this should always be safe. Suggested-by: Andy Shevchenko Signed-off-by: Heikki Krogerus Acked-by: Mika Westerberg Reviewed-by: Andy Shevchenko --- drivers/i2c/busses/i2c-designware-common.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busse= s/i2c-designware-common.c index 1a934283f650..3d78abd0e965 100644 --- a/drivers/i2c/busses/i2c-designware-common.c +++ b/drivers/i2c/busses/i2c-designware-common.c @@ -396,11 +396,9 @@ static void i2c_dw_write_timings(struct dw_i2c_dev *de= v) regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt); regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt); =20 - /* Write high speed timing parameters if supported */ - if (dev->hs_hcnt && dev->hs_lcnt) { - regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt); - regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt); - } + /* Write high speed timing parameters */ + regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt); + regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt); } =20 /** --=20 2.50.1