From nobody Tue Feb 10 01:15:19 2026 Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D32C3D6670 for ; Tue, 20 Jan 2026 12:52:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768913568; cv=none; b=W7imnmKNbc52Cbjy8NkCtdqJKa+ukmJa6TW8iL7UH1ChWClzmWGqoSkjdKMjSc5O1Oye4tFQIPhapo9w1zjPbsEnQOXYP/MjxB/61hf6gNSDpMzdMz6weGqwBMMv5IrCVwfXqwJTib7sWUwwKG1Gev038dJqyprRgQS6j0/J8dA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768913568; c=relaxed/simple; bh=Nfa8i3hFAJR4fbsq8fVd9XYjNY9cNE+DUlltjZDFInQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UUWmcnB9aLMD+1hYe9ZOlZYCLhtyLqgnuNdvyIfdbKtTQs3EyRd0GlZxBPXK5aWwO/hZqsmBm8hHc2TKwT2GZhGzGyIL9ZG6NLZotw84cX5aVyDJDu5xFdqZInYZClQx1OAaRo/TF+hIJsbEe8TxcdbVXB0qMFJNajEtKJifIz8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=kokrqn4l; arc=none smtp.client-ip=209.85.218.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="kokrqn4l" Received: by mail-ej1-f46.google.com with SMTP id a640c23a62f3a-b8715a4d9fdso731661666b.0 for ; Tue, 20 Jan 2026 04:52:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1768913561; x=1769518361; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/jilfeDYFkK+8nob6Qzv/8NiCq9AziKZbge2iPfiIO8=; b=kokrqn4lf3up4fChg6tyN0gEOB0+wl2S/w3xkxahJHSzVKud4DTH9bvwbFSqBrk7VI pBSQ/ZP42QYuL6P2wmQxW2wI8u2jLE1qNw+UeJM5+95CHGBNXWlSnxPkq7jdpjyYfiD3 sEujigzYXUKZwJf8N4MTwhVnSXz12LjjiitClAR/boXD3v7iidb915rvwCgwlijmHzbf sTFqWzGDde1DjVu5Vzm0cJsi7fMoP7xeBKlGuRFPPSs5E24IIbOaZfI7HduNyDIqwEbQ yPr3d2GJDVFVtrcHGVEYlNO+GRNpvRNLBrO56Q8ck+0BG4j83ROFI+TLSg0awDiVGDEz DlmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768913561; x=1769518361; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=/jilfeDYFkK+8nob6Qzv/8NiCq9AziKZbge2iPfiIO8=; b=Tva6MFosgQZRuStv+REtowVvIkW+WbxA8qv2F8ojLjWviu49JtWe1wtiMFqiPZ+3+c Qw3CLzBYzhrqcTNtGe2CR5fuHf2DDPQCyZ3PCK8Sn/VUbrx2DxJga1lf5SeuKIv4sG66 wnLDpVk9DvitMwt6Gd0TZIhMEXJri8FD77f/PgCOHPdE7qOUw5kG75Brc9pOvYpMgHOI P/wQgWxNrc7ptsAe+9RObWlkBzHfVqfSiImhUJmPgYKDR5Lg3of67/Z4e4Byo7+z3aFw SRtzGcnhybQkRhmlaGsCMF9v5i88B7dXZG8gnLmcAt/SLig6uMzyP1LyNRF+V1AQ11Xq yfAw== X-Forwarded-Encrypted: i=1; AJvYcCV3ppM2GybM0eY+ZPQk6jOVvEc3VkQ0x234XmvmuaeqxDDZVN8pWCSVV10SkQ8cGHnGbXG3qIboSvW2CTM=@vger.kernel.org X-Gm-Message-State: AOJu0YxXYyvvx9JfkynB72byhSoU9WBy043dcXMIllXDGY+5k+hi2ApY 6QgGyoliGxqDMtzvfbDElxu5tItjmmAhNdWqiEzZEGi5PpRVG1b4KTx4 X-Gm-Gg: AZuq6aKVtzjXBI85ZAVNgXyvdh/724TqHKN82pPaduNei+WN7xVLazbJ41LXurQ/5aR Xw60p75kZYBsdgHNFQ6bSh9u+x+ruCyEIOtrDs1ofpKGWUEUDRkH5WgPqxZNgxhufJZaWoE04Mj U1VbDEvduE9zGYhWYYkk6zf0oPFY086VJBxupeow1leXrMJrttc2LnnHLOCJCRzC0vqnvhqLZSw wm5670rf4X3v+iXHaWR7Vbv9VxmN9zHC+PTXez7i7EZQNff65dCADsN27+vaJNruZnVMzQUWz+x a5L4ajdgk21P31XK9B7oMa3MIsL6DreLHqgQVPRzJ3HAPaIbvrLyXTLI4hR2OdkgEroQFH9y+0Q jVtCFoOo643Io/kwOm+nAVpts3Yn7HuGZrJK8oOIhfrokf8wxG8Jcq08fyrReUKW3DDgXA/9Y6R CqW6bpStwjqF3jDlyiVUA6abjkUYwrCel9sIE= X-Received: by 2002:a17:907:9443:b0:b3b:5fe6:577a with SMTP id a640c23a62f3a-b87968b6ac7mr1197451266b.8.1768913560794; Tue, 20 Jan 2026 04:52:40 -0800 (PST) Received: from localhost.localdomain ([2a00:23c4:a758:8a01:c8c7:2ef6:8ac5:5556]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b87959ca32esm1420626066b.41.2026.01.20.04.52.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jan 2026 04:52:40 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH 09/12] arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC Date: Tue, 20 Jan 2026 12:52:20 +0000 Message-ID: <20260120125232.349708-10-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120125232.349708-1-biju.das.jz@bp.renesas.com> References: <20260120125232.349708-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add the initial DTSI for the RZ/G3L SoC. The files in this commit have the following meaning: - r9a08g046.dtsi: RZ/G3L family SoC common parts - r9a08g046l48.dtsi: RZ/G3L R0A08G046L{46,48} SoC specific parts Added place holders to reuse the code for Renesas SMARC II carrier board. Signed-off-by: Biju Das --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 219 ++++++++++++++++++ arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi | 13 ++ 2 files changed, 232 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g046.dtsi new file mode 100644 index 000000000000..0619c296a8d0 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -0,0 +1,219 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3L SoC + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +#include +#include + +/ { + compatible =3D "renesas,r9a08g046"; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic>; + + audio_clk1: audio-clk1 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by boards that provide it. */ + clock-frequency =3D <0>; + }; + + audio_clk2: audio-clk2 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by boards that provide it. */ + clock-frequency =3D <0>; + }; + + can_clk: can-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by boards that provide it. */ + clock-frequency =3D <0>; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a55"; + reg =3D <0>; + device_type =3D "cpu"; + next-level-cache =3D <&L3_CA55>; + enable-method =3D "psci"; + }; + + cpu1: cpu@100 { + compatible =3D "arm,cortex-a55"; + reg =3D <0x100>; + device_type =3D "cpu"; + next-level-cache =3D <&L3_CA55>; + enable-method =3D "psci"; + }; + + cpu2: cpu@200 { + compatible =3D "arm,cortex-a55"; + reg =3D <0x200>; + device_type =3D "cpu"; + next-level-cache =3D <&L3_CA55>; + enable-method =3D "psci"; + }; + + cpu3: cpu@300 { + compatible =3D "arm,cortex-a55"; + reg =3D <0x300>; + device_type =3D "cpu"; + next-level-cache =3D <&L3_CA55>; + enable-method =3D "psci"; + }; + + L3_CA55: cache-controller-0 { + compatible =3D "cache"; + cache-unified; + cache-size =3D <0x80000>; + cache-level =3D <3>; + }; + }; + + extal_clk: extal-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board. */ + clock-frequency =3D <0>; + }; + + psci { + compatible =3D "arm,psci-1.0", "arm,psci-0.2"; + method =3D "smc"; + }; + + soc: soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + scif0: serial@100ac000 { + compatible =3D "renesas,scif-r9a08g046", "renesas,scif-r9a07g044"; + reg =3D <0 0x100ac000 0 0x400>; + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks =3D <&cpg CPG_MOD R9A08G046_SCIF0_CLK_PCK>; + clock-names =3D "fck"; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A08G046_SCIF0_RST_SYSTEM_N>; + status =3D "disabled"; + }; + + i2c0: i2c@100ae000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0x100AE000 0 0x400>; + /* placeholder */ + }; + + canfd: can@100c0000 { + reg =3D <0 0x100c0000 0 0x20000>; + /* placeholder */ + }; + + cpg: clock-controller@11010000 { + compatible =3D "renesas,r9a08g046-cpg"; + reg =3D <0 0x11010000 0 0x10000>; + clocks =3D <&extal_clk>; + clock-names =3D "extal"; + #clock-cells =3D <2>; + #reset-cells =3D <1>; + #power-domain-cells =3D <0>; + }; + + sysc: system-controller@11020000 { + compatible =3D "renesas,r9a08g046-sysc"; + reg =3D <0 0x11020000 0 0x10000>; + interrupts =3D , + , + , + ; + interrupt-names =3D "lpm_int", "ca55stbydone_int", + "cm33stbyr_int", "ca55_deny"; + }; + + pinctrl: pinctrl@11030000 { + reg =3D <0 0x11030000 0 0x10000>; + gpio-controller; + #gpio-cells =3D <2>; + }; + + dmac: dma-controller@11820000 { + compatible =3D "renesas,r9a08g046-dmac", "renesas,rz-dmac"; + reg =3D <0 0x11820000 0 0x10000>, + <0 0x11830000 0 0x10000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks =3D <&cpg CPG_MOD R9A08G046_DMAC_ACLK>, + <&cpg CPG_MOD R9A08G046_DMAC_PCLK>; + clock-names =3D "main", "register"; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A08G046_DMAC_ARESETN>, + <&cpg R9A08G046_DMAC_RST_ASYNC>; + reset-names =3D "arst", "rst_async"; + #dma-cells =3D <1>; + dma-channels =3D <16>; + }; + + sdhi1: mmc@11c10000 { + reg =3D <0x0 0x11c10000 0 0x10000>; + /* placeholder */ + }; + + gic: interrupt-controller@12400000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x12400000 0 0x20000>, + <0x0 0x12440000 0 0x80000>; + #interrupt-cells =3D <3>; + #address-cells =3D <0>; + interrupt-controller; + interrupts =3D ; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + , + ; + interrupt-names =3D "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi b/arch/arm64/boo= t/dts/renesas/r9a08g046l48.dtsi new file mode 100644 index 000000000000..f6f673abc01b --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3E R9A08G046L48 SoC specific parts + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a08g046.dtsi" + +/ { + compatible =3D "renesas,r9a08g046l48", "renesas,r9a08g046"; +}; --=20 2.43.0