From nobody Sat Feb 7 21:15:26 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E8A036BCE9 for ; Tue, 20 Jan 2026 06:20:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768890052; cv=none; b=KU44riKnYoQf+7uJ6Bq22VcnAWWTpWscXb235neCdAjMLI3DFD8qjd4XX5GkoYp2zE5zUDEWMUgeEFEFnOzGI90EgeN6qVIsUD/WWjzIZQ5nJ9gOc8yUzDmMQINNjj1bEhsNWo5CPMwxCeAHTdhZ9aCTf1RFzF5DjAaz2hdtMaY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768890052; c=relaxed/simple; bh=/WYsX64qJwlOy49NaeAGZcfXuqecSO9XVNigfGEGZ94=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=B63/TdNX5Z0w22blTCLd4wuoAJUu9IsWIF/Dii+to+97NEjBCW1BrcVLjpqO2HeAJI4jV+A7Pye+yZjSVXg3HWdxQM9IMK1YfaUgW1meOpn1AwN5qXixkKjEC4ULt1JrMqWLEMdvwOSklSWvZyhLTKvmLxu2hfmGSUFDeW2u52U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=F2zcjY2y; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="F2zcjY2y" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768890050; x=1800426050; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/WYsX64qJwlOy49NaeAGZcfXuqecSO9XVNigfGEGZ94=; b=F2zcjY2y0CAgPsfWP1g+uE/oiMy8Of527n3ehJtk+xWWJk1/M1ch2GeX fn1xqAzfq0vWSJiHL+3+qsFvBm27Uogc9saL1Bpe1rH0n9gO00VBaIzD7 zL1uuQAgFCZBOXc+z7FNgCiMPq3pZ3x7G9tlyzx2l94prml9hOBL+8/FM L5glglECyZAnN0eCg5qzjUiZ0eyjP0pgE8egmFcwRZcbIB2wkboR4KUfE pH16EqiWEAgELZBjpKZhOPg5Q68IPcjWiPlWyQNf1vupX8f55TXKInzTC +tJIXICT2hSAq0iT4cDwnSPnMESfD7A3CtAa71pI1z0gs9TlCiilJuERB Q==; X-CSE-ConnectionGUID: 2p7DtVI/Tg6X8pdBaFraJw== X-CSE-MsgGUID: 5jIUQNceRSafZQv0RzAUhQ== X-IronPort-AV: E=McAfee;i="6800,10657,11676"; a="69991308" X-IronPort-AV: E=Sophos;i="6.21,240,1763452800"; d="scan'208";a="69991308" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jan 2026 22:20:49 -0800 X-CSE-ConnectionGUID: 2LA9h3nxTJqFjkXa+Fi7Pw== X-CSE-MsgGUID: whgXCnaiTGC4P5LotsOFqg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,240,1763452800"; d="scan'208";a="206464267" Received: from allen-box.sh.intel.com ([10.239.159.52]) by fmviesa009.fm.intel.com with ESMTP; 19 Jan 2026 22:20:47 -0800 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Kevin Tian , Jason Gunthorpe Cc: Dmytro Maluka , Samiullah Khawaja , iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v2 1/3] iommu/vt-d: Clear Present bit before tearing down PASID entry Date: Tue, 20 Jan 2026 14:18:12 +0800 Message-ID: <20260120061816.2132558-2-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120061816.2132558-1-baolu.lu@linux.intel.com> References: <20260120061816.2132558-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Intel VT-d Scalable Mode PASID table entry consists of 512 bits (64 bytes). When tearing down an entry, the current implementation zeros the entire 64-byte structure immediately using multiple 64-bit writes. Since the IOMMU hardware may fetch these 64 bytes using multiple internal transactions (e.g., four 128-bit bursts), updating or zeroing the entire entry while it is active (P=3D1) risks a "torn" read. If a hardware fetch occurs simultaneously with the CPU zeroing the entry, the hardware could observe an inconsistent state, leading to unpredictable behavior or spurious faults. Follow the "Guidance to Software for Invalidations" in the VT-d spec (Section 6.5.3.3) by implementing the recommended ownership handshake: 1. Clear only the 'Present' (P) bit of the PASID entry. 2. Use a dma_wmb() to ensure the cleared bit is visible to hardware before proceeding. 3. Execute the required invalidation sequence (PASID cache, IOTLB, and Device-TLB flush) to ensure the hardware has released all cached references. 4. Only after the flushes are complete, zero out the remaining fields of the PASID entry. Also, add a dma_wmb() in pasid_set_present() to ensure that all other fields of the PASID entry are visible to the hardware before the Present bit is set. Fixes: 0bbeb01a4faf ("iommu/vt-d: Manage scalalble mode PASID tables") Signed-off-by: Lu Baolu Reviewed-by: Dmytro Maluka Reviewed-by: Kevin Tian Reviewed-by: Samiullah Khawaja --- drivers/iommu/intel/pasid.h | 14 ++++++++++++++ drivers/iommu/intel/pasid.c | 6 +++++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/intel/pasid.h b/drivers/iommu/intel/pasid.h index b4c85242dc79..0b303bd0b0c1 100644 --- a/drivers/iommu/intel/pasid.h +++ b/drivers/iommu/intel/pasid.h @@ -234,9 +234,23 @@ static inline void pasid_set_wpe(struct pasid_entry *p= e) */ static inline void pasid_set_present(struct pasid_entry *pe) { + dma_wmb(); pasid_set_bits(&pe->val[0], 1 << 0, 1); } =20 +/* + * Clear the Present (P) bit (bit 0) of a scalable-mode PASID table entry. + * This initiates the transition of the entry's ownership from hardware + * to software. The caller is responsible for fulfilling the invalidation + * handshake recommended by the VT-d spec, Section 6.5.3.3 (Guidance to + * Software for Invalidations). + */ +static inline void pasid_clear_present(struct pasid_entry *pe) +{ + pasid_set_bits(&pe->val[0], 1 << 0, 0); + dma_wmb(); +} + /* * Setup Page Walk Snoop bit (Bit 87) of a scalable mode PASID * entry. diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index 3e2255057079..eb069aefa4fa 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -272,7 +272,7 @@ void intel_pasid_tear_down_entry(struct intel_iommu *io= mmu, struct device *dev, =20 did =3D pasid_get_domain_id(pte); pgtt =3D pasid_pte_get_pgtt(pte); - intel_pasid_clear_entry(dev, pasid, fault_ignore); + pasid_clear_present(pte); spin_unlock(&iommu->lock); =20 if (!ecap_coherent(iommu->ecap)) @@ -286,6 +286,10 @@ void intel_pasid_tear_down_entry(struct intel_iommu *i= ommu, struct device *dev, iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH); =20 devtlb_invalidation_with_pasid(iommu, dev, pasid); + intel_pasid_clear_entry(dev, pasid, fault_ignore); + if (!ecap_coherent(iommu->ecap)) + clflush_cache_range(pte, sizeof(*pte)); + if (!fault_ignore) intel_iommu_drain_pasid_prq(dev, pasid); } --=20 2.43.0 From nobody Sat Feb 7 21:15:26 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB30436C5A2 for ; Tue, 20 Jan 2026 06:20:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768890055; cv=none; b=JXrHsB9y6TkpWlv28gZQsNx5n/IpTnWaQ1fD3OXDWuXJasTN4V3+/eF8ZdJDiOEUDebjROT3hlQ6IBP5Ttmcz/ie+j77HJ+KtLXv/1HdsyeqEiNcvLyY6rDbQ+k0APmp1WiAgCGQ9RcqK2z2CNpLwskXv/VCYa6qp6iH+YYrJ3k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768890055; c=relaxed/simple; bh=nlGjv1mM5tMvlnslmN6pYf6e5Nhw0JtdAENFmV64fis=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Sh3w4VKLCDOGWlsIuodKznsyn9kmQG779w3nChqTmn95LFfhJKp1qgqJoGCu3aQf61nE5yNxy7s/8E4XxXyiPKhosPTZm01EDb4SFVY6j77lvJwcSmRbuL7ZvuVg2/XjQff1IBhhONHqjM4gGlSsUK+frfHKmhyyk2xrZdXwjVM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ac12WcoP; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ac12WcoP" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768890052; x=1800426052; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nlGjv1mM5tMvlnslmN6pYf6e5Nhw0JtdAENFmV64fis=; b=ac12WcoPENlTqnlaTm/qAW2g455bG0PtoHVFitBbOvPR0FD88DHKie4d TTOnp/RzDiwghN9z7pQn+dnVsC5DBr/dXSbrzBvLt3IapVU/uzOeXr5Ja nEmuOOR9MiNcDSyglXSo3U7a/5b/YsbuUSAxTdOd2uawQ/Tjmp/JfPUfP IBO4LVUXfBnHeU6RrP9fTuLbQJNzzwwh+c1/fBt0SfPRZ/9CJ8JwGC9sU ix2unTXKzY5IixCtuvYj7u/CKErC+FiE69rbabNGSiV5T1v9ebUX8+v8/ 28iPhjWPPIihSnzZSplw1YPMdOfb538IavXkNVAlTNqu2M1BaX+Mc8q82 w==; X-CSE-ConnectionGUID: ZQChr5xQSwitI2REuRqLBg== X-CSE-MsgGUID: vtAorvHSSUCs4Q1IrGkWzA== X-IronPort-AV: E=McAfee;i="6800,10657,11676"; a="69991316" X-IronPort-AV: E=Sophos;i="6.21,240,1763452800"; d="scan'208";a="69991316" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jan 2026 22:20:52 -0800 X-CSE-ConnectionGUID: Vv0VerFIQ+CoTJlkLrTZfA== X-CSE-MsgGUID: 8sNwlj9fRvm1AoXQ3uSiog== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,240,1763452800"; d="scan'208";a="206464271" Received: from allen-box.sh.intel.com ([10.239.159.52]) by fmviesa009.fm.intel.com with ESMTP; 19 Jan 2026 22:20:50 -0800 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Kevin Tian , Jason Gunthorpe Cc: Dmytro Maluka , Samiullah Khawaja , iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v2 2/3] iommu/vt-d: Clear Present bit before tearing down context entry Date: Tue, 20 Jan 2026 14:18:13 +0800 Message-ID: <20260120061816.2132558-3-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120061816.2132558-1-baolu.lu@linux.intel.com> References: <20260120061816.2132558-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable When tearing down a context entry, the current implementation zeros the entire 128-bit entry using multiple 64-bit writes. This creates a window where the hardware can fetch a "torn" entry =E2=80=94 where some fields are already zeroed while the 'Present' bit is still set =E2=80=94 leading to unpredictable behavior or spurious faults. While x86 provides strong write ordering, the compiler may reorder writes to the two 64-bit halves of the context entry. Even without compiler reordering, the hardware fetch is not guaranteed to be atomic with respect to multiple CPU writes. Align with the "Guidance to Software for Invalidations" in the VT-d spec (Section 6.5.3.3) by implementing the recommended ownership handshake: 1. Clear only the 'Present' (P) bit of the context entry first to signal the transition of ownership from hardware to software. 2. Use dma_wmb() to ensure the cleared bit is visible to the IOMMU. 3. Perform the required cache and context-cache invalidation to ensure hardware no longer has cached references to the entry. 4. Fully zero out the entry only after the invalidation is complete. Also, add a dma_wmb() to context_set_present() to ensure the entry is fully initialized before the 'Present' bit becomes visible. Fixes: ba39592764ed2 ("Intel IOMMU: Intel IOMMU driver") Reported-by: Dmytro Maluka Closes: https://lore.kernel.org/all/aTG7gc7I5wExai3S@google.com/ Signed-off-by: Lu Baolu Reviewed-by: Dmytro Maluka Reviewed-by: Kevin Tian Reviewed-by: Samiullah Khawaja --- drivers/iommu/intel/iommu.h | 21 ++++++++++++++++++++- drivers/iommu/intel/iommu.c | 4 +++- 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index 25c5e22096d4..599913fb65d5 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -900,7 +900,26 @@ static inline int pfn_level_offset(u64 pfn, int level) =20 static inline void context_set_present(struct context_entry *context) { - context->lo |=3D 1; + u64 val; + + dma_wmb(); + val =3D READ_ONCE(context->lo) | 1; + WRITE_ONCE(context->lo, val); +} + +/* + * Clear the Present (P) bit (bit 0) of a context table entry. This initia= tes + * the transition of the entry's ownership from hardware to software. The + * caller is responsible for fulfilling the invalidation handshake recomme= nded + * by the VT-d spec, Section 6.5.3.3 (Guidance to Software for Invalidatio= ns). + */ +static inline void context_clear_present(struct context_entry *context) +{ + u64 val; + + val =3D READ_ONCE(context->lo) & GENMASK_ULL(63, 1); + WRITE_ONCE(context->lo, val); + dma_wmb(); } =20 static inline void context_set_fault_enable(struct context_entry *context) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 134302fbcd92..c66cc51f9e51 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -1240,10 +1240,12 @@ static void domain_context_clear_one(struct device_= domain_info *info, u8 bus, u8 } =20 did =3D context_domain_id(context); - context_clear_entry(context); + context_clear_present(context); __iommu_flush_cache(iommu, context, sizeof(*context)); spin_unlock(&iommu->lock); intel_context_flush_no_pasid(info, context, did); + context_clear_entry(context); + __iommu_flush_cache(iommu, context, sizeof(*context)); } =20 int __domain_setup_first_level(struct intel_iommu *iommu, struct device *d= ev, --=20 2.43.0 From nobody Sat Feb 7 21:15:26 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F8B936C58F for ; Tue, 20 Jan 2026 06:20:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768890057; cv=none; b=XHZbhFvZanP7znPyBif6QWLfmDBVANjFeT4dpJRqRTa+KdBsSRtG0mlfcNvNAE3PRFDy+nKKkew3wfJcF8dJMIAKJbfzSb05FT9fQ+dL0SpuSYML6pKvxLRUwidyqUIeAfZTa8i8P3mCR360JT8WM9oiA4hC+xfkg3eoN3HVCUE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768890057; c=relaxed/simple; bh=Wsf8+Tqw1vh/9VsN5YjTjdQxnbGm1mUm8mSEQp+1Las=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kQJAMy5Un///SRhXZqnol+gOZ4xv2hfLKaCri+uNbl3iwgi+3EluR3Q31WWjd3nsRZ0yTpCjol+qTzeaA3d7QxR4TD3Z/uWy/PowPTA9RVz33bekP8yby4HGICZp2zwtLuVGw+Wv/g9s/LlkbLp7nFV9QKO9S4OTjbMbWDij4pY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Bt/hs+sL; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Bt/hs+sL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768890055; x=1800426055; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Wsf8+Tqw1vh/9VsN5YjTjdQxnbGm1mUm8mSEQp+1Las=; b=Bt/hs+sL6q3WRGqz3rCZBqB8UE8WkjqemnaWHE2kIdKpJZ09qV6WFfK6 2FZ/4NXwPHH5elYIEfQC1UMCqiAsGR+UngPbFiPCSUXyEi0DF+bIG76v7 9MCmAN3VoNSKpn5nzoXQreEQSQEWds5Wx62smspicxib4nRC+dHSoxv56 yRXudwkT5Mn1XdXK6jqbUtHA1g6xfQmbwJLAkfNA/GCcT6MlThbf8IQy2 rjzcGFSOrw0h89DxY7ir7MUD81RRvdE6MeyCUSb2jSfHknFDPqCiitTX/ mC+tQ7mzdP2SHqoQrIGZyogRiY62UybFKo0o4Nbmt6R85iTngi6IXDOjc Q==; X-CSE-ConnectionGUID: ZdX4dEeETrmde+0YAN+I7Q== X-CSE-MsgGUID: D4Lxi9MURgmjVXEeOXBnLw== X-IronPort-AV: E=McAfee;i="6800,10657,11676"; a="69991324" X-IronPort-AV: E=Sophos;i="6.21,240,1763452800"; d="scan'208";a="69991324" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jan 2026 22:20:54 -0800 X-CSE-ConnectionGUID: EPNpNMMiS36U2q/soj20FQ== X-CSE-MsgGUID: CIRPfzxSQ0a4y7gqSvl5ZA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,240,1763452800"; d="scan'208";a="206464274" Received: from allen-box.sh.intel.com ([10.239.159.52]) by fmviesa009.fm.intel.com with ESMTP; 19 Jan 2026 22:20:52 -0800 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Kevin Tian , Jason Gunthorpe Cc: Dmytro Maluka , Samiullah Khawaja , iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH v2 3/3] iommu/vt-d: Fix race condition during PASID entry replacement Date: Tue, 20 Jan 2026 14:18:14 +0800 Message-ID: <20260120061816.2132558-4-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120061816.2132558-1-baolu.lu@linux.intel.com> References: <20260120061816.2132558-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The Intel VT-d PASID table entry is 512 bits (64 bytes). When replacing an active PASID entry (e.g., during domain replacement), the current implementation calculates a new entry on the stack and copies it to the table using a single structure assignment. struct pasid_entry *pte, new_pte; pte =3D intel_pasid_get_entry(dev, pasid); pasid_pte_config_first_level(iommu, &new_pte, ...); *pte =3D new_pte; Because the hardware may fetch the 512-bit PASID entry in multiple 128-bit chunks, updating the entire entry while it is active (Present bit set) risks a "torn" read. In this scenario, the IOMMU hardware could observe an inconsistent state =E2=80=94 partially new data and partia= lly old data =E2=80=94 leading to unpredictable behavior or spurious faults. Fix this by removing the unsafe "replace" helpers and following the "clear-then-update" flow, which ensures the Present bit is cleared and the required invalidation handshake is completed before the new configuration is applied. Fixes: 7543ee63e811 ("iommu/vt-d: Add pasid replace helpers") Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian Reviewed-by: Samiullah Khawaja --- drivers/iommu/intel/pasid.h | 14 --- drivers/iommu/intel/iommu.c | 29 +++--- drivers/iommu/intel/nested.c | 9 +- drivers/iommu/intel/pasid.c | 184 ----------------------------------- 4 files changed, 16 insertions(+), 220 deletions(-) diff --git a/drivers/iommu/intel/pasid.h b/drivers/iommu/intel/pasid.h index 0b303bd0b0c1..c3c8c907983e 100644 --- a/drivers/iommu/intel/pasid.h +++ b/drivers/iommu/intel/pasid.h @@ -316,20 +316,6 @@ int intel_pasid_setup_pass_through(struct intel_iommu = *iommu, struct device *dev, u32 pasid); int intel_pasid_setup_nested(struct intel_iommu *iommu, struct device *dev, u32 pasid, struct dmar_domain *domain); -int intel_pasid_replace_first_level(struct intel_iommu *iommu, - struct device *dev, phys_addr_t fsptptr, - u32 pasid, u16 did, u16 old_did, int flags); -int intel_pasid_replace_second_level(struct intel_iommu *iommu, - struct dmar_domain *domain, - struct device *dev, u16 old_did, - u32 pasid); -int intel_pasid_replace_pass_through(struct intel_iommu *iommu, - struct device *dev, u16 old_did, - u32 pasid); -int intel_pasid_replace_nested(struct intel_iommu *iommu, - struct device *dev, u32 pasid, - u16 old_did, struct dmar_domain *domain); - void intel_pasid_tear_down_entry(struct intel_iommu *iommu, struct device *dev, u32 pasid, bool fault_ignore); diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index c66cc51f9e51..705828b06e32 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -1252,12 +1252,10 @@ int __domain_setup_first_level(struct intel_iommu *= iommu, struct device *dev, ioasid_t pasid, u16 did, phys_addr_t fsptptr, int flags, struct iommu_domain *old) { - if (!old) - return intel_pasid_setup_first_level(iommu, dev, fsptptr, pasid, - did, flags); - return intel_pasid_replace_first_level(iommu, dev, fsptptr, pasid, did, - iommu_domain_did(old, iommu), - flags); + if (old) + intel_pasid_tear_down_entry(iommu, dev, pasid, false); + + return intel_pasid_setup_first_level(iommu, dev, fsptptr, pasid, did, fla= gs); } =20 static int domain_setup_second_level(struct intel_iommu *iommu, @@ -1265,23 +1263,20 @@ static int domain_setup_second_level(struct intel_i= ommu *iommu, struct device *dev, ioasid_t pasid, struct iommu_domain *old) { - if (!old) - return intel_pasid_setup_second_level(iommu, domain, - dev, pasid); - return intel_pasid_replace_second_level(iommu, domain, dev, - iommu_domain_did(old, iommu), - pasid); + if (old) + intel_pasid_tear_down_entry(iommu, dev, pasid, false); + + return intel_pasid_setup_second_level(iommu, domain, dev, pasid); } =20 static int domain_setup_passthrough(struct intel_iommu *iommu, struct device *dev, ioasid_t pasid, struct iommu_domain *old) { - if (!old) - return intel_pasid_setup_pass_through(iommu, dev, pasid); - return intel_pasid_replace_pass_through(iommu, dev, - iommu_domain_did(old, iommu), - pasid); + if (old) + intel_pasid_tear_down_entry(iommu, dev, pasid, false); + + return intel_pasid_setup_pass_through(iommu, dev, pasid); } =20 static int domain_setup_first_level(struct intel_iommu *iommu, diff --git a/drivers/iommu/intel/nested.c b/drivers/iommu/intel/nested.c index a3fb8c193ca6..e9a440e9c960 100644 --- a/drivers/iommu/intel/nested.c +++ b/drivers/iommu/intel/nested.c @@ -136,11 +136,10 @@ static int domain_setup_nested(struct intel_iommu *io= mmu, struct device *dev, ioasid_t pasid, struct iommu_domain *old) { - if (!old) - return intel_pasid_setup_nested(iommu, dev, pasid, domain); - return intel_pasid_replace_nested(iommu, dev, pasid, - iommu_domain_did(old, iommu), - domain); + if (old) + intel_pasid_tear_down_entry(iommu, dev, pasid, false); + + return intel_pasid_setup_nested(iommu, dev, pasid, domain); } =20 static int intel_nested_set_dev_pasid(struct iommu_domain *domain, diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index eb069aefa4fa..4b880b9ad49d 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -416,50 +416,6 @@ int intel_pasid_setup_first_level(struct intel_iommu *= iommu, struct device *dev, return 0; } =20 -int intel_pasid_replace_first_level(struct intel_iommu *iommu, - struct device *dev, phys_addr_t fsptptr, - u32 pasid, u16 did, u16 old_did, - int flags) -{ - struct pasid_entry *pte, new_pte; - - if (!ecap_flts(iommu->ecap)) { - pr_err("No first level translation support on %s\n", - iommu->name); - return -EINVAL; - } - - if ((flags & PASID_FLAG_FL5LP) && !cap_fl5lp_support(iommu->cap)) { - pr_err("No 5-level paging support for first-level on %s\n", - iommu->name); - return -EINVAL; - } - - pasid_pte_config_first_level(iommu, &new_pte, fsptptr, did, flags); - - spin_lock(&iommu->lock); - pte =3D intel_pasid_get_entry(dev, pasid); - if (!pte) { - spin_unlock(&iommu->lock); - return -ENODEV; - } - - if (!pasid_pte_is_present(pte)) { - spin_unlock(&iommu->lock); - return -EINVAL; - } - - WARN_ON(old_did !=3D pasid_get_domain_id(pte)); - - *pte =3D new_pte; - spin_unlock(&iommu->lock); - - intel_pasid_flush_present(iommu, dev, pasid, old_did, pte); - intel_iommu_drain_pasid_prq(dev, pasid); - - return 0; -} - /* * Set up the scalable mode pasid entry for second only translation type. */ @@ -526,51 +482,6 @@ int intel_pasid_setup_second_level(struct intel_iommu = *iommu, return 0; } =20 -int intel_pasid_replace_second_level(struct intel_iommu *iommu, - struct dmar_domain *domain, - struct device *dev, u16 old_did, - u32 pasid) -{ - struct pasid_entry *pte, new_pte; - u16 did; - - /* - * If hardware advertises no support for second level - * translation, return directly. - */ - if (!ecap_slts(iommu->ecap)) { - pr_err("No second level translation support on %s\n", - iommu->name); - return -EINVAL; - } - - did =3D domain_id_iommu(domain, iommu); - - pasid_pte_config_second_level(iommu, &new_pte, domain, did); - - spin_lock(&iommu->lock); - pte =3D intel_pasid_get_entry(dev, pasid); - if (!pte) { - spin_unlock(&iommu->lock); - return -ENODEV; - } - - if (!pasid_pte_is_present(pte)) { - spin_unlock(&iommu->lock); - return -EINVAL; - } - - WARN_ON(old_did !=3D pasid_get_domain_id(pte)); - - *pte =3D new_pte; - spin_unlock(&iommu->lock); - - intel_pasid_flush_present(iommu, dev, pasid, old_did, pte); - intel_iommu_drain_pasid_prq(dev, pasid); - - return 0; -} - /* * Set up dirty tracking on a second only or nested translation type. */ @@ -683,38 +594,6 @@ int intel_pasid_setup_pass_through(struct intel_iommu = *iommu, return 0; } =20 -int intel_pasid_replace_pass_through(struct intel_iommu *iommu, - struct device *dev, u16 old_did, - u32 pasid) -{ - struct pasid_entry *pte, new_pte; - u16 did =3D FLPT_DEFAULT_DID; - - pasid_pte_config_pass_through(iommu, &new_pte, did); - - spin_lock(&iommu->lock); - pte =3D intel_pasid_get_entry(dev, pasid); - if (!pte) { - spin_unlock(&iommu->lock); - return -ENODEV; - } - - if (!pasid_pte_is_present(pte)) { - spin_unlock(&iommu->lock); - return -EINVAL; - } - - WARN_ON(old_did !=3D pasid_get_domain_id(pte)); - - *pte =3D new_pte; - spin_unlock(&iommu->lock); - - intel_pasid_flush_present(iommu, dev, pasid, old_did, pte); - intel_iommu_drain_pasid_prq(dev, pasid); - - return 0; -} - /* * Set the page snoop control for a pasid entry which has been set up. */ @@ -848,69 +727,6 @@ int intel_pasid_setup_nested(struct intel_iommu *iommu= , struct device *dev, return 0; } =20 -int intel_pasid_replace_nested(struct intel_iommu *iommu, - struct device *dev, u32 pasid, - u16 old_did, struct dmar_domain *domain) -{ - struct iommu_hwpt_vtd_s1 *s1_cfg =3D &domain->s1_cfg; - struct dmar_domain *s2_domain =3D domain->s2_domain; - u16 did =3D domain_id_iommu(domain, iommu); - struct pasid_entry *pte, new_pte; - - /* Address width should match the address width supported by hardware */ - switch (s1_cfg->addr_width) { - case ADDR_WIDTH_4LEVEL: - break; - case ADDR_WIDTH_5LEVEL: - if (!cap_fl5lp_support(iommu->cap)) { - dev_err_ratelimited(dev, - "5-level paging not supported\n"); - return -EINVAL; - } - break; - default: - dev_err_ratelimited(dev, "Invalid stage-1 address width %d\n", - s1_cfg->addr_width); - return -EINVAL; - } - - if ((s1_cfg->flags & IOMMU_VTD_S1_SRE) && !ecap_srs(iommu->ecap)) { - pr_err_ratelimited("No supervisor request support on %s\n", - iommu->name); - return -EINVAL; - } - - if ((s1_cfg->flags & IOMMU_VTD_S1_EAFE) && !ecap_eafs(iommu->ecap)) { - pr_err_ratelimited("No extended access flag support on %s\n", - iommu->name); - return -EINVAL; - } - - pasid_pte_config_nestd(iommu, &new_pte, s1_cfg, s2_domain, did); - - spin_lock(&iommu->lock); - pte =3D intel_pasid_get_entry(dev, pasid); - if (!pte) { - spin_unlock(&iommu->lock); - return -ENODEV; - } - - if (!pasid_pte_is_present(pte)) { - spin_unlock(&iommu->lock); - return -EINVAL; - } - - WARN_ON(old_did !=3D pasid_get_domain_id(pte)); - - *pte =3D new_pte; - spin_unlock(&iommu->lock); - - intel_pasid_flush_present(iommu, dev, pasid, old_did, pte); - intel_iommu_drain_pasid_prq(dev, pasid); - - return 0; -} - /* * Interfaces to setup or teardown a pasid table to the scalable-mode * context table entry: --=20 2.43.0