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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 10:44:28.2776 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: afe2d3fb-6f92-442c-0884-08de5810e2fc X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.195];Helo=[lewvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FC.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR10MB6862 Update the bindings to allow setting per-line interrupt-types. Some Interrupt Router instances can only work with a specific trigger type (edge or level), while others act as simple passthroughs that preserve the source interrupt type unchanged. In addition to existing edge or level interrupt setting, add a third enum value 15 (IRQ_TYPE_DEFAULT) for "ti,intr-trigger-type" property, to indicate that the router acts as a passthrough. When set to 15, "#interrupt-cells" must be 2 to allow each interrupt source to specify its trigger type per-line. Signed-off-by: Aniket Limaye --- Changes in v2: - Reword Commit msg to better describe the patch - Link to v1: https://lore.kernel.org/r/20260116-ul-driver-i2c-j722s-v1-1-c= 28e8ba38a9e@ti.com --- .../bindings/interrupt-controller/ti,sci-intr.yaml | 42 ++++++++++++++++++= +--- 1 file changed, 37 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-= intr.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-i= ntr.yaml index c99cc7323c71..59c01f327f3b 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.ya= ml +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.ya= ml @@ -15,8 +15,7 @@ allOf: description: | The Interrupt Router (INTR) module provides a mechanism to mux M interrupt inputs to N interrupt outputs, where all M inputs are selectab= le - to be driven per N output. An Interrupt Router can either handle edge - triggered or level triggered interrupts and that is fixed in hardware. + to be driven per N output. =20 Interrupt Router +----------------------+ @@ -52,11 +51,12 @@ properties: =20 ti,intr-trigger-type: $ref: /schemas/types.yaml#/definitions/uint32 - enum: [1, 4] + enum: [1, 4, 15] description: | Should be one of the following. 1 =3D If intr supports edge triggered interrupts. 4 =3D If intr supports level triggered interrupts. + 15 =3D If intr preserves the source interrupt type. =20 reg: maxItems: 1 @@ -64,9 +64,14 @@ properties: interrupt-controller: true =20 '#interrupt-cells': - const: 1 + enum: [1, 2] description: | - The 1st cell should contain interrupt router input hw number. + Number of cells in interrupt specifier. Depends on ti,intr-trigger-t= ype: + - If ti,intr-trigger-type is 1 or 4: must be 1 + The 1st cell should contain interrupt router input hw number. + - If ti,intr-trigger-type is 15: must be 2 + The 1st cell should contain interrupt router input hw number. + The 2nd cell should contain interrupt trigger type (preserved by r= outer). =20 ti,interrupt-ranges: $ref: /schemas/types.yaml#/definitions/uint32-matrix @@ -82,6 +87,21 @@ properties: - description: | "limit" specifies the limit for translation =20 +if: + properties: + ti,intr-trigger-type: + enum: [1, 4] +then: + properties: + '#interrupt-cells': + const: 1 + description: Interrupt ID only. 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Tue, 20 Jan 2026 04:44:31 -0600 Received: from DFLE212.ent.ti.com (10.64.6.70) by DFLE203.ent.ti.com (10.64.6.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 20 Jan 2026 04:44:31 -0600 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE212.ent.ti.com (10.64.6.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Tue, 20 Jan 2026 04:44:31 -0600 Received: from psdkl-workstation0.dhcp.ti.com (psdkl-workstation0.dhcp.ti.com [172.24.234.127]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 60KAiIEh939676; Tue, 20 Jan 2026 04:44:27 -0600 From: Aniket Limaye Date: Tue, 20 Jan 2026 16:13:47 +0530 Subject: [PATCH v2 2/2] irqchip/ti-sci-intr: Allow parsing interrupt-types per-line Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260120-ul-driver-i2c-j722s-v2-2-832097c6b64f@ti.com> References: <20260120-ul-driver-i2c-j722s-v2-0-832097c6b64f@ti.com> In-Reply-To: <20260120-ul-driver-i2c-j722s-v2-0-832097c6b64f@ti.com> To: Vignesh Raghavendra , , Nishanth Menon , Tero Kristo , Santosh Shilimkar , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , Aniket Limaye X-Mailer: b4 0.14.3 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000468A:EE_|SJ0PR10MB5719:EE_ X-MS-Office365-Filtering-Correlation-Id: 50021586-ec26-46ba-b6a9-08de5810e654 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|36860700013; 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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 10:44:33.8984 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 50021586-ec26-46ba-b6a9-08de5810e654 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.195];Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468A.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR10MB5719 Some INTR router instances act as simple passthroughs that preserve the source interrupt type unchanged at the output line, rather than converting all interrupts to a fixed type. When interrupt sources are not homogeneous with respect to trigger type, the driver needs to read each source's interrupt type from DT and pass it unchanged to its interrupt parent. Add support for "ti,intr-trigger-type" =3D 15 (IRQ_TYPE_DEFAULT) to indicate passthrough mode. When set to 15, parse interrupt type per-line from the DT fwspec provided by the interrupt source. Else, use the global setting for all interrupt lines. Signed-off-by: Aniket Limaye --- Changes in v2: - Use correct Patch Subject prefix - Reword Commit msg to better describe the patch - Fix function argument alignment as per coding style - Fix variable declaration ordering as per coding style - Link to v1: https://lore.kernel.org/r/20260116-ul-driver-i2c-j722s-v1-2-c= 28e8ba38a9e@ti.com --- drivers/irqchip/irq-ti-sci-intr.c | 49 ++++++++++++++++++++++++++++++-----= ---- 1 file changed, 38 insertions(+), 11 deletions(-) diff --git a/drivers/irqchip/irq-ti-sci-intr.c b/drivers/irqchip/irq-ti-sci= -intr.c index 354613e74ad0..e0b06796c86e 100644 --- a/drivers/irqchip/irq-ti-sci-intr.c +++ b/drivers/irqchip/irq-ti-sci-intr.c @@ -61,11 +61,22 @@ static int ti_sci_intr_irq_domain_translate(struct irq_= domain *domain, { struct ti_sci_intr_irq_domain *intr =3D domain->host_data; =20 - if (fwspec->param_count !=3D 1) - return -EINVAL; =20 - *hwirq =3D fwspec->param[0]; - *type =3D intr->type; + if (intr->type !=3D IRQ_TYPE_DEFAULT) { + /* Global interrupt-type */ + if (fwspec->param_count !=3D 1) + return -EINVAL; + + *hwirq =3D fwspec->param[0]; + *type =3D intr->type; + } else { + /* Per-Line interrupt-type */ + if (fwspec->param_count !=3D 2) + return -EINVAL; + + *hwirq =3D fwspec->param[0]; + *type =3D fwspec->param[1]; + } =20 return 0; } @@ -128,11 +139,12 @@ static void ti_sci_intr_irq_domain_free(struct irq_do= main *domain, * @domain: Pointer to the interrupt router IRQ domain * @virq: Corresponding Linux virtual IRQ number * @hwirq: Corresponding hwirq for the IRQ within this IRQ domain + * @hwirq_type: Corresponding hwirq trigger type for the IRQ within this I= RQ domain * * Returns intr output irq if all went well else appropriate error pointer. */ static int ti_sci_intr_alloc_parent_irq(struct irq_domain *domain, - unsigned int virq, u32 hwirq) + unsigned int virq, u32 hwirq, u32 hwirq_type) { struct ti_sci_intr_irq_domain *intr =3D domain->host_data; struct device_node *parent_node; @@ -156,11 +168,26 @@ static int ti_sci_intr_alloc_parent_irq(struct irq_do= main *domain, fwspec.param_count =3D 3; fwspec.param[0] =3D 0; /* SPI */ fwspec.param[1] =3D p_hwirq - 32; /* SPI offset */ - fwspec.param[2] =3D intr->type; + fwspec.param[2] =3D hwirq_type; } else { /* Parent is Interrupt Router */ - fwspec.param_count =3D 1; - fwspec.param[0] =3D p_hwirq; + u32 parent_trigger_type; + + err =3D of_property_read_u32(parent_node, "ti,intr-trigger-type", + &parent_trigger_type); + if (err) + goto err_irqs; + + if (parent_trigger_type !=3D IRQ_TYPE_DEFAULT) { + /* Parent has global trigger type */ + fwspec.param_count =3D 1; + fwspec.param[0] =3D p_hwirq; + } else { + /* Parent supports per-line trigger types */ + fwspec.param_count =3D 2; + fwspec.param[0] =3D p_hwirq; + fwspec.param[1] =3D hwirq_type; + } } =20 err =3D irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec); @@ -196,15 +223,15 @@ static int ti_sci_intr_irq_domain_alloc(struct irq_do= main *domain, void *data) { struct irq_fwspec *fwspec =3D data; + unsigned int hwirq_type; unsigned long hwirq; - unsigned int flags; int err, out_irq; =20 - err =3D ti_sci_intr_irq_domain_translate(domain, fwspec, &hwirq, &flags); + err =3D ti_sci_intr_irq_domain_translate(domain, fwspec, &hwirq, &hwirq_t= ype); if (err) return err; =20 - out_irq =3D ti_sci_intr_alloc_parent_irq(domain, virq, hwirq); + out_irq =3D ti_sci_intr_alloc_parent_irq(domain, virq, hwirq, hwirq_type); if (out_irq < 0) return out_irq; =20 --=20 2.52.0