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[83.110.134.52]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4359314bbc6sm2404931f8f.12.2026.01.20.04.53.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jan 2026 04:53:58 -0800 (PST) From: Alexey Charkov Date: Tue, 20 Jan 2026 16:53:54 +0400 Subject: [PATCH v2] arm64: dts: rockchip: Explicitly request UFS reset pin on RK3576 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260120-ufs-rst-v2-1-b5735f1996f6@gmail.com> X-B4-Tracking: v=1; b=H4sIAOJ6b2kC/2XMQQ6CMBCF4auQWTumrQRbV97DsMA6hUmEkg4SD endrWxd/i8v3wZCiUngUm2QaGXhOJUwhwr80E09IT9Kg1GmUVo7fAXBJAuGcPeKvLWkzlDec6L A7126taUHliWmzw6v+rf+G6tGjd6Sa2p3crX1137s+Hn0cYQ25/wFnfrYUZ4AAAA= X-Change-ID: 20260119-ufs-rst-ffbc0ec88e07 To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , "Martin K. Petersen" , Shawn Lin , Manivannan Sadhasivam Cc: Quentin Schulz , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Alexey Charkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3949; i=alchark@gmail.com; h=from:subject:message-id; bh=rfOiA6dgd2q0nYUa0afVp2YzXs7KfO8y6Iz2Tj9FhBc=; b=owGbwMvMwCW2adGNfoHIK0sZT6slMWTmVz3XL1lyvd75GNP0eb61RZziFU95Xl/9JufO+euHZ 1/TbTO5joksDGJcDJZiiixzvy2xnWrEN2uXh8dXmDmsTCBDpEUaGICAhYEvNzGv1EjHSM9U21DP 0FDHWMeIgYtTAKZ6kgYjw5mWgCsLt615obBhzdf1sW2hq2tunGW/kRGw+7/1kR2F63QY/ns83rl iguGy5HC/X5uftM4tUF5Y53WUyeLuSZFLLwNOczAAAA== X-Developer-Key: i=alchark@gmail.com; a=openpgp; fpr=9DF6A43D95320E9ABA4848F5B2A2D88F1059D4A5 Rockchip RK3576 UFS controller uses a dedicated pin to reset the connected UFS device, which can operate either in a hardware controlled mode or as a GPIO pin. Power-on default is GPIO mode, but the boot ROM reconfigures it to a hardware controlled mode if it uses UFS to load the next boot stage. Given that existing bindings (and rk3576.dtsi) expect a GPIO-controlled device reset, request the required pin config explicitly. This doesn't appear to affect Linux, but it does affect U-boot: Before: =3D> md.l 0x2604b398 2604b398: 00000011 00000000 00000000 00000000 ................ < ... snip ... > =3D> ufs init ufshcd-rockchip ufshc@2a2d0000: [RX, TX]: gear=3D[3, 3], lane[2, 2], pwr[FA= STAUTO_MODE, FASTAUTO_MODE], rate =3D 2 =3D> md.l 0x2604b398 2604b398: 00000011 00000000 00000000 00000000 ................ After: =3D> md.l 0x2604b398 2604b398: 00000011 00000000 00000000 00000000 ................ < ... snip ...> =3D> ufs init ufshcd-rockchip ufshc@2a2d0000: [RX, TX]: gear=3D[3, 3], lane[2, 2], pwr[FA= STAUTO_MODE, FASTAUTO_MODE], rate =3D 2 =3D> md.l 0x2604b398 2604b398: 00000010 00000000 00000000 00000000 ................ (0x2604b398 is the respective pin mux register, with its BIT0 driving the mode of UFS_RST: unset =3D GPIO, set =3D hardware controlled UFS_RST) This helps ensure that GPIO-driven device reset actually fires when the system requests it, not when whatever black box magic inside the UFSHC decides to reset the flash chip. Cc: stable@vger.kernel.org Fixes: c75e5e010fef ("scsi: arm64: dts: rockchip: Add UFS support for RK357= 6 SoC") Reported-by: Quentin Schulz Signed-off-by: Alexey Charkov Reviewed-by: Quentin Schulz --- This has originally surfaced during the review of UFS patches for U-boot at [1], where it was found that the UFS reset line is not requested to be configured as GPIO but used as such. This leads in some cases to the UFS driver appearing to control device resets, while in fact it is the internal controller logic that drives the reset line (perhaps in unexpected ways). Thanks Quentin Schulz for spotting this issue. [1] https://lore.kernel.org/u-boot/259fc358-f72b-4a24-9a71-ad90f2081335@che= rry.de/ --- Changes in v2: - Change default pin pull to pull-down in line with the SoC power-on default - Link to v1: https://lore.kernel.org/r/20260119-ufs-rst-v1-1-c8e96493948c@= gmail.com --- arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi | 7 +++++++ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi b/arch/arm64/= boot/dts/rockchip/rk3576-pinctrl.dtsi index 0b0851a7e4ea..7bcfa393416f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi @@ -5228,6 +5228,13 @@ ufs_rst: ufs-rst { /* ufs_rstn */ <4 RK_PD0 1 &pcfg_pull_none>; }; + + /omit-if-no-ref/ + ufs_rst_gpio: ufs-rst-gpio { + rockchip,pins =3D + /* ufs_rstn */ + <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; =20 ufs_testdata0 { diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts= /rockchip/rk3576.dtsi index 3a29c627bf6d..db610f57c845 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1865,7 +1865,7 @@ ufshc: ufshc@2a2d0000 { assigned-clock-parents =3D <&cru CLK_REF_MPHY_26M>; interrupts =3D ; power-domains =3D <&power RK3576_PD_USB>; - pinctrl-0 =3D <&ufs_refclk>; + pinctrl-0 =3D <&ufs_refclk &ufs_rst_gpio>; pinctrl-names =3D "default"; resets =3D <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>, <&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>; --- base-commit: 46fe65a2c28ecf5df1a7475aba1f08ccf4c0ac1b change-id: 20260119-ufs-rst-ffbc0ec88e07 Best regards, --=20 Alexey Charkov