From nobody Mon Feb 9 13:11:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 83EA834A779; Tue, 20 Jan 2026 11:19:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768907992; cv=none; b=H7Am8HdrlF42DcDdSe2sYhv0R5JDJRGJBYKdof7mEtxWBjkBxKdMcvx2aFn9YJHmP3uQ1LzdOwU7FGa6jgxsUZWBZHy8juJIE9W8zVhfrd0+fNA1RVdVTEUx3R3EIbFlBRa6zuSVhkYHq2WjYtRQ3c1wGBSaywK+nr85EqKaaGU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768907992; c=relaxed/simple; bh=AWF1I4/2mnXqG5VXvaQF0vNKnvlUDNLbPYa6QfQQu7U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=W+C5GDIc3ZZH/sxiFwhJbLweZDeeHwSxUShKUQQOB8k3qRbWsxCe2GyqrHdUeGW00YBLTkNC6Ev/h6FoumtuseVnrHX9p79P3fPilxrDEsSNQFQyuNUFoNEpf80iY+Y3cY/fdFRMXPN85UXzKsT1/8D0xZ/O/M4VoobSpt5i20U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=s67FqRWK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="s67FqRWK" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 61EA9C19421; Tue, 20 Jan 2026 11:19:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1768907992; bh=AWF1I4/2mnXqG5VXvaQF0vNKnvlUDNLbPYa6QfQQu7U=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=s67FqRWKHPhVqgA/RDQWEP5DN5ejPAXPMpZ6il/EqoapjR5Myb8jQVVfmsUT3/vif OlTBaxNRynJULUEkwifr4wpl5VfpjRxn6AJwnpKl7RyJYNR85RzHHdjaieoNnWVElv +vAWkowBUWlCqeXIJeTgcda3ZrKajRSsv7u8nrBNnYIlJd8ypIWaB9kp5EvDC2lDow 7Pbp3tMV/wFXleY5p23KsDh6GbkXAvsbjw0RdRvP6EcSFRgkN4fJ24hBGllT/voGkE ftsTmxncYMy7nFrUQoboej0qVD+g9kw1wAhuXOOG5QK57ESLlCceRk7FCbqMeabbwq oJdhnhDj7ry2Q== From: Konrad Dybcio Date: Tue, 20 Jan 2026 12:19:25 +0100 Subject: [PATCH 1/3] dt-bindings: clock: qcom,dispcc-sc7180: Define MDSS resets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260120-topic-7180_dispcc_bcr-v1-1-0b1b442156c3@oss.qualcomm.com> References: <20260120-topic-7180_dispcc_bcr-v1-0-0b1b442156c3@oss.qualcomm.com> In-Reply-To: <20260120-topic-7180_dispcc_bcr-v1-0-0b1b442156c3@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , cros-qcom-dts-watchers@chromium.org, Konrad Dybcio , Kalyan Thota , Douglas Anderson , Harigovindan P Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768907983; l=1098; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=dXI3dItKonHkC7E3ASyfGG/IfR5PMoX/TLWS/5xG4JM=; b=xxHmqfKeY6/exGirICMt+f6z+PjvqnmpdkT2Fw8LAj3eB7ftLUleibngK9GhxGDuu1CbDBAyR hOdj5gr/gHQAJckaK4NqXZss6OF3lB4vtEX22i+NnvlUrynMf2TfrOo X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio The MDSS resets have so far been left undescribed. Fix that. Fixes: 75616da71291 ("dt-bindings: clock: Introduce QCOM sc7180 display clo= ck bindings") Signed-off-by: Konrad Dybcio Acked-by: Krzysztof Kozlowski Reviewed-by: Taniya Das Tested-by: Val Packett # sc7180-ecs-liva-qc710 --- include/dt-bindings/clock/qcom,dispcc-sc7180.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/qcom,dispcc-sc7180.h b/include/dt-bi= ndings/clock/qcom,dispcc-sc7180.h index b9b51617a335..070510306074 100644 --- a/include/dt-bindings/clock/qcom,dispcc-sc7180.h +++ b/include/dt-bindings/clock/qcom,dispcc-sc7180.h @@ -6,6 +6,7 @@ #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H =20 +/* Clocks */ #define DISP_CC_PLL0 0 #define DISP_CC_PLL0_OUT_EVEN 1 #define DISP_CC_MDSS_AHB_CLK 2 @@ -40,7 +41,11 @@ #define DISP_CC_MDSS_VSYNC_CLK_SRC 31 #define DISP_CC_XO_CLK 32 =20 -/* DISP_CC GDSCR */ +/* Resets */ +#define DISP_CC_MDSS_CORE_BCR 0 +#define DISP_CC_MDSS_RSCC_BCR 1 + +/* GDSCs */ #define MDSS_GDSC 0 =20 #endif --=20 2.52.0 From nobody Mon Feb 9 13:11:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15AAD421EE6; Tue, 20 Jan 2026 11:19:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768907997; cv=none; b=mrmZgg04TaypXW/UhxX8C9XgmAle7ry8BCHMlC6JqFgC2GGgd+hLON9JQUc4qHbs3jCH8/B7YGm9OkZ0X8mN2Tkjeq6OtoERAIElpJFFmBgtIrjUIeqGQu8dNO1RSFoj7+hu/rDERt+NS4ftH+KC0mizFPpcW186n8t+/uieMBg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768907997; c=relaxed/simple; bh=goKGK1LGG+MNlqbM0Sgh9lkoW+uoM9IRy49fxa/8P3Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Bt8oD75MgNkbyWJUMZucgMfQd42LO1VKUy1ZwKkotolmz6Yfn3K3q6DBeeyq/MQk3dyn0gU9jQPuMlAuMOFpHlsuY2vml4DyleAmJ7UttsrLZ7mP+G7lSsmOFVRdGZYBVMD/FLaJ8muRbGX+XQq7SlmkOe6lPwJnkt1GRZx+PJo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ISLRi0OO; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ISLRi0OO" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A5F95C19423; Tue, 20 Jan 2026 11:19:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1768907996; bh=goKGK1LGG+MNlqbM0Sgh9lkoW+uoM9IRy49fxa/8P3Y=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ISLRi0OOoediiMygI2Fi3wDlj1zAwl+4l6mcwIwLa6mgDHfbwL85objfTRFXkBZ27 arPuHGD8Nktszz1jwG7xGXOsnNq0u+LsrVC9XwABpaImlPqbGgsrrkJCOQ+NhRo/Aq jP7hCe1a7YqJzTXe3E8qwSgxUTnQBXKLVjQpizNdWTqqScejRvEMoEPlYVW9ZzCE9r kjhwg5H0fhN+wLCkzRJUs+wWNkPWvADM5xvjuHQwCMHbMeRiuui5x2IWN6Q1LwRWgJ 3ToIgqmDljk2IoQ/YMYEQrsK207U5oIoayAamL+yKzIiK169FIhyQbhJJTJuJrqYt5 fY4pK+yJPksPw== From: Konrad Dybcio Date: Tue, 20 Jan 2026 12:19:26 +0100 Subject: [PATCH 2/3] clk: qcom: dispcc-sc7180: Add missing MDSS resets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260120-topic-7180_dispcc_bcr-v1-2-0b1b442156c3@oss.qualcomm.com> References: <20260120-topic-7180_dispcc_bcr-v1-0-0b1b442156c3@oss.qualcomm.com> In-Reply-To: <20260120-topic-7180_dispcc_bcr-v1-0-0b1b442156c3@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , cros-qcom-dts-watchers@chromium.org, Konrad Dybcio , Kalyan Thota , Douglas Anderson , Harigovindan P Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768907983; l=1364; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=5uioIRX5bNPGEXJdAqjegWWAkYww9nYj6t1Oh9jO/1c=; b=6Jqee0Y1Z1DmVLI92TbHkYsSH7bhZvOETJGTdZ4GK+gHDRKvnNhLmbbpI9ebK7hm6U4CbqqTV 6dbj1baPOmzBHped3k0ti9iYtA/+wEJsgfb3vSpa8f2q2aI6h8BXrtS X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio The MDSS resets have so far been left undescribed. Fix that. Fixes: dd3d06622138 ("clk: qcom: Add display clock controller driver for SC= 7180") Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Reviewed-by: Taniya Das Tested-by: Val Packett # sc7180-ecs-liva-qc710 --- drivers/clk/qcom/dispcc-sc7180.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/qcom/dispcc-sc7180.c b/drivers/clk/qcom/dispcc-sc7= 180.c index ab1a8d419863..d7e37fbbe87e 100644 --- a/drivers/clk/qcom/dispcc-sc7180.c +++ b/drivers/clk/qcom/dispcc-sc7180.c @@ -17,6 +17,7 @@ #include "clk-regmap-divider.h" #include "common.h" #include "gdsc.h" +#include "reset.h" =20 enum { P_BI_TCXO, @@ -636,6 +637,11 @@ static struct gdsc mdss_gdsc =3D { .flags =3D HW_CTRL, }; =20 +static const struct qcom_reset_map disp_cc_sc7180_resets[] =3D { + [DISP_CC_MDSS_CORE_BCR] =3D { 0x2000 }, + [DISP_CC_MDSS_RSCC_BCR] =3D { 0x4000 }, +}; + static struct gdsc *disp_cc_sc7180_gdscs[] =3D { [MDSS_GDSC] =3D &mdss_gdsc, }; @@ -687,6 +693,8 @@ static const struct qcom_cc_desc disp_cc_sc7180_desc = =3D { .config =3D &disp_cc_sc7180_regmap_config, .clks =3D disp_cc_sc7180_clocks, .num_clks =3D ARRAY_SIZE(disp_cc_sc7180_clocks), + .resets =3D disp_cc_sc7180_resets, + .num_resets =3D ARRAY_SIZE(disp_cc_sc7180_resets), .gdscs =3D disp_cc_sc7180_gdscs, .num_gdscs =3D ARRAY_SIZE(disp_cc_sc7180_gdscs), }; --=20 2.52.0 From nobody Mon Feb 9 13:11:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70E294219E3; Tue, 20 Jan 2026 11:20:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768908001; cv=none; b=HMK/cDKWZCbN4djZYpBAiC6LwK0lffCwGOzl0dwa0FwBPfdVL4MgTwASjc5ReMsPjImk/d5ZmdU2/dEY9zLzi1qL6jX1NUOH2qrXgNK86WVuxX35MD9oC4nL6OG3HHQDdlA6vyxFbq9iaQGB4A9CfvtL+HGrk0/nkzoa5Vc0+EM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768908001; c=relaxed/simple; bh=lXA7xXuvlXD/gm2j6AzGoRANYcJpsALguHdGsdxgbr8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=orxw3ZPsimRzQvq2oa9JG9RceSyR1neLRi6Eo1xdGG0rvI3rplt8jFY8fG/rdzuFFrsQvbxbo9rEE9M2JrEssF/e51mM5/xNslVuW25qVsFEsRDgZDefHZoGGUB0yAt6vGJx3Y+EyAi1/hMRIXPjS9X6EpNNymBr5g6yZKvNHU8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lbnFej/q; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lbnFej/q" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3308AC19421; Tue, 20 Jan 2026 11:19:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1768908001; bh=lXA7xXuvlXD/gm2j6AzGoRANYcJpsALguHdGsdxgbr8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=lbnFej/qP5JCu9kfvaDXL80HYnJDqnMvFP8BPBuzA8fVFlK++F1VUZ7WKraKIyoIJ IM2f9KeTbNcmZ6/H9562eRpu+N856RRJNgCSHCquZcZUJpcBqIj52iJdwhkt1UPMOt 8mkLu/ASxQxJZX4K1T3NvW3i54SplCU82uFv+RCckEBUOR1QtwhRVnDoEEG7b+JJTR dN2Oq+Cw25QGHZKzCAEfy1VphayrJI2HvjvroCj8i5JWjFjgKcmWdt9uFz3KqeCmbG RDrKIlS+OjQHslaiuQTcEmKpkqdoN2xpQyXZluW8O0ujxMWFKWcXTJKYnj9NKQmmJP uQLHD0LPsC6pA== From: Konrad Dybcio Date: Tue, 20 Jan 2026 12:19:27 +0100 Subject: [PATCH 3/3] arm64: dts: qcom: sc7180: Add missing MDSS core reset Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260120-topic-7180_dispcc_bcr-v1-3-0b1b442156c3@oss.qualcomm.com> References: <20260120-topic-7180_dispcc_bcr-v1-0-0b1b442156c3@oss.qualcomm.com> In-Reply-To: <20260120-topic-7180_dispcc_bcr-v1-0-0b1b442156c3@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , cros-qcom-dts-watchers@chromium.org, Konrad Dybcio , Kalyan Thota , Douglas Anderson , Harigovindan P Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Val Packett X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768907983; l=955; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=2dPiGu+ReEYYtC3VfBXo5TkLCObP/kpIYgcp9+6W0CY=; b=8m45au3DfCytfz4q/h/ct8eXpl+zTmaFd3jee3fUxwb2ygnA2ZWdgHgTB90TO1xXD16M0pENe etrAmbi6yeJDL/V4gf0h2PQKcvcc5G/zJupSWyvh7e9v4HcUL+3YSzb X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio To make sure the core starts in a predictable state, it's useful to first reset it. Wire up the reset to fulfill that missing part of the HW description. Reported-by: Val Packett Fixes: a3db7ad1af49 ("arm64: dts: sc7180: add display dt nodes") Signed-off-by: Konrad Dybcio Tested-by: Val Packett # sc7180-ecs-liva-qc710 --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qco= m/sc7180.dtsi index 45b9864e3304..f7937fa88536 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3221,6 +3221,8 @@ mdss: display-subsystem@ae00000 { <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names =3D "iface", "ahb", "core"; =20 + resets =3D <&dispcc DISPCC_MDSS_CORE_BCR>; + interrupts =3D ; interrupt-controller; #interrupt-cells =3D <1>; --=20 2.52.0