From nobody Mon Feb 9 04:03:42 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A91C42D46A9 for ; Mon, 19 Jan 2026 19:50:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768852261; cv=none; b=dUjiDQ9gsbhFewjD6sZLl8fzsAh2VKQETNsBryfEj69DVjAx/+5dImwoALw1kP08WfgWyoqAErl7JIBDmsh937bxbIJHWBrGxw2XR7dfKJMsT0XzV5dDYQZqxnP4fMj9O+JaIQd0F5oToZCrQXsQCYQI2FvM8tITa7jrcU3d4WI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768852261; c=relaxed/simple; bh=nnICPMYogrU7JrvgjXgmhEXg2sYtJSi3orub4d6EoS4=; h=Subject:To:Cc:From:Date:References:In-Reply-To:Message-Id; b=TfvPmhtvHIWJ8EFyyjLr5Rb0xUKro5EKV3rne4dE8ACKxGFmBwbWmt0djkMqDmf9LZr07e3azwQ9B/gO5vjka1zrTIzAZp7EAblwY1Ef3kDRXggyfKIDZjkxniPpVChBbrQN5jL8ksoLp553+lEtXfUB84SEvStra1896eqz/6E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=IBoNAYkA; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="IBoNAYkA" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768852257; x=1800388257; h=subject:to:cc:from:date:references:in-reply-to: message-id; bh=nnICPMYogrU7JrvgjXgmhEXg2sYtJSi3orub4d6EoS4=; b=IBoNAYkAMiAKafsQTA9ov7SsODI7CgchNT54pQ/+dUSRH67qthzO7Qdl ZKuMpFeyhlufC7QZ1BjFSdoOoBNKrD48Ee4eYJTgtyaDnalEcRKs3pb/I AGSBb2D1lTjbmJggfQhzDrEz/aysRAXSGlBbSpidEpkqFgHNMLFoKd8X+ FWSeXMmNWYOOjzWsKz8g19Dy9ii+o+snqXqxG0mXjPqPCEN9wdCrQTwEa 06T/ViIS5DfiiT5KyIPJATWaBTVFdyM53VyksbH+5nCFndD31ejhsZDfC ULUGSpDeQwVM8YAarYDEwhLPCPUZ9YXrYMKGc3yvzU6gaAnAfFG5Sm4XP g==; X-CSE-ConnectionGUID: mNMWaAnGQ5Cm5VRlTli1IA== X-CSE-MsgGUID: WLlm943WTW2F52D23wzX7Q== X-IronPort-AV: E=McAfee;i="6800,10657,11676"; a="57623080" X-IronPort-AV: E=Sophos;i="6.21,238,1763452800"; d="scan'208";a="57623080" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jan 2026 11:50:56 -0800 X-CSE-ConnectionGUID: 17q24TDrQ7+VPjV9GMpfpA== X-CSE-MsgGUID: uHiNYeDwQ/i/MQ2R+Ne+5A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,238,1763452800"; d="scan'208";a="210786576" Received: from davehans-spike.ostc.intel.com (HELO localhost.localdomain) ([10.165.164.11]) by fmviesa004.fm.intel.com with ESMTP; 19 Jan 2026 11:50:56 -0800 Subject: [PATCH 4/6] x86/cpu: Add platform ID to CPU info structure To: linux-kernel@vger.kernel.org Cc: sohil.mehta@intel.com, Dave Hansen , Borislav Petkov , "H. Peter Anvin" , Ingo Molnar , Jon Kohler , Pawan Gupta , "Peter Zijlstra (Intel)" , Thomas Gleixner , Tony Luck , x86@kernel.org From: Dave Hansen Date: Mon, 19 Jan 2026 11:50:55 -0800 References: <20260119195047.86E3C696@davehans-spike.ostc.intel.com> In-Reply-To: <20260119195047.86E3C696@davehans-spike.ostc.intel.com> Message-Id: <20260119195055.0B00B57E@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen The end goal here is to be able to do x86_match_cpu() and match on a specific platform ID. While it would be possible to stash this ID off somewhere or read it dynamically, that approaches would not be consistent with the other fields which can be matched. Read the platform ID and store it in cpuinfo_x86->x86_platform_id. There are lots of sites to set this new field. Place it near the place c->microcode is established since the platform ID is so closely intertwined with microcode updates. Note: This should not grow the size of 'struct cpuinfo_x86' in practice since the u8 fits next to another u8 in the structure. Signed-off-by: Dave Hansen Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Borislav Petkov Cc: Dave Hansen Cc: "H. Peter Anvin" Cc: Tony Luck Cc: Pawan Gupta Cc: "Peter Zijlstra (Intel)" Cc: x86@kernel.org Cc: Jon Kohler --- b/arch/x86/include/asm/processor.h | 1 + b/arch/x86/kernel/cpu/common.c | 4 +++- b/arch/x86/kernel/cpu/intel.c | 1 + 3 files changed, 5 insertions(+), 1 deletion(-) diff -puN arch/x86/include/asm/processor.h~cpu-x86_stepping arch/x86/includ= e/asm/processor.h --- a/arch/x86/include/asm/processor.h~cpu-x86_stepping 2026-01-19 11:38:09= .341914025 -0800 +++ b/arch/x86/include/asm/processor.h 2026-01-19 11:38:09.444917962 -0800 @@ -140,6 +140,7 @@ struct cpuinfo_x86 { __u32 x86_vfm; }; __u8 x86_stepping; + __u8 x86_platform_id; /* Intel-only. 3 bits */ #ifdef CONFIG_X86_64 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ int x86_tlbsize; diff -puN arch/x86/kernel/cpu/common.c~cpu-x86_stepping arch/x86/kernel/cpu= /common.c --- a/arch/x86/kernel/cpu/common.c~cpu-x86_stepping 2026-01-19 11:38:09.428= 917350 -0800 +++ b/arch/x86/kernel/cpu/common.c 2026-01-19 11:38:09.445918000 -0800 @@ -1981,7 +1981,9 @@ static void identify_cpu(struct cpuinfo_ c->loops_per_jiffy =3D loops_per_jiffy; c->x86_cache_size =3D 0; c->x86_vendor =3D X86_VENDOR_UNKNOWN; - c->x86_model =3D c->x86_stepping =3D 0; /* So far unknown... */ + c->x86_model =3D 0; + c->x86_stepping =3D 0; + c->x86_platform_id =3D 0; c->x86_vendor_id[0] =3D '\0'; /* Unset */ c->x86_model_id[0] =3D '\0'; /* Unset */ #ifdef CONFIG_X86_64 diff -puN arch/x86/kernel/cpu/intel.c~cpu-x86_stepping arch/x86/kernel/cpu/= intel.c --- a/arch/x86/kernel/cpu/intel.c~cpu-x86_stepping 2026-01-19 11:38:09.4419= 17848 -0800 +++ b/arch/x86/kernel/cpu/intel.c 2026-01-19 11:38:09.445918000 -0800 @@ -205,6 +205,7 @@ static void early_init_intel(struct cpui =20 if (c->x86 >=3D 6 && !cpu_has(c, X86_FEATURE_IA64)) c->microcode =3D intel_get_microcode_revision(); + c->x86_platform_id =3D intel_get_platform_id(); =20 /* Now if any of them are set, check the blacklist and clear the lot */ if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) || _