From nobody Sun Feb 8 09:11:10 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C56E92741B5 for ; Mon, 19 Jan 2026 19:50:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768852252; cv=none; b=r0OudDOcxqMKPgOMxJ+sS4zW2WtJvlR4IjTRn7s4icriOeYYOnzmNtOYSxzLzqF6p4xCYY4fEVyW/FdiR4hkaoya8qTJZl8Ay+ozLzQ0BRphiFxinAV3TEbfdxCEVm6X7QuUXuJryVMD4Jwb6gAMUPobxv4KjCiMLdg+2YsgCCc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768852252; c=relaxed/simple; bh=YNJ7izt4sOz1UMackROPNeT2WK37KjKCDMC5eJjUxrA=; h=Subject:To:Cc:From:Date:References:In-Reply-To:Message-Id; b=AE+MauHXxwn610rEm1um9G2kPcpi15thZLYZuROG2zFVat7elrGjLZ4qm3MS34+M4O0S0AZ9PO3Sbcq8UV/jRYIBYEDdH6ERR2/nlG6gIGv9ab76uVdLByw7HFzZDkaWDCaJA0Qm3w5YaZom3Z17CJhZOYkXytnCeBJ6eVzfmFk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=O+KuAdKZ; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="O+KuAdKZ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768852251; x=1800388251; h=subject:to:cc:from:date:references:in-reply-to: message-id; bh=YNJ7izt4sOz1UMackROPNeT2WK37KjKCDMC5eJjUxrA=; b=O+KuAdKZkl4VMPIcbCi52KdTc+278OrHU1fm2kBFdKEJH1DkUffIjK+k pUXkEqwM+ym94Sftlpyd5R2iRcij6/Uccsog4Yl0ieNdljngwgQrEP78b 0hUIlT12cD4pv37kXS1Uy/6yBdAkzbb5DfCM7PU6QRBv5sWgZllaLBogX WdOZBztf9SOJ4MQB9lMGwSLVD8LkBakut5wXazuKaZ4pQdZxHMosVZg/t 2srvra72+rcpWuTqeYisGtraEoOzy/7tYRxHF/qsDWDc1yDc/19yGtIOJ 5+eIk3EfPklnb6Mt5c+OgjLVqQWq3slRzVcxImJtfgrGIKq/0tnfxgV5R w==; X-CSE-ConnectionGUID: veXb+g7AR+u10xKyeIwE9Q== X-CSE-MsgGUID: Z6tVohefQXey0yqoJzFy7A== X-IronPort-AV: E=McAfee;i="6800,10657,11676"; a="57623056" X-IronPort-AV: E=Sophos;i="6.21,238,1763452800"; d="scan'208";a="57623056" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jan 2026 11:50:50 -0800 X-CSE-ConnectionGUID: Zr4DzgpZQBeDP0zeehw3fw== X-CSE-MsgGUID: lE+bvA+dTHi3yK2fKbR2JQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,238,1763452800"; d="scan'208";a="210786557" Received: from davehans-spike.ostc.intel.com (HELO localhost.localdomain) ([10.165.164.11]) by fmviesa004.fm.intel.com with ESMTP; 19 Jan 2026 11:50:50 -0800 Subject: [PATCH 1/6] x86/cpu: Break Vendor/Family/Model macros into separate header To: linux-kernel@vger.kernel.org Cc: sohil.mehta@intel.com, Dave Hansen , Borislav Petkov , "H. Peter Anvin" , Ingo Molnar , Jon Kohler , Pawan Gupta , "Peter Zijlstra (Intel)" , Thomas Gleixner , Tony Luck , x86@kernel.org From: Dave Hansen Date: Mon, 19 Jan 2026 11:50:49 -0800 References: <20260119195047.86E3C696@davehans-spike.ostc.intel.com> In-Reply-To: <20260119195047.86E3C696@davehans-spike.ostc.intel.com> Message-Id: <20260119195049.43DDFD4E@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen The intel-family.h header uses Vendor/Family/Model macros but it does not #include the header where they are defined. If that header is included, the build blows up in #include hell. Luckily, these macros are completely independent and do not themselves have any dependencies on other code. Break the VFM_*() macros out into their own header. Signed-off-by: Dave Hansen Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Borislav Petkov Cc: Dave Hansen Cc: "H. Peter Anvin" Cc: Tony Luck Cc: Pawan Gupta Cc: "Peter Zijlstra (Intel)" Cc: x86@kernel.org Cc: Jon Kohler Tested-by: Ricardo Neri --- b/arch/x86/include/asm/cpu_device_id.h | 33 ---------------------------- b/arch/x86/include/asm/vfm.h | 38 ++++++++++++++++++++++++++++= +++++ 2 files changed, 39 insertions(+), 32 deletions(-) diff -puN arch/x86/include/asm/cpu_device_id.h~x86-vfm_h arch/x86/include/a= sm/cpu_device_id.h --- a/arch/x86/include/asm/cpu_device_id.h~x86-vfm_h 2026-01-19 11:38:07.71= 4851835 -0800 +++ b/arch/x86/include/asm/cpu_device_id.h 2026-01-19 11:38:07.717851949 -0= 800 @@ -2,38 +2,7 @@ #ifndef _ASM_X86_CPU_DEVICE_ID #define _ASM_X86_CPU_DEVICE_ID =20 -/* - * Can't use because it generates expressions that - * cannot be used in structure initializers. Bitfield construction - * here must match the union in struct cpuinfo_86: - * union { - * struct { - * __u8 x86_model; - * __u8 x86; - * __u8 x86_vendor; - * __u8 x86_reserved; - * }; - * __u32 x86_vfm; - * }; - */ -#define VFM_MODEL_BIT 0 -#define VFM_FAMILY_BIT 8 -#define VFM_VENDOR_BIT 16 -#define VFM_RSVD_BIT 24 - -#define VFM_MODEL_MASK GENMASK(VFM_FAMILY_BIT - 1, VFM_MODEL_BIT) -#define VFM_FAMILY_MASK GENMASK(VFM_VENDOR_BIT - 1, VFM_FAMILY_BIT) -#define VFM_VENDOR_MASK GENMASK(VFM_RSVD_BIT - 1, VFM_VENDOR_BIT) - -#define VFM_MODEL(vfm) (((vfm) & VFM_MODEL_MASK) >> VFM_MODEL_BIT) -#define VFM_FAMILY(vfm) (((vfm) & VFM_FAMILY_MASK) >> VFM_FAMILY_BIT) -#define VFM_VENDOR(vfm) (((vfm) & VFM_VENDOR_MASK) >> VFM_VENDOR_BIT) - -#define VFM_MAKE(_vendor, _family, _model) ( \ - ((_model) << VFM_MODEL_BIT) | \ - ((_family) << VFM_FAMILY_BIT) | \ - ((_vendor) << VFM_VENDOR_BIT) \ -) +#include =20 /* * Declare drivers belonging to specific x86 CPUs diff -puN /dev/null arch/x86/include/asm/vfm.h --- /dev/null 2025-12-13 18:24:00.793641044 -0800 +++ b/arch/x86/include/asm/vfm.h 2026-01-19 11:38:07.717851949 -0800 @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_VFM +#define _ASM_X86_VFM + +/* + * Can't use because it generates expressions that + * cannot be used in structure initializers. Bitfield construction + * here must match the union in struct cpuinfo_86: + * union { + * struct { + * __u8 x86_model; + * __u8 x86; + * __u8 x86_vendor; + * __u8 x86_reserved; + * }; + * __u32 x86_vfm; + * }; + */ +#define VFM_MODEL_BIT 0 +#define VFM_FAMILY_BIT 8 +#define VFM_VENDOR_BIT 16 +#define VFM_RSVD_BIT 24 + +#define VFM_MODEL_MASK GENMASK(VFM_FAMILY_BIT - 1, VFM_MODEL_BIT) +#define VFM_FAMILY_MASK GENMASK(VFM_VENDOR_BIT - 1, VFM_FAMILY_BIT) +#define VFM_VENDOR_MASK GENMASK(VFM_RSVD_BIT - 1, VFM_VENDOR_BIT) + +#define VFM_MODEL(vfm) (((vfm) & VFM_MODEL_MASK) >> VFM_MODEL_BIT) +#define VFM_FAMILY(vfm) (((vfm) & VFM_FAMILY_MASK) >> VFM_FAMILY_BIT) +#define VFM_VENDOR(vfm) (((vfm) & VFM_VENDOR_MASK) >> VFM_VENDOR_BIT) + +#define VFM_MAKE(_vendor, _family, _model) ( \ + ((_model) << VFM_MODEL_BIT) | \ + ((_family) << VFM_FAMILY_BIT) | \ + ((_vendor) << VFM_VENDOR_BIT) \ +) + +#endif /* _ASM_X86_VFM */ _ From nobody Sun Feb 8 09:11:10 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 351D92E0412 for ; Mon, 19 Jan 2026 19:50:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768852256; cv=none; b=nJRx2EN8p0UC1yw0whs+1HymXkeEHXBsoXVL5ZeWeaCweRWgKIQy2U2TaLK/WRm/kY5LMFIK1Rfrvps7FbOj6xL1g9Xf7EoyPlcSkxyYDMqC4mu7gIVgc7BSxtXv2xLfkMW8rwd7WCqgPAtnrAbIWjyTx4IKyrdjCWQEW/uJItM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768852256; c=relaxed/simple; bh=Ax6t49Zw2uURym0bObMkQeo7NHZCFeRTq94vP4UBKWw=; h=Subject:To:Cc:From:Date:References:In-Reply-To:Message-Id; b=mmoiD74m1jFTIqtFljMg4KjiWPVcjRa7JtiZvQ9APD9ZHqHY67fHfIe70+r3OPt+1dA3fZ2RJ+VAHrpgBNCMaUtFkiXNjEO09Rgbaxixz5i4iTwZudl0ihydcfnWut3Zu2twov2NeaiXA/2SzUs7Yofnhb/fmrVYLNmA68TCbg8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=nyMbN8f6; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nyMbN8f6" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768852253; x=1800388253; h=subject:to:cc:from:date:references:in-reply-to: message-id; bh=Ax6t49Zw2uURym0bObMkQeo7NHZCFeRTq94vP4UBKWw=; b=nyMbN8f6vMcsgMBBH2clVLwR2oBPV3HG+w1O1t3CCkHrZLKnXK+vKWf0 Qu6u0Ak6/Jl1PxWIKqwW7JdBb5y32zhbImp0XWLOzg143yKXpVAN5FsR6 nvTtegHswABS9mE9c/CSXjuupQvLaSRNcRDZZGaDNsO3eVF7cjfCurbxM 9D96Wf40DYAGEGMFq5cJbgOcSVFo0GQLJaG5lAby7nHjeeQ9yv0WOGDNC /eAnhvXkNnbyW7/MJjgDDeH1ii7d64dbFhtwi8T5y43x6bFhIbI6AkA0P fd9+ghwlIfb9QlesnxJJ+lu7PhM9RXgPGYcHJx1BaBJbIIZ3ScFuQ1bJE Q==; X-CSE-ConnectionGUID: ku6r7FP4R0uGCGxwaTCpbg== X-CSE-MsgGUID: NgyTsb45RmakmBCpT0t6/A== X-IronPort-AV: E=McAfee;i="6800,10657,11676"; a="57623063" X-IronPort-AV: E=Sophos;i="6.21,238,1763452800"; d="scan'208";a="57623063" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jan 2026 11:50:53 -0800 X-CSE-ConnectionGUID: wDfw+4fLRWaMpfshX14a0Q== X-CSE-MsgGUID: rEnOTDJtT7GCkmCXSY5JOw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,238,1763452800"; d="scan'208";a="210786569" Received: from davehans-spike.ostc.intel.com (HELO localhost.localdomain) ([10.165.164.11]) by fmviesa004.fm.intel.com with ESMTP; 19 Jan 2026 11:50:52 -0800 Subject: [PATCH 2/6] x86/cpu: Add missing #include To: linux-kernel@vger.kernel.org Cc: sohil.mehta@intel.com, Dave Hansen , Borislav Petkov , "H. Peter Anvin" , Ingo Molnar , Jon Kohler , Pawan Gupta , "Peter Zijlstra (Intel)" , Thomas Gleixner , Tony Luck , x86@kernel.org From: Dave Hansen Date: Mon, 19 Jan 2026 11:50:51 -0800 References: <20260119195047.86E3C696@davehans-spike.ostc.intel.com> In-Reply-To: <20260119195047.86E3C696@davehans-spike.ostc.intel.com> Message-Id: <20260119195051.4235E147@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen The intel-family.h header uses Vendor/Family/Model macros but it does not #include the header where they are defined. It must be depending on implicit includes. Include the required header explicitly. Signed-off-by: Dave Hansen Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Borislav Petkov Cc: Dave Hansen Cc: "H. Peter Anvin" Cc: Tony Luck Cc: Pawan Gupta Cc: "Peter Zijlstra (Intel)" Cc: x86@kernel.org Cc: Jon Kohler Tested-by: Ricardo Neri --- b/arch/x86/include/asm/intel-family.h | 2 ++ 1 file changed, 2 insertions(+) diff -puN arch/x86/include/asm/intel-family.h~fam-missing-include arch/x86/= include/asm/intel-family.h --- a/arch/x86/include/asm/intel-family.h~fam-missing-include 2026-01-19 11= :38:08.254872476 -0800 +++ b/arch/x86/include/asm/intel-family.h 2026-01-19 11:38:08.257872590 -08= 00 @@ -2,6 +2,8 @@ #ifndef _ASM_X86_INTEL_FAMILY_H #define _ASM_X86_INTEL_FAMILY_H =20 +#include + /* * "Big Core" Processors (Branded as Core, Xeon, etc...) * _ From nobody Sun Feb 8 09:11:10 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D115283C89 for ; Mon, 19 Jan 2026 19:50:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768852256; cv=none; b=JOvy1GsDRSvizY+4ETsiTEFPIwoyCffLO9t4Ri1eJ5OBSQakaVpRGFCLuMzcxeMMd2GcE+m6ECWR/Q0+PRt5oRYq28ZMvJfT5xL7692dpss3EqpqxLBiKYM5XgurWD1VW6C4gQsXVHyn0wuSCbkH1ls5KP7N3gC9n+rv/vGo10o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768852256; c=relaxed/simple; bh=js/tbUrWHL1+HK8ri0RL7x8munS7AvU/zHUUf643g/8=; h=Subject:To:Cc:From:Date:References:In-Reply-To:Message-Id; b=LfeV979vxTDcpdAnsEeaRtUTbVGAZdbO06CZHdeB6E5LJVRr6OxUjjWwQH2D+POsOzqjKv7SR+vS/0h2MqOszDp6CnzGg35hcFporSvEb7I0QwQWUEp9N9Osk+1cWkuzjd5K1HsY4bgrHvStruxF10SG1l1UeF6epekTHKe2a+Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ZFkghx8h; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ZFkghx8h" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768852255; x=1800388255; h=subject:to:cc:from:date:references:in-reply-to: message-id; bh=js/tbUrWHL1+HK8ri0RL7x8munS7AvU/zHUUf643g/8=; b=ZFkghx8hhbngnpoYO48IFb0Q68rsj3qTD52eFbuUFMqLo4EXNcE8XaCO Wbq4E3ICwkZolx2w1pr3eIYIBuDAHRVOEHmVdeFpLpXnYDONdzJ4dH1dr dMbD1JJIYOZL00nn9SzHeQAa0iBqrW+UFyWugccYxZHMcthFjswb3Q8NW Z52ztEVgwSUZYkEM+ZG51frmKZYokAdwGTwak7fnyc2U9jpPdbVk4P67X kPFKjYEfuc46mVYUr+V5ttpi26itw1GJKZV0T3c95Fvb7mq0fcXWsimuG kzzAcRsnInXp/T/GCLrnAQ0E46MCvn7nsrBFO8psiqqEVVbRPWWZRKsfK w==; X-CSE-ConnectionGUID: OB17eZn6QnWuF6VndshgXA== X-CSE-MsgGUID: wbai5N7gS1WILeCbeAJWLg== X-IronPort-AV: E=McAfee;i="6800,10657,11676"; a="57623072" X-IronPort-AV: E=Sophos;i="6.21,238,1763452800"; d="scan'208";a="57623072" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jan 2026 11:50:55 -0800 X-CSE-ConnectionGUID: Gj3aadFLTzGKE83a7RyF+A== X-CSE-MsgGUID: 5DapstgWT1e1UK1e6L26Xw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,238,1763452800"; d="scan'208";a="210786572" Received: from davehans-spike.ostc.intel.com (HELO localhost.localdomain) ([10.165.164.11]) by fmviesa004.fm.intel.com with ESMTP; 19 Jan 2026 11:50:54 -0800 Subject: [PATCH 3/6] x86/microcode: Refactor platform ID enumeration into a helper To: linux-kernel@vger.kernel.org Cc: sohil.mehta@intel.com, Dave Hansen , Borislav Petkov , "H. Peter Anvin" , Ingo Molnar , Jon Kohler , Pawan Gupta , "Peter Zijlstra (Intel)" , Thomas Gleixner , Tony Luck , x86@kernel.org From: Dave Hansen Date: Mon, 19 Jan 2026 11:50:53 -0800 References: <20260119195047.86E3C696@davehans-spike.ostc.intel.com> In-Reply-To: <20260119195047.86E3C696@davehans-spike.ostc.intel.com> Message-Id: <20260119195053.E0850F99@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen The only code that cares about the platform ID is the microcode update code itself. To facilitate storing the platform ID in a more generic place and using it outside of the microcode update itself, put the enumeration into a helper function in a header. Mirror intel_get_microcode_revision()'s naming and location. But, moving away from intel_collect_cpu_info() means that the model and family information in CPUID is not readily available. Just call CPUID again. Signed-off-by: Dave Hansen Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Borislav Petkov Cc: Dave Hansen Cc: "H. Peter Anvin" Cc: Tony Luck Cc: Pawan Gupta Cc: "Peter Zijlstra (Intel)" Cc: x86@kernel.org Cc: Jon Kohler Tested-by: Ricardo Neri --- b/arch/x86/include/asm/microcode.h | 31 +++++++++++++++++++++++++++= ++++ b/arch/x86/kernel/cpu/microcode/intel.c | 10 +--------- 2 files changed, 32 insertions(+), 9 deletions(-) diff -puN arch/x86/include/asm/microcode.h~refactor-get-processor-flags arc= h/x86/include/asm/microcode.h --- a/arch/x86/include/asm/microcode.h~refactor-get-processor-flags 2026-01= -19 11:38:08.775892390 -0800 +++ b/arch/x86/include/asm/microcode.h 2026-01-19 11:38:08.783892696 -0800 @@ -2,7 +2,9 @@ #ifndef _ASM_X86_MICROCODE_H #define _ASM_X86_MICROCODE_H =20 +#include #include +#include =20 struct cpu_signature { unsigned int sig; @@ -75,6 +77,35 @@ static inline u32 intel_get_microcode_re =20 return rev; } + +/* + * Use CPUID to generate a "vfm" value. Useful + * before 'cpuinfo_x86' structures are populated. + */ +static inline u32 intel_cpuid_vfm(void) +{ + u32 eax =3D cpuid_eax(1); + u32 fam =3D x86_family(eax); + u32 model =3D x86_model(eax); + + return IFM(fam, model); +} + +static inline u32 intel_get_platform_id(void) +{ + unsigned int val[2]; + + /* + * This can be called early. Use CPUID directly to + * generate the VFM value for this CPU. + */ + if (intel_cpuid_vfm() < INTEL_PENTIUM_III_DESCHUTES) + return 0; + + /* get processor flags from MSR 0x17 */ + native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); + return 1 << ((val[1] >> 18) & 7); +} #endif /* !CONFIG_CPU_SUP_INTEL */ =20 bool microcode_nmi_handler(void); diff -puN arch/x86/kernel/cpu/microcode/intel.c~refactor-get-processor-flag= s arch/x86/kernel/cpu/microcode/intel.c --- a/arch/x86/kernel/cpu/microcode/intel.c~refactor-get-processor-flags 20= 26-01-19 11:38:08.780892582 -0800 +++ b/arch/x86/kernel/cpu/microcode/intel.c 2026-01-19 11:38:08.783892696 -= 0800 @@ -123,16 +123,8 @@ static inline unsigned int exttable_size void intel_collect_cpu_info(struct cpu_signature *sig) { sig->sig =3D cpuid_eax(1); - sig->pf =3D 0; sig->rev =3D intel_get_microcode_revision(); - - if (IFM(x86_family(sig->sig), x86_model(sig->sig)) >=3D INTEL_PENTIUM_III= _DESCHUTES) { - unsigned int val[2]; - - /* get processor flags from MSR 0x17 */ - native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); - sig->pf =3D 1 << ((val[1] >> 18) & 7); - } + sig->pf =3D intel_get_platform_id(); } EXPORT_SYMBOL_GPL(intel_collect_cpu_info); =20 _ From nobody Sun Feb 8 09:11:10 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A91C42D46A9 for ; Mon, 19 Jan 2026 19:50:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768852261; cv=none; b=dUjiDQ9gsbhFewjD6sZLl8fzsAh2VKQETNsBryfEj69DVjAx/+5dImwoALw1kP08WfgWyoqAErl7JIBDmsh937bxbIJHWBrGxw2XR7dfKJMsT0XzV5dDYQZqxnP4fMj9O+JaIQd0F5oToZCrQXsQCYQI2FvM8tITa7jrcU3d4WI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768852261; c=relaxed/simple; bh=nnICPMYogrU7JrvgjXgmhEXg2sYtJSi3orub4d6EoS4=; h=Subject:To:Cc:From:Date:References:In-Reply-To:Message-Id; b=TfvPmhtvHIWJ8EFyyjLr5Rb0xUKro5EKV3rne4dE8ACKxGFmBwbWmt0djkMqDmf9LZr07e3azwQ9B/gO5vjka1zrTIzAZp7EAblwY1Ef3kDRXggyfKIDZjkxniPpVChBbrQN5jL8ksoLp553+lEtXfUB84SEvStra1896eqz/6E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=IBoNAYkA; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="IBoNAYkA" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768852257; x=1800388257; h=subject:to:cc:from:date:references:in-reply-to: message-id; bh=nnICPMYogrU7JrvgjXgmhEXg2sYtJSi3orub4d6EoS4=; b=IBoNAYkAMiAKafsQTA9ov7SsODI7CgchNT54pQ/+dUSRH67qthzO7Qdl ZKuMpFeyhlufC7QZ1BjFSdoOoBNKrD48Ee4eYJTgtyaDnalEcRKs3pb/I AGSBb2D1lTjbmJggfQhzDrEz/aysRAXSGlBbSpidEpkqFgHNMLFoKd8X+ FWSeXMmNWYOOjzWsKz8g19Dy9ii+o+snqXqxG0mXjPqPCEN9wdCrQTwEa 06T/ViIS5DfiiT5KyIPJATWaBTVFdyM53VyksbH+5nCFndD31ejhsZDfC ULUGSpDeQwVM8YAarYDEwhLPCPUZ9YXrYMKGc3yvzU6gaAnAfFG5Sm4XP g==; X-CSE-ConnectionGUID: mNMWaAnGQ5Cm5VRlTli1IA== X-CSE-MsgGUID: WLlm943WTW2F52D23wzX7Q== X-IronPort-AV: E=McAfee;i="6800,10657,11676"; a="57623080" X-IronPort-AV: E=Sophos;i="6.21,238,1763452800"; d="scan'208";a="57623080" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jan 2026 11:50:56 -0800 X-CSE-ConnectionGUID: 17q24TDrQ7+VPjV9GMpfpA== X-CSE-MsgGUID: uHiNYeDwQ/i/MQ2R+Ne+5A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,238,1763452800"; d="scan'208";a="210786576" Received: from davehans-spike.ostc.intel.com (HELO localhost.localdomain) ([10.165.164.11]) by fmviesa004.fm.intel.com with ESMTP; 19 Jan 2026 11:50:56 -0800 Subject: [PATCH 4/6] x86/cpu: Add platform ID to CPU info structure To: linux-kernel@vger.kernel.org Cc: sohil.mehta@intel.com, Dave Hansen , Borislav Petkov , "H. Peter Anvin" , Ingo Molnar , Jon Kohler , Pawan Gupta , "Peter Zijlstra (Intel)" , Thomas Gleixner , Tony Luck , x86@kernel.org From: Dave Hansen Date: Mon, 19 Jan 2026 11:50:55 -0800 References: <20260119195047.86E3C696@davehans-spike.ostc.intel.com> In-Reply-To: <20260119195047.86E3C696@davehans-spike.ostc.intel.com> Message-Id: <20260119195055.0B00B57E@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen The end goal here is to be able to do x86_match_cpu() and match on a specific platform ID. While it would be possible to stash this ID off somewhere or read it dynamically, that approaches would not be consistent with the other fields which can be matched. Read the platform ID and store it in cpuinfo_x86->x86_platform_id. There are lots of sites to set this new field. Place it near the place c->microcode is established since the platform ID is so closely intertwined with microcode updates. Note: This should not grow the size of 'struct cpuinfo_x86' in practice since the u8 fits next to another u8 in the structure. Signed-off-by: Dave Hansen Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Borislav Petkov Cc: Dave Hansen Cc: "H. Peter Anvin" Cc: Tony Luck Cc: Pawan Gupta Cc: "Peter Zijlstra (Intel)" Cc: x86@kernel.org Cc: Jon Kohler Tested-by: Ricardo Neri --- b/arch/x86/include/asm/processor.h | 1 + b/arch/x86/kernel/cpu/common.c | 4 +++- b/arch/x86/kernel/cpu/intel.c | 1 + 3 files changed, 5 insertions(+), 1 deletion(-) diff -puN arch/x86/include/asm/processor.h~cpu-x86_stepping arch/x86/includ= e/asm/processor.h --- a/arch/x86/include/asm/processor.h~cpu-x86_stepping 2026-01-19 11:38:09= .341914025 -0800 +++ b/arch/x86/include/asm/processor.h 2026-01-19 11:38:09.444917962 -0800 @@ -140,6 +140,7 @@ struct cpuinfo_x86 { __u32 x86_vfm; }; __u8 x86_stepping; + __u8 x86_platform_id; /* Intel-only. 3 bits */ #ifdef CONFIG_X86_64 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ int x86_tlbsize; diff -puN arch/x86/kernel/cpu/common.c~cpu-x86_stepping arch/x86/kernel/cpu= /common.c --- a/arch/x86/kernel/cpu/common.c~cpu-x86_stepping 2026-01-19 11:38:09.428= 917350 -0800 +++ b/arch/x86/kernel/cpu/common.c 2026-01-19 11:38:09.445918000 -0800 @@ -1981,7 +1981,9 @@ static void identify_cpu(struct cpuinfo_ c->loops_per_jiffy =3D loops_per_jiffy; c->x86_cache_size =3D 0; c->x86_vendor =3D X86_VENDOR_UNKNOWN; - c->x86_model =3D c->x86_stepping =3D 0; /* So far unknown... */ + c->x86_model =3D 0; + c->x86_stepping =3D 0; + c->x86_platform_id =3D 0; c->x86_vendor_id[0] =3D '\0'; /* Unset */ c->x86_model_id[0] =3D '\0'; /* Unset */ #ifdef CONFIG_X86_64 diff -puN arch/x86/kernel/cpu/intel.c~cpu-x86_stepping arch/x86/kernel/cpu/= intel.c --- a/arch/x86/kernel/cpu/intel.c~cpu-x86_stepping 2026-01-19 11:38:09.4419= 17848 -0800 +++ b/arch/x86/kernel/cpu/intel.c 2026-01-19 11:38:09.445918000 -0800 @@ -205,6 +205,7 @@ static void early_init_intel(struct cpui =20 if (c->x86 >=3D 6 && !cpu_has(c, X86_FEATURE_IA64)) c->microcode =3D intel_get_microcode_revision(); + c->x86_platform_id =3D intel_get_platform_id(); =20 /* Now if any of them are set, check the blacklist and clear the lot */ if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) || _ From nobody Sun Feb 8 09:11:10 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E646B2C3248 for ; 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a="57623089" X-IronPort-AV: E=Sophos;i="6.21,238,1763452800"; d="scan'208";a="57623089" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jan 2026 11:50:59 -0800 X-CSE-ConnectionGUID: AltSH20wTSuDGMJxutD8iw== X-CSE-MsgGUID: WjQYwbF8TuqXmmfwsj/rqA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,238,1763452800"; d="scan'208";a="210786583" Received: from davehans-spike.ostc.intel.com (HELO localhost.localdomain) ([10.165.164.11]) by fmviesa004.fm.intel.com with ESMTP; 19 Jan 2026 11:50:58 -0800 Subject: [PATCH 5/6] x86/cpu: Add platform ID to CPU matching structure To: linux-kernel@vger.kernel.org Cc: sohil.mehta@intel.com, Dave Hansen , Borislav Petkov , "H. Peter Anvin" , Ingo Molnar , Jon Kohler , Pawan Gupta , "Peter Zijlstra (Intel)" , Thomas Gleixner , Tony Luck , x86@kernel.org From: Dave Hansen Date: Mon, 19 Jan 2026 11:50:57 -0800 References: <20260119195047.86E3C696@davehans-spike.ostc.intel.com> In-Reply-To: <20260119195047.86E3C696@davehans-spike.ostc.intel.com> Message-Id: <20260119195057.E6728139@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen The existing x86_match_cpu() infrastructure can be used to match a bunch of attributes of a CPU: vendor, family, model, steppings and CPU features. But, there's one more attribute that's missing and unable to be matched against: the platform ID, enumerated on Intel CPUs in MSR_IA32_PLATFORM_ID. It is a little more obscure and is only queried during microcode loading. This is because Intel sometimes has CPUs with identical family/model/stepping but which need different microcode. These CPUs are differentiated with the platform ID. Add a field in 'struct x86_cpu_id' for the platform ID. Similar to the stepping field, make the new field a mask of platform IDs. Some examples: 0x01: matches only platform ID 0x0 0x02: matches only platform ID 0x1 0x03: matches platform IDs 0x0 or 0x1 0x80: matches only platform ID 0x7 0xff: matches all 8 possible platform IDs Since the mask is only a byte wide, it nestles in next to another u8 and does not even increase the size of 'struct x86_cpu_id'. Reserve the all 0's value as the wildcard (X86_PLATFORM_ANY). This avoids forcing changes changes to existing 'struct x86_cpu_id' users. They can just continue to fill the field with 0's and their matching will work exactly as before. Note: If someone is ever looking for space in 'struct x86_cpu_id', this new field could probably get stuck over in ->driver_data for the one user that there is. Signed-off-by: Dave Hansen Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Borislav Petkov Cc: Dave Hansen Cc: "H. Peter Anvin" Cc: Tony Luck Cc: Pawan Gupta Cc: "Peter Zijlstra (Intel)" Cc: x86@kernel.org Cc: Jon Kohler Tested-by: Ricardo Neri --- b/arch/x86/kernel/cpu/match.c | 3 +++ b/include/linux/mod_devicetable.h | 2 ++ 2 files changed, 5 insertions(+) diff -puN arch/x86/kernel/cpu/match.c~platform-match arch/x86/kernel/cpu/ma= tch.c --- a/arch/x86/kernel/cpu/match.c~platform-match 2026-01-19 11:38:10.020939= 979 -0800 +++ b/arch/x86/kernel/cpu/match.c 2026-01-19 11:38:10.046940973 -0800 @@ -76,6 +76,9 @@ const struct x86_cpu_id *x86_match_cpu(c if (m->steppings !=3D X86_STEPPING_ANY && !(BIT(c->x86_stepping) & m->steppings)) continue; + if (m->platform_mask !=3D X86_PLATFORM_ANY && + !(c->x86_platform_id & m->platform_mask)) + continue; if (m->feature !=3D X86_FEATURE_ANY && !cpu_has(c, m->feature)) continue; if (!x86_match_vendor_cpu_type(c, m)) diff -puN include/linux/mod_devicetable.h~platform-match include/linux/mod_= devicetable.h --- a/include/linux/mod_devicetable.h~platform-match 2026-01-19 11:38:10.04= 3940858 -0800 +++ b/include/linux/mod_devicetable.h 2026-01-19 11:38:10.046940973 -0800 @@ -692,6 +692,7 @@ struct x86_cpu_id { __u16 feature; /* bit index */ /* Solely for kernel-internal use: DO NOT EXPORT to userspace! */ __u16 flags; + __u8 platform_mask; __u8 type; kernel_ulong_t driver_data; }; @@ -703,6 +704,7 @@ struct x86_cpu_id { #define X86_STEPPING_ANY 0 #define X86_STEP_MIN 0 #define X86_STEP_MAX 0xf +#define X86_PLATFORM_ANY 0x0 #define X86_FEATURE_ANY 0 /* Same as FPU, you can't test for that */ #define X86_CPU_TYPE_ANY 0 =20 _ From nobody Sun Feb 8 09:11:10 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 919392DB791 for ; Mon, 19 Jan 2026 19:51:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768852266; cv=none; b=hvZOz7HxTu1/GMxGO0hqdqKjGHs0eB8ovGc1qsZDhtnwRhzBzg8dEFeLL1oNWrpYPzB6LJG0NStrxRjoccSrhN4a04q9j5Mj0ZDUbTX9hJ2RKk2dpOIuwu3PQyUrIxiVeZTzVVKFU/vS/QUM36xqaid84lzQuek+/jWvaQDA8V4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768852266; c=relaxed/simple; bh=DHeoXypN+eUSV1UN7cp/Xc47SvVzFrh9Jmxu9Q1DsHk=; h=Subject:To:Cc:From:Date:References:In-Reply-To:Message-Id; b=bQ1SblHKIfkAqLre+tOrHLC+1kdgnHz2FU//xdjgWwI7jiDbdZrmmdukPwHGPnsa7HGaGzqj80VJOsOBL5dqu1zZbGp58slbFvX0T+/MgrWa3T6+W+TZaf9vcfbVHHltN6sjwQM+b875lG2VWagFLIb5gjRfQzucPavdMIKU8jE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=T0+AGgaB; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="T0+AGgaB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768852262; x=1800388262; h=subject:to:cc:from:date:references:in-reply-to: message-id; bh=DHeoXypN+eUSV1UN7cp/Xc47SvVzFrh9Jmxu9Q1DsHk=; b=T0+AGgaB1WdrHu3nNv44CsYRppb3WkmBcb7G6f4WfKUt+YGPRe9xi4ev PRzuh7wgBSUP4FIbvSmDksClkoDp5FX6Gkmd9++aO4IPTsAJ56HFWBfs/ Qic4WFBSt2VRgyfvEWLTioddKvUAdCwoSJDZeVodwKfAU3kQMo4yyTPgW A5p8qbqYvL4/b9ZHBZn4Ut61muJ5ADfAEawjn0i193Z5RR1MvNiEo65HK Ks54qqyq87Sd26dvyo4mt+MkYnWpEIf4WqF79D3AxP9i3Rf+s9xcgk6Oz F8ueOIfw7DsRhVch99t1MnStI+/XYsN+SkjXylIPWB1OqOZlsZDVE1sll w==; X-CSE-ConnectionGUID: PhuOekLzTJukeCb5kYWitA== X-CSE-MsgGUID: cbuAbq1ARs6Y9yQiKA4aZA== X-IronPort-AV: E=McAfee;i="6800,10657,11676"; a="57623098" X-IronPort-AV: E=Sophos;i="6.21,238,1763452800"; d="scan'208";a="57623098" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jan 2026 11:51:01 -0800 X-CSE-ConnectionGUID: 4Kl92BrYRK+KC0+r9CQAxg== X-CSE-MsgGUID: jaTYUfYoSgK1JULjpPrBtQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,238,1763452800"; d="scan'208";a="210786591" Received: from davehans-spike.ostc.intel.com (HELO localhost.localdomain) ([10.165.164.11]) by fmviesa004.fm.intel.com with ESMTP; 19 Jan 2026 11:51:00 -0800 Subject: [PATCH 6/6] x86/microcode: Add platform mask to Intel microcode "old" list To: linux-kernel@vger.kernel.org Cc: sohil.mehta@intel.com, Dave Hansen , Borislav Petkov , "H. Peter Anvin" , Ingo Molnar , Jon Kohler , Pawan Gupta , "Peter Zijlstra (Intel)" , Thomas Gleixner , Tony Luck , x86@kernel.org From: Dave Hansen Date: Mon, 19 Jan 2026 11:51:00 -0800 References: <20260119195047.86E3C696@davehans-spike.ostc.intel.com> In-Reply-To: <20260119195047.86E3C696@davehans-spike.ostc.intel.com> Message-Id: <20260119195100.C96636C3@davehans-spike.ostc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Dave Hansen Intel sometimes has CPUs with identical family/model/stepping but which need different microcode. These CPUs are differentiated with the platform ID. The Intel "microcode-20250512" release was used to generate the existing contents of intel-ucode-defs.h. Use that same release and add the platform mask to the definitions. This makes the list a few entries longer. For example for the ancient Pentium III there are two CPUs that differ only in their platform and have two different microcode versions: { ..., .model =3D 0x05, .steppings =3D 0x0001, .platform_mask =3D 0x01, .d= river_data =3D 0x40 }, { ..., .model =3D 0x05, .steppings =3D 0x0001, .platform_mask =3D 0x08, .d= river_data =3D 0x45 }, These CPUs previously shared a definition. Another example is the state-of-the-art Granite Rapids: { ..., .model =3D 0xad, .steppings =3D 0x0002, .platform_mask =3D 0x20, .= driver_data =3D 0xa0000d1 }, { ..., .model =3D 0xad, .steppings =3D 0x0002, .platform_mask =3D 0x95, .= driver_data =3D 0x10003a2 }, As you can see, this differentiation with platform ID has been necessary for a long time and is still relevant today. Without the platform matching, the old microcode table is incomplete. For instance, it might lead someone with a Pentium III, platform 0x0, and microcode 0x40 to think that they should have microcode 0x45, which is really only for platform 0x4 (.platform_mask=3D=3D0x08). In practice, this meant that folks with fully updated microcode were seeing "Vulnerable" in the "old_microcode" file. 1. https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files Signed-off-by: Dave Hansen Reported-by: Jon Kohler Fixes: 4e2c719782a8 ("x86/cpu: Help users notice when running old Intel mic= rocode") Link: https://lore.kernel.org/all/3ECBB974-C6F0-47A7-94B6-3646347F1CC2@nuta= nix.com/ Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Borislav Petkov Cc: Dave Hansen Cc: "H. Peter Anvin" Cc: Tony Luck Cc: Pawan Gupta Cc: "Peter Zijlstra (Intel)" Cc: x86@kernel.org Tested-by: Ricardo Neri Tested-by: Zhao Liu --- b/arch/x86/kernel/cpu/microcode/intel-ucode-defs.h | 368 +++++++++++-----= ----- 1 file changed, 208 insertions(+), 160 deletions(-) diff -puN arch/x86/kernel/cpu/microcode/intel-ucode-defs.h~add-platform-to-= defs arch/x86/kernel/cpu/microcode/intel-ucode-defs.h --- a/arch/x86/kernel/cpu/microcode/intel-ucode-defs.h~add-platform-to-defs= 2026-01-19 11:38:10.615962723 -0800 +++ b/arch/x86/kernel/cpu/microcode/intel-ucode-defs.h 2026-01-19 11:38:10.= 619962876 -0800 @@ -1,160 +1,208 @@ -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x03, .steppings =3D 0x0004, .driver_data =3D 0x= 2 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x05, .steppings =3D 0x0001, .driver_data =3D 0x= 45 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x05, .steppings =3D 0x0002, .driver_data =3D 0x= 40 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x05, .steppings =3D 0x0004, .driver_data =3D 0x= 2c }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x05, .steppings =3D 0x0008, .driver_data =3D 0x= 10 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x06, .steppings =3D 0x0001, .driver_data =3D 0x= a }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x06, .steppings =3D 0x0020, .driver_data =3D 0x= 3 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x06, .steppings =3D 0x0400, .driver_data =3D 0x= d }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x06, .steppings =3D 0x2000, .driver_data =3D 0x= 7 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x07, .steppings =3D 0x0002, .driver_data =3D 0x= 14 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x07, .steppings =3D 0x0004, .driver_data =3D 0x= 38 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x07, .steppings =3D 0x0008, .driver_data =3D 0x= 2e }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x08, .steppings =3D 0x0002, .driver_data =3D 0x= 11 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x08, .steppings =3D 0x0008, .driver_data =3D 0x= 8 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x08, .steppings =3D 0x0040, .driver_data =3D 0x= c }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x08, .steppings =3D 0x0400, .driver_data =3D 0x= 5 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x09, .steppings =3D 0x0020, .driver_data =3D 0x= 47 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0a, .steppings =3D 0x0001, .driver_data =3D 0x= 3 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0a, .steppings =3D 0x0002, .driver_data =3D 0x= 1 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0b, .steppings =3D 0x0002, .driver_data =3D 0x= 1d }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0b, .steppings =3D 0x0010, .driver_data =3D 0x= 2 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0d, .steppings =3D 0x0040, .driver_data =3D 0x= 18 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0e, .steppings =3D 0x0100, .driver_data =3D 0x= 39 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0e, .steppings =3D 0x1000, .driver_data =3D 0x= 59 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0f, .steppings =3D 0x0004, .driver_data =3D 0x= 5d }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0f, .steppings =3D 0x0040, .driver_data =3D 0x= d2 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0f, .steppings =3D 0x0080, .driver_data =3D 0x= 6b }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0f, .steppings =3D 0x0400, .driver_data =3D 0x= 95 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0f, .steppings =3D 0x0800, .driver_data =3D 0x= bc }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0f, .steppings =3D 0x2000, .driver_data =3D 0x= a4 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x16, .steppings =3D 0x0002, .driver_data =3D 0x= 44 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x17, .steppings =3D 0x0040, .driver_data =3D 0x= 60f }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x17, .steppings =3D 0x0080, .driver_data =3D 0x= 70a }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x17, .steppings =3D 0x0400, .driver_data =3D 0x= a0b }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x1a, .steppings =3D 0x0010, .driver_data =3D 0x= 12 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x1a, .steppings =3D 0x0020, .driver_data =3D 0x= 1d }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x1c, .steppings =3D 0x0004, .driver_data =3D 0x= 219 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x1c, .steppings =3D 0x0400, .driver_data =3D 0x= 107 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x1d, .steppings =3D 0x0002, .driver_data =3D 0x= 29 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x1e, .steppings =3D 0x0020, .driver_data =3D 0x= a }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x25, .steppings =3D 0x0004, .driver_data =3D 0x= 11 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x25, .steppings =3D 0x0020, .driver_data =3D 0x= 7 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x26, .steppings =3D 0x0002, .driver_data =3D 0x= 105 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x2a, .steppings =3D 0x0080, .driver_data =3D 0x= 2f }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x2c, .steppings =3D 0x0004, .driver_data =3D 0x= 1f }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x2d, .steppings =3D 0x0040, .driver_data =3D 0x= 621 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x2d, .steppings =3D 0x0080, .driver_data =3D 0x= 71a }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x2e, .steppings =3D 0x0040, .driver_data =3D 0x= d }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x2f, .steppings =3D 0x0004, .driver_data =3D 0x= 3b }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x37, .steppings =3D 0x0100, .driver_data =3D 0x= 838 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x37, .steppings =3D 0x0200, .driver_data =3D 0x= 90d }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x3a, .steppings =3D 0x0200, .driver_data =3D 0x= 21 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D 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X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x02, .steppings =3D 0x0200, .driver_data =3D 0x= 2f }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x03, .steppings =3D 0x0004, .driver_data =3D 0x= a }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x03, .steppings =3D 0x0008, .driver_data =3D 0x= c }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x03, .steppings =3D 0x0010, .driver_data =3D 0x= 17 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x04, .steppings =3D 0x0002, .driver_data =3D 0x= 17 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x04, .steppings =3D 0x0008, .driver_data =3D 0x= 5 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x04, .steppings =3D 0x0010, .driver_data =3D 0x= 6 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x04, .steppings =3D 0x0080, .driver_data =3D 0x= 3 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x04, .steppings =3D 0x0100, .driver_data =3D 0x= e }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x04, .steppings =3D 0x0200, .driver_data =3D 0x= 3 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x04, .steppings =3D 0x0400, .driver_data =3D 0x= 4 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x06, .steppings =3D 0x0004, .driver_data =3D 0x= f }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x06, .steppings =3D 0x0010, .driver_data =3D 0x= 4 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x06, .steppings =3D 0x0020, .driver_data =3D 0x= 8 }, -{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x06, .steppings =3D 0x0100, .driver_data =3D 0x= 9 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x03, .steppings =3D 0x0004, .platform_mask =3D = 0x00, .driver_data =3D 0x2 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x05, .steppings =3D 0x0001, .platform_mask =3D = 0x01, .driver_data =3D 0x40 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x05, .steppings =3D 0x0001, .platform_mask =3D = 0x08, .driver_data =3D 0x45 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x05, .steppings =3D 0x0002, .platform_mask =3D = 0x01, .driver_data =3D 0x40 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x05, .steppings =3D 0x0008, .platform_mask =3D = 0x01, .driver_data =3D 0x10 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x05, .steppings =3D 0x0008, .platform_mask =3D = 0x02, .driver_data =3D 0xc }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x05, .steppings =3D 0x0008, .platform_mask =3D = 0x04, .driver_data =3D 0xb }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x05, .steppings =3D 0x0008, .platform_mask =3D = 0x08, .driver_data =3D 0xd }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x06, .steppings =3D 0x0001, .platform_mask =3D = 0x01, .driver_data =3D 0xa }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x06, .steppings =3D 0x0400, .platform_mask =3D = 0x02, .driver_data =3D 0xc }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x06, .steppings =3D 0x0400, .platform_mask =3D = 0x08, .driver_data =3D 0xd }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x06, .steppings =3D 0x2000, .platform_mask =3D = 0x02, .driver_data =3D 0x5 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x06, .steppings =3D 0x2000, .platform_mask =3D = 0x20, .driver_data =3D 0x7 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x07, .steppings =3D 0x0002, .platform_mask =3D = 0x04, .driver_data =3D 0x14 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x07, .steppings =3D 0x0004, .platform_mask =3D = 0x04, .driver_data =3D 0x38 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x07, .steppings =3D 0x0008, .platform_mask =3D = 0x04, .driver_data =3D 0x2e }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x08, .steppings =3D 0x0002, .platform_mask =3D = 0x01, .driver_data =3D 0xd }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x08, .steppings =3D 0x0002, .platform_mask =3D = 0x04, .driver_data =3D 0x10 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x08, .steppings =3D 0x0002, .platform_mask =3D = 0x08, .driver_data =3D 0xf }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x08, .steppings =3D 0x0002, .platform_mask =3D = 0x10, .driver_data =3D 0x11 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x08, .steppings =3D 0x0002, .platform_mask =3D = 0x20, .driver_data =3D 0xe }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x08, .steppings =3D 0x0008, .platform_mask =3D = 0x08, .driver_data =3D 0x8 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x08, .steppings =3D 0x0008, .platform_mask =3D = 0x20, .driver_data =3D 0x7 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x08, .steppings =3D 0x0040, .platform_mask =3D = 0x04, .driver_data =3D 0x2 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x08, .steppings =3D 0x0040, .platform_mask =3D = 0x01, .driver_data =3D 0x7 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x08, .steppings =3D 0x0040, .platform_mask =3D = 0x02, .driver_data =3D 0xa }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x08, .steppings =3D 0x0040, .platform_mask =3D = 0x10, .driver_data =3D 0x8 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x08, .steppings =3D 0x0040, .platform_mask =3D = 0x80, .driver_data =3D 0xc }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x08, .steppings =3D 0x0400, .platform_mask =3D = 0x20, .driver_data =3D 0x4 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x08, .steppings =3D 0x0400, .platform_mask =3D = 0x80, .driver_data =3D 0x5 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x09, .steppings =3D 0x0020, .platform_mask =3D = 0x10, .driver_data =3D 0x7 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x09, .steppings =3D 0x0020, .platform_mask =3D = 0x20, .driver_data =3D 0x7 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x09, .steppings =3D 0x0020, .platform_mask =3D = 0x80, .driver_data =3D 0x47 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0a, .steppings =3D 0x0001, .platform_mask =3D = 0x04, .driver_data =3D 0x3 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0b, .steppings =3D 0x0002, .platform_mask =3D = 0x10, .driver_data =3D 0x1c }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0b, .steppings =3D 0x0002, .platform_mask =3D = 0x20, .driver_data =3D 0x1d }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0b, .steppings =3D 0x0010, .platform_mask =3D = 0x10, .driver_data =3D 0x1 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0b, .steppings =3D 0x0010, .platform_mask =3D = 0x20, .driver_data =3D 0x2 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0d, .steppings =3D 0x0040, .platform_mask =3D = 0x20, .driver_data =3D 0x18 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0e, .steppings =3D 0x0100, .platform_mask =3D = 0x20, .driver_data =3D 0x39 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0e, .steppings =3D 0x1000, .platform_mask =3D = 0x20, .driver_data =3D 0x54 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0e, .steppings =3D 0x1000, .platform_mask =3D = 0x80, .driver_data =3D 0x59 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0f, .steppings =3D 0x0004, .platform_mask =3D = 0x01, .driver_data =3D 0x5d }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0f, .steppings =3D 0x0004, .platform_mask =3D = 0x20, .driver_data =3D 0x5c }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0f, .steppings =3D 0x0040, .platform_mask =3D = 0x01, .driver_data =3D 0xd0 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0f, .steppings =3D 0x0040, .platform_mask =3D = 0x04, .driver_data =3D 0xd2 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0f, .steppings =3D 0x0040, .platform_mask =3D = 0x20, .driver_data =3D 0xd1 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0f, .steppings =3D 0x0800, .platform_mask =3D = 0x01, .driver_data =3D 0xba }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0f, .steppings =3D 0x0800, .platform_mask =3D = 0x04, .driver_data =3D 0xbc }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0f, .steppings =3D 0x0800, .platform_mask =3D = 0x08, .driver_data =3D 0xbb }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0f, .steppings =3D 0x0800, .platform_mask =3D = 0x10, .driver_data =3D 0xba }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0f, .steppings =3D 0x0800, .platform_mask =3D = 0x20, .driver_data =3D 0xba }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0f, .steppings =3D 0x0800, .platform_mask =3D = 0x40, .driver_data =3D 0xbc }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0f, .steppings =3D 0x0800, .platform_mask =3D = 0x80, .driver_data =3D 0xba }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0f, .steppings =3D 0x2000, .platform_mask =3D = 0x01, .driver_data =3D 0xa4 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0f, .steppings =3D 0x2000, .platform_mask =3D = 0x20, .driver_data =3D 0xa4 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x0f, .steppings =3D 0x2000, .platform_mask =3D = 0x80, .driver_data =3D 0xa4 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x16, .steppings =3D 0x0002, .platform_mask =3D = 0x01, .driver_data =3D 0x43 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x16, .steppings =3D 0x0002, .platform_mask =3D = 0x02, .driver_data =3D 0x42 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x16, .steppings =3D 0x0002, .platform_mask =3D = 0x80, .driver_data =3D 0x44 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x17, .steppings =3D 0x0040, .platform_mask =3D = 0x01, .driver_data =3D 0x60f }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x17, .steppings =3D 0x0040, .platform_mask =3D = 0x04, .driver_data =3D 0x60f }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x17, .steppings =3D 0x0040, .platform_mask =3D = 0x10, .driver_data =3D 0x60f }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x17, .steppings =3D 0x0040, .platform_mask =3D = 0x40, .driver_data =3D 0x60f }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x17, .steppings =3D 0x0040, .platform_mask =3D = 0x80, .driver_data =3D 0x60f }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x17, .steppings =3D 0x0080, .platform_mask =3D = 0x10, .driver_data =3D 0x70a }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x17, .steppings =3D 0x0400, .platform_mask =3D = 0x11, .driver_data =3D 0xa0b }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x17, .steppings =3D 0x0400, .platform_mask =3D = 0x44, .driver_data =3D 0xa0b }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x17, .steppings =3D 0x0400, .platform_mask =3D = 0xa0, .driver_data =3D 0xa0b }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x1a, .steppings =3D 0x0010, .platform_mask =3D = 0x03, .driver_data =3D 0x12 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x1a, .steppings =3D 0x0020, .platform_mask =3D = 0x03, .driver_data =3D 0x1d }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x1c, .steppings =3D 0x0004, .platform_mask =3D = 0x01, .driver_data =3D 0x217 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x1c, .steppings =3D 0x0004, .platform_mask =3D = 0x04, .driver_data =3D 0x218 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x1c, .steppings =3D 0x0004, .platform_mask =3D = 0x08, .driver_data =3D 0x219 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x1d, .steppings =3D 0x0002, .platform_mask =3D = 0x08, .driver_data =3D 0x29 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x1e, .steppings =3D 0x0020, .platform_mask =3D = 0x13, .driver_data =3D 0xa }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x25, .steppings =3D 0x0004, .platform_mask =3D = 0x12, .driver_data =3D 0x11 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x25, .steppings =3D 0x0020, .platform_mask =3D = 0x92, .driver_data =3D 0x7 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x26, .steppings =3D 0x0002, .platform_mask =3D = 0x01, .driver_data =3D 0x104 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x26, .steppings =3D 0x0002, .platform_mask =3D = 0x02, .driver_data =3D 0x105 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x2a, .steppings =3D 0x0080, .platform_mask =3D = 0x12, .driver_data =3D 0x2f }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x2c, .steppings =3D 0x0004, .platform_mask =3D = 0x03, .driver_data =3D 0x1f }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x2d, .steppings =3D 0x0040, .platform_mask =3D = 0x6d, .driver_data =3D 0x621 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x2d, .steppings =3D 0x0080, .platform_mask =3D = 0x6d, .driver_data =3D 0x71a }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x2e, .steppings =3D 0x0040, .platform_mask =3D = 0x04, .driver_data =3D 0xd }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x2f, .steppings =3D 0x0004, .platform_mask =3D = 0x05, .driver_data =3D 0x3b }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x37, .steppings =3D 0x0100, .platform_mask =3D = 0x02, .driver_data =3D 0x838 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x37, .steppings =3D 0x0100, .platform_mask =3D = 0x0c, .driver_data =3D 0x838 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x37, .steppings =3D 0x0200, .platform_mask =3D = 0x0f, .driver_data =3D 0x90d }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x3a, .steppings =3D 0x0200, .platform_mask =3D = 0x12, .driver_data =3D 0x21 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x3c, .steppings =3D 0x0008, .platform_mask =3D = 0x32, .driver_data =3D 0x28 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x3d, .steppings =3D 0x0010, .platform_mask =3D = 0xc0, .driver_data =3D 0x2f }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x3e, .steppings =3D 0x0010, .platform_mask =3D = 0xed, .driver_data =3D 0x42e }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x3e, .steppings =3D 0x0040, .platform_mask =3D = 0xed, .driver_data =3D 0x600 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x3e, .steppings =3D 0x0080, .platform_mask =3D = 0xed, .driver_data =3D 0x715 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x3f, .steppings =3D 0x0004, .platform_mask =3D = 0x6f, .driver_data =3D 0x49 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x3f, .steppings =3D 0x0010, .platform_mask =3D = 0x80, .driver_data =3D 0x1a }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x45, .steppings =3D 0x0002, .platform_mask =3D = 0x72, .driver_data =3D 0x26 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x47, .steppings =3D 0x0002, .platform_mask =3D = 0x22, .driver_data =3D 0x22 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x4c, .steppings =3D 0x0008, .platform_mask =3D = 0x01, .driver_data =3D 0x368 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x4c, .steppings =3D 0x0010, .platform_mask =3D = 0x01, .driver_data =3D 0x411 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x4d, .steppings =3D 0x0100, .platform_mask =3D = 0x01, .driver_data =3D 0x12d }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x4e, .steppings =3D 0x0008, .platform_mask =3D = 0xc0, .driver_data =3D 0xf0 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x55, .steppings =3D 0x0008, .platform_mask =3D = 0x97, .driver_data =3D 0x1000191 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x55, .steppings =3D 0x0010, .platform_mask =3D = 0xb7, .driver_data =3D 0x2007006 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x55, .steppings =3D 0x0020, .platform_mask =3D = 0xb7, .driver_data =3D 0x3000010 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x55, .steppings =3D 0x0080, .platform_mask =3D = 0xbf, .driver_data =3D 0x5003901 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x55, .steppings =3D 0x0800, .platform_mask =3D = 0xbf, .driver_data =3D 0x7002b01 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x56, .steppings =3D 0x0004, .platform_mask =3D = 0x10, .driver_data =3D 0x1c }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x56, .steppings =3D 0x0008, .platform_mask =3D = 0x10, .driver_data =3D 0x700001c }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x56, .steppings =3D 0x0010, .platform_mask =3D = 0x10, .driver_data =3D 0xf00001a }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x56, .steppings =3D 0x0020, .platform_mask =3D = 0x10, .driver_data =3D 0xe000015 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x5c, .steppings =3D 0x0004, .platform_mask =3D = 0x01, .driver_data =3D 0x14 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x5c, .steppings =3D 0x0200, .platform_mask =3D = 0x03, .driver_data =3D 0x48 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x5c, .steppings =3D 0x0400, .platform_mask =3D = 0x03, .driver_data =3D 0x28 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x5e, .steppings =3D 0x0008, .platform_mask =3D = 0x36, .driver_data =3D 0xf0 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x5f, .steppings =3D 0x0002, .platform_mask =3D = 0x01, .driver_data =3D 0x3e }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x66, .steppings =3D 0x0008, .platform_mask =3D = 0x80, .driver_data =3D 0x2a }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x6a, .steppings =3D 0x0020, .platform_mask =3D = 0x87, .driver_data =3D 0xc0002f0 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x6a, .steppings =3D 0x0040, .platform_mask =3D = 0x87, .driver_data =3D 0xd000404 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x6c, .steppings =3D 0x0002, .platform_mask =3D = 0x10, .driver_data =3D 0x10002d0 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x7a, .steppings =3D 0x0002, .platform_mask =3D = 0x01, .driver_data =3D 0x42 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x7a, .steppings =3D 0x0100, .platform_mask =3D = 0x01, .driver_data =3D 0x26 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x7e, .steppings =3D 0x0020, .platform_mask =3D = 0x80, .driver_data =3D 0xca }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x8a, .steppings =3D 0x0002, .platform_mask =3D = 0x10, .driver_data =3D 0x33 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x8c, .steppings =3D 0x0002, .platform_mask =3D = 0x80, .driver_data =3D 0xbc }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x8c, .steppings =3D 0x0004, .platform_mask =3D = 0xc2, .driver_data =3D 0x3c }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x8d, .steppings =3D 0x0002, .platform_mask =3D = 0xc2, .driver_data =3D 0x56 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x8e, .steppings =3D 0x0200, .platform_mask =3D = 0x10, .driver_data =3D 0xf6 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x8e, .steppings =3D 0x0200, .platform_mask =3D = 0xc0, .driver_data =3D 0xf6 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x8e, .steppings =3D 0x0400, .platform_mask =3D = 0xc0, .driver_data =3D 0xf6 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x8e, .steppings =3D 0x0800, .platform_mask =3D = 0xd0, .driver_data =3D 0xf6 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x8e, .steppings =3D 0x1000, .platform_mask =3D = 0x94, .driver_data =3D 0x100 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x8f, .steppings =3D 0x0010, .platform_mask =3D = 0x87, .driver_data =3D 0x2b000639 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x8f, .steppings =3D 0x0010, .platform_mask =3D = 0x10, .driver_data =3D 0x2c0003f7 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x8f, .steppings =3D 0x0020, .platform_mask =3D = 0x87, .driver_data =3D 0x2b000639 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x8f, .steppings =3D 0x0020, .platform_mask =3D = 0x10, .driver_data =3D 0x2c0003f7 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x8f, .steppings =3D 0x0040, .platform_mask =3D = 0x87, .driver_data =3D 0x2b000639 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x8f, .steppings =3D 0x0040, .platform_mask =3D = 0x10, .driver_data =3D 0x2c0003f7 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x8f, .steppings =3D 0x0080, .platform_mask =3D = 0x87, .driver_data =3D 0x2b000639 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x8f, .steppings =3D 0x0100, .platform_mask =3D = 0x87, .driver_data =3D 0x2b000639 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x8f, .steppings =3D 0x0100, .platform_mask =3D = 0x10, .driver_data =3D 0x2c0003f7 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x96, .steppings =3D 0x0002, .platform_mask =3D = 0x01, .driver_data =3D 0x1a }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x97, .steppings =3D 0x0004, .platform_mask =3D = 0x07, .driver_data =3D 0x3a }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x97, .steppings =3D 0x0020, .platform_mask =3D = 0x07, .driver_data =3D 0x3a }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x9a, .steppings =3D 0x0008, .platform_mask =3D = 0x80, .driver_data =3D 0x437 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x9a, .steppings =3D 0x0010, .platform_mask =3D = 0x80, .driver_data =3D 0x437 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x9a, .steppings =3D 0x0010, .platform_mask =3D = 0x40, .driver_data =3D 0xa }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x9c, .steppings =3D 0x0001, .platform_mask =3D = 0x01, .driver_data =3D 0x24000026 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x9e, .steppings =3D 0x0200, .platform_mask =3D = 0x2a, .driver_data =3D 0xf8 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x9e, .steppings =3D 0x0400, .platform_mask =3D = 0x22, .driver_data =3D 0xfa }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x9e, .steppings =3D 0x0800, .platform_mask =3D = 0x02, .driver_data =3D 0xf6 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x9e, .steppings =3D 0x1000, .platform_mask =3D = 0x22, .driver_data =3D 0xf8 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0x9e, .steppings =3D 0x2000, .platform_mask =3D = 0x22, .driver_data =3D 0x104 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0xa5, .steppings =3D 0x0004, .platform_mask =3D = 0x20, .driver_data =3D 0x100 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0xa5, .steppings =3D 0x0008, .platform_mask =3D = 0x22, .driver_data =3D 0x100 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0xa5, .steppings =3D 0x0020, .platform_mask =3D = 0x22, .driver_data =3D 0x100 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0xa6, .steppings =3D 0x0001, .platform_mask =3D = 0x80, .driver_data =3D 0x102 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0xa6, .steppings =3D 0x0002, .platform_mask =3D = 0x80, .driver_data =3D 0x100 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0xa7, .steppings =3D 0x0002, .platform_mask =3D = 0x02, .driver_data =3D 0x64 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0xaa, .steppings =3D 0x0010, .platform_mask =3D = 0xe6, .driver_data =3D 0x24 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0xad, .steppings =3D 0x0002, .platform_mask =3D = 0x20, .driver_data =3D 0xa0000d1 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0xad, .steppings =3D 0x0002, .platform_mask =3D = 0x95, .driver_data =3D 0x10003a2 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0xaf, .steppings =3D 0x0008, .platform_mask =3D = 0x01, .driver_data =3D 0x3000341 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0xb5, .steppings =3D 0x0001, .platform_mask =3D = 0x80, .driver_data =3D 0xa }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0xb7, .steppings =3D 0x0002, .platform_mask =3D = 0x32, .driver_data =3D 0x12f }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0xb7, .steppings =3D 0x0010, .platform_mask =3D = 0x32, .driver_data =3D 0x12f }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0xba, .steppings =3D 0x0004, .platform_mask =3D = 0xe0, .driver_data =3D 0x4128 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0xba, .steppings =3D 0x0008, .platform_mask =3D = 0xe0, .driver_data =3D 0x4128 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0xba, .steppings =3D 0x0100, .platform_mask =3D = 0xe0, .driver_data =3D 0x4128 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0xbd, .steppings =3D 0x0002, .platform_mask =3D = 0x80, .driver_data =3D 0x11f }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0xbf, .steppings =3D 0x0004, .platform_mask =3D = 0x07, .driver_data =3D 0x3a }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0xbf, .steppings =3D 0x0020, .platform_mask =3D = 0x07, .driver_data =3D 0x3a }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0xbf, .steppings =3D 0x0040, .platform_mask =3D = 0x07, .driver_data =3D 0x3a }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0xbf, .steppings =3D 0x0080, .platform_mask =3D = 0x07, .driver_data =3D 0x3a }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0xc5, .steppings =3D 0x0004, .platform_mask =3D = 0x82, .driver_data =3D 0x118 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0xc6, .steppings =3D 0x0004, .platform_mask =3D = 0x82, .driver_data =3D 0x118 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0xc6, .steppings =3D 0x0010, .platform_mask =3D = 0x82, .driver_data =3D 0x118 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0xca, .steppings =3D 0x0004, .platform_mask =3D = 0x82, .driver_data =3D 0x118 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0xcf, .steppings =3D 0x0002, .platform_mask =3D = 0x87, .driver_data =3D 0x210002a9 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0x6, .model =3D 0xcf, .steppings =3D 0x0004, .platform_mask =3D = 0x87, .driver_data =3D 0x210002a9 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x00, .steppings =3D 0x0080, .platform_mask =3D = 0x01, .driver_data =3D 0x12 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x00, .steppings =3D 0x0080, .platform_mask =3D = 0x02, .driver_data =3D 0x8 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x00, .steppings =3D 0x0400, .platform_mask =3D = 0x01, .driver_data =3D 0x13 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x00, .steppings =3D 0x0400, .platform_mask =3D = 0x02, .driver_data =3D 0x15 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x00, .steppings =3D 0x0400, .platform_mask =3D = 0x04, .driver_data =3D 0x14 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x01, .steppings =3D 0x0004, .platform_mask =3D = 0x04, .driver_data =3D 0x2e }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x02, .steppings =3D 0x0010, .platform_mask =3D = 0x04, .driver_data =3D 0x1e }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x02, .steppings =3D 0x0010, .platform_mask =3D = 0x10, .driver_data =3D 0x21 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x02, .steppings =3D 0x0020, .platform_mask =3D = 0x01, .driver_data =3D 0x29 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x02, .steppings =3D 0x0020, .platform_mask =3D = 0x02, .driver_data =3D 0x2a }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x02, .steppings =3D 0x0020, .platform_mask =3D = 0x10, .driver_data =3D 0x2c }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x02, .steppings =3D 0x0080, .platform_mask =3D = 0x02, .driver_data =3D 0x38 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x02, .steppings =3D 0x0080, .platform_mask =3D = 0x04, .driver_data =3D 0x37 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x02, .steppings =3D 0x0080, .platform_mask =3D = 0x08, .driver_data =3D 0x39 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x03, .steppings =3D 0x0004, .platform_mask =3D = 0x0d, .driver_data =3D 0xa }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x03, .steppings =3D 0x0008, .platform_mask =3D = 0x0d, .driver_data =3D 0xc }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x04, .steppings =3D 0x0002, .platform_mask =3D = 0x02, .driver_data =3D 0x16 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x04, .steppings =3D 0x0002, .platform_mask =3D = 0xbd, .driver_data =3D 0x17 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x04, .steppings =3D 0x0010, .platform_mask =3D = 0x9d, .driver_data =3D 0x6 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x04, .steppings =3D 0x0080, .platform_mask =3D = 0x9d, .driver_data =3D 0x3 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x04, .steppings =3D 0x0100, .platform_mask =3D = 0x01, .driver_data =3D 0xc }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x04, .steppings =3D 0x0100, .platform_mask =3D = 0x02, .driver_data =3D 0xe }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x04, .steppings =3D 0x0100, .platform_mask =3D = 0x5f, .driver_data =3D 0x7 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x06, .steppings =3D 0x0010, .platform_mask =3D = 0x01, .driver_data =3D 0x2 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x06, .steppings =3D 0x0010, .platform_mask =3D = 0x34, .driver_data =3D 0x4 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x06, .steppings =3D 0x0020, .platform_mask =3D = 0x01, .driver_data =3D 0x8 }, +{ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, .vendor =3D X86_VENDOR_INTEL, .f= amily =3D 0xf, .model =3D 0x06, .steppings =3D 0x0100, .platform_mask =3D = 0x22, .driver_data =3D 0x9 }, _