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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Russell King , linux-kernel@vger.kernel.org Subject: [PATCH net-next 2/2] net: dsa: yt921x: Add DCB/priority support Date: Tue, 20 Jan 2026 02:59:30 +0800 Message-ID: <20260119185935.2072685-3-mmyangfl@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260119185935.2072685-1-mmyangfl@gmail.com> References: <20260119185935.2072685-1-mmyangfl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Set up global DSCP/PCP priority mappings and add related DSA methods. Signed-off-by: David Yang --- drivers/net/dsa/Kconfig | 2 + drivers/net/dsa/yt921x.c | 232 +++++++++++++++++++++++++++++++++++++++ drivers/net/dsa/yt921x.h | 54 +++++++-- 3 files changed, 278 insertions(+), 10 deletions(-) diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig index 7eb301fd987d..d73d7fa7f7d2 100644 --- a/drivers/net/dsa/Kconfig +++ b/drivers/net/dsa/Kconfig @@ -158,6 +158,8 @@ config NET_DSA_VITESSE_VSC73XX_PLATFORM config NET_DSA_YT921X tristate "Motorcomm YT9215 ethernet switch chip support" select NET_DSA_TAG_YT921X + select NET_IEEE8021Q_HELPERS + select DCB help This enables support for the Motorcomm YT9215 ethernet switch chip. diff --git a/drivers/net/dsa/yt921x.c b/drivers/net/dsa/yt921x.c index 0b3df732c0d1..cf811545fb8b 100644 --- a/drivers/net/dsa/yt921x.c +++ b/drivers/net/dsa/yt921x.c @@ -18,8 +18,11 @@ #include #include #include +#include =20 #include +#include +#include =20 #include "yt921x.h" =20 @@ -2209,6 +2212,140 @@ yt921x_dsa_port_stp_state_set(struct dsa_switch *ds= , int port, u8 state) port, res); } =20 +static int +yt921x_dsa_port_get_default_prio(struct dsa_switch *ds, int port) +{ + struct yt921x_priv *priv =3D to_yt921x_priv(ds); + u32 val; + int res; + + mutex_lock(&priv->reg_lock); + res =3D yt921x_reg_read(priv, YT921X_PORTn_QOS(port), &val); + mutex_unlock(&priv->reg_lock); + + if (res) + return res; + + return FIELD_GET(YT921X_PORT_QOS_PRIO_M, val); +} + +static int +yt921x_dsa_port_set_default_prio(struct dsa_switch *ds, int port, u8 prio) +{ + struct yt921x_priv *priv =3D to_yt921x_priv(ds); + u32 mask; + u32 ctrl; + int res; + + if (prio >=3D YT921X_PRIO_NUM) + return -EINVAL; + + mutex_lock(&priv->reg_lock); + mask =3D YT921X_PORT_QOS_PRIO_M | YT921X_PORT_QOS_PRIO_EN; + ctrl =3D YT921X_PORT_QOS_PRIO(prio) | YT921X_PORT_QOS_PRIO_EN; + res =3D yt921x_reg_update_bits(priv, YT921X_PORTn_QOS(port), mask, ctrl); + mutex_unlock(&priv->reg_lock); + + return res; +} + +static const u8 yt921x_apps[] =3D { + 0, /* MAC SA */ + 0, /* MAC DA */ + 0, /* VID */ + 0, /* ACL */ + IEEE_8021QAZ_APP_SEL_DSCP, /* DSCP */ + DCB_APP_SEL_PCP, /* CVLAN PCP */ + 0, /* SVLAN PCP */ + 0, /* Port */ +}; + +static int appprios_cmp(const void *a, const void *b) +{ + return ((const u8 *)b)[1] - ((const u8 *)a)[1]; +} + +static int +yt921x_dsa_port_get_apptrust(struct dsa_switch *ds, int port, u8 *sel, + int *nselp) +{ + struct yt921x_priv *priv =3D to_yt921x_priv(ds); + u8 appprios[ARRAY_SIZE(yt921x_apps)][2]; + int nsel; + u32 val; + int res; + + mutex_lock(&priv->reg_lock); + res =3D yt921x_reg_read(priv, YT921X_PORTn_PRIO_ORD(port), &val); + mutex_unlock(&priv->reg_lock); + + if (res) + return res; + + for (int src =3D 0; src < ARRAY_SIZE(yt921x_apps); src++) { + appprios[src][0] =3D yt921x_apps[src]; + appprios[src][1] =3D (val >> (3 * src)) & 7; + } + sort(appprios, ARRAY_SIZE(appprios), sizeof(appprios[0]), appprios_cmp, + NULL); + + nsel =3D 0; + for (int i =3D 0; i < ARRAY_SIZE(appprios) && appprios[i][1]; i++) + if (appprios[i][0]) { + sel[nsel] =3D appprios[i][0]; + nsel++; + } + *nselp =3D nsel; + + return 0; +} + +static int +yt921x_dsa_port_set_apptrust(struct dsa_switch *ds, int port, const u8 *se= l, + int nsel) +{ + struct yt921x_priv *priv =3D to_yt921x_priv(ds); + u8 prios[ARRAY_SIZE(yt921x_apps)] =3D {}; + u32 ctrl; + u8 prio; + int res; + + if (nsel > ARRAY_SIZE(yt921x_apps)) + return -EINVAL; + + /* always take the port prio (port_set_default_prio) into + * consideration, by giving it the lowest priority + */ + prios[7] =3D 1; + prio =3D 7; + for (int i =3D 0; i < nsel; i++) { + bool found =3D false; + + for (int src =3D 0; src < ARRAY_SIZE(yt921x_apps); src++) { + if (yt921x_apps[src] !=3D sel[i]) + continue; + + prios[src] =3D prio; + prio--; + found =3D true; + break; + } + + if (!found) + return -EOPNOTSUPP; + } + + ctrl =3D 0; + for (int src =3D 0; src < ARRAY_SIZE(yt921x_apps); src++) + ctrl |=3D YT921X_PORT_PRIO_ORD_SRCm(src, prios[src]); + + mutex_lock(&priv->reg_lock); + res =3D yt921x_reg_write(priv, YT921X_PORTn_PRIO_ORD(port), ctrl); + mutex_unlock(&priv->reg_lock); + + return res; +} + static int yt921x_port_down(struct yt921x_priv *priv, int port) { u32 mask; @@ -2577,6 +2714,58 @@ static int yt921x_dsa_port_setup(struct dsa_switch *= ds, int port) return res; } =20 +#define ipm_drop(prio) \ + YT921X_IPM_DROP_PRIO((prio) <=3D IEEE8021Q_TT_EE ? 2 : \ + (prio) <=3D IEEE8021Q_TT_VO ? 1 : 0) +#define ipm_ctrl(prio) (YT921X_IPM_PRIO(prio) | ipm_drop(prio)) + +static int +yt921x_dsa_port_get_dscp_prio(struct dsa_switch *ds, int port, u8 dscp) +{ + struct yt921x_priv *priv =3D to_yt921x_priv(ds); + u32 val; + int res; + + mutex_lock(&priv->reg_lock); + res =3D yt921x_reg_read(priv, YT921X_IPM_DSCPn(dscp), &val); + mutex_unlock(&priv->reg_lock); + + if (res) + return res; + + return FIELD_GET(YT921X_IPM_PRIO_M, val); +} + +static int +yt921x_dsa_port_del_dscp_prio(struct dsa_switch *ds, int port, u8 dscp, u8= prio) +{ + struct yt921x_priv *priv =3D to_yt921x_priv(ds); + int res; + + mutex_lock(&priv->reg_lock); + res =3D yt921x_reg_write(priv, YT921X_IPM_DSCPn(dscp), + ipm_ctrl(IEEE8021Q_TT_BK)); + mutex_unlock(&priv->reg_lock); + + return res; +} + +static int +yt921x_dsa_port_add_dscp_prio(struct dsa_switch *ds, int port, u8 dscp, u8= prio) +{ + struct yt921x_priv *priv =3D to_yt921x_priv(ds); + int res; + + if (prio >=3D YT921X_PRIO_NUM) + return -EINVAL; + + mutex_lock(&priv->reg_lock); + res =3D yt921x_reg_write(priv, YT921X_IPM_DSCPn(dscp), ipm_ctrl(prio)); + mutex_unlock(&priv->reg_lock); + + return res; +} + static int yt921x_edata_wait(struct yt921x_priv *priv, u32 *valp) { u32 val =3D YT921X_EDATA_DATA_IDLE; @@ -2796,6 +2985,40 @@ static int yt921x_chip_setup(struct yt921x_priv *pri= v) if (res) return res; =20 + /* 802.1Q QoS to priority mapping table */ + for (u8 pcp =3D 0; pcp < 8; pcp++) { + u32 drop =3D ipm_drop(pcp); + + for (u8 dei =3D 0; dei < 2; dei++) { + ctrl =3D YT921X_IPM_PRIO(pcp); + if (!dei) + ctrl |=3D drop; + else + ctrl |=3D YT921X_IPM_DROP_PRIO(2); + + for (u8 svlan =3D 0; svlan < 2; svlan++) { + u32 reg =3D YT921X_IPM_PCPn(svlan, dei, pcp); + + res =3D yt921x_reg_write(priv, reg, ctrl); + if (res) + return res; + } + } + } + + /* DSCP to priority mapping table */ + for (u8 dscp =3D 0; dscp < DSCP_MAX; dscp++) { + int prio =3D ietf_dscp_to_ieee8021q_tt(dscp); + + if (prio < 0) + return prio; + + res =3D yt921x_reg_write(priv, YT921X_IPM_DSCPn(dscp), + ipm_ctrl(prio)); + if (res) + return res; + } + /* Miscellaneous */ res =3D yt921x_reg_set_bits(priv, YT921X_SENSOR, YT921X_SENSOR_TEMP); if (res) @@ -2902,10 +3125,19 @@ static const struct dsa_switch_ops yt921x_dsa_switc= h_ops =3D { .port_mst_state_set =3D yt921x_dsa_port_mst_state_set, .vlan_msti_set =3D yt921x_dsa_vlan_msti_set, .port_stp_state_set =3D yt921x_dsa_port_stp_state_set, + /* dcb */ + .port_get_default_prio =3D yt921x_dsa_port_get_default_prio, + .port_set_default_prio =3D yt921x_dsa_port_set_default_prio, + .port_get_apptrust =3D yt921x_dsa_port_get_apptrust, + .port_set_apptrust =3D yt921x_dsa_port_set_apptrust, /* port */ .get_tag_protocol =3D yt921x_dsa_get_tag_protocol, .phylink_get_caps =3D yt921x_dsa_phylink_get_caps, .port_setup =3D yt921x_dsa_port_setup, + /* dscp */ + .port_get_dscp_prio =3D yt921x_dsa_port_get_dscp_prio, + .port_del_dscp_prio =3D yt921x_dsa_port_del_dscp_prio, + .port_add_dscp_prio =3D yt921x_dsa_port_add_dscp_prio, /* chip */ .setup =3D yt921x_dsa_setup, }; diff --git a/drivers/net/dsa/yt921x.h b/drivers/net/dsa/yt921x.h index 61bb0ab3b09a..1498ccdb3932 100644 --- a/drivers/net/dsa/yt921x.h +++ b/drivers/net/dsa/yt921x.h @@ -269,6 +269,37 @@ #define YT921X_TPID_EGRn(x) (0x100300 + 4 * (x)) /* [0, 3] */ #define YT921X_TPID_EGR_TPID_M GENMASK(15, 0) =20 +#define YT921X_IPM_DSCPn(n) (0x180000 + 4 * (n)) /* Internal Priority Map= */ +#define YT921X_IPM_PCPn(map, dei, pcp) (0x180100 + 4 * (16 * (map) + 8 * (= dei) + (pcp))) +#define YT921X_IPM_PRIO_M GENMASK(4, 2) +#define YT921X_IPM_PRIO(x) FIELD_PREP(YT921X_IPM_PRIO_M, (x)) +#define YT921X_IPM_DROP_PRIO_M GENMASK(1, 0) +#define YT921X_IPM_DROP_PRIO(x) FIELD_PREP(YT921X_IPM_DROP_PRIO_M, (x)) +#define YT921X_PORTn_QOS(port) (0x180180 + 4 * (port)) +#define YT921X_PORT_QOS_CVLAN_PRIO_MAP_SEL BIT(5) +#define YT921X_PORT_QOS_SVLAN_PRIO_MAP_SEL BIT(4) +#define YT921X_PORT_QOS_PRIO_M GENMASK(3, 1) +#define YT921X_PORT_QOS_PRIO(x) FIELD_PREP(YT921X_PORT_QOS_PRIO_M, (x)) +#define YT921X_PORT_QOS_PRIO_EN BIT(0) +#define YT921X_PORTn_PRIO_ORD(port) (0x180200 + 4 * (port)) +#define YT921X_PORT_PRIO_ORD_SRCm_M(m) GENMASK(3 * (m) + 2, 3 * (m)) +#define YT921X_PORT_PRIO_ORD_SRCm(m, x) ((x) << (3 * (m))) +#define YT921X_PORT_PRIO_ORD_PORT_M GENMASK(23, 21) +#define YT921X_PORT_PRIO_ORD_PORT(x) FIELD_PREP(YT921X_PORT_PRIO_ORD_P= ORT_M, (x)) +#define YT921X_PORT_PRIO_ORD_SVLAN_M GENMASK(20, 18) +#define YT921X_PORT_PRIO_ORD_SVLAN(x) FIELD_PREP(YT921X_PORT_PRIO_ORD_= SVLAN_M, (x)) +#define YT921X_PORT_PRIO_ORD_CVLAN_M GENMASK(17, 15) +#define YT921X_PORT_PRIO_ORD_CVLAN(x) FIELD_PREP(YT921X_PORT_PRIO_ORD_= CVLAN_M, (x)) +#define YT921X_PORT_PRIO_ORD_DSCP_M GENMASK(14, 12) +#define YT921X_PORT_PRIO_ORD_DSCP(x) FIELD_PREP(YT921X_PORT_PRIO_ORD_D= SCP_M, (x)) +#define YT921X_PORT_PRIO_ORD_ACL_M GENMASK(11, 9) +#define YT921X_PORT_PRIO_ORD_ACL(x) FIELD_PREP(YT921X_PORT_PRIO_ORD_AC= L_M, (x)) +#define YT921X_PORT_PRIO_ORD_VID_M GENMASK(8, 6) +#define YT921X_PORT_PRIO_ORD_VID(x) FIELD_PREP(YT921X_PORT_PRIO_ORD_VI= D_M, (x)) +#define YT921X_PORT_PRIO_ORD_MAC_DA_M GENMASK(5, 3) +#define YT921X_PORT_PRIO_ORD_MAC_DA(x) FIELD_PREP(YT921X_PORT_PRIO_ORD_= MAC_DA_M, (x)) +#define YT921X_PORT_PRIO_ORD_MAC_SA_M GENMASK(2, 0) +#define YT921X_PORT_PRIO_ORD_MAC_SA(x) FIELD_PREP(YT921X_PORT_PRIO_ORD_= MAC_SA_M, (x)) #define YT921X_VLAN_IGR_FILTER 0x180280 #define YT921X_VLAN_IGR_FILTER_PORTn_BYPASS_IGMP(port) BIT((port) + 11) #define YT921X_VLAN_IGR_FILTER_PORTn(port) BIT(port) @@ -337,7 +368,7 @@ #define YT921X_FDB_OUT0 0x1804b0 #define YT921X_FDB_IO0_ADDR_HI4_M GENMASK(31, 0) #define YT921X_FDB_OUT1 0x1804b4 -#define YT921X_FDB_IO1_EGR_INT_PRI_EN BIT(31) +#define YT921X_FDB_IO1_EGR_PRIO_EN BIT(31) #define YT921X_FDB_IO1_STATUS_M GENMASK(30, 28) #define YT921X_FDB_IO1_STATUS(x) FIELD_PREP(YT921X_FDB_IO1_STATUS_M, (= x)) #define YT921X_FDB_IO1_STATUS_INVALID YT921X_FDB_IO1_STATUS(0) @@ -356,9 +387,9 @@ #define YT921X_FDB_IO2_EGR_PORTS(x) FIELD_PREP(YT921X_FDB_IO2_EGR_PORT= S_M, (x)) #define YT921X_FDB_IO2_EGR_DROP BIT(17) #define YT921X_FDB_IO2_COPY_TO_CPU BIT(16) -#define YT921X_FDB_IO2_IGR_INT_PRI_EN BIT(15) -#define YT921X_FDB_IO2_INT_PRI_M GENMASK(14, 12) -#define YT921X_FDB_IO2_INT_PRI(x) FIELD_PREP(YT921X_FDB_IO2_INT_PRI_M,= (x)) +#define YT921X_FDB_IO2_IGR_PRIO_EN BIT(15) +#define YT921X_FDB_IO2_PRIO_M GENMASK(14, 12) +#define YT921X_FDB_IO2_PRIO(x) FIELD_PREP(YT921X_FDB_IO2_PRIO_M, (x)) #define YT921X_FDB_IO2_NEW_VID_M GENMASK(11, 0) #define YT921X_FDB_IO2_NEW_VID(x) FIELD_PREP(YT921X_FDB_IO2_NEW_VID_M,= (x)) #define YT921X_FILTER_UNK_UCAST 0x180508 @@ -398,8 +429,9 @@ #define YT921X_VLAN_CTRL_FID_M GENMASK_ULL(34, 23) #define YT921X_VLAN_CTRL_FID(x) FIELD_PREP(YT921X_VLAN_CTRL_FID_M, (x)) #define YT921X_VLAN_CTRL_LEARN_DIS BIT_ULL(22) -#define YT921X_VLAN_CTRL_INT_PRI_EN BIT_ULL(21) -#define YT921X_VLAN_CTRL_INT_PRI_M GENMASK_ULL(20, 18) +#define YT921X_VLAN_CTRL_PRIO_EN BIT_ULL(21) +#define YT921X_VLAN_CTRL_PRIO_M GENMASK_ULL(20, 18) +#define YT921X_VLAN_CTRL_PRIO(x) FIELD_PREP(YT921X_VLAN_CTRL_PRIO_M, (= x)) #define YT921X_VLAN_CTRL_PORTS_M GENMASK_ULL(17, 7) #define YT921X_VLAN_CTRL_PORTS(x) FIELD_PREP(YT921X_VLAN_CTRL_PORTS_M,= (x)) #define YT921X_VLAN_CTRL_PORTn(port) BIT_ULL((port) + 7) @@ -416,14 +448,14 @@ #define YT921X_PORT_IGR_TPIDn_CTAG(x) BIT(x) =20 #define YT921X_PORTn_VLAN_CTRL(port) (0x230010 + 4 * (port)) -#define YT921X_PORT_VLAN_CTRL_SVLAN_PRI_EN BIT(31) -#define YT921X_PORT_VLAN_CTRL_CVLAN_PRI_EN BIT(30) +#define YT921X_PORT_VLAN_CTRL_SVLAN_PRIO_EN BIT(31) +#define YT921X_PORT_VLAN_CTRL_CVLAN_PRIO_EN BIT(30) #define YT921X_PORT_VLAN_CTRL_SVID_M GENMASK(29, 18) #define YT921X_PORT_VLAN_CTRL_SVID(x) FIELD_PREP(YT921X_PORT_VLAN_CTRL= _SVID_M, (x)) #define YT921X_PORT_VLAN_CTRL_CVID_M GENMASK(17, 6) #define YT921X_PORT_VLAN_CTRL_CVID(x) FIELD_PREP(YT921X_PORT_VLAN_CTRL= _CVID_M, (x)) -#define YT921X_PORT_VLAN_CTRL_SVLAN_PRI_M GENMASK(5, 3) -#define YT921X_PORT_VLAN_CTRL_CVLAN_PRI_M GENMASK(2, 0) +#define YT921X_PORT_VLAN_CTRL_SVLAN_PRIO_M GENMASK(5, 3) +#define YT921X_PORT_VLAN_CTRL_CVLAN_PRIO_M GENMASK(2, 0) #define YT921X_PORTn_VLAN_CTRL1(port) (0x230080 + 4 * (port)) #define YT921X_PORT_VLAN_CTRL1_VLAN_RANGE_EN BIT(8) #define YT921X_PORT_VLAN_CTRL1_VLAN_RANGE_PROFILE_ID_M GENMASK(7, 4) @@ -458,6 +490,8 @@ enum yt921x_fdb_entry_status { =20 #define YT921X_MSTI_NUM 16 =20 +#define YT921X_PRIO_NUM 8 + #define YT9215_MAJOR 0x9002 #define YT9218_MAJOR 0x9001 =20 --=20 2.51.0