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charset="utf-8" This is a trivial change with no functional effect which replaces the pattern: if (a) { if (b) { do_stuff(); } } with: if (a && b) { do_stuff(); }; The purpose is to reduce the delta of a subsequent functional change. Signed-off-by: Vladimir Oltean Reviewed-by: Russell King (Oracle) --- drivers/net/phy/phylink.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index 43d8380aaefb..b96ef3d1517a 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -1683,18 +1683,16 @@ static void phylink_resolve(struct work_struct *w) if (pl->act_link_an_mode !=3D MLO_AN_FIXED) phylink_apply_manual_flow(pl, &link_state); =20 - if (mac_config) { - if (link_state.interface !=3D pl->link_config.interface) { - /* The interface has changed, force the link down and - * then reconfigure. - */ - if (cur_link_state) { - phylink_link_down(pl); - cur_link_state =3D false; - } - phylink_major_config(pl, false, &link_state); - pl->link_config.interface =3D link_state.interface; + if (mac_config && link_state.interface !=3D pl->link_config.interface) { + /* The interface has changed, so force the link down and then + * reconfigure. + */ + if (cur_link_state) { + phylink_link_down(pl); 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charset="utf-8" Some drivers of MAC + tightly integrated PCS (example: SJA1105 + XPCS covered by same reset domain) need to perform resets at runtime. The reset is triggered by the MAC driver, and it needs to restore its and the PCS' registers, all invisible to phylink. However, there is a desire to simplify the API through which the MAC and the PCS interact, so this becomes challenging. Phylink holds all the necessary state to help with this operation, and can offer two helpers which walk the MAC and PCS drivers again through the callbacks required during a destructive reset operation. The procedure is as follows: Before reset, MAC driver calls phylink_replay_link_begin(): - Triggers phylink mac_link_down() and pcs_link_down() methods After reset, MAC driver calls phylink_replay_link_end(): - Triggers phylink mac_config() -> pcs_config() -> mac_link_up() -> pcs_link_up() methods. MAC and PCS registers are restored with no other custom driver code. Signed-off-by: Vladimir Oltean Reviewed-by: Russell King (Oracle) --- drivers/net/phy/phylink.c | 61 +++++++++++++++++++++++++++++++++++++-- include/linux/phylink.h | 5 ++++ 2 files changed, 63 insertions(+), 3 deletions(-) diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index b96ef3d1517a..bf4b72fa683a 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -28,6 +28,7 @@ enum { PHYLINK_DISABLE_STOPPED, PHYLINK_DISABLE_LINK, PHYLINK_DISABLE_MAC_WOL, + PHYLINK_DISABLE_REPLAY, =20 PCS_STATE_DOWN =3D 0, PCS_STATE_STARTING, @@ -77,6 +78,7 @@ struct phylink { =20 bool link_failed; bool suspend_link_up; + bool force_major_config; bool major_config_failed; bool mac_supports_eee_ops; bool mac_supports_eee; @@ -1683,9 +1685,10 @@ static void phylink_resolve(struct work_struct *w) if (pl->act_link_an_mode !=3D MLO_AN_FIXED) phylink_apply_manual_flow(pl, &link_state); =20 - if (mac_config && link_state.interface !=3D pl->link_config.interface) { - /* The interface has changed, so force the link down and then - * reconfigure. + if ((mac_config && link_state.interface !=3D pl->link_config.interface) || + pl->force_major_config) { + /* The interface has changed or a forced major configuration + * was requested, so force the link down and then reconfigure. */ if (cur_link_state) { phylink_link_down(pl); @@ -1693,6 +1696,7 @@ static void phylink_resolve(struct work_struct *w) } phylink_major_config(pl, false, &link_state); pl->link_config.interface =3D link_state.interface; + pl->force_major_config =3D false; } =20 /* If configuration of the interface failed, force the link down @@ -4356,6 +4360,57 @@ void phylink_mii_c45_pcs_get_state(struct mdio_devic= e *pcs, } EXPORT_SYMBOL_GPL(phylink_mii_c45_pcs_get_state); =20 +/** + * phylink_replay_link_begin() - begin replay of link callbacks for driver + * which loses state + * @pl: a pointer to a &struct phylink returned from phylink_create() + * + * Helper for MAC drivers which may perform a destructive reset at runtime. + * Both the own driver's mac_link_down() method is called, as well as the + * pcs_link_down() method of the split PCS (if any). + * + * This is similar to phylink_stop(), except it does not alter the state of + * the phylib PHY (it is assumed that it is not affected by the MAC destru= ctive + * reset). + */ +void phylink_replay_link_begin(struct phylink *pl) +{ + ASSERT_RTNL(); + + phylink_run_resolve_and_disable(pl, PHYLINK_DISABLE_REPLAY); +} +EXPORT_SYMBOL_GPL(phylink_replay_link_begin); + +/** + * phylink_replay_link_end() - end replay of link callbacks for driver + * which lost state + * @pl: a pointer to a &struct phylink returned from phylink_create() + * + * Helper for MAC drivers which may perform a destructive reset at runtime. + * Both the own driver's mac_config() and mac_link_up() methods, as well a= s the + * pcs_config() and pcs_link_up() method of the split PCS (if any), are ca= lled. + * + * This is similar to phylink_start(), except it does not alter the state = of + * the phylib PHY. + * + * One must call this method only within the same rtnl_lock() critical sec= tion + * as a previous phylink_replay_link_start(). + */ +void phylink_replay_link_end(struct phylink *pl) +{ + ASSERT_RTNL(); + + if (WARN(!test_bit(PHYLINK_DISABLE_REPLAY, + &pl->phylink_disable_state), + "phylink_replay_link_end() called without a prior phylink_replay_link_b= egin()\n")) + return; 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charset="utf-8" sja1105_static_config_reload() changes major settings in the switch and it requires a reset. A use case is to change things like Qdiscs (but see sja1105_reset_reasons[] for full list) while PTP synchronization is running, and the servo loop must not exit the locked state (s2). Therefore, stopping and restarting the phylink instances of all ports is not desirable, because that also stops the phylib state machine, and retriggers a seconds-long auto-negotiation process that breaks PTP. Thus, saving and restoring the link management settings is handled privately by the driver. The method got progressively more complex as SGMII support got added, because this is handled through the xpcs phylink_pcs component, to which we don't have unfettered access. Nonetheless, the switch reset line is hardwired to also reset the XPCS, creating a situation where it loses state and needs to be reprogrammed at a moment in time outside phylink's control. Although commits 907476c66d73 ("net: dsa: sja1105: call PCS config/link_up via pcs_ops structure") and 41bf58314b17 ("net: dsa: sja1105: use phylink_pcs internally") made the sja1105 <-> xpcs interaction slightly prettier, we still depend heavily on the PCS being "XPCS-like", because to back up its settings, we read the MII_BMCR register, through a mdiobus_c45_read() operation, breaking all layering separation. With the existence of phylink link callback replay helpers, we can do away with all this custom code and become even more PCS-agnostic, even though the reset domain is tightly coupled. This creates the unique opportunity to simplify away even more code than just the xpcs handling from sja1105_static_config_reload(). The sja1105_set_port_config() method is also invoked from sja1105_mac_link_up(). And since that is now called directly by phylink - we can just remove it from sja1105_static_config_reload(). This makes it possible to re-merge sja1105_set_port_speed() and sja1105_set_port_config() in a later change. Note that my only setups with sja1105 where the xpcs is used is with the xpcs on the CPU-facing port (fixed-link). Thus, I cannot test xpcs + PHY. But the replay procedure walks through all ports, and I did test a regular RGMII user port + a PHY. ptp4l[54.552]: master offset 5 s2 freq -931 path delay 764 ptp4l[55.551]: master offset 22 s2 freq -913 path delay 764 ptp4l[56.551]: master offset 13 s2 freq -915 path delay 765 ptp4l[57.552]: master offset 5 s2 freq -919 path delay 765 ptp4l[58.553]: master offset 13 s2 freq -910 path delay 765 ptp4l[59.553]: master offset 13 s2 freq -906 path delay 765 ptp4l[60.553]: master offset 6 s2 freq -909 path delay 765 ptp4l[61.553]: master offset 6 s2 freq -907 path delay 765 ptp4l[62.553]: master offset 6 s2 freq -906 path delay 765 ptp4l[63.553]: master offset 14 s2 freq -896 path delay 765 $ ip link set br0 type bridge vlan_filtering 1 [ 63.983283] sja1105 spi2.0 sw0p0: Link is Down [ 63.991913] sja1105 spi2.0: Link is Down [ 64.009784] sja1105 spi2.0: Reset switch and programmed static config. R= eason: VLAN filtering [ 64.020217] sja1105 spi2.0 sw0p0: Link is Up - 1Gbps/Full - flow control= off [ 64.030683] sja1105 spi2.0: Link is Up - 1Gbps/Full - flow control off ptp4l[64.554]: master offset 7397 s2 freq +6491 path delay 765 ptp4l[65.554]: master offset 38 s2 freq +1352 path delay 765 ptp4l[66.554]: master offset -2225 s2 freq -900 path delay 764 ptp4l[67.555]: master offset -2226 s2 freq -1569 path delay 765 ptp4l[68.555]: master offset -1553 s2 freq -1563 path delay 765 ptp4l[69.555]: master offset -865 s2 freq -1341 path delay 765 ptp4l[70.555]: master offset -401 s2 freq -1137 path delay 765 ptp4l[71.556]: master offset -145 s2 freq -1001 path delay 765 ptp4l[72.558]: master offset -26 s2 freq -926 path delay 765 ptp4l[73.557]: master offset 30 s2 freq -877 path delay 765 ptp4l[74.557]: master offset 47 s2 freq -851 path delay 765 ptp4l[75.557]: master offset 29 s2 freq -855 path delay 765 Signed-off-by: Vladimir Oltean --- drivers/net/dsa/sja1105/sja1105_main.c | 58 ++++---------------------- 1 file changed, 8 insertions(+), 50 deletions(-) diff --git a/drivers/net/dsa/sja1105/sja1105_main.c b/drivers/net/dsa/sja11= 05/sja1105_main.c index aa2145cf29a6..3936d63f0645 100644 --- a/drivers/net/dsa/sja1105/sja1105_main.c +++ b/drivers/net/dsa/sja1105/sja1105_main.c @@ -2280,14 +2280,12 @@ int sja1105_static_config_reload(struct sja1105_pri= vate *priv, { struct ptp_system_timestamp ptp_sts_before; struct ptp_system_timestamp ptp_sts_after; - u16 bmcr[SJA1105_MAX_NUM_PORTS] =3D {0}; - u64 mac_speed[SJA1105_MAX_NUM_PORTS]; struct sja1105_mac_config_entry *mac; struct dsa_switch *ds =3D priv->ds; + struct dsa_port *dp; s64 t1, t2, t3, t4; - s64 t12, t34; - int rc, i; - s64 now; + s64 t12, t34, now; + int rc; =20 mutex_lock(&priv->fdb_lock); mutex_lock(&priv->mgmt_lock); @@ -2299,13 +2297,9 @@ int sja1105_static_config_reload(struct sja1105_priv= ate *priv, * switch wants to see in the static config in order to allow us to * change it through the dynamic interface later. */ - for (i =3D 0; i < ds->num_ports; i++) { - mac_speed[i] =3D mac[i].speed; - mac[i].speed =3D priv->info->port_speed[SJA1105_SPEED_AUTO]; - - if (priv->pcs[i]) - bmcr[i] =3D mdiobus_c45_read(priv->mdio_pcs, i, - MDIO_MMD_VEND2, MDIO_CTRL1); + dsa_switch_for_each_available_port(dp, ds) { + phylink_replay_link_begin(dp->pl); + mac[dp->index].speed =3D priv->info->port_speed[SJA1105_SPEED_AUTO]; } =20 /* No PTP operations can run right now */ @@ -2359,44 +2353,8 @@ int sja1105_static_config_reload(struct sja1105_priv= ate *priv, goto out; } =20 - for (i =3D 0; i < ds->num_ports; i++) { - struct phylink_pcs *pcs =3D priv->pcs[i]; - unsigned int neg_mode; - - mac[i].speed =3D mac_speed[i]; - rc =3D sja1105_set_port_config(priv, i); - if (rc < 0) - goto out; - - if (!pcs) - continue; - - if (bmcr[i] & BMCR_ANENABLE) - neg_mode =3D PHYLINK_PCS_NEG_INBAND_ENABLED; - else - neg_mode =3D PHYLINK_PCS_NEG_OUTBAND; - - rc =3D pcs->ops->pcs_config(pcs, neg_mode, priv->phy_mode[i], - NULL, true); - if (rc < 0) - goto out; - - if (neg_mode =3D=3D PHYLINK_PCS_NEG_OUTBAND) { - int speed =3D SPEED_UNKNOWN; - - if (priv->phy_mode[i] =3D=3D PHY_INTERFACE_MODE_2500BASEX) - speed =3D SPEED_2500; - else if (bmcr[i] & BMCR_SPEED1000) - speed =3D SPEED_1000; - else if (bmcr[i] & BMCR_SPEED100) - speed =3D SPEED_100; - else - speed =3D SPEED_10; - - pcs->ops->pcs_link_up(pcs, neg_mode, priv->phy_mode[i], - speed, DUPLEX_FULL); - } - } + dsa_switch_for_each_available_port(dp, ds) + phylink_replay_link_end(dp->pl); =20 rc =3D sja1105_reload_cbs(priv); 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charset="utf-8" Commit a18891b55703 ("net: dsa: sja1105: simplify static configuration reload") split sja1105_mac_link_up() -> sja1105_adjust_port_config() into two separate: - sja1105_set_port_speed() - sja1105_set_port_config() in order to pick up the second sja1105_set_port_config() and reuse it for the sja1105_static_config_reload() procedure which involves saving and restoring MAC and PCS settings. Now that these settings are restored by phylink itself, the driver no longer needs to call its own sja1105_set_port_config(), and the splitting is unnatural. Merge the functions back, which is to say that the only supported internal code path is to submit the MAC Configuration Table entry to hardware after phylink has dictated what we should set it to. Signed-off-by: Vladimir Oltean --- drivers/net/dsa/sja1105/sja1105_main.c | 26 +++----------------------- 1 file changed, 3 insertions(+), 23 deletions(-) diff --git a/drivers/net/dsa/sja1105/sja1105_main.c b/drivers/net/dsa/sja11= 05/sja1105_main.c index 3936d63f0645..2a4a0fe20dae 100644 --- a/drivers/net/dsa/sja1105/sja1105_main.c +++ b/drivers/net/dsa/sja1105/sja1105_main.c @@ -1260,7 +1260,9 @@ static int sja1105_set_port_speed(struct sja1105_priv= ate *priv, int port, int speed_mbps) { struct sja1105_mac_config_entry *mac; + struct device *dev =3D priv->ds->dev; u64 speed; + int rc; =20 /* On P/Q/R/S, one can read from the device via the MAC reconfiguration * tables. On E/T, MAC reconfig tables are not readable, only writable. @@ -1305,26 +1307,6 @@ static int sja1105_set_port_speed(struct sja1105_pri= vate *priv, int port, */ mac[port].speed =3D speed; =20 - return 0; -} - -/* Write the MAC Configuration Table entry and, if necessary, the CGU sett= ings, - * after a link speedchange for this port. - */ -static int sja1105_set_port_config(struct sja1105_private *priv, int port) -{ - struct sja1105_mac_config_entry *mac; - struct device *dev =3D priv->ds->dev; - int rc; - - /* On P/Q/R/S, one can read from the device via the MAC reconfiguration - * tables. On E/T, MAC reconfig tables are not readable, only writable. - * We have to *know* what the MAC looks like. For the sake of keeping - * the code common, we'll use the static configuration tables as a - * reasonable approximation for both E/T and P/Q/R/S. - */ - mac =3D priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; - /* Write to the dynamic reconfiguration tables */ rc =3D sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port, &mac[port], true); @@ -1380,9 +1362,7 @@ static void sja1105_mac_link_up(struct phylink_config= *config, struct sja1105_private *priv =3D dp->ds->priv; int port =3D dp->index; =20 - if (!sja1105_set_port_speed(priv, port, speed)) - sja1105_set_port_config(priv, port); - + sja1105_set_port_speed(priv, port, speed); sja1105_inhibit_tx(priv, BIT(port), false); } =20 --=20 2.34.1