From nobody Tue Feb 10 04:13:47 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CFBA2475D0; Mon, 19 Jan 2026 12:16:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768824966; cv=none; b=mn07ivJsSBVzyE3X503Isg80ZdW7bM1gWYMwP4TaudfBvAwvdgZWwZbR2ZXd4JrULG9uili7Vg+jTTACYxcaSeXGxul1o+K2YMNuCmd4omOwhOxG8lDCjnsKtlHhVo+9qqG4FDBWEBtxbE1D1H3q685gdrr/4vQQghMHeLnU+3M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768824966; c=relaxed/simple; bh=pNYNSUyL1HOsyww96CqaGvEFrfFH4JWObFMRkUCSyMs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=Xk8N43L6xj86EDdL6sLNIKFkI4gxOdJz7ixas8+IQn7AiNmqMoWlTrQi7txbHg7TquSmfevLSQUCOerkkGKXIFqxWEZnEX4JFihw3l/vL0lCFn5s+Go+A/MKXEd9YC5HbEIu6MEZWYWjZYSdtenQ/aQyUKEwj6rrNvpqNPQaxd8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=QXkCPIQe; arc=none smtp.client-ip=117.135.210.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="QXkCPIQe" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id; bh=ekmcjPYBNBB/V0T JtT1FuIoSPurJCu2djLYW10Uw6WM=; b=QXkCPIQexK6eljSJwHQCQZ1C6SHx3Eb 5KqhRAD9cSK73iNGREmtNL2UE/xEhhWIs+B+aggzthl+Z5qoytxrN0QeXrZ42jkK kLAkn8ZR4sQ/0VwYt/HyK98n5GxyDDU3mgHq9s9uTHmbu5bXWxe0pUP+/On0XBLs ehg4AZfii9vk= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-4 (Coremail) with SMTP id _____wBHtZdDIG5pljmWGw--.3726S10; Mon, 19 Jan 2026 20:15:14 +0800 (CST) From: Wenliang Yan To: linux@roeck-us.net, Jean Delvare Cc: Wenliang Yan , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 8/8] hwmon: (ina3221) Modify write/read functions for 'in' and 'curr' attribute Date: Mon, 19 Jan 2026 07:14:46 -0500 Message-Id: <20260119121446.17469-9-wenliang202407@163.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260119121446.17469-1-wenliang202407@163.com> References: <20260119121446.17469-1-wenliang202407@163.com> X-CM-TRANSID: _____wBHtZdDIG5pljmWGw--.3726S10 X-Coremail-Antispam: 1Uf129KBjvJXoWxurW5uFy5GFW7Ar15ZF4fXwb_yoW7Gryrp3 yUGFWrtrWjq3WSgrs2kF4DWr15tr4xW3y2yr9rK3sYva1UAryqkFyrG3Wq93y5Gr93WF4x JayxtFW8ua1qqr7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0JUXeOdUUUUU= X-CM-SenderInfo: xzhqzxhdqjjiisuqlqqrwthudrp/xtbCvxIS5WluIFJMKwAA3I Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Modified the relevant read/write functions for 'in' and 'curr' attributes, adding support for crit, lcrit, crit_alarm, and lcrit_alarm features. Signed-off-by: Wenliang Yan --- drivers/hwmon/ina3221.c | 105 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 101 insertions(+), 4 deletions(-) diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c index 2338b3288950..fdcd92082c02 100644 --- a/drivers/hwmon/ina3221.c +++ b/drivers/hwmon/ina3221.c @@ -380,6 +380,12 @@ static const u8 ina3221_in_reg[] =3D { INA3221_SHUNT_SUM, }; =20 +static const u8 alert_flag[] =3D { + F_AFF1, + F_AFF2, + F_AFF3, +}; + static int ina3221_read_chip(struct device *dev, u32 attr, long *val) { struct ina3221_data *ina =3D dev_get_drvdata(dev); @@ -442,6 +448,40 @@ static int ina3221_read_in(struct device *dev, u32 att= r, int channel, long *val) case hwmon_in_enable: *val =3D ina3221_is_enabled(ina, channel); return 0; + case hwmon_in_crit: + case hwmon_in_lcrit: + if (channel >=3D INA3221_NUM_CHANNELS) + return -EOPNOTSUPP; + + if (!ina3221_is_enabled(ina, channel)) + return -ENODATA; + + reg =3D limit_regs[channel]; + ret =3D ina3221_read_value(ina, reg, ®val); + if (ret) + return ret; + /* + * Scale of bus voltage (mV): LSB is 8mV + */ + *val =3D regval * 8; + return 0; + case hwmon_in_crit_alarm: + case hwmon_in_lcrit_alarm: + if (channel >=3D INA3221_NUM_CHANNELS) + return -EOPNOTSUPP; + /* No actual register read if channel is disabled */ + if (!ina3221_is_enabled(ina, channel)) { + /* Return 0 for alert flags */ + *val =3D 0; + return 0; + } + + reg =3D alert_flag[channel]; + ret =3D regmap_field_read(ina->fields[reg], ®val); + if (ret) + return ret; + *val =3D regval; + return 0; default: return -EOPNOTSUPP; } @@ -501,6 +541,28 @@ static int ina3221_read_curr(struct device *dev, u32 a= ttr, /* Return current in mA */ *val =3D DIV_ROUND_CLOSEST(voltage_nv, resistance_uo); return 0; + case hwmon_curr_lcrit: + if (!resistance_uo) + return -ENODATA; + + if (channel >=3D INA3221_NUM_CHANNELS) + return -EOPNOTSUPP; + + reg =3D limit_regs[channel]; + ret =3D ina3221_read_value(ina, reg, ®val); + if (ret) + return ret; + + /* Return current in mA */ + *val =3D DIV_S64_ROUND_CLOSEST((s64)regval * (s64)ina->current_lsb_uA, 1= 000); + return 0; + case hwmon_curr_lcrit_alarm: + if (channel >=3D INA3221_NUM_CHANNELS) + return -EOPNOTSUPP; + + reg =3D alert_flag[channel]; + + fallthrough; case hwmon_curr_crit_alarm: case hwmon_curr_max_alarm: /* No actual register read if channel is disabled */ @@ -703,10 +765,9 @@ static int ina3221_write_chip(struct device *dev, u32 = attr, long val) } } =20 -static int ina3221_write_curr(struct device *dev, u32 attr, - int channel, long val) +static int ina3221_write_curr_shunt(struct ina3221_data *ina, u32 attr, + int channel, long val) { - struct ina3221_data *ina =3D dev_get_drvdata(dev); struct ina3221_input *input =3D ina->inputs; u8 reg =3D ina3221_curr_reg[attr][channel]; int resistance_uo, current_ma, voltage_uv; @@ -749,6 +810,22 @@ static int ina3221_write_curr(struct device *dev, u32 = attr, return regmap_write(ina->regmap, reg, regval); } =20 +static int ina3221_write_curr(struct device *dev, u32 attr, + int channel, long val) +{ + struct ina3221_data *ina =3D dev_get_drvdata(dev); + + switch (attr) { + case hwmon_curr_crit: + case hwmon_curr_max: + return ina3221_write_curr_shunt(ina, attr, channel, val); + case hwmon_curr_lcrit: + return sq52210_alert_limit_write(ina, SQ52210_ALERT_SUL, channel, val); + default: + return 0; + } +} + static int ina3221_write_enable(struct device *dev, int channel, bool enab= le) { struct ina3221_data *ina =3D dev_get_drvdata(dev); @@ -797,6 +874,26 @@ static int ina3221_write_enable(struct device *dev, in= t channel, bool enable) return ret; } =20 +static int ina3221_write_in(struct device *dev, u32 attr, int channel, lon= g val) +{ + struct ina3221_data *ina =3D dev_get_drvdata(dev); + + if (attr =3D=3D hwmon_in_lcrit || attr =3D=3D hwmon_in_crit) + if (channel >=3D INA3221_NUM_CHANNELS) + return -EOPNOTSUPP; + + switch (attr) { + case hwmon_in_lcrit: + return sq52210_alert_limit_write(ina, SQ52210_ALERT_BUL, channel, val); + case hwmon_in_crit: + return sq52210_alert_limit_write(ina, SQ52210_ALERT_BOL, channel, val); + case hwmon_in_enable: + return ina3221_write_enable(dev, channel, val); + default: + return 0; + } +} + static int ina3221_write_power(struct device *dev, u32 attr, int channel, = long val) { struct ina3221_data *ina =3D dev_get_drvdata(dev); @@ -846,7 +943,7 @@ static int ina3221_write(struct device *dev, enum hwmon= _sensor_types type, break; case hwmon_in: /* 0-align channel ID */ - ret =3D ina3221_write_enable(dev, channel - 1, val); + ret =3D ina3221_write_in(dev, attr, channel - 1, val); break; case hwmon_curr: ret =3D ina3221_write_curr(dev, attr, channel, val); --=20 2.17.1