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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SJ5PEPF000001E9.mail.protection.outlook.com (10.167.242.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9542.4 via Frontend Transport; Mon, 19 Jan 2026 09:10:18 +0000 Received: from satlexmb07.amd.com (10.181.42.216) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Mon, 19 Jan 2026 03:10:17 -0600 Received: from xhdapps-pcie2.xilinx.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Mon, 19 Jan 2026 01:10:15 -0800 From: Devendra K Verma To: , , CC: , , , , Subject: [PATCH v9 2/2] dmaengine: dw-edma: Add non-LL mode Date: Mon, 19 Jan 2026 14:40:09 +0530 Message-ID: <20260119091009.70288-3-devendra.verma@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260119091009.70288-1-devendra.verma@amd.com> References: <20260119091009.70288-1-devendra.verma@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001E9:EE_|IA0PPFB67404FBA:EE_ X-MS-Office365-Filtering-Correlation-Id: 29b06a19-6a9f-445d-8586-08de573a90d6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|376014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2026 09:10:18.1785 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 29b06a19-6a9f-445d-8586-08de573a90d6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001E9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PPFB67404FBA Content-Type: text/plain; charset="utf-8" AMD MDB IP supports Linked List (LL) mode as well as non-LL mode. The current code does not have the mechanisms to enable the DMA transactions using the non-LL mode. The following two cases are added with this patch: - For the AMD (Xilinx) only, when a valid physical base address of the device side DDR is not configured, then the IP can still be used in non-LL mode. For all the channels DMA transactions will be using the non-LL mode only. This, the default non-LL mode, is not applicable for Synopsys IP with the current code addition. - If the default mode is LL-mode, for both AMD (Xilinx) and Synosys, and if user wants to use non-LL mode then user can do so via configuring the peripheral_config param of dma_slave_config. Signed-off-by: Devendra K Verma --- Changes in v9 Fixed compilation errors related to macro name mismatch. Changes in v8 Cosmetic change related to comment and code. Changes in v7 No change Changes in v6 Gave definition to bits used for channel configuration. Removed the comment related to doorbell. Changes in v5 Variable name 'nollp' changed to 'non_ll'. In the dw_edma_device_config() WARN_ON replaced with dev_err(). Comments follow the 80-column guideline. Changes in v4 No change Changes in v3 No change Changes in v2 Reverted the function return type to u64 for dw_edma_get_phys_addr(). Changes in v1 Changed the function return type for dw_edma_get_phys_addr(). Corrected the typo raised in review. --- drivers/dma/dw-edma/dw-edma-core.c | 42 +++++++++++++++--- drivers/dma/dw-edma/dw-edma-core.h | 1 + drivers/dma/dw-edma/dw-edma-pcie.c | 44 +++++++++++++------ drivers/dma/dw-edma/dw-hdma-v0-core.c | 61 ++++++++++++++++++++++++++- drivers/dma/dw-edma/dw-hdma-v0-regs.h | 1 + include/linux/dma/edma.h | 1 + 6 files changed, 131 insertions(+), 19 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-ed= ma-core.c index b43255f914f3..d37112bc2e16 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -223,8 +223,32 @@ static int dw_edma_device_config(struct dma_chan *dcha= n, struct dma_slave_config *config) { struct dw_edma_chan *chan =3D dchan2dw_edma_chan(dchan); + int non_ll =3D 0; + + if (config->peripheral_config && + config->peripheral_size !=3D sizeof(int)) { + dev_err(dchan->device->dev, + "config param peripheral size mismatch\n"); + return -EINVAL; + } =20 memcpy(&chan->config, config, sizeof(*config)); + + /* + * When there is no valid LLP base address available then the default + * DMA ops will use the non-LL mode. + * + * Cases where LL mode is enabled and client wants to use the non-LL + * mode then also client can do so via providing the peripheral_config + * param. + */ + if (config->peripheral_config) + non_ll =3D *(int *)config->peripheral_config; + + chan->non_ll =3D false; + if (chan->dw->chip->non_ll || (!chan->dw->chip->non_ll && non_ll)) + chan->non_ll =3D true; + chan->configured =3D true; =20 return 0; @@ -353,7 +377,7 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer) struct dw_edma_chan *chan =3D dchan2dw_edma_chan(xfer->dchan); enum dma_transfer_direction dir =3D xfer->direction; struct scatterlist *sg =3D NULL; - struct dw_edma_chunk *chunk; + struct dw_edma_chunk *chunk =3D NULL; struct dw_edma_burst *burst; struct dw_edma_desc *desc; u64 src_addr, dst_addr; @@ -419,9 +443,11 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer) if (unlikely(!desc)) goto err_alloc; =20 - chunk =3D dw_edma_alloc_chunk(desc); - if (unlikely(!chunk)) - goto err_alloc; + if (!chan->non_ll) { + chunk =3D dw_edma_alloc_chunk(desc); + if (unlikely(!chunk)) + goto err_alloc; + } =20 if (xfer->type =3D=3D EDMA_XFER_INTERLEAVED) { src_addr =3D xfer->xfer.il->src_start; @@ -450,7 +476,13 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer) if (xfer->type =3D=3D EDMA_XFER_SCATTER_GATHER && !sg) break; =20 - if (chunk->bursts_alloc =3D=3D chan->ll_max) { + /* + * For non-LL mode, only a single burst can be handled + * in a single chunk unlike LL mode where multiple bursts + * can be configured in a single chunk. + */ + if ((chunk && chunk->bursts_alloc =3D=3D chan->ll_max) || + chan->non_ll) { chunk =3D dw_edma_alloc_chunk(desc); if (unlikely(!chunk)) goto err_alloc; diff --git a/drivers/dma/dw-edma/dw-edma-core.h b/drivers/dma/dw-edma/dw-ed= ma-core.h index 71894b9e0b15..c8e3d196a549 100644 --- a/drivers/dma/dw-edma/dw-edma-core.h +++ b/drivers/dma/dw-edma/dw-edma-core.h @@ -86,6 +86,7 @@ struct dw_edma_chan { u8 configured; =20 struct dma_slave_config config; + bool non_ll; }; =20 struct dw_edma_irq { diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-ed= ma-pcie.c index 76fedeb1ec8d..004c0a7132b2 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -298,6 +298,15 @@ static void dw_edma_pcie_get_xilinx_dma_data(struct pc= i_dev *pdev, pdata->devmem_phys_off =3D off; } =20 +static u64 dw_edma_get_phys_addr(struct pci_dev *pdev, + struct dw_edma_pcie_data *pdata, + enum pci_barno bar) +{ + if (pdev->vendor =3D=3D PCI_VENDOR_ID_XILINX) + return pdata->devmem_phys_off; + return pci_bus_address(pdev, bar); +} + static int dw_edma_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *pid) { @@ -307,6 +316,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, struct dw_edma_chip *chip; int err, nr_irqs; int i, mask; + bool non_ll =3D false; =20 vsec_data =3D kmalloc(sizeof(*vsec_data), GFP_KERNEL); if (!vsec_data) @@ -332,21 +342,24 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, =20 /* * There is no valid address found for the LL memory - * space on the device side. + * space on the device side. In the absence of LL base + * address use the non-LL mode or simple mode supported by + * the HDMA IP. */ if (vsec_data->devmem_phys_off =3D=3D DW_PCIE_XILINX_MDB_INVALID_ADDR) - return -ENOMEM; + non_ll =3D true; =20 /* * Configure the channel LL and data blocks if number of * channels enabled in VSEC capability are more than the * channels configured in xilinx_mdb_data. */ - dw_edma_set_chan_region_offset(vsec_data, BAR_2, 0, - DW_PCIE_XILINX_MDB_LL_OFF_GAP, - DW_PCIE_XILINX_MDB_LL_SIZE, - DW_PCIE_XILINX_MDB_DT_OFF_GAP, - DW_PCIE_XILINX_MDB_DT_SIZE); + if (!non_ll) + dw_edma_set_chan_region_offset(vsec_data, BAR_2, 0, + DW_PCIE_XILINX_MDB_LL_OFF_GAP, + DW_PCIE_XILINX_MDB_LL_SIZE, + DW_PCIE_XILINX_MDB_DT_OFF_GAP, + DW_PCIE_XILINX_MDB_DT_SIZE); } =20 /* Mapping PCI BAR regions */ @@ -394,6 +407,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, chip->mf =3D vsec_data->mf; chip->nr_irqs =3D nr_irqs; chip->ops =3D &dw_edma_pcie_plat_ops; + chip->non_ll =3D non_ll; =20 chip->ll_wr_cnt =3D vsec_data->wr_ch_cnt; chip->ll_rd_cnt =3D vsec_data->rd_ch_cnt; @@ -402,7 +416,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, if (!chip->reg_base) return -ENOMEM; =20 - for (i =3D 0; i < chip->ll_wr_cnt; i++) { + for (i =3D 0; i < chip->ll_wr_cnt && !non_ll; i++) { struct dw_edma_region *ll_region =3D &chip->ll_region_wr[i]; struct dw_edma_region *dt_region =3D &chip->dt_region_wr[i]; struct dw_edma_block *ll_block =3D &vsec_data->ll_wr[i]; @@ -413,7 +427,8 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, return -ENOMEM; =20 ll_region->vaddr.io +=3D ll_block->off; - ll_region->paddr =3D pci_bus_address(pdev, ll_block->bar); + ll_region->paddr =3D dw_edma_get_phys_addr(pdev, vsec_data, + ll_block->bar); ll_region->paddr +=3D ll_block->off; ll_region->sz =3D ll_block->sz; =20 @@ -422,12 +437,13 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, return -ENOMEM; =20 dt_region->vaddr.io +=3D dt_block->off; - dt_region->paddr =3D pci_bus_address(pdev, dt_block->bar); + dt_region->paddr =3D dw_edma_get_phys_addr(pdev, vsec_data, + dt_block->bar); dt_region->paddr +=3D dt_block->off; dt_region->sz =3D dt_block->sz; } =20 - for (i =3D 0; i < chip->ll_rd_cnt; i++) { + for (i =3D 0; i < chip->ll_rd_cnt && !non_ll; i++) { struct dw_edma_region *ll_region =3D &chip->ll_region_rd[i]; struct dw_edma_region *dt_region =3D &chip->dt_region_rd[i]; struct dw_edma_block *ll_block =3D &vsec_data->ll_rd[i]; @@ -438,7 +454,8 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, return -ENOMEM; =20 ll_region->vaddr.io +=3D ll_block->off; - ll_region->paddr =3D pci_bus_address(pdev, ll_block->bar); + ll_region->paddr =3D dw_edma_get_phys_addr(pdev, vsec_data, + ll_block->bar); ll_region->paddr +=3D ll_block->off; ll_region->sz =3D ll_block->sz; =20 @@ -447,7 +464,8 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, return -ENOMEM; =20 dt_region->vaddr.io +=3D dt_block->off; - dt_region->paddr =3D pci_bus_address(pdev, dt_block->bar); + dt_region->paddr =3D dw_edma_get_phys_addr(pdev, vsec_data, + dt_block->bar); dt_region->paddr +=3D dt_block->off; dt_region->sz =3D dt_block->sz; } diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw= -hdma-v0-core.c index e3f8db4fe909..a5d12bc400ea 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c @@ -225,7 +225,7 @@ static void dw_hdma_v0_sync_ll_data(struct dw_edma_chun= k *chunk) readl(chunk->ll_region.vaddr.io); } =20 -static void dw_hdma_v0_core_start(struct dw_edma_chunk *chunk, bool first) +static void dw_hdma_v0_core_ll_start(struct dw_edma_chunk *chunk, bool fir= st) { struct dw_edma_chan *chan =3D chunk->chan; struct dw_edma *dw =3D chan->dw; @@ -263,6 +263,65 @@ static void dw_hdma_v0_core_start(struct dw_edma_chunk= *chunk, bool first) SET_CH_32(dw, chan->dir, chan->id, doorbell, HDMA_V0_DOORBELL_START); } =20 +static void dw_hdma_v0_core_non_ll_start(struct dw_edma_chunk *chunk) +{ + struct dw_edma_chan *chan =3D chunk->chan; + struct dw_edma *dw =3D chan->dw; + struct dw_edma_burst *child; + u32 val; + + list_for_each_entry(child, &chunk->burst->list, list) { + SET_CH_32(dw, chan->dir, chan->id, ch_en, HDMA_V0_CH_EN); + + /* Source address */ + SET_CH_32(dw, chan->dir, chan->id, sar.lsb, + lower_32_bits(child->sar)); + SET_CH_32(dw, chan->dir, chan->id, sar.msb, + upper_32_bits(child->sar)); + + /* Destination address */ + SET_CH_32(dw, chan->dir, chan->id, dar.lsb, + lower_32_bits(child->dar)); + SET_CH_32(dw, chan->dir, chan->id, dar.msb, + upper_32_bits(child->dar)); + + /* Transfer size */ + SET_CH_32(dw, chan->dir, chan->id, transfer_size, child->sz); + + /* Interrupt setup */ + val =3D GET_CH_32(dw, chan->dir, chan->id, int_setup) | + HDMA_V0_STOP_INT_MASK | + HDMA_V0_ABORT_INT_MASK | + HDMA_V0_LOCAL_STOP_INT_EN | + HDMA_V0_LOCAL_ABORT_INT_EN; + + if (!(dw->chip->flags & DW_EDMA_CHIP_LOCAL)) { + val |=3D HDMA_V0_REMOTE_STOP_INT_EN | + HDMA_V0_REMOTE_ABORT_INT_EN; + } + + SET_CH_32(dw, chan->dir, chan->id, int_setup, val); + + /* Channel control setup */ + val =3D GET_CH_32(dw, chan->dir, chan->id, control1); + val &=3D ~HDMA_V0_LINKLIST_EN; + SET_CH_32(dw, chan->dir, chan->id, control1, val); + + SET_CH_32(dw, chan->dir, chan->id, doorbell, + HDMA_V0_DOORBELL_START); + } +} + +static void dw_hdma_v0_core_start(struct dw_edma_chunk *chunk, bool first) +{ + struct dw_edma_chan *chan =3D chunk->chan; + + if (chan->non_ll) + dw_hdma_v0_core_non_ll_start(chunk); + else + dw_hdma_v0_core_ll_start(chunk, first); +} + static void dw_hdma_v0_core_ch_config(struct dw_edma_chan *chan) { struct dw_edma *dw =3D chan->dw; diff --git a/drivers/dma/dw-edma/dw-hdma-v0-regs.h b/drivers/dma/dw-edma/dw= -hdma-v0-regs.h index eab5fd7177e5..7759ba9b4850 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-regs.h +++ b/drivers/dma/dw-edma/dw-hdma-v0-regs.h @@ -12,6 +12,7 @@ #include =20 #define HDMA_V0_MAX_NR_CH 8 +#define HDMA_V0_CH_EN BIT(0) #define HDMA_V0_LOCAL_ABORT_INT_EN BIT(6) #define HDMA_V0_REMOTE_ABORT_INT_EN BIT(5) #define HDMA_V0_LOCAL_STOP_INT_EN BIT(4) diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index 3080747689f6..78ce31b049ae 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -99,6 +99,7 @@ struct dw_edma_chip { enum dw_edma_map_format mf; =20 struct dw_edma *dw; + bool non_ll; }; =20 /* Export to the platform drivers */ --=20 2.43.0