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smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tRPacVIB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tRPacVIB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EE6D4C19424; Tue, 20 Jan 2026 04:15:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1768882527; bh=08+NoXyvW3Xk6Oo5KOcsUwbtLfO2FJFdCtJSOZ1Zuws=; h=From:Date:Subject:References:In-Reply-To:To:From; b=tRPacVIB4t2VbsUGJIO2a17wCy77QjWXAqYWwS+DmywWQ4CWeiln7CdoF7NgrS5WO QctBL5aVxNJi9c4/0f0XNETkCdcbkj5n0ztIYdU9Mbr0gJzs7QpYdlecRDZg9xYIe+ uE/TOVtnIlYqqra03dzwi5VJodv6Bhdk6Ky0sTFNwhoEU3aTMPuXGRURkPrgwkh0Vp 9nJo0cOP4H6KavTf6THwQiyeigZ17k9C4fnZx4rQPy1tYmDSAmaywdZv1CxvaxyEHa zlQbXvbGESSPyLfKcu5hgSEZDfutLFOyGI/vdAMsc2gc4QoK4BZhGE+rBO3g7wG/Ae 2xdke4ZtlmOdw== From: Drew Fustini Date: Mon, 19 Jan 2026 20:14:54 -0800 Subject: [PATCH NFU RFC 17/19] riscv: dts: qemu: add dump from virt machine Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-ssqosid-cbqri-v1-17-aa2a75153832@kernel.org> References: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> In-Reply-To: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Conor Dooley , Krzysztof Kozlowski , Rob Herring , Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=17006; i=fustini@kernel.org; h=from:subject:message-id; bh=08+NoXyvW3Xk6Oo5KOcsUwbtLfO2FJFdCtJSOZ1Zuws=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTmMwY3Jj7gXmZ++ZKKxNwG3X8sSgwn27sPfVXYGlV3e JL8woNPOkpZGMS4GGTFFFk2fci7sMQr9OuC+S+2wcxhZQIZwsDFKQATmWbFyLBL4M0U39MWP16x ZByefHHb1xbd//PaHiTNPVG+SO2xi1IXw//8Lc5J4SvPOkR0/vQxNpD/lTzvQqm8REaej170hLb 6RC4A X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 [NOT FOR UPSTREAM] Dumped dtb from qemu branch based on the v4 riscv-ssqosid-cbqri series. $ qemu-system-riscv64 -version QEMU emulator version 10.2.50 (v10.2.0-208-g087112467867) Copyright (c) 2003-2025 Fabrice Bellard and the QEMU Project developers $ qemu-system-riscv64 \ -M virt \ -nographic \ -smp 8 \ -bios output/images/fw_jump.elf \ -kernel $HOME/kernel/cbqri-linux/arch/riscv/boot/Image \ -append "root=3D/dev/vda ro" \ -drive file=3Doutput/images/rootfs.ext2,format=3Draw,id=3Dhd0 \ -device virtio-blk-device,drive=3Dhd0 \ -machine dumpdtb=3Dqemu.dtb Link: https://lore.kernel.org/all/20260105-riscv-ssqosid-cbqri-v4-0-9ad7671= dde78@kernel.org/ Link: https://github.com/tt-fustini/qemu/tree/b4/riscv-ssqosid-cbqri Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts | 399 +++++++++++++++++++++++= ++++ 1 file changed, 399 insertions(+) diff --git a/arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts b/arch/riscv/boot= /dts/qemu/qemu-virt-cbqri.dts new file mode 100644 index 000000000000..4c6257bec42d --- /dev/null +++ b/arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts @@ -0,0 +1,399 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/dts-v1/; + +/ { + #address-cells =3D <0x02>; + #size-cells =3D <0x02>; + compatible =3D "riscv-virtio"; + model =3D "riscv-virtio,qemu"; + + poweroff { + value =3D <0x5555>; + offset =3D <0x00>; + regmap =3D <0x12>; + compatible =3D "syscon-poweroff"; + }; + + reboot { + value =3D <0x7777>; + offset =3D <0x00>; + regmap =3D <0x12>; + compatible =3D "syscon-reboot"; + }; + + platform-bus@4000000 { + interrupt-parent =3D <0x11>; + ranges =3D <0x00 0x00 0x4000000 0x2000000>; + #address-cells =3D <0x01>; + #size-cells =3D <0x01>; + compatible =3D "qemu,platform\0simple-bus"; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x00 0x80000000 0x00 0x8000000>; + }; + + cpus { + #address-cells =3D <0x01>; + #size-cells =3D <0x00>; + timebase-frequency =3D <0x989680>; + + cpu@0 { + phandle =3D <0x0f>; + device_type =3D "cpu"; + reg =3D <0x00>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cbop-block-size =3D <0x40>; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa-extensions =3D "i\0m\0a\0f\0d\0c\0h\0zic64b\0zicbom\0zicbop\0= zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicntr\0zicsr\0zifencei\0zihint= ntl\0zihintpause\0zihpm\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zca\0zcd= \0zba\0zbb\0zbc\0zbs\0sdtrig\0shcounterenw\0shgatpa\0shtvala\0shvsatpa\0shv= stvala\0shvstvecd\0ssccptr\0sscounterenw\0ssqosid\0ssstrict\0sstc\0sstvala\= 0sstvecd\0ssu64xl\0svadu\0svvptc"; + riscv,isa-base =3D "rv64i"; + riscv,isa =3D "rv64imafdch_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_= zicclsm_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zmmul_za6= 4rs_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_sdtrig_shcounterenw_shga= tpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscounterenw_ssqosid_ssstr= ict_sstc_sstvala_sstvecd_ssu64xl_svadu_svvptc"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x10>; + }; + }; + + cpu@1 { + phandle =3D <0x0d>; + device_type =3D "cpu"; + reg =3D <0x01>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cbop-block-size =3D <0x40>; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa-extensions =3D "i\0m\0a\0f\0d\0c\0h\0zic64b\0zicbom\0zicbop\0= zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicntr\0zicsr\0zifencei\0zihint= ntl\0zihintpause\0zihpm\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zca\0zcd= \0zba\0zbb\0zbc\0zbs\0sdtrig\0shcounterenw\0shgatpa\0shtvala\0shvsatpa\0shv= stvala\0shvstvecd\0ssccptr\0sscounterenw\0ssqosid\0ssstrict\0sstc\0sstvala\= 0sstvecd\0ssu64xl\0svadu\0svvptc"; + riscv,isa-base =3D "rv64i"; + riscv,isa =3D "rv64imafdch_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_= zicclsm_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zmmul_za6= 4rs_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_sdtrig_shcounterenw_shga= tpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscounterenw_ssqosid_ssstr= ict_sstc_sstvala_sstvecd_ssu64xl_svadu_svvptc"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x0e>; + }; + }; + + cpu@2 { + phandle =3D <0x0b>; + device_type =3D "cpu"; + reg =3D <0x02>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cbop-block-size =3D <0x40>; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa-extensions =3D "i\0m\0a\0f\0d\0c\0h\0zic64b\0zicbom\0zicbop\0= zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicntr\0zicsr\0zifencei\0zihint= ntl\0zihintpause\0zihpm\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zca\0zcd= \0zba\0zbb\0zbc\0zbs\0sdtrig\0shcounterenw\0shgatpa\0shtvala\0shvsatpa\0shv= stvala\0shvstvecd\0ssccptr\0sscounterenw\0ssqosid\0ssstrict\0sstc\0sstvala\= 0sstvecd\0ssu64xl\0svadu\0svvptc"; + riscv,isa-base =3D "rv64i"; + riscv,isa =3D "rv64imafdch_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_= zicclsm_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zmmul_za6= 4rs_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_sdtrig_shcounterenw_shga= tpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscounterenw_ssqosid_ssstr= ict_sstc_sstvala_sstvecd_ssu64xl_svadu_svvptc"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x0c>; + }; + }; + + cpu@3 { + phandle =3D <0x09>; + device_type =3D "cpu"; + reg =3D <0x03>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cbop-block-size =3D <0x40>; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa-extensions =3D "i\0m\0a\0f\0d\0c\0h\0zic64b\0zicbom\0zicbop\0= zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicntr\0zicsr\0zifencei\0zihint= ntl\0zihintpause\0zihpm\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zca\0zcd= \0zba\0zbb\0zbc\0zbs\0sdtrig\0shcounterenw\0shgatpa\0shtvala\0shvsatpa\0shv= stvala\0shvstvecd\0ssccptr\0sscounterenw\0ssqosid\0ssstrict\0sstc\0sstvala\= 0sstvecd\0ssu64xl\0svadu\0svvptc"; + riscv,isa-base =3D "rv64i"; + riscv,isa =3D "rv64imafdch_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_= zicclsm_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zmmul_za6= 4rs_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_sdtrig_shcounterenw_shga= tpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscounterenw_ssqosid_ssstr= ict_sstc_sstvala_sstvecd_ssu64xl_svadu_svvptc"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x0a>; + }; + }; + + cpu@4 { + phandle =3D <0x07>; + device_type =3D "cpu"; + reg =3D <0x04>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cbop-block-size =3D <0x40>; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa-extensions =3D "i\0m\0a\0f\0d\0c\0h\0zic64b\0zicbom\0zicbop\0= zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicntr\0zicsr\0zifencei\0zihint= ntl\0zihintpause\0zihpm\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zca\0zcd= \0zba\0zbb\0zbc\0zbs\0sdtrig\0shcounterenw\0shgatpa\0shtvala\0shvsatpa\0shv= stvala\0shvstvecd\0ssccptr\0sscounterenw\0ssqosid\0ssstrict\0sstc\0sstvala\= 0sstvecd\0ssu64xl\0svadu\0svvptc"; + riscv,isa-base =3D "rv64i"; + riscv,isa =3D "rv64imafdch_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_= zicclsm_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zmmul_za6= 4rs_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_sdtrig_shcounterenw_shga= tpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscounterenw_ssqosid_ssstr= ict_sstc_sstvala_sstvecd_ssu64xl_svadu_svvptc"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x08>; + }; + }; + + cpu@5 { + phandle =3D <0x05>; + device_type =3D "cpu"; + reg =3D <0x05>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cbop-block-size =3D <0x40>; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa-extensions =3D "i\0m\0a\0f\0d\0c\0h\0zic64b\0zicbom\0zicbop\0= zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicntr\0zicsr\0zifencei\0zihint= ntl\0zihintpause\0zihpm\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zca\0zcd= \0zba\0zbb\0zbc\0zbs\0sdtrig\0shcounterenw\0shgatpa\0shtvala\0shvsatpa\0shv= stvala\0shvstvecd\0ssccptr\0sscounterenw\0ssqosid\0ssstrict\0sstc\0sstvala\= 0sstvecd\0ssu64xl\0svadu\0svvptc"; + riscv,isa-base =3D "rv64i"; + riscv,isa =3D "rv64imafdch_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_= zicclsm_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zmmul_za6= 4rs_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_sdtrig_shcounterenw_shga= tpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscounterenw_ssqosid_ssstr= ict_sstc_sstvala_sstvecd_ssu64xl_svadu_svvptc"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x06>; + }; + }; + + cpu@6 { + phandle =3D <0x03>; + device_type =3D "cpu"; + reg =3D <0x06>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cbop-block-size =3D <0x40>; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa-extensions =3D "i\0m\0a\0f\0d\0c\0h\0zic64b\0zicbom\0zicbop\0= zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicntr\0zicsr\0zifencei\0zihint= ntl\0zihintpause\0zihpm\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zca\0zcd= \0zba\0zbb\0zbc\0zbs\0sdtrig\0shcounterenw\0shgatpa\0shtvala\0shvsatpa\0shv= stvala\0shvstvecd\0ssccptr\0sscounterenw\0ssqosid\0ssstrict\0sstc\0sstvala\= 0sstvecd\0ssu64xl\0svadu\0svvptc"; + riscv,isa-base =3D "rv64i"; + riscv,isa =3D "rv64imafdch_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_= zicclsm_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zmmul_za6= 4rs_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_sdtrig_shcounterenw_shga= tpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscounterenw_ssqosid_ssstr= ict_sstc_sstvala_sstvecd_ssu64xl_svadu_svvptc"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x04>; + }; + }; + + cpu@7 { + phandle =3D <0x01>; + device_type =3D "cpu"; + reg =3D <0x07>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cbop-block-size =3D <0x40>; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa-extensions =3D "i\0m\0a\0f\0d\0c\0h\0zic64b\0zicbom\0zicbop\0= zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicntr\0zicsr\0zifencei\0zihint= ntl\0zihintpause\0zihpm\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zca\0zcd= \0zba\0zbb\0zbc\0zbs\0sdtrig\0shcounterenw\0shgatpa\0shtvala\0shvsatpa\0shv= stvala\0shvstvecd\0ssccptr\0sscounterenw\0ssqosid\0ssstrict\0sstc\0sstvala\= 0sstvecd\0ssu64xl\0svadu\0svvptc"; + riscv,isa-base =3D "rv64i"; + riscv,isa =3D "rv64imafdch_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_= zicclsm_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zmmul_za6= 4rs_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_sdtrig_shcounterenw_shga= tpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscounterenw_ssqosid_ssstr= ict_sstc_sstvala_sstvecd_ssu64xl_svadu_svvptc"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x02>; + }; + }; + + cpu-map { + + cluster0 { + + core0 { + cpu =3D <0x0f>; + }; + + core1 { + cpu =3D <0x0d>; + }; + + core2 { + cpu =3D <0x0b>; + }; + + core3 { + cpu =3D <0x09>; + }; + + core4 { + cpu =3D <0x07>; + }; + + core5 { + cpu =3D <0x05>; + }; + + core6 { + cpu =3D <0x03>; + }; + + core7 { + cpu =3D <0x01>; + }; + }; + }; + }; + + pmu { + riscv,event-to-mhpmcounters =3D <0x01 0x01 0x7fff9 0x02 0x02 0x7fffc 0x1= 0019 0x10019 0x7fff8 0x1001b 0x1001b 0x7fff8 0x10021 0x10021 0x7fff8>; + compatible =3D "riscv,pmu"; + }; + + fw-cfg@10100000 { + dma-coherent; + reg =3D <0x00 0x10100000 0x00 0x18>; + compatible =3D "qemu,fw-cfg-mmio"; + }; + + flash@20000000 { + bank-width =3D <0x04>; + reg =3D <0x00 0x20000000 0x00 0x2000000 0x00 0x22000000 0x00 0x2000000>; + compatible =3D "cfi-flash"; + }; + + aliases { + serial0 =3D "/soc/serial@10000000"; + }; + + chosen { + bootargs =3D "root=3D/dev/vda ro loglevel=3D8"; + stdout-path =3D "/soc/serial@10000000"; + rng-seed =3D <0x56a2904d 0x281bbaec 0x55c405c1 0x602a34cd 0x3490edca 0x3= ed9ed5d 0xa98e5ed6 0xa663e102>; + }; + + soc { + #address-cells =3D <0x02>; + #size-cells =3D <0x02>; + compatible =3D "simple-bus"; + ranges; + + rtc@101000 { + interrupts =3D <0x0b>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x101000 0x00 0x1000>; + compatible =3D "google,goldfish-rtc"; + }; + + serial@10000000 { + interrupts =3D <0x0a>; + interrupt-parent =3D <0x11>; + clock-frequency =3D "\08@"; + reg =3D <0x00 0x10000000 0x00 0x100>; + compatible =3D "ns16550a"; + }; + + test@100000 { + phandle =3D <0x12>; + reg =3D <0x00 0x100000 0x00 0x1000>; + compatible =3D "sifive,test1\0sifive,test0\0syscon"; + }; + + virtio_mmio@10008000 { + interrupts =3D <0x08>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10008000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + virtio_mmio@10007000 { + interrupts =3D <0x07>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10007000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + virtio_mmio@10006000 { + interrupts =3D <0x06>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10006000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + virtio_mmio@10005000 { + interrupts =3D <0x05>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10005000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + virtio_mmio@10004000 { + interrupts =3D <0x04>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10004000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + virtio_mmio@10003000 { + interrupts =3D <0x03>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10003000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + virtio_mmio@10002000 { + interrupts =3D <0x02>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10002000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + virtio_mmio@10001000 { + interrupts =3D <0x01>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10001000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + plic@c000000 { + phandle =3D <0x11>; + riscv,ndev =3D <0x5f>; + reg =3D <0x00 0xc000000 0x00 0x600000>; + interrupts-extended =3D <0x10 0x0b 0x10 0x09 0x0e 0x0b 0x0e 0x09 0x0c 0= x0b 0x0c 0x09 0x0a 0x0b 0x0a 0x09 0x08 0x0b 0x08 0x09 0x06 0x0b 0x06 0x09 0= x04 0x0b 0x04 0x09 0x02 0x0b 0x02 0x09>; + interrupt-controller; + compatible =3D "sifive,plic-1.0.0\0riscv,plic0"; + #address-cells =3D <0x00>; + #interrupt-cells =3D <0x01>; + }; + + clint@2000000 { + interrupts-extended =3D <0x10 0x03 0x10 0x07 0x0e 0x03 0x0e 0x07 0x0c 0= x03 0x0c 0x07 0x0a 0x03 0x0a 0x07 0x08 0x03 0x08 0x07 0x06 0x03 0x06 0x07 0= x04 0x03 0x04 0x07 0x02 0x03 0x02 0x07>; + reg =3D <0x00 0x2000000 0x00 0x10000>; + compatible =3D "sifive,clint0\0riscv,clint0"; + }; + + pci@30000000 { + interrupt-map-mask =3D <0x1800 0x00 0x00 0x07>; + interrupt-map =3D <0x00 0x00 0x00 0x01 0x11 0x20 0x00 0x00 0x00 0x02 0x= 11 0x21 0x00 0x00 0x00 0x03 0x11 0x22 0x00 0x00 0x00 0x04 0x11 0x23 0x800 0= x00 0x00 0x01 0x11 0x21 0x800 0x00 0x00 0x02 0x11 0x22 0x800 0x00 0x00 0x03= 0x11 0x23 0x800 0x00 0x00 0x04 0x11 0x20 0x1000 0x00 0x00 0x01 0x11 0x22 0= x1000 0x00 0x00 0x02 0x11 0x23 0x1000 0x00 0x00 0x03 0x11 0x20 0x1000 0x00 = 0x00 0x04 0x11 0x21 0x1800 0x00 0x00 0x01 0x11 0x23 0x1800 0x00 0x00 0x02 0= x11 0x20 0x1800 0x00 0x00 0x03 0x11 0x21 0x1800 0x00 0x00 0x04 0x11 0x22>; + ranges =3D <0x1000000 0x00 0x00 0x00 0x3000000 0x00 0x10000 0x2000000 0= x00 0x40000000 0x00 0x40000000 0x00 0x40000000 0x3000000 0x04 0x00 0x04 0x0= 0 0x04 0x00>; + reg =3D <0x00 0x30000000 0x00 0x10000000>; + dma-coherent; + bus-range =3D <0x00 0xff>; + linux,pci-domain =3D <0x00>; + device_type =3D "pci"; + compatible =3D "pci-host-ecam-generic"; + #size-cells =3D <0x02>; + #interrupt-cells =3D <0x01>; + #address-cells =3D <0x03>; + }; + }; +}; --=20 2.43.0