From nobody Tue Feb 10 04:02:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 273A433CEBC; Tue, 20 Jan 2026 04:15:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768882526; cv=none; b=YQ9uKX5lZFLqoFzgq0AC93ladeYT/7YwYpKSlIds2TohvN5kaRlT8BGIvZsieL5EvyPsHQIPJQtuEDgm2VFw8Y1tPD8X4Y9sG6CGxzJCG1QEiUShC7N4vIZdbUep0pFUQDLFprjfge9KVxHF3tl+oawQzgS/YuVno3B08SXkR6E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768882526; c=relaxed/simple; bh=R1lDGdU7iIiekrd1oymtfCVNrLHfj85DdbG3x9sBksw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To; b=OklOgfga1uWZFbhSnXfflRGn+dhmpr+TMIyaSa6AEQk8TnO9CQ/rlJYnqcGwqaefBWvKzwm04alegOOeRpN/aQ0Ck8q4jEo/9dB8hJX6bqKOmQUNE1msztuE3enYsbWAvPs324MldQwAo8Npy2JH1BEYgDu/EEK9d7d0rEArYKc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=o5O6wA2S; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="o5O6wA2S" Received: by smtp.kernel.org (Postfix) with ESMTPSA id F2260C2BC87; Tue, 20 Jan 2026 04:15:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1768882525; bh=R1lDGdU7iIiekrd1oymtfCVNrLHfj85DdbG3x9sBksw=; h=From:Date:Subject:References:In-Reply-To:To:From; b=o5O6wA2Sa7mj9exOhlWMr60IUo9V+uZYDFgj/AhtuKNokK4T3QyFOibJGyRd/1tvh OlI8fL+nnGEs9NWYESHV2Ln6pnEEjX1xeBGGxoAFo6Yjtgv4DJxBR67E1V19Ji1w0T ru6gkzgY1nuC/RU8Nt7mQvtbTH1brAy6rmgME1DwHJBF7uTBQ/uheBfPdA85pqFZy0 TTpO4Ua/33Wtye91iWendEhluYKw7bEVDuNHZuECacmYeyVzJIQ8R7fPgk9c9Gsn5f QQJVQkom/0DVWSGuPP29AUkhY8ygZTpcvbJCaOZQeOJbb4SBneVreDS6c0YgELxqKh UtBt/nasszGpg== From: Drew Fustini Date: Mon, 19 Jan 2026 20:14:51 -0800 Subject: [PATCH NFU RFC 14/19] resctrl: riscv: add CBQRI cache controller driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-ssqosid-cbqri-v1-14-aa2a75153832@kernel.org> References: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> In-Reply-To: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Conor Dooley , Krzysztof Kozlowski , Rob Herring , Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3582; i=fustini@kernel.org; h=from:subject:message-id; bh=R1lDGdU7iIiekrd1oymtfCVNrLHfj85DdbG3x9sBksw=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTmMwbPd3m6brnUfHdzF68gA205o7A5f5Y/vX7961zf9 V6HTss+6yhlYRDjYpAVU2TZ9CHvwhKv0K8L5r/YBjOHlQlkCAMXpwBM5KMZI0NvyR13W+maSyv5 81fnPVsf/LTjXeQOW5t5nClJBgc62h4y/I/4cJxpakut2He/3U9mLlK4Eq8vvf2afgnHv7lGHCu mf2IDAA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 [NOT FOR UPSTREAM] Add example driver for a cache controller that implements CBQRI capacity allocation. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- drivers/resctrl/riscv/cbqri_cache.c | 106 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 106 insertions(+) diff --git a/drivers/resctrl/riscv/cbqri_cache.c b/drivers/resctrl/riscv/cb= qri_cache.c new file mode 100644 index 000000000000..0bee65eefb2d --- /dev/null +++ b/drivers/resctrl/riscv/cbqri_cache.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0-only +#define pr_fmt(fmt) "cbqri-cache: " fmt + +#include +#include +#include + +static const struct of_device_id cbqri_cache_ids[] =3D { + { .compatible =3D "riscv,cbqri-cache" }, + { } +}; + +static int __init cbqri_cache_init(void) +{ + struct cbqri_controller_info *ctrl_info; + struct device_node *np; + u32 value; + int err; + + for_each_matching_node(np, cbqri_cache_ids) { + if (!of_device_is_available(np)) { + of_node_put(np); + continue; + } + + ctrl_info =3D kzalloc(sizeof(*ctrl_info), GFP_KERNEL); + if (!ctrl_info) + goto err_node_put; + ctrl_info->type =3D CBQRI_CONTROLLER_TYPE_CAPACITY; + + err =3D of_property_read_u32_index(np, "reg", 1, &value); + if (err) { + pr_err("Failed to read reg base address (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->addr =3D value; + + err =3D of_property_read_u32_index(np, "reg", 3, &value); + if (err) { + pr_err("Failed to read reg size (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->size =3D value; + + err =3D of_property_read_u32(np, "cache-level", &value); + if (err) { + pr_err("Failed to read cache level (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->cache.cache_level =3D value; + + err =3D of_property_read_u32(np, "cache-size", &value); + if (err) { + pr_err("Failed to read cache size (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->cache.cache_size =3D value; + + err =3D of_property_read_u32(np, "riscv,cbqri-rcid", &value); + if (err) { + pr_err("Failed to read RCID count (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->rcid_count =3D value; + + err =3D of_property_read_u32(np, "riscv,cbqri-mcid", &value); + if (err) { + pr_err("Failed to read MCID count (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->mcid_count =3D value; + + /* + * For CBQRI, any cpu (technically a hart in RISC-V terms) + * can access the memory-mapped registers of any CBQRI + * controller in the system. Therefore, set the CPU mask + * to 'FF' to allow all 8 cores in the example Qemu SoC + */ + err =3D cpumask_parse("FF", &ctrl_info->cache.cpu_mask); + if (err) { + pr_err("Failed to convert cores mask string to cpumask (%d)", err); + goto err_kfree_ctrl_info; + } + + of_node_put(np); + + pr_debug("addr=3D0x%lx max-rcid=3D%u max-mcid=3D%u level=3D%d size=3D%u", + ctrl_info->addr, ctrl_info->rcid_count, ctrl_info->mcid_count, + ctrl_info->cache.cache_level, ctrl_info->cache.cache_size); + + /* Fill the list shared with RISC-V QoS resctrl */ + INIT_LIST_HEAD(&ctrl_info->list); + list_add_tail(&ctrl_info->list, &cbqri_controllers); + } + + return 0; + +err_kfree_ctrl_info: + kfree(ctrl_info); + +err_node_put: + of_node_put(np); + + return err; +} +device_initcall(cbqri_cache_init); --=20 2.43.0