From nobody Sun Feb 8 15:53:51 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F13612D73B9; Tue, 20 Jan 2026 04:15:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768882518; cv=none; b=L4YCY3YbUnp5j60BOq813OCdwALAoDPRzJGTkKHBxWjEbvl6Omg8mNGeiXzFd0wlIulDUt0+ra2nC6As2Cb6WsA8kWZT8sr3w0xjVSk90Iv6vLdy29fAif1oPBjokRCR7TSbPbxqLmKtGIlvM6838NCNP+cL92CQCRRr2rya96Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768882518; c=relaxed/simple; bh=iU4P/QyFDo51iNRXh33LwyQncDIl37ClLj6x8G/smfI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sfNaEF0Dsk+uxQrxELr9Q+jjhDGj4aqZaxE/aExLdoCxl76raUhjH7SUv9LWWWeEPCPkC2TMVI7xqFVzU8bNVu5EenrcNZAyd5Tpm5hikD52S8VO2U9Sy3Td3y0jU+cZhyohrMkyNAruzD1u0VePriAg+EKZ4Cdsc0cg4RduZso= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lAO4/Bnb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lAO4/Bnb" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2B57AC19421; Tue, 20 Jan 2026 04:15:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1768882517; bh=iU4P/QyFDo51iNRXh33LwyQncDIl37ClLj6x8G/smfI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=lAO4/BnbIJGMFBU6rw5rtclBpMc/bLFKl51zwghdn10xpbcRPrOI12DDkY5tBP7y/ H9vwDPIcAVldqp8vpW2UdGyL3XfkQBloJ5bWCWGK9KjIJA8tfZ0h9W4NCf1hddTdZy QZ4gF1LvFoHHidFaN4grFraxNjKoQMg+ZTFCbjjntTDCDXMjxiCL9hwUoTa0Y9ISvh g3ga5fW3z6sewiAJ6gww5xya3zmMK7djRwFrIto/3S+rR0HuMr0L01yhUm3i/uOOWl 3UKgoAapCcOG8tp3enwvGFvfQGXTBUkd0GhWBAE9566UP/Yw5Ix8PMdc2EajL7C8MN awNhAcclqqQeg== From: Drew Fustini Date: Mon, 19 Jan 2026 20:14:38 -0800 Subject: [PATCH RFC 01/19] dt-bindings: riscv: Add Ssqosid extension description Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-ssqosid-cbqri-v1-1-aa2a75153832@kernel.org> References: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> In-Reply-To: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Conor Dooley , Krzysztof Kozlowski , Rob Herring , Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org Cc: Conor Dooley X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1214; i=fustini@kernel.org; h=from:subject:message-id; bh=iU4P/QyFDo51iNRXh33LwyQncDIl37ClLj6x8G/smfI=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTmMwa1Ly2YIabU0/8gM63YMrzk9xeJsC1P2WwDPVsi9 9yca3G8o5SFQYyLQVZMkWXTh7wLS7xCvy6Y/2IbzBxWJpAhDFycAjCRiSKMDNdXt29ra/yp8HOB yly9DVJeB+NvH+SWM/GKbTFRfOm2I5GR4cSeCsk6ieJPJqxBCkGXxY2WFoR0rd7y1bosNtLBzaG aCwA= X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Document the ratified Supervisor-mode Quality of Service ID (Ssqosid) extension v1.0. Link: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0 Acked-by: Conor Dooley Signed-off-by: Drew Fustini --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 5bab356addc8..27a7b4e63eb1 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -165,6 +165,12 @@ properties: ratified at commit d70011dde6c2 ("Update to ratified state") of riscv-j-extension. =20 + - const: ssqosid + description: | + The Ssqosid extension for Quality of Service ID is ratified + as v1.0 in commit 5059e0ca641c ("Merge pull request #7 from + ved-rivos/Ratified") of riscv-ssqosid. + - const: sstc description: | The standard Sstc supervisor-level extension for time compare = as --=20 2.43.0 From nobody Sun Feb 8 15:53:51 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 902A2338581; Tue, 20 Jan 2026 04:15:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768882518; cv=none; b=lQ/C1eZP7ZTuC5/XLQRUwLDH4Wqleg+gxQp80yCcpHth7zChF5hz2c2TiUnotB5XCX9ZOY6OesVYyqk3W0o9amZPRf2OSQkruNcEouHCiTql9dJKs+mFgUGA+7ZrX0n39GO3j+NMnNc86uhaOG6Fj2kGSHRJAljA8EUBoLiQiYY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768882518; c=relaxed/simple; bh=/bDxWcPBw7DqP8cMaBdDBq6xIoctZXAai1IBsm35Yn8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To; b=ZEiTQcHpjL19WTqaCKAGpxlMQ0sXlWB4l9tXHVTpqKMsUhU42VuXJlSYwz++/1MKQS6PmFFV4pkJPtSX451wFt4nqYlwCO1BxsEGE82bt9wb65GSmyjS7eniswL3kRXP+BIAHeD9+CGRPXBmEclPYI3tzxMCdjMFeKiDEWD1t40= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bDM3mPlo; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bDM3mPlo" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B39C6C2BCB1; Tue, 20 Jan 2026 04:15:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1768882518; bh=/bDxWcPBw7DqP8cMaBdDBq6xIoctZXAai1IBsm35Yn8=; h=From:Date:Subject:References:In-Reply-To:To:From; b=bDM3mPlopQCjNR/5OkhnqbDNy0mwIxVLOtVwPt9ZZx5D5Q0FZUc+6BWgmg3VfnWWS Zb0OL+UJkjW7nPdztp5vTl4eRqhgm11FeuwOZN6p3577GlNVEDdZgEOgsDJ/6OUJJg 3FgtEalpwkoip9rRqZDsBhEbAN5OiuSkmvhhLzCJo7RbminDTApqvC417B8v5IqoLi nm1o3HvUM5KK8AKNZAigLmEaYmtyABPqqcgtZ7VsH7O9T7qO9Mvqc1tN+Rk2lFl3q4 bnQTbGOQbQhfPC3O93SEfPL3h3arHyRr9jHehextMspa+b2qdQpwkC1iSV20hRhGOK D0Vbd6YGihZRw== From: Drew Fustini Date: Mon, 19 Jan 2026 20:14:39 -0800 Subject: [PATCH RFC 02/19] RISC-V: Detect the Ssqosid extension Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-ssqosid-cbqri-v1-2-aa2a75153832@kernel.org> References: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> In-Reply-To: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Conor Dooley , Krzysztof Kozlowski , Rob Herring , Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1616; i=fustini@kernel.org; h=from:subject:message-id; bh=/bDxWcPBw7DqP8cMaBdDBq6xIoctZXAai1IBsm35Yn8=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTmMwYd63/sYelVnyTbru5XsFpk6pZXaw5kP2Bttitf/ OzCidJ3HaUsDGJcDLJiiiybPuRdWOIV+nXB/BfbYOawMoEMYeDiFICJ8Jxi+MNh7ek95cANA71l NoynT361jD3iMs3USktfNfvW3EWPo78z/FO5cLCG+Zh+3n/FP4vql317FycVra55s1s+S+xdHHd 0GQsA X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Ssqosid is the RISC-V Quality-of-Service (QoS) Identifiers specification which defines the Supervisor Resource Management Configuration (srmcfg) register. Link: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0 Signed-off-by: Kornel Dul=C4=99ba [fustini: rebase on riscv/for-next] Signed-off-by: Drew Fustini --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 4369a2338541..28dff8233b34 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -110,6 +110,7 @@ #define RISCV_ISA_EXT_ZALASR 101 #define RISCV_ISA_EXT_ZILSD 102 #define RISCV_ISA_EXT_ZCLSD 103 +#define RISCV_ISA_EXT_SSQOSID 104 =20 #define RISCV_ISA_EXT_XLINUXENVCFG 127 =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c05b11596c19..bf704b48679c 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -558,6 +558,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_e= xts), + __RISCV_ISA_EXT_DATA(ssqosid, RISCV_ISA_EXT_SSQOSID), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), __RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE), __RISCV_ISA_EXT_DATA_VALIDATE(svadu, RISCV_ISA_EXT_SVADU, riscv_ext_svadu= _validate), --=20 2.43.0 From nobody Sun Feb 8 15:53:51 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0DD8C33ADBF; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HTuGYsFd" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 43C5DC19424; Tue, 20 Jan 2026 04:15:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1768882518; bh=n49I+XgNGUzalkmdigSz5QNq3iv1xpZlLnoYtkjg2J0=; h=From:Date:Subject:References:In-Reply-To:To:From; b=HTuGYsFdkqtY92X2f7i67Yk0ZDpPHcWcqXvauMO3aqkvBt5wh1nn7/qPUDT4yoP0l rT7/cHn291oIoaFhJ3mS8k8KIg7NzgXPjAUvCxmWgFNJLZT9H8+C03TCIcUskF4W7j Vxq77Er9Qb4vbwL1Z++2RBqWYjurIz55s+I+AWauRw633wY48E5Q26TZWJu+FuoRQl MhCLkaI8urDgtuEvV3KkgQN11keN6F/GsXkpicmcLRvZC17ddbsWIW6NQpbt7VcWB7 UzoElflzyeoB+x2WkV2SYaXI113dXnT58bsBWWQBmzfa1i0LCB6ltpHa5pNL+/KRVP YGKujc6yEzuSg== From: Drew Fustini Date: Mon, 19 Jan 2026 20:14:40 -0800 Subject: [PATCH RFC 03/19] RISC-V: Add support for srmcfg CSR from Ssqosid ext Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-ssqosid-cbqri-v1-3-aa2a75153832@kernel.org> References: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> In-Reply-To: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Conor Dooley , Krzysztof Kozlowski , Rob Herring , Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=7824; i=fustini@kernel.org; h=from:subject:message-id; bh=n49I+XgNGUzalkmdigSz5QNq3iv1xpZlLnoYtkjg2J0=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTmMwY1pqnMnVJzQW4Sw6sPG0LP3zd+s/g5c+yFrFl7r VimyDxr7ChlYRDjYpAVU2TZ9CHvwhKv0K8L5r/YBjOHlQlkCAMXpwBMROYFI8M/CfanGyPyvm27 fjY4rMJD4uXqcq+TnXNqakqWJjk6luQy/Hf1r0mZ/lfc4rpSvHZWSyTL7R2CiYYuTmLbrBu1ZxV HMwMA X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Add support for the srmcfg CSR defined in the Ssqosid ISA extension (Supervisor-mode Quality of Service ID). The CSR contains two fields: - Resource Control ID (RCID) used determine resource allocation - Monitoring Counter ID (MCID) used to track resource usage Requests from a hart to shared resources like cache will be tagged with these IDs. This allows the usage of shared resources to be associated with the task currently running on the hart. A srmcfg field is added to thread_struct and has the same format as the srmcfg CSR. This allows the scheduler to set the hart's srmcfg CSR to contain the RCID and MCID for the task that is being scheduled in. The srmcfg CSR is only written to if the thread_struct.srmcfg is different than the current value of the CSR. A per-cpu variable cpu_srmcfg is used to mirror that state of the CSR. This is because access to L1D hot memory should be several times faster than a CSR read. Also, in the case of virtualization, accesses to this CSR are trapped in the hypervisor. Link: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0 Co-developed-by: Kornel Dul=C4=99ba Signed-off-by: Kornel Dul=C4=99ba [fustini: rename csr, refactor switch_to, rebase on riscv/for-next] Signed-off-by: Drew Fustini --- MAINTAINERS | 7 +++++++ arch/riscv/Kconfig | 17 ++++++++++++++++ arch/riscv/include/asm/csr.h | 8 ++++++++ arch/riscv/include/asm/processor.h | 3 +++ arch/riscv/include/asm/qos.h | 41 ++++++++++++++++++++++++++++++++++= ++++ arch/riscv/include/asm/switch_to.h | 3 +++ arch/riscv/kernel/Makefile | 2 ++ arch/riscv/kernel/qos/Makefile | 2 ++ arch/riscv/kernel/qos/qos.c | 5 +++++ 9 files changed, 88 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 765ad2daa218..e98d553bd0ca 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22505,6 +22505,13 @@ F: drivers/perf/riscv_pmu.c F: drivers/perf/riscv_pmu_legacy.c F: drivers/perf/riscv_pmu_sbi.c =20 +RISC-V QOS RESCTRL SUPPORT +M: Drew Fustini +L: linux-riscv@lists.infradead.org +S: Supported +F: arch/riscv/include/asm/qos.h +F: arch/riscv/kernel/qos/ + RISC-V RPMI AND MPXY DRIVERS M: Rahul Pathak M: Anup Patel diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6b39f37f769a..35a6238b02c5 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -595,6 +595,23 @@ config RISCV_ISA_SVNAPOT =20 If you don't know what to do here, say Y. =20 +config RISCV_ISA_SSQOSID + bool "Ssqosid extension support for supervisor mode Quality of Service ID" + default y + help + Adds support for the Ssqosid ISA extension (Supervisor-mode + Quality of Service ID). + + Ssqosid defines the srmcfg CSR which allows the system to tag the + running process with an RCID (Resource Control ID) and MCID + (Monitoring Counter ID). The RCID is used to determine resource + allocation. The MCID is used to track resource usage in event + counters. + + For example, a cache controller may use the RCID to apply a + cache partitioning scheme and use the MCID to track how much + cache a process, or a group of processes, is using. + config RISCV_ISA_SVPBMT bool "Svpbmt extension support for supervisor mode page-based memory type= s" depends on 64BIT && MMU diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 4a37a98398ad..2590b89b8f72 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -75,6 +75,13 @@ #define SATP_ASID_MASK _AC(0xFFFF, UL) #endif =20 +/* SRMCFG fields */ +#define SRMCFG_RCID_MASK _AC(0x00000FFF, UL) +#define SRMCFG_MCID_MASK SRMCFG_RCID_MASK +#define SRMCFG_MCID_SHIFT 16 +#define SRMCFG_MASK ((SRMCFG_MCID_MASK << SRMCFG_MCID_SHIFT) | \ + SRMCFG_RCID_MASK) + /* Exception cause high bit - is an interrupt if set */ #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) =20 @@ -317,6 +324,7 @@ #define CSR_STVAL 0x143 #define CSR_SIP 0x144 #define CSR_SATP 0x180 +#define CSR_SRMCFG 0x181 =20 #define CSR_STIMECMP 0x14D #define CSR_STIMECMPH 0x15D diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/pr= ocessor.h index da5426122d28..183c55e32b96 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -122,6 +122,9 @@ struct thread_struct { /* A forced icache flush is not needed if migrating to the previous cpu. = */ unsigned int prev_cpu; #endif +#ifdef CONFIG_RISCV_ISA_SSQOSID + u32 srmcfg; +#endif }; =20 /* Whitelist the fstate from the task_struct for hardened usercopy */ diff --git a/arch/riscv/include/asm/qos.h b/arch/riscv/include/asm/qos.h new file mode 100644 index 000000000000..84830d7c6dc4 --- /dev/null +++ b/arch/riscv/include/asm/qos.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_RISCV_QOS_H +#define _ASM_RISCV_QOS_H + +#ifdef CONFIG_RISCV_ISA_SSQOSID + +#include +#include + +#include +#include +#include + +/* cached value of srmcfg csr for each cpu */ +DECLARE_PER_CPU(u32, cpu_srmcfg); + +static inline void __switch_to_srmcfg(struct task_struct *next) +{ + u32 *cpu_srmcfg_ptr =3D this_cpu_ptr(&cpu_srmcfg); + u32 thread_srmcfg; + + thread_srmcfg =3D READ_ONCE(next->thread.srmcfg); + + if (thread_srmcfg !=3D *cpu_srmcfg_ptr) { + *cpu_srmcfg_ptr =3D thread_srmcfg; + csr_write(CSR_SRMCFG, thread_srmcfg); + } +} + +static __always_inline bool has_srmcfg(void) +{ + return riscv_has_extension_unlikely(RISCV_ISA_EXT_SSQOSID); +} + +#else /* ! CONFIG_RISCV_ISA_SSQOSID */ + +static __always_inline bool has_srmcfg(void) { return false; } +#define __switch_to_srmcfg(__next) do { } while (0) + +#endif /* CONFIG_RISCV_ISA_SSQOSID */ +#endif /* _ASM_RISCV_QOS_H */ diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/sw= itch_to.h index 0e71eb82f920..a684a3795d3d 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -14,6 +14,7 @@ #include #include #include +#include =20 #ifdef CONFIG_FPU extern void __fstate_save(struct task_struct *save_to); @@ -119,6 +120,8 @@ do { \ __switch_to_fpu(__prev, __next); \ if (has_vector() || has_xtheadvector()) \ __switch_to_vector(__prev, __next); \ + if (has_srmcfg()) \ + __switch_to_srmcfg(__next); \ if (switch_to_should_flush_icache(__next)) \ local_flush_icache_all(); \ __switch_to_envcfg(__next); \ diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index f60fce69b725..a3c36d18145c 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -125,3 +125,5 @@ obj-$(CONFIG_ACPI) +=3D acpi.o obj-$(CONFIG_ACPI_NUMA) +=3D acpi_numa.o =20 obj-$(CONFIG_GENERIC_CPU_VULNERABILITIES) +=3D bugs.o + +obj-$(CONFIG_RISCV_ISA_SSQOSID) +=3D qos/ diff --git a/arch/riscv/kernel/qos/Makefile b/arch/riscv/kernel/qos/Makefile new file mode 100644 index 000000000000..9f996263a86d --- /dev/null +++ b/arch/riscv/kernel/qos/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_RISCV_ISA_SSQOSID) +=3D qos.o diff --git a/arch/riscv/kernel/qos/qos.c b/arch/riscv/kernel/qos/qos.c new file mode 100644 index 000000000000..7b06f7ae9056 --- /dev/null +++ b/arch/riscv/kernel/qos/qos.c @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include + +/* cached value of sqoscfg csr for each cpu */ +DEFINE_PER_CPU(u32, cpu_srmcfg); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-ssqosid-cbqri-v1-4-aa2a75153832@kernel.org> References: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> In-Reply-To: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Conor Dooley , Krzysztof Kozlowski , Rob Herring , Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1881; i=fustini@kernel.org; h=from:subject:message-id; bh=e1gD37k8W4Pzp7U55pR9/mebQe/hwn2pjhUSiquHa+s=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTmMwZN5rP20bO/dDmHP7S/7cIfjRLnCTPvKu/bpdMrd k1Rtkyho5SFQYyLQVZMkWXTh7wLS7xCvy6Y/2IbzBxWJpAhDFycAjCR/+WMDCdWXmdxLXSdYd+X 7Jqy/MAknU83Y5fYaG5kF2bp/ftC7gUjwxP9amW2zDSJeYve7TkxOcxI59RiGR8vtguPhbXezL2 6kwEA X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Define data structure to represent the CBQRI properties that a driver for an CBQRI-capable controller would discover during probe. Each instance of a CBQRI-capable controller is added to a list that the RISC-V CBQRI resctrl implementation will consume. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- MAINTAINERS | 1 + include/linux/riscv_qos.h | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e98d553bd0ca..31e536304972 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22511,6 +22511,7 @@ L: linux-riscv@lists.infradead.org S: Supported F: arch/riscv/include/asm/qos.h F: arch/riscv/kernel/qos/ +F: include/linux/riscv_qos.h =20 RISC-V RPMI AND MPXY DRIVERS M: Rahul Pathak diff --git a/include/linux/riscv_qos.h b/include/linux/riscv_qos.h new file mode 100644 index 000000000000..51c3a96bbcd0 --- /dev/null +++ b/include/linux/riscv_qos.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __LINUX_RISCV_QOS_H +#define __LINUX_RISCV_QOS_H + +#include +#include + +#include + +enum cbqri_controller_type { + CBQRI_CONTROLLER_TYPE_CAPACITY, + CBQRI_CONTROLLER_TYPE_BANDWIDTH, + CBQRI_CONTROLLER_TYPE_UNKNOWN +}; + +struct cbqri_controller_info { + unsigned long addr; + unsigned long size; + enum cbqri_controller_type type; + u32 rcid_count; + u32 mcid_count; + struct list_head list; + + struct cache_controller { + u32 cache_level; + u32 cache_size; /* in bytes */ + struct cpumask cpu_mask; + } cache; +}; + +extern struct list_head cbqri_controllers; + +#endif /* __LINUX_RISCV_QOS_H */ --=20 2.43.0 From nobody Sun Feb 8 15:53:51 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36E2E2857C7; Tue, 20 Jan 2026 04:15:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768882520; cv=none; b=XIFRSBQldbSB8/lJQFbGsFjuZiuOVU4GonRIU3snpGMd1UB9Jkul46RTN+cbK2j0g4t5ZvIsVHSAtWpRrHRvRhy47iCUXwTl3+e5qYu3m+RHxW0XDS9bb3hToFU22VGYroIdlHtpZFAyhm5wYTCHWGZkPWl9YQwHaP46b4bAhZk= ARC-Message-Signature: i=1; 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b=Jai76DbanQ5IUF9DJVoNKN6aw5/2fizcOT+y1rFd5QRfGD3T+F7L4Vwk2Vrw5WLjG Tu999t924KW+7k3ERLZTgpVZQbmvq+vpXYA2EgQl98YKPURV9KvUaTb7hklYBIjwDm Yiz71/fL45fmtFhJikGN/KmuvkS49J1YA8XGxAOufn33Xn880cIxyrIvmDoXbzpqC6 UcWry79PcViEKZLu76wAW4wtmjlk2u3FnoJi7jnZeM0bvZljd690UgkbGd39KZBYZq sGI+1hkPMmRJWo5tVWpV4dyKZNjVUE9fmSW+XFHLqYOLh2wzy9hrNyAlciW/dvmMWY djk3n+y6qfCKA== From: Drew Fustini Date: Mon, 19 Jan 2026 20:14:42 -0800 Subject: [PATCH RFC 05/19] RISC-V: QoS: define CBQRI capacity and bandwidth capabilities Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-ssqosid-cbqri-v1-5-aa2a75153832@kernel.org> References: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> In-Reply-To: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Conor Dooley , Krzysztof Kozlowski , Rob Herring , Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=4712; i=fustini@kernel.org; h=from:subject:message-id; bh=uuacy5TWBWCqGEovDfg1uYj/N0C7aRhzBOjqrPUPGZE=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTmMwbtNAsIevn73zNt4bBKu+gDQj3PdcS2r/dxkA++3 fSEcZt2RykLgxgXg6yYIsumD3kXlniFfl0w/8U2mDmsTCBDGLg4BWAiy+4yMmx8ps2tXLfitMMC af+nhz9Pi3RY76T+YlHKevvp3KlKZ8oZ/mk5pR4tlvN3vLJcYUlEcLXLNg0l+y+CrLJHpfrr3/x 6xwIA X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Define data structures to store the capacity and bandwidth capabilities that are discovered for a CBQRI-capable controller. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- arch/riscv/kernel/qos/internal.h | 128 +++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 128 insertions(+) diff --git a/arch/riscv/kernel/qos/internal.h b/arch/riscv/kernel/qos/inter= nal.h new file mode 100644 index 000000000000..ff2c7eff50be --- /dev/null +++ b/arch/riscv/kernel/qos/internal.h @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASM_RISCV_QOS_INTERNAL_H +#define _ASM_RISCV_QOS_INTERNAL_H + +#include + +#define CBQRI_CC_CAPABILITIES_OFF 0 +#define CBQRI_CC_MON_CTL_OFF 8 +#define CBQRI_CC_MON_CTL_VAL_OFF 16 +#define CBQRI_CC_ALLOC_CTL_OFF 24 +#define CBQRI_CC_BLOCK_MASK_OFF 32 + +#define CBQRI_BC_CAPABILITIES_OFF 0 +#define CBQRI_BC_MON_CTL_OFF 8 +#define CBQRI_BC_MON_CTR_VAL_OFF 16 +#define CBQRI_BC_ALLOC_CTL_OFF 24 +#define CBQRI_BC_BW_ALLOC_OFF 32 + +#define CBQRI_CC_CAPABILITIES_VER_MINOR_MASK GENMASK(3, 0) +#define CBQRI_CC_CAPABILITIES_VER_MAJOR_MASK GENMASK(7, 4) + +#define CBQRI_CC_CAPABILITIES_FRCID_MASK 0x1 +#define CBQRI_CC_CAPABILITIES_FRCID_SHIFT 24 + +#define CBQRI_CC_CAPABILITIES_NCBLKS_SHIFT 8 +#define CBQRI_CC_CAPABILITIES_NCBLKS_MASK 0xFFFF + +#define CBQRI_BC_CAPABILITIES_VER_MINOR_MASK GENMASK(3, 0) +#define CBQRI_BC_CAPABILITIES_VER_MAJOR_MASK GENMASK(7, 4) + +#define CBQRI_BC_CAPABILITIES_NBWBLKS_SHIFT 8 +#define CBQRI_BC_CAPABILITIES_NBWBLKS_MASK 0xFFFF +#define CBQRI_BC_CAPABILITIES_MRBWB_SHIFT 32 +#define CBQRI_BC_CAPABILITIES_MRBWB_MASK 0xFFFF + +#define CBQRI_CONTROL_REGISTERS_BUSY_SHIFT 39 +#define CBQRI_CONTROL_REGISTERS_BUSY_MASK 0x01 +#define CBQRI_CONTROL_REGISTERS_STATUS_SHIFT 32 +#define CBQRI_CONTROL_REGISTERS_STATUS_MASK 0x7F +#define CBQRI_CONTROL_REGISTERS_OP_SHIFT 0 +#define CBQRI_CONTROL_REGISTERS_OP_MASK 0x1F +#define CBQRI_CONTROL_REGISTERS_AT_SHIFT 5 +#define CBQRI_CONTROL_REGISTERS_AT_MASK 0x07 +#define CBQRI_CONTROL_REGISTERS_AT_DATA 0 +#define CBQRI_CONTROL_REGISTERS_AT_CODE 1 +#define CBQRI_CONTROL_REGISTERS_RCID_SHIFT 8 +#define CBQRI_CONTROL_REGISTERS_RCID_MASK 0xFFF +#define CBQRI_CONTROL_REGISTERS_RBWB_SHIFT 0 +#define CBQRI_CONTROL_REGISTERS_RBWB_MASK 0xFFFF + +#define CBQRI_CC_MON_CTL_OP_CONFIG_EVENT 1 +#define CBQRI_CC_MON_CTL_OP_READ_COUNTER 2 +#define CBQRI_CC_MON_CTL_STATUS_SUCCESS 1 + +#define CBQRI_CC_ALLOC_CTL_OP_CONFIG_LIMIT 1 +#define CBQRI_CC_ALLOC_CTL_OP_READ_LIMIT 2 +#define CBQRI_CC_ALLOC_CTL_OP_FLUSH_RCID 3 +#define CBQRI_CC_ALLOC_CTL_STATUS_SUCCESS 1 + +#define CBQRI_BC_MON_CTL_OP_CONFIG_EVENT 1 +#define CBQRI_BC_MON_CTL_OP_READ_COUNTER 2 +#define CBQRI_BC_MON_CTL_STATUS_SUCCESS 1 + +#define CBQRI_BC_ALLOC_CTL_OP_CONFIG_LIMIT 1 +#define CBQRI_BC_ALLOC_CTL_OP_READ_LIMIT 2 +#define CBQRI_BC_ALLOC_CTL_STATUS_SUCCESS 1 + +/* Capacity Controller hardware capabilities */ +struct riscv_cbqri_capacity_caps { + u16 ncblks; /* number of capacity blocks */ + u16 cache_level; + u32 blk_size; + + bool supports_alloc_at_data; + bool supports_alloc_at_code; + + bool supports_alloc_op_config_limit; + bool supports_alloc_op_read_limit; + bool supports_alloc_op_flush_rcid; + + bool supports_mon_at_data; + bool supports_mon_at_code; + + bool supports_mon_op_config_event; + bool supports_mon_op_read_counter; + + bool supports_mon_evt_id_none; + bool supports_mon_evt_id_occupancy; +}; + +/* Bandwidth Controller hardware capabilities */ +struct riscv_cbqri_bandwidth_caps { + u16 nbwblks; /* number of bandwidth blocks */ + u16 mrbwb; /* max reserved bw blocks */ + + bool supports_alloc_at_data; + bool supports_alloc_at_code; + + bool supports_alloc_op_config_limit; + bool supports_alloc_op_read_limit; + + bool supports_mon_at_data; + bool supports_mon_at_code; + + bool supports_mon_op_config_event; + bool supports_mon_op_read_counter; + + bool supports_mon_evt_id_none; + bool supports_mon_evt_id_rdwr_count; + bool supports_mon_evt_id_rdonly_count; + bool supports_mon_evt_id_wronly_count; +}; + +struct cbqri_controller { + struct cbqri_controller_info *ctrl_info; + void __iomem *base; + + int ver_major; + int ver_minor; + + struct riscv_cbqri_bandwidth_caps bc; + struct riscv_cbqri_capacity_caps cc; + + bool alloc_capable; + bool mon_capable; +}; + +#endif /* _ASM_RISCV_QOS_INTERNAL_H */ --=20 2.43.0 From nobody Sun Feb 8 15:53:51 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F269133BBD8; Tue, 20 Jan 2026 04:15:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768882521; cv=none; b=OBHBQFYLi2Z3bn1Ev3NV1uf1UeD4IaVSk4Cm0uGvbKoobn2cqCm162/tuLXJFRe51gcdn+MrrCB8E23VElB0NQbEKYdtXoURrjpI8cSfQ1xoLIrT+wCYle35csOexEHQanu8ayNWkP8Xpvol4M9l4LjVULjDqwsw9U2P7+Qpbgs= ARC-Message-Signature: i=1; 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b=iTqecJFgy7DP7NJEXOG0D+7xVxQpbpFr7ExRdsq8hnn7jzrAeapDKTeemFT3VCg/k ugjrp/u0Bq74wcUnOJUUJDcU/5a5RK4B8FbgUzuMPibkq8zvqnHugbf7U2rS35INK7 NG+/+r+PO4JCWAVPXmNRcTNDDXoV075Bv6Ychxyb3DfobiKFZby2PIIoGPBU0PrPU4 Te++cye6IHxqeETHYapq1519jlMVONamWiWWqf5H1+JHRkrDxfErpbmz3FNwPOA0es difE0Lh3wNUtWpdgi9creZ0DynzBJJzi/hC0O2KBFksYqPMzZXjDtFKUBfVcX//pEs vkj6bwVoi0jxw== From: Drew Fustini Date: Mon, 19 Jan 2026 20:14:43 -0800 Subject: [PATCH RFC 06/19] RISC-V: QoS: define CBQRI resctrl resources and domains Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-ssqosid-cbqri-v1-6-aa2a75153832@kernel.org> References: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> In-Reply-To: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Conor Dooley , Krzysztof Kozlowski , Rob Herring , Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1672; i=fustini@kernel.org; h=from:subject:message-id; bh=W0zogC96arTBm1Kk9wlCZRwh/gtmVd8rFFkcBWq21X8=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTmMwZNSRLbqHRN41jHZ+f3/4p3tXBd8bolqeqnpzvxm PT5bVGHOkpZGMS4GGTFFFk2fci7sMQr9OuC+S+2wcxhZQIZwsDFKQATmbKf4X/dW63JwsGf3j5a fP2myTNf9SVGr/PNtfbaXnXlqD+wOSeD4a80d7iIif7v6rZ5c646TTr8151x7fm0ttCnv54I1Gf PE+UDAA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Define data structures to encapsulate the resctrl resource and domain structures. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi [fustini: rebased on riscv/for-next] Signed-off-by: Drew Fustini --- arch/riscv/kernel/qos/internal.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/riscv/kernel/qos/internal.h b/arch/riscv/kernel/qos/inter= nal.h index ff2c7eff50be..c0402dd06cfa 100644 --- a/arch/riscv/kernel/qos/internal.h +++ b/arch/riscv/kernel/qos/internal.h @@ -65,6 +65,11 @@ #define CBQRI_BC_ALLOC_CTL_OP_READ_LIMIT 2 #define CBQRI_BC_ALLOC_CTL_STATUS_SUCCESS 1 =20 +int qos_resctrl_setup(void); +void qos_resctrl_exit(void); +int qos_resctrl_online_cpu(unsigned int cpu); +int qos_resctrl_offline_cpu(unsigned int cpu); + /* Capacity Controller hardware capabilities */ struct riscv_cbqri_capacity_caps { u16 ncblks; /* number of capacity blocks */ @@ -125,4 +130,26 @@ struct cbqri_controller { bool mon_capable; }; =20 +struct cbqri_resctrl_res { + struct rdt_resource resctrl_res; + struct cbqri_controller controller; + u32 max_rcid; + u32 max_mcid; +}; + +struct cbqri_resctrl_dom { + struct rdt_domain_hdr resctrl_dom_hdr; + struct rdt_ctrl_domain resctrl_ctrl_dom; + struct rdt_mon_domain resctrl_mon_dom; + u64 cbm; + u64 rbwb; + u64 *ctrl_val; + struct cbqri_controller *hw_ctrl; +}; + +struct cbqri_config { + u64 cbm; /* capacity block mask */ + u64 rbwb; /* reserved bandwidth blocks */ +}; + #endif /* _ASM_RISCV_QOS_INTERNAL_H */ --=20 2.43.0 From nobody Sun Feb 8 15:53:51 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1ADD733C528; Tue, 20 Jan 2026 04:15:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768882522; cv=none; b=rvJjkiIyAiRh0AatsdcoTEe7QVpm2C64oL8xEDHM+xeSFMuO7wSWN65gSZ8EfUI9wyTGzMtw6Ba6NWxRbz43mMvN+fjX2RgDohmxdmO04YqcJUJ7JEKf9aw+17jOYx50vd8BMhP5WQKz8w0ZX/HV0urwKpTQOuZ0pBXzi55vz9g= ARC-Message-Signature: i=1; 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b=tJrWM4Jlv8EPiNguXi34IMmH900SeLGHOZKnLesPNJ3HxYkOle3hygR3We4ASD7QD tDGiAZ9C0/hzar4PZkjwedtXys5obJMOBOyxyeoDNZ8l0ARpcSY+s+Y+X80LXq8BLL EJ9xZJK5BI1gZ4rqiIoPSBb/he6UJRMT2BeCiMZh6JuWBTP7n3CneJ+vRBLYCFKNye YHiwXT3E8QOn+pwjF2/PyENV3IwYbi/4EZMnt46JDYrdpkjVsZ6I+dUUC1QyTzwcmv 6hsdNewZriAif/INmK6b8vr6a+iklQxqIAi4fiuafVgxfHf3HFgzr/rHKpkSc2K2Em zVQEirZQ4nEjg== From: Drew Fustini Date: Mon, 19 Jan 2026 20:14:44 -0800 Subject: [PATCH RFC 07/19] RISC-V: QoS: define prototypes for resctrl interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-ssqosid-cbqri-v1-7-aa2a75153832@kernel.org> References: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> In-Reply-To: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Conor Dooley , Krzysztof Kozlowski , Rob Herring , Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2765; i=fustini@kernel.org; h=from:subject:message-id; bh=VY+L/H7NAb+kbLIgJH0JdAYq+trW362UFibAaSaVSAU=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTmMwZlv0240nxloabf7If7vILvexoe0PBM3nw3NsBX6 lNMg59SRykLgxgXg6yYIsumD3kXlniFfl0w/8U2mDmsTCBDGLg4BWAiF5czMvQ5y7P3Wzn6ii8r u7hkcV6B7aV6x7WOCh3Hdpz8pt6Vspbhf16/75FGy9h3zWb32npTDolJlNtv6ZYqrNT9HBgd934 VAwA= X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Define the prototypes for the resctrl interface functions that are implemented on RISC-V. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi [fustini: rebased on riscv/for-next] Signed-off-by: Drew Fustini --- include/linux/riscv_qos.h | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/include/linux/riscv_qos.h b/include/linux/riscv_qos.h index 51c3a96bbcd0..0c551ed85fe1 100644 --- a/include/linux/riscv_qos.h +++ b/include/linux/riscv_qos.h @@ -3,6 +3,7 @@ #ifndef __LINUX_RISCV_QOS_H #define __LINUX_RISCV_QOS_H =20 +#include #include #include =20 @@ -31,4 +32,47 @@ struct cbqri_controller_info { =20 extern struct list_head cbqri_controllers; =20 +bool resctrl_arch_alloc_capable(void); +bool resctrl_arch_mon_capable(void); +bool resctrl_arch_is_llc_occupancy_enabled(void); +bool resctrl_arch_is_mbm_local_enabled(void); +bool resctrl_arch_is_mbm_total_enabled(void); + +struct rdt_resource; +/* + * Note about terminology between x86 (Intel RDT/AMD QoS) and RISC-V: + * CLOSID on x86 is RCID on RISC-V + * RMID on x86 is MCID on RISC-V + * CDP on x86 is AT (access type) on RISC-V + */ +u32 resctrl_arch_rmid_idx_encode(u32 closid, u32 rmid); +void resctrl_arch_rmid_idx_decode(u32 idx, u32 *closid, u32 *rmid); +void resctrl_arch_set_cpu_default_closid_rmid(int cpu, u32 closid, u32 pmg= ); +void resctrl_arch_sched_in(struct task_struct *tsk); +void resctrl_arch_set_closid_rmid(struct task_struct *tsk, u32 closid, u32= rmid); +bool resctrl_arch_match_closid(struct task_struct *tsk, u32 closid); +bool resctrl_arch_match_rmid(struct task_struct *tsk, u32 closid, u32 rmid= ); +void resctrl_arch_reset_resources(void); +void *resctrl_arch_mon_ctx_alloc(struct rdt_resource *r, enum resctrl_even= t_id evtid); +void resctrl_arch_mon_ctx_free(struct rdt_resource *r, enum resctrl_event_= id evtid, + void *arch_mon_ctx); +struct rdt_domain_hdr *resctrl_arch_find_domain(struct list_head *domain_l= ist, int id); + +static inline bool resctrl_arch_event_is_free_running(enum resctrl_event_i= d evt) +{ + /* must be true for resctrl L3 monitoring files to be created */ + return true; +} + +static inline unsigned int resctrl_arch_round_mon_val(unsigned int val) +{ + return val; +} + +/* Not needed for RISC-V */ +static inline void resctrl_arch_enable_mon(void) { } +static inline void resctrl_arch_disable_mon(void) { } +static inline void resctrl_arch_enable_alloc(void) { } +static inline void resctrl_arch_disable_alloc(void) { } + #endif /* __LINUX_RISCV_QOS_H */ --=20 2.43.0 From nobody Sun Feb 8 15:53:51 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B191027B347; Tue, 20 Jan 2026 04:15:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768882522; cv=none; b=F25Yj/nItpjwSKDJSeN4YvuieSjdA2CJkgvis0+ugr9pj7pK2nJ+O+z5sl2gls0quNmBrJiS6qxT0VwrqlUci/LJcCMgp1gCCAI1P9NQoCCo2hIbbcuin2LLBkqXbQTY9qY7W23ckXxvA7jGJcDCLT9HswXDihtNiCH1KYxAeVk= ARC-Message-Signature: i=1; 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b=dWPVSPW62JHmpwzK2XL1D9uuKviDukrutG0IwGpmcSuIX1nxmJczWSQY8xUoXpmqd CXMjx+xnAUY+kRPtqHNMWYcZnSYSx9pue0a1MQq6VileH+HlqzTaYOJVTyLWlHFCYs 68YdGDn5lQcJkJkiCq+ctClyTvk5Y5gRmGgDlAKucEQH4tDGNg8y3GLoHOscdrQFcm o7hXDRi3tY33+5SDPovDm2maD8QHSr2fUuqykcFv/Q4rbgkQsQHupF3EpplkE3tXGO jNW+P7vDuvpP5KwGu/RulMy9n5CWvHDU2BkWqfw+URIiHKWKgB+8UqC8hCDKDdMJPL bQOdaVu8DPW3w== From: Drew Fustini Date: Mon, 19 Jan 2026 20:14:45 -0800 Subject: [PATCH RFC 08/19] RISC-V: QoS: add resctrl interface for CBQRI controllers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-ssqosid-cbqri-v1-8-aa2a75153832@kernel.org> References: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> In-Reply-To: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Conor Dooley , Krzysztof Kozlowski , Rob Herring , Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=36778; i=fustini@kernel.org; h=from:subject:message-id; bh=dH0W24y4dujuFI0YrGHR3kslgfglscHm15aPNDwtIDs=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTmMwbtmXvMa3nxxdOP5ZNWplq3Jl35xbie5Xo047NlY Yfvict/6ChlYRDjYpAVU2TZ9CHvwhKv0K8L5r/YBjOHlQlkCAMXpwBMJFGMkaH3FdunaZN6C5+e c7yc+mqf59H93JMirLgulN48EbifS3U3w28WvTM7Pbl8ol9L9n5vf2ydbBvnoe7H8TBi68YFV0+ +9WcGAA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Add interface for CBQRI controller drivers to make use of the resctrl filesystem. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- arch/riscv/kernel/qos/qos_resctrl.c | 1191 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 1191 insertions(+) diff --git a/arch/riscv/kernel/qos/qos_resctrl.c b/arch/riscv/kernel/qos/qo= s_resctrl.c new file mode 100644 index 000000000000..5e3a65342e9b --- /dev/null +++ b/arch/riscv/kernel/qos/qos_resctrl.c @@ -0,0 +1,1191 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#define pr_fmt(fmt) "qos: resctrl: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include "internal.h" + +#define MAX_CONTROLLERS 6 +static struct cbqri_controller controllers[MAX_CONTROLLERS]; +static struct cbqri_resctrl_res cbqri_resctrl_resources[RDT_NUM_RESOURCES]; + +static bool exposed_alloc_capable; +static bool exposed_mon_capable; +/* CDP (code data prioritization) on x86 is AT (access type) on RISC-V */ +static bool exposed_cdp_l2_capable; +static bool exposed_cdp_l3_capable; +static bool is_cdp_l2_enabled; +static bool is_cdp_l3_enabled; + +/* used by resctrl_arch_system_num_rmid_idx() */ +static u32 max_rmid; + +LIST_HEAD(cbqri_controllers); + +static int cbqri_wait_busy_flag(struct cbqri_controller *ctrl, int reg_off= set); + +bool resctrl_arch_alloc_capable(void) +{ + return exposed_alloc_capable; +} + +bool resctrl_arch_mon_capable(void) +{ + return exposed_mon_capable; +} + +bool resctrl_arch_is_llc_occupancy_enabled(void) +{ + return true; +} + +bool resctrl_arch_is_mbm_local_enabled(void) +{ + return false; +} + +bool resctrl_arch_is_mbm_total_enabled(void) +{ + return false; +} + +bool resctrl_arch_get_cdp_enabled(enum resctrl_res_level rid) +{ + switch (rid) { + case RDT_RESOURCE_L2: + return is_cdp_l2_enabled; + + case RDT_RESOURCE_L3: + return is_cdp_l3_enabled; + + default: + return false; + } +} + +int resctrl_arch_set_cdp_enabled(enum resctrl_res_level rid, bool enable) +{ + switch (rid) { + case RDT_RESOURCE_L2: + if (!exposed_cdp_l2_capable) + return -ENODEV; + is_cdp_l2_enabled =3D enable; + break; + + case RDT_RESOURCE_L3: + if (!exposed_cdp_l3_capable) + return -ENODEV; + is_cdp_l3_enabled =3D enable; + break; + + default: + return -ENODEV; + } + + return 0; +} + +struct rdt_resource *resctrl_arch_get_resource(enum resctrl_res_level l) +{ + if (l >=3D RDT_NUM_RESOURCES) + return NULL; + + return &cbqri_resctrl_resources[l].resctrl_res; +} + +struct rdt_domain_hdr *resctrl_arch_find_domain(struct list_head *domain_l= ist, int id) +{ + struct rdt_domain_hdr *hdr; + + lockdep_assert_cpus_held(); + + list_for_each_entry(hdr, domain_list, list) { + if (hdr->id =3D=3D id) + return hdr; + } + + return NULL; +} + +bool resctrl_arch_is_evt_configurable(enum resctrl_event_id evt) +{ + return false; +} + +void *resctrl_arch_mon_ctx_alloc(struct rdt_resource *r, + enum resctrl_event_id evtid) +{ + /* RISC-V can always read an rmid, nothing needs allocating */ + return NULL; +} + +void resctrl_arch_mon_ctx_free(struct rdt_resource *r, + enum resctrl_event_id evtid, void *arch_mon_ctx) +{ + /* not implemented for the RISC-V resctrl interface */ +} + +void resctrl_arch_reset_resources(void) +{ + /* not implemented for the RISC-V resctrl implementation */ +} + +void resctrl_arch_config_cntr(struct rdt_resource *r, struct rdt_mon_domai= n *d, + enum resctrl_event_id evtid, u32 rmid, u32 closid, + u32 cntr_id, bool assign) +{ + /* not implemented for the RISC-V resctrl implementation */ +} + +int resctrl_arch_cntr_read(struct rdt_resource *r, struct rdt_mon_domain *= d, + u32 unused, u32 rmid, int cntr_id, + enum resctrl_event_id eventid, u64 *val) +{ + /* not implemented for the RISC-V resctrl implementation */ + return 0; +} + +bool resctrl_arch_mbm_cntr_assign_enabled(struct rdt_resource *r) +{ + /* not implemented for the RISC-V resctrl implementation */ + return false; +} + +int resctrl_arch_mbm_cntr_assign_set(struct rdt_resource *r, bool enable) +{ + /* not implemented for the RISC-V resctrl implementation */ + return 0; +} + +void resctrl_arch_reset_cntr(struct rdt_resource *r, struct rdt_mon_domain= *d, + u32 unused, u32 rmid, int cntr_id, + enum resctrl_event_id eventid) +{ + /* not implemented for the RISC-V resctrl implementation */ +} + +bool resctrl_arch_get_io_alloc_enabled(struct rdt_resource *r) +{ + /* not implemented for the RISC-V resctrl implementation */ + return false; +} + +int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable) +{ + /* not implemented for the RISC-V resctrl implementation */ + return 0; +} + +/* + * Note about terminology between x86 (Intel RDT/AMD QoS) and RISC-V: + * CLOSID on x86 is RCID on RISC-V + * RMID on x86 is MCID on RISC-V + */ +u32 resctrl_arch_get_num_closid(struct rdt_resource *res) +{ + struct cbqri_resctrl_res *hw_res; + + hw_res =3D container_of(res, struct cbqri_resctrl_res, resctrl_res); + + return hw_res->max_rcid; +} + +u32 resctrl_arch_system_num_rmid_idx(void) +{ + return max_rmid; +} + +u32 resctrl_arch_rmid_idx_encode(u32 closid, u32 rmid) +{ + return rmid; +} + +void resctrl_arch_rmid_idx_decode(u32 idx, u32 *closid, u32 *rmid) +{ + *closid =3D ((u32)~0); /* refer to X86_RESCTRL_BAD_CLOSID */ + *rmid =3D idx; +} + +/* RISC-V resctrl interface does not maintain a default srmcfg value for a= given CPU */ +void resctrl_arch_set_cpu_default_closid_rmid(int cpu, u32 closid, u32 rmi= d) { } + +void resctrl_arch_sched_in(struct task_struct *tsk) +{ + __switch_to_srmcfg(tsk); +} + +void resctrl_arch_set_closid_rmid(struct task_struct *tsk, u32 closid, u32= rmid) +{ + u32 srmcfg; + + WARN_ON_ONCE((closid & SRMCFG_RCID_MASK) !=3D closid); + WARN_ON_ONCE((rmid & SRMCFG_MCID_MASK) !=3D rmid); + + srmcfg =3D rmid << SRMCFG_MCID_SHIFT; + srmcfg |=3D closid; + WRITE_ONCE(tsk->thread.srmcfg, srmcfg); +} + +void resctrl_arch_sync_cpu_closid_rmid(void *info) +{ + struct resctrl_cpu_defaults *r =3D info; + + lockdep_assert_preemption_disabled(); + + if (r) { + resctrl_arch_set_cpu_default_closid_rmid(smp_processor_id(), + r->closid, r->rmid); + } + + resctrl_arch_sched_in(current); +} + +bool resctrl_arch_match_closid(struct task_struct *tsk, u32 closid) +{ + u32 srmcfg; + bool match; + + srmcfg =3D READ_ONCE(tsk->thread.srmcfg); + match =3D (srmcfg & SRMCFG_RCID_MASK) =3D=3D closid; + return match; +} + +bool resctrl_arch_match_rmid(struct task_struct *tsk, u32 closid, u32 rmid) +{ + u32 tsk_rmid; + + tsk_rmid =3D READ_ONCE(tsk->thread.srmcfg); + tsk_rmid >>=3D SRMCFG_MCID_SHIFT; + tsk_rmid &=3D SRMCFG_MCID_MASK; + + return tsk_rmid =3D=3D rmid; +} + +int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_mon_domain *= d, + u32 closid, u32 rmid, enum resctrl_event_id eventid, + u64 *val, void *arch_mon_ctx) +{ + /* + * The current Qemu implementation of CBQRI capacity and bandwidth + * controllers do not emulate the utilization of resources over + * time. Therefore, Qemu currently sets the invalid bit in + * cc_mon_ctr_val and bc_mon_ctr_val, and there is no meaningful + * value other than 0 to return for reading an RMID (e.g. MCID in + * CBQRI terminology) + */ + + return 0; +} + +void resctrl_arch_reset_rmid(struct rdt_resource *r, struct rdt_mon_domain= *d, + u32 closid, u32 rmid, enum resctrl_event_id eventid) +{ + /* not implemented for the RISC-V resctrl interface */ +} + +void resctrl_arch_mon_event_config_read(void *info) +{ + /* not implemented for the RISC-V resctrl interface */ +} + +void resctrl_arch_mon_event_config_write(void *info) +{ + /* not implemented for the RISC-V resctrl interface */ +} + +void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_mon_do= main *d) +{ + /* not implemented for the RISC-V resctrl implementation */ +} + +void resctrl_arch_reset_all_ctrls(struct rdt_resource *r) +{ + /* not implemented for the RISC-V resctrl implementation */ +} + +/* Set capacity block mask (cc_block_mask) */ +static void cbqri_set_cbm(struct cbqri_controller *ctrl, u64 cbm) +{ + int reg_offset; + u64 reg; + + reg_offset =3D CBQRI_CC_BLOCK_MASK_OFF; + reg =3D ioread64(ctrl->base + reg_offset); + + reg =3D cbm; + iowrite64(reg, ctrl->base + reg_offset); +} + +/* Set the Rbwb (reserved bandwidth blocks) field in bc_bw_alloc */ +static void cbqri_set_rbwb(struct cbqri_controller *ctrl, u64 rbwb) +{ + int reg_offset; + u64 reg; + + reg_offset =3D CBQRI_BC_BW_ALLOC_OFF; + reg =3D ioread64(ctrl->base + reg_offset); + reg &=3D ~CBQRI_CONTROL_REGISTERS_RBWB_MASK; + rbwb &=3D CBQRI_CONTROL_REGISTERS_RBWB_MASK; + reg |=3D rbwb; + iowrite64(reg, ctrl->base + reg_offset); +} + +/* Get the Rbwb (reserved bandwidth blocks) field in bc_bw_alloc */ +static u64 cbqri_get_rbwb(struct cbqri_controller *ctrl) +{ + int reg_offset; + u64 reg; + + reg_offset =3D CBQRI_BC_BW_ALLOC_OFF; + reg =3D ioread64(ctrl->base + reg_offset); + reg &=3D CBQRI_CONTROL_REGISTERS_RBWB_MASK; + return reg; +} + +static int cbqri_wait_busy_flag(struct cbqri_controller *ctrl, int reg_off= set) +{ + unsigned long timeout =3D jiffies + (HZ / 10); /* Timeout after 100ms */ + int busy; + u64 reg; + + while (time_before(jiffies, timeout)) { + reg =3D ioread64(ctrl->base + reg_offset); + busy =3D (reg >> CBQRI_CONTROL_REGISTERS_BUSY_SHIFT) & + CBQRI_CONTROL_REGISTERS_BUSY_MASK; + if (!busy) + return 0; + } + + pr_warn("%s(): busy timeout", __func__); + return -EIO; +} + +/* Perform capacity allocation control operation on capacity controller */ +static int cbqri_cc_alloc_op(struct cbqri_controller *ctrl, int operation,= int rcid, + enum resctrl_conf_type type) +{ + int reg_offset =3D CBQRI_CC_ALLOC_CTL_OFF; + int status; + u64 reg; + + reg =3D ioread64(ctrl->base + reg_offset); + reg &=3D ~(CBQRI_CONTROL_REGISTERS_OP_MASK << CBQRI_CONTROL_REGISTERS_OP_= SHIFT); + reg |=3D (operation & CBQRI_CONTROL_REGISTERS_OP_MASK) << + CBQRI_CONTROL_REGISTERS_OP_SHIFT; + reg &=3D ~(CBQRI_CONTROL_REGISTERS_RCID_MASK << + CBQRI_CONTROL_REGISTERS_RCID_SHIFT); + reg |=3D (rcid & CBQRI_CONTROL_REGISTERS_RCID_MASK) << + CBQRI_CONTROL_REGISTERS_RCID_SHIFT; + + /* CBQRI capacity AT is only supported on L2 and L3 caches for now */ + if (ctrl->ctrl_info->type =3D=3D CBQRI_CONTROLLER_TYPE_CAPACITY && + ((ctrl->ctrl_info->cache.cache_level =3D=3D 2 && is_cdp_l2_enabled) || + (ctrl->ctrl_info->cache.cache_level =3D=3D 3 && is_cdp_l3_enabled))) { + reg &=3D ~(CBQRI_CONTROL_REGISTERS_AT_MASK << + CBQRI_CONTROL_REGISTERS_AT_SHIFT); + switch (type) { + case CDP_CODE: + reg |=3D (CBQRI_CONTROL_REGISTERS_AT_CODE & + CBQRI_CONTROL_REGISTERS_AT_MASK) << + CBQRI_CONTROL_REGISTERS_AT_SHIFT; + break; + case CDP_DATA: + default: + reg |=3D (CBQRI_CONTROL_REGISTERS_AT_DATA & + CBQRI_CONTROL_REGISTERS_AT_MASK) << + CBQRI_CONTROL_REGISTERS_AT_SHIFT; + break; + } + } + + iowrite64(reg, ctrl->base + reg_offset); + + if (cbqri_wait_busy_flag(ctrl, reg_offset) < 0) { + pr_err("%s(): BUSY timeout when executing the operation", __func__); + return -EIO; + } + + reg =3D ioread64(ctrl->base + reg_offset); + status =3D (reg >> CBQRI_CONTROL_REGISTERS_STATUS_SHIFT) & + CBQRI_CONTROL_REGISTERS_STATUS_MASK; + if (status !=3D 1) { + pr_err("%s(): operation %d failed: status=3D%d", __func__, operation, st= atus); + return -EIO; + } + + return 0; +} + +static int cbqri_apply_cache_config(struct cbqri_resctrl_dom *hw_dom, u32 = closid, + enum resctrl_conf_type type, struct cbqri_config *cfg) +{ + struct cbqri_controller *ctrl =3D hw_dom->hw_ctrl; + int reg_offset; + int err =3D 0; + u64 reg; + + if (cfg->cbm !=3D hw_dom->ctrl_val[closid]) { + /* Store the new cbm in the ctrl_val array for this closid in this domai= n */ + hw_dom->ctrl_val[closid] =3D cfg->cbm; + + /* Set capacity block mask (cc_block_mask) */ + cbqri_set_cbm(ctrl, cfg->cbm); + + /* Capacity config limit operation */ + err =3D cbqri_cc_alloc_op(ctrl, CBQRI_CC_ALLOC_CTL_OP_CONFIG_LIMIT, clos= id, type); + if (err < 0) { + pr_err("%s(): operation failed: err =3D %d", __func__, err); + return err; + } + + /* Clear cc_block_mask before read limit to verify op works*/ + cbqri_set_cbm(ctrl, 0); + + /* Performa capacity read limit operation to verify blockmask */ + err =3D cbqri_cc_alloc_op(ctrl, CBQRI_CC_ALLOC_CTL_OP_READ_LIMIT, closid= , type); + if (err < 0) { + pr_err("%s(): operation failed: err =3D %d", __func__, err); + return err; + } + + /* Read capacity blockmask to verify it matches the requested config */ + reg_offset =3D CBQRI_CC_BLOCK_MASK_OFF; + reg =3D ioread64(ctrl->base + reg_offset); + if (reg !=3D cfg->cbm) { + pr_warn("%s(): failed to verify allocation (reg:%llx !=3D cbm:%llx)", + __func__, reg, cfg->cbm); + return -EIO; + } + } + + return err; +} + +/* Perform bandwidth allocation control operation on bandwidth controller = */ +static int cbqri_bc_alloc_op(struct cbqri_controller *ctrl, int operation,= int rcid) +{ + int reg_offset =3D CBQRI_BC_ALLOC_CTL_OFF; + int status; + u64 reg; + + reg =3D ioread64(ctrl->base + reg_offset); + reg &=3D ~(CBQRI_CONTROL_REGISTERS_OP_MASK << CBQRI_CONTROL_REGISTERS_OP_= SHIFT); + reg |=3D (operation & CBQRI_CONTROL_REGISTERS_OP_MASK) << + CBQRI_CONTROL_REGISTERS_OP_SHIFT; + reg &=3D ~(CBQRI_CONTROL_REGISTERS_RCID_MASK << CBQRI_CONTROL_REGISTERS_R= CID_SHIFT); + reg |=3D (rcid & CBQRI_CONTROL_REGISTERS_RCID_MASK) << + CBQRI_CONTROL_REGISTERS_RCID_SHIFT; + iowrite64(reg, ctrl->base + reg_offset); + + if (cbqri_wait_busy_flag(ctrl, reg_offset) < 0) { + pr_err("%s(): BUSY timeout when executing the operation", __func__); + return -EIO; + } + + reg =3D ioread64(ctrl->base + reg_offset); + status =3D (reg >> CBQRI_CONTROL_REGISTERS_STATUS_SHIFT) & + CBQRI_CONTROL_REGISTERS_STATUS_MASK; + if (status !=3D 1) { + pr_err("%s(): operation %d failed with status =3D %d", + __func__, operation, status); + return -EIO; + } + + return 0; +} + +static int cbqri_apply_bw_config(struct cbqri_resctrl_dom *hw_dom, u32 clo= sid, + enum resctrl_conf_type type, struct cbqri_config *cfg) +{ + struct cbqri_controller *ctrl =3D hw_dom->hw_ctrl; + int ret =3D 0; + u64 reg; + + if (cfg->rbwb !=3D hw_dom->ctrl_val[closid]) { + /* Store the new rbwb in the ctrl_val array for this closid in this doma= in */ + hw_dom->ctrl_val[closid] =3D cfg->rbwb; + + /* Set reserved bandwidth blocks */ + cbqri_set_rbwb(ctrl, cfg->rbwb); + + /* Bandwidth config limit operation */ + ret =3D cbqri_bc_alloc_op(ctrl, CBQRI_CC_ALLOC_CTL_OP_CONFIG_LIMIT, clos= id); + if (ret < 0) { + pr_err("%s(): operation failed: ret =3D %d", __func__, ret); + return ret; + } + + /* Clear rbwb before read limit to verify op works*/ + cbqri_set_rbwb(ctrl, 0); + + /* Bandwidth allocation read limit operation to verify */ + ret =3D cbqri_bc_alloc_op(ctrl, CBQRI_CC_ALLOC_CTL_OP_READ_LIMIT, closid= ); + if (ret < 0) { + pr_err("%s(): operation failed: ret =3D %d", __func__, ret); + return ret; + } + + /* Read bandwidth allocation to verify it matches the requested config */ + reg =3D cbqri_get_rbwb(ctrl); + if (reg !=3D cfg->rbwb) { + pr_warn("%s(): failed to verify allocation (reg:%llx !=3D rbwb:%llu)", + __func__, reg, cfg->rbwb); + return -EIO; + } + } + + return ret; +} + +int resctrl_arch_update_one(struct rdt_resource *r, struct rdt_ctrl_domain= *d, + u32 closid, enum resctrl_conf_type t, u32 cfg_val) +{ + struct cbqri_controller *ctrl; + struct cbqri_resctrl_dom *dom; + struct cbqri_config cfg; + int err =3D 0; + + dom =3D container_of(d, struct cbqri_resctrl_dom, resctrl_ctrl_dom); + ctrl =3D dom->hw_ctrl; + + if (!r->alloc_capable) + return -EINVAL; + + switch (r->rid) { + case RDT_RESOURCE_L2: + case RDT_RESOURCE_L3: + cfg.cbm =3D cfg_val; + err =3D cbqri_apply_cache_config(dom, closid, t, &cfg); + break; + case RDT_RESOURCE_MBA: + /* covert from percentage to bandwidth blocks */ + cfg.rbwb =3D cfg_val * ctrl->bc.nbwblks / 100; + err =3D cbqri_apply_bw_config(dom, closid, t, &cfg); + break; + default: + return -EINVAL; + } + + return err; +} + +int resctrl_arch_update_domains(struct rdt_resource *r, u32 closid) +{ + struct resctrl_staged_config *cfg; + enum resctrl_conf_type t; + struct rdt_ctrl_domain *d; + int err =3D 0; + + list_for_each_entry(d, &r->ctrl_domains, hdr.list) { + for (t =3D 0; t < CDP_NUM_TYPES; t++) { + cfg =3D &d->staged_config[t]; + if (!cfg->have_new_ctrl) + continue; + err =3D resctrl_arch_update_one(r, d, closid, t, cfg->new_ctrl); + if (err) { + pr_warn("%s(): update failed (err=3D%d)", __func__, err); + return err; + } + } + } + return err; +} + +u32 resctrl_arch_get_config(struct rdt_resource *r, struct rdt_ctrl_domain= *d, + u32 closid, enum resctrl_conf_type type) +{ + struct cbqri_resctrl_dom *hw_dom; + struct cbqri_controller *ctrl; + int reg_offset; + u32 percent; + u32 rbwb; + u64 reg; + int err; + + hw_dom =3D container_of(d, struct cbqri_resctrl_dom, resctrl_ctrl_dom); + + ctrl =3D hw_dom->hw_ctrl; + + if (!r->alloc_capable) + return -EINVAL; + + switch (r->rid) { + case RDT_RESOURCE_L2: + case RDT_RESOURCE_L3: + /* Clear cc_block_mask before read limit operation */ + cbqri_set_cbm(ctrl, 0); + + /* Capacity read limit operation for RCID (closid) */ + err =3D cbqri_cc_alloc_op(ctrl, CBQRI_CC_ALLOC_CTL_OP_READ_LIMIT, type, = closid); + if (err < 0) { + pr_err("%s(): operation failed: err =3D %d", __func__, err); + return -EIO; + } + + /* Read capacity block mask for RCID (closid) */ + reg_offset =3D CBQRI_CC_BLOCK_MASK_OFF; + reg =3D ioread64(ctrl->base + reg_offset); + + /* Update the config value for the closid in this domain */ + hw_dom->ctrl_val[closid] =3D reg; + return hw_dom->ctrl_val[closid]; + + case RDT_RESOURCE_MBA: + /* Capacity read limit operation for RCID (closid) */ + err =3D cbqri_bc_alloc_op(ctrl, CBQRI_CC_ALLOC_CTL_OP_READ_LIMIT, closid= ); + if (err < 0) { + pr_err("%s(): operation failed: err =3D %d", __func__, err); + return -EIO; + } + + hw_dom->ctrl_val[closid] =3D cbqri_get_rbwb(ctrl); + + /* Convert from bandwidth blocks to percent */ + rbwb =3D hw_dom->ctrl_val[closid]; + rbwb *=3D 100; + percent =3D rbwb / ctrl->bc.nbwblks; + if (rbwb % ctrl->bc.nbwblks) + percent++; + return percent; + + default: + return -EINVAL; + } +} + +static int cbqri_probe_feature(struct cbqri_controller *ctrl, int reg_offs= et, + int operation, int *status, bool *access_type_supported) +{ + u64 reg, saved_reg; + int at; + + /* Keep the initial register value to preserve the WPRI fields */ + reg =3D ioread64(ctrl->base + reg_offset); + saved_reg =3D reg; + + /* Execute the requested operation to find if the register is implemented= */ + reg &=3D ~(CBQRI_CONTROL_REGISTERS_OP_MASK << CBQRI_CONTROL_REGISTERS_OP_= SHIFT); + reg |=3D (operation & CBQRI_CONTROL_REGISTERS_OP_MASK) << CBQRI_CONTROL_R= EGISTERS_OP_SHIFT; + iowrite64(reg, ctrl->base + reg_offset); + if (cbqri_wait_busy_flag(ctrl, reg_offset) < 0) { + pr_err("%s(): BUSY timeout when executing the operation", __func__); + return -EIO; + } + + /* Get the operation status */ + reg =3D ioread64(ctrl->base + reg_offset); + *status =3D (reg >> CBQRI_CONTROL_REGISTERS_STATUS_SHIFT) & + CBQRI_CONTROL_REGISTERS_STATUS_MASK; + + /* + * Check for the AT support if the register is implemented + * (if not, the status value will remain 0) + */ + if (*status !=3D 0) { + /* Set the AT field to a valid value */ + reg =3D saved_reg; + reg &=3D ~(CBQRI_CONTROL_REGISTERS_AT_MASK << CBQRI_CONTROL_REGISTERS_AT= _SHIFT); + reg |=3D CBQRI_CONTROL_REGISTERS_AT_CODE << CBQRI_CONTROL_REGISTERS_AT_S= HIFT; + iowrite64(reg, ctrl->base + reg_offset); + if (cbqri_wait_busy_flag(ctrl, reg_offset) < 0) { + pr_err("%s(): BUSY timeout when setting AT field", __func__); + return -EIO; + } + + /* + * If the AT field value has been reset to zero, + * then the AT support is not present + */ + reg =3D ioread64(ctrl->base + reg_offset); + at =3D (reg >> CBQRI_CONTROL_REGISTERS_AT_SHIFT) & CBQRI_CONTROL_REGISTE= RS_AT_MASK; + if (at =3D=3D CBQRI_CONTROL_REGISTERS_AT_CODE) + *access_type_supported =3D true; + else + *access_type_supported =3D false; + } + + /* Restore the original register value */ + iowrite64(saved_reg, ctrl->base + reg_offset); + if (cbqri_wait_busy_flag(ctrl, reg_offset) < 0) { + pr_err("%s(): BUSY timeout when restoring the original register value", = __func__); + return -EIO; + } + + return 0; +} + +/* + * Note: for the purposes of the CBQRI proof-of-concept, debug logging + * has been left in this function that detects the properties of CBQRI + * capable controllers in the system. pr_info calls would be removed + * before submitting non-RFC patches. + */ +static int cbqri_probe_controller(struct cbqri_controller_info *ctrl_info, + struct cbqri_controller *ctrl) +{ + int err =3D 0, status; + u64 reg; + + pr_info("controller info: type=3D%d addr=3D0x%lx size=3D%lu max-rcid=3D%u= max-mcid=3D%u", + ctrl_info->type, ctrl_info->addr, ctrl_info->size, + ctrl_info->rcid_count, ctrl_info->mcid_count); + + /* max_rmid is used by resctrl_arch_system_num_rmid_idx() */ + max_rmid =3D ctrl_info->mcid_count; + + ctrl->ctrl_info =3D ctrl_info; + + /* Try to access the memory-mapped CBQRI registers */ + if (!request_mem_region(ctrl_info->addr, ctrl_info->size, "cbqri_controll= er")) { + pr_warn("%s(): return %d", __func__, err); + return err; + } + ctrl->base =3D ioremap(ctrl_info->addr, ctrl_info->size); + if (!ctrl->base) { + pr_warn("%s(): goto err_release_mem_region", __func__); + goto err_release_mem_region; + } + + ctrl->alloc_capable =3D false; + ctrl->mon_capable =3D false; + + /* Probe capacity allocation and monitoring features */ + if (ctrl_info->type =3D=3D CBQRI_CONTROLLER_TYPE_CAPACITY) { + pr_info("probe capacity controller"); + + /* Make sure the register is implemented */ + reg =3D ioread64(ctrl->base + CBQRI_CC_CAPABILITIES_OFF); + if (reg =3D=3D 0) { + err =3D -ENODEV; + goto err_iounmap; + } + + ctrl->ver_minor =3D reg & CBQRI_CC_CAPABILITIES_VER_MINOR_MASK; + ctrl->ver_major =3D reg & CBQRI_CC_CAPABILITIES_VER_MAJOR_MASK; + + ctrl->cc.supports_alloc_op_flush_rcid =3D (reg >> CBQRI_CC_CAPABILITIES_= FRCID_SHIFT) + & CBQRI_CC_CAPABILITIES_FRCID_MASK; + + ctrl->cc.ncblks =3D (reg >> CBQRI_CC_CAPABILITIES_NCBLKS_SHIFT) & + CBQRI_CC_CAPABILITIES_NCBLKS_MASK; + + /* Calculate size of capacity block in bytes */ + ctrl->cc.blk_size =3D ctrl_info->cache.cache_size / ctrl->cc.ncblks; + ctrl->cc.cache_level =3D ctrl_info->cache.cache_level; + + pr_info("version=3D%d.%d ncblks=3D%d blk_size=3D%d cache_level=3D%d", + ctrl->ver_major, ctrl->ver_minor, + ctrl->cc.ncblks, ctrl->cc.blk_size, ctrl->cc.cache_level); + + /* Probe monitoring features */ + err =3D cbqri_probe_feature(ctrl, CBQRI_CC_MON_CTL_OFF, + CBQRI_CC_MON_CTL_OP_READ_COUNTER, &status, + &ctrl->cc.supports_mon_at_code); + if (err) { + pr_warn("%s() failed to probe cc_mon_ctl feature", __func__); + goto err_iounmap; + } + + if (status =3D=3D CBQRI_CC_MON_CTL_STATUS_SUCCESS) { + pr_info("cc_mon_ctl is supported"); + ctrl->cc.supports_mon_op_config_event =3D true; + ctrl->cc.supports_mon_op_read_counter =3D true; + ctrl->mon_capable =3D true; + } else { + pr_info("cc_mon_ctl is NOT supported"); + ctrl->cc.supports_mon_op_config_event =3D false; + ctrl->cc.supports_mon_op_read_counter =3D false; + ctrl->mon_capable =3D false; + } + /* + * AT data is "always" supported as it has the same value + * than when AT field is not supported. + */ + ctrl->cc.supports_mon_at_data =3D true; + pr_info("supports_mon_at_data: %d, supports_mon_at_code: %d", + ctrl->cc.supports_mon_at_data, ctrl->cc.supports_mon_at_code); + + /* Probe allocation features */ + err =3D cbqri_probe_feature(ctrl, CBQRI_CC_ALLOC_CTL_OFF, + CBQRI_CC_ALLOC_CTL_OP_READ_LIMIT, + &status, &ctrl->cc.supports_alloc_at_code); + if (err) { + pr_warn("%s() failed to probe cc_alloc_ctl feature", __func__); + goto err_iounmap; + } + + if (status =3D=3D CBQRI_CC_ALLOC_CTL_STATUS_SUCCESS) { + pr_info("cc_alloc_ctl is supported"); + ctrl->cc.supports_alloc_op_config_limit =3D true; + ctrl->cc.supports_alloc_op_read_limit =3D true; + ctrl->alloc_capable =3D true; + exposed_alloc_capable =3D true; + } else { + pr_info("cc_alloc_ctl is NOT supported"); + ctrl->cc.supports_alloc_op_config_limit =3D false; + ctrl->cc.supports_alloc_op_read_limit =3D false; + ctrl->alloc_capable =3D false; + } + /* + * AT data is "always" supported as it has the same value + * than when AT field is not supported + */ + ctrl->cc.supports_alloc_at_data =3D true; + pr_info("supports_alloc_at_data: %d, supports_alloc_at_code: %d", + ctrl->cc.supports_alloc_at_data, + ctrl->cc.supports_alloc_at_code); + } else if (ctrl_info->type =3D=3D CBQRI_CONTROLLER_TYPE_BANDWIDTH) { + pr_info("probe bandwidth controller"); + + /* Make sure the register is implemented */ + reg =3D ioread64(ctrl->base + CBQRI_BC_CAPABILITIES_OFF); + if (reg =3D=3D 0) { + err =3D -ENODEV; + goto err_iounmap; + } + + ctrl->ver_minor =3D reg & CBQRI_BC_CAPABILITIES_VER_MINOR_MASK; + ctrl->ver_major =3D reg & CBQRI_BC_CAPABILITIES_VER_MAJOR_MASK; + + ctrl->bc.nbwblks =3D (reg >> CBQRI_BC_CAPABILITIES_NBWBLKS_SHIFT) & + CBQRI_BC_CAPABILITIES_NBWBLKS_MASK; + ctrl->bc.mrbwb =3D (reg >> CBQRI_BC_CAPABILITIES_MRBWB_SHIFT) & + CBQRI_BC_CAPABILITIES_MRBWB_MASK; + + pr_info("version=3D%d.%d nbwblks=3D%d mrbwb=3D%d", + ctrl->ver_major, ctrl->ver_minor, + ctrl->bc.nbwblks, ctrl->bc.mrbwb); + + /* Probe monitoring features */ + err =3D cbqri_probe_feature(ctrl, CBQRI_BC_MON_CTL_OFF, + CBQRI_BC_MON_CTL_OP_READ_COUNTER, + &status, &ctrl->bc.supports_mon_at_code); + if (err) { + pr_warn("%s() failed to probe bc_mon_ctl feature", __func__); + goto err_iounmap; + } + + if (status =3D=3D CBQRI_BC_MON_CTL_STATUS_SUCCESS) { + pr_info("bc_mon_ctl is supported"); + ctrl->bc.supports_mon_op_config_event =3D true; + ctrl->bc.supports_mon_op_read_counter =3D true; + ctrl->mon_capable =3D true; + exposed_mon_capable =3D true; + } else { + pr_info("bc_mon_ctl is NOT supported"); + ctrl->bc.supports_mon_op_config_event =3D false; + ctrl->bc.supports_mon_op_read_counter =3D false; + ctrl->mon_capable =3D false; + } + /* + * AT data is "always" supported as it has the same value + * than when AT field is not supported + */ + ctrl->bc.supports_mon_at_data =3D true; + pr_info("supports_mon_at_data: %d, supports_mon_at_code: %d", + ctrl->bc.supports_mon_at_data, ctrl->bc.supports_mon_at_code); + + /* Probe allocation features */ + err =3D cbqri_probe_feature(ctrl, CBQRI_BC_ALLOC_CTL_OFF, + CBQRI_BC_ALLOC_CTL_OP_READ_LIMIT, + &status, &ctrl->bc.supports_alloc_at_code); + if (err) { + pr_warn("%s() failed to probe bc_alloc_ctl feature", __func__); + goto err_iounmap; + } + + if (status =3D=3D CBQRI_BC_ALLOC_CTL_STATUS_SUCCESS) { + pr_warn("bc_alloc_ctl is supported"); + ctrl->bc.supports_alloc_op_config_limit =3D true; + ctrl->bc.supports_alloc_op_read_limit =3D true; + ctrl->alloc_capable =3D true; + exposed_alloc_capable =3D true; + } else { + pr_warn("bc_alloc_ctl is NOT supported"); + ctrl->bc.supports_alloc_op_config_limit =3D false; + ctrl->bc.supports_alloc_op_read_limit =3D false; + ctrl->alloc_capable =3D false; + } + + /* + * AT data is "always" supported as it has the same value + * than when AT field is not supported + */ + ctrl->bc.supports_alloc_at_data =3D true; + pr_warn("supports_alloc_at_data: %d, supports_alloc_at_code: %d", + ctrl->bc.supports_alloc_at_data, ctrl->bc.supports_alloc_at_code); + } else { + pr_warn("controller type is UNKNOWN"); + err =3D -ENODEV; + goto err_release_mem_region; + } + + return 0; + +err_iounmap: + pr_warn("%s(): err_iounmap", __func__); + iounmap(ctrl->base); + +err_release_mem_region: + pr_warn("%s(): err_release_mem_region", __func__); + release_mem_region(ctrl_info->addr, ctrl_info->size); + + return err; +} + +static struct rdt_ctrl_domain *qos_new_domain(struct cbqri_controller *ctr= l) +{ + struct cbqri_resctrl_dom *hw_dom; + struct rdt_ctrl_domain *domain; + + hw_dom =3D kzalloc(sizeof(*hw_dom), GFP_KERNEL); + if (!hw_dom) + return NULL; + + /* associate this cbqri_controller with the domain */ + hw_dom->hw_ctrl =3D ctrl; + + /* the rdt_domain struct from inside the cbqri_resctrl_dom struct */ + domain =3D &hw_dom->resctrl_ctrl_dom; + + INIT_LIST_HEAD(&domain->hdr.list); + + return domain; +} + +static int qos_init_domain_ctrlval(struct rdt_resource *r, struct rdt_ctrl= _domain *d) +{ + struct cbqri_resctrl_res *hw_res; + struct cbqri_resctrl_dom *hw_dom; + u64 *dc; + int err =3D 0; + int i; + + hw_res =3D container_of(r, struct cbqri_resctrl_res, resctrl_res); + if (!hw_res) + return -ENOMEM; + + hw_dom =3D container_of(d, struct cbqri_resctrl_dom, resctrl_ctrl_dom); + if (!hw_dom) + return -ENOMEM; + + dc =3D kmalloc_array(hw_res->max_rcid, sizeof(*hw_dom->ctrl_val), + GFP_KERNEL); + if (!dc) + return -ENOMEM; + + hw_dom->ctrl_val =3D dc; + + for (i =3D 0; i < hw_res->max_rcid; i++, dc++) { + err =3D resctrl_arch_update_one(r, d, i, 0, resctrl_get_default_ctrl(r)); + if (err) + return 0; + *dc =3D resctrl_get_default_ctrl(r); + } + return 0; +} + +static int qos_resctrl_add_controller_domain(struct cbqri_controller *ctrl= , int *id) +{ + struct rdt_ctrl_domain *domain =3D NULL; + struct cbqri_resctrl_res *cbqri_res =3D NULL; + struct rdt_resource *res =3D NULL; + int internal_id =3D *id; + int err =3D 0; + + domain =3D qos_new_domain(ctrl); + if (!domain) + return -ENOSPC; + if (ctrl->ctrl_info->type =3D=3D CBQRI_CONTROLLER_TYPE_CAPACITY) { + cpumask_copy(&domain->hdr.cpu_mask, &ctrl->ctrl_info->cache.cpu_mask); + if (ctrl->ctrl_info->cache.cache_level =3D=3D 2) { + cbqri_res =3D &cbqri_resctrl_resources[RDT_RESOURCE_L2]; + cbqri_res->max_rcid =3D ctrl->ctrl_info->rcid_count; + cbqri_res->max_mcid =3D ctrl->ctrl_info->mcid_count; + res =3D &cbqri_res->resctrl_res; + res->mon.num_rmid =3D ctrl->ctrl_info->mcid_count; + res->rid =3D RDT_RESOURCE_L2; + res->name =3D "L2"; + res->alloc_capable =3D ctrl->alloc_capable; + res->mon_capable =3D ctrl->mon_capable; + res->schema_fmt =3D RESCTRL_SCHEMA_BITMAP; + res->ctrl_scope =3D RESCTRL_L2_CACHE; + res->cache.arch_has_sparse_bitmasks =3D false; + res->cache.arch_has_per_cpu_cfg =3D false; + res->cache.cbm_len =3D ctrl->cc.ncblks; + res->cache.shareable_bits =3D resctrl_get_default_ctrl(res); + res->cache.min_cbm_bits =3D 1; + } else if (ctrl->ctrl_info->cache.cache_level =3D=3D 3) { + cbqri_res =3D &cbqri_resctrl_resources[RDT_RESOURCE_L3]; + cbqri_res->max_rcid =3D ctrl->ctrl_info->rcid_count; + cbqri_res->max_mcid =3D ctrl->ctrl_info->mcid_count; + res =3D &cbqri_res->resctrl_res; + res->mon.num_rmid =3D ctrl->ctrl_info->mcid_count; + res->rid =3D RDT_RESOURCE_L3; + res->name =3D "L3"; + res->schema_fmt =3D RESCTRL_SCHEMA_BITMAP; + res->ctrl_scope =3D RESCTRL_L3_CACHE; + res->alloc_capable =3D ctrl->alloc_capable; + res->mon_capable =3D ctrl->mon_capable; + res->cache.arch_has_sparse_bitmasks =3D false; + res->cache.arch_has_per_cpu_cfg =3D false; + res->cache.cbm_len =3D ctrl->cc.ncblks; + res->cache.shareable_bits =3D resctrl_get_default_ctrl(res); + res->cache.min_cbm_bits =3D 1; + } else { + pr_warn("%s(): unknown cache level %d", __func__, + ctrl->ctrl_info->cache.cache_level); + err =3D -ENODEV; + goto err_free_domain; + } + } else if (ctrl->ctrl_info->type =3D=3D CBQRI_CONTROLLER_TYPE_BANDWIDTH) { + if (ctrl->alloc_capable) { + cbqri_res =3D &cbqri_resctrl_resources[RDT_RESOURCE_MBA]; + cbqri_res->max_rcid =3D ctrl->ctrl_info->rcid_count; + cbqri_res->max_mcid =3D ctrl->ctrl_info->mcid_count; + res =3D &cbqri_res->resctrl_res; + res->mon.num_rmid =3D ctrl->ctrl_info->mcid_count; + res->rid =3D RDT_RESOURCE_MBA; + res->name =3D "MB"; + res->schema_fmt =3D RESCTRL_SCHEMA_RANGE; + res->ctrl_scope =3D RESCTRL_L3_CACHE; + res->alloc_capable =3D ctrl->alloc_capable; + res->mon_capable =3D false; + res->membw.delay_linear =3D true; + res->membw.arch_needs_linear =3D true; + res->membw.throttle_mode =3D THREAD_THROTTLE_UNDEFINED; + // The minimum percentage allowed by the CBQRI spec + res->membw.min_bw =3D 1; + // The maximum percentage allowed by the CBQRI spec + res->membw.max_bw =3D 80; + res->membw.bw_gran =3D 1; + } + } else { + pr_warn("%s(): unknown resource %d", __func__, ctrl->ctrl_info->type); + err =3D -ENODEV; + goto err_free_domain; + } + + domain->hdr.id =3D internal_id; + err =3D qos_init_domain_ctrlval(res, domain); + if (err) + goto err_free_domain; + + if (cbqri_res) { + list_add_tail(&domain->hdr.list, &cbqri_res->resctrl_res.ctrl_domains); + *id =3D internal_id; + err =3D resctrl_online_ctrl_domain(res, domain); + if (err) { + pr_warn("%s(): failed to online cbqri_res domain", __func__); + goto err_free_domain; + } + } + + return 0; + +err_free_domain: + pr_warn("%s(): err_free_domain", __func__); + kfree(container_of(domain, struct cbqri_resctrl_dom, resctrl_ctrl_dom)); + + return err; +} + +int qos_resctrl_setup(void) +{ + struct rdt_ctrl_domain *domain, *domain_temp; + struct cbqri_controller_info *ctrl_info; + struct cbqri_controller *ctrl; + struct cbqri_resctrl_res *res; + static int found_controllers; + int err =3D 0; + int id =3D 0; + int i; + + list_for_each_entry(ctrl_info, &cbqri_controllers, list) { + err =3D cbqri_probe_controller(ctrl_info, &controllers[found_controllers= ]); + if (err) { + pr_warn("%s(): failed (%d)", __func__, err); + goto err_unmap_controllers; + } + + found_controllers++; + if (found_controllers > MAX_CONTROLLERS) { + pr_warn("%s(): increase MAX_CONTROLLERS value", __func__); + break; + } + } + + for (i =3D 0; i < RDT_NUM_RESOURCES; i++) { + res =3D &cbqri_resctrl_resources[i]; + INIT_LIST_HEAD(&res->resctrl_res.ctrl_domains); + INIT_LIST_HEAD(&res->resctrl_res.mon_domains); + res->resctrl_res.rid =3D i; + } + + for (i =3D 0; i < found_controllers; i++) { + ctrl =3D &controllers[i]; + err =3D qos_resctrl_add_controller_domain(ctrl, &id); + if (err) { + pr_warn("%s(): failed to add controller domain (%d)", __func__, err); + goto err_free_controllers_list; + } + id++; + + /* + * CDP (code data prioritization) on x86 is similar to + * the AT (access type) field in CBQRI. CDP only supports + * caches so this must be a CBQRI capacity controller. + */ + if (ctrl->ctrl_info->type =3D=3D CBQRI_CONTROLLER_TYPE_CAPACITY && + ctrl->cc.supports_alloc_at_code && + ctrl->cc.supports_alloc_at_data) { + if (ctrl->ctrl_info->cache.cache_level =3D=3D 2) + exposed_cdp_l2_capable =3D true; + else + exposed_cdp_l3_capable =3D true; + } + } + + pr_info("exposed_alloc_capable =3D %d", exposed_alloc_capable); + pr_info("exposed_mon_capable =3D %d", exposed_mon_capable); + pr_info("exposed_cdp_l2_capable =3D %d", exposed_cdp_l2_capable); + pr_info("exposed_cdp_l3_capable =3D %d", exposed_cdp_l3_capable); + + return resctrl_init(); + +err_free_controllers_list: + for (i =3D 0; i < RDT_NUM_RESOURCES; i++) { + res =3D &cbqri_resctrl_resources[i]; + list_for_each_entry_safe(domain, domain_temp, &res->resctrl_res.ctrl_dom= ains, + hdr.list) { + kfree(domain); + } + } + +err_unmap_controllers: + for (i =3D 0; i < found_controllers; i++) { + iounmap(controllers[i].base); + release_mem_region(controllers[i].ctrl_info->addr, controllers[i].ctrl_i= nfo->size); + } + + return err; +} + +int qos_resctrl_online_cpu(unsigned int cpu) +{ + resctrl_online_cpu(cpu); + return 0; +} + +int qos_resctrl_offline_cpu(unsigned int cpu) +{ + resctrl_offline_cpu(cpu); + return 0; +} + --=20 2.43.0 From nobody Sun Feb 8 15:53:51 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7A7433CE8A; Tue, 20 Jan 2026 04:15:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768882522; cv=none; b=FeyiRkSNYLZ41y1LOOpRHOVHhbNPzSoeT+ya7l8wqjOW5KSUlIX9mcf+rkv50S4JgjCItA6cen4WwPObzSburQNapJfOCPkxbbRSR2F4WAKe6hQ007VN+QI/DzmT2EUvTXaUthZY1uaDhYGT6E2POdIoDbznnjbhTTEfHLroz6c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-ssqosid-cbqri-v1-9-aa2a75153832@kernel.org> References: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> In-Reply-To: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Conor Dooley , Krzysztof Kozlowski , Rob Herring , Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1087; i=fustini@kernel.org; h=from:subject:message-id; bh=SXrtFbN0ix7KxT0GqeIs7HkzT3FdlhgaF3gCwM+F2Mc=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTmMwZF1c69f1YjasXrHwXVb9bd+FXizcnw+PAc2dmcu Zary9hedJSyMIhxMciKKbJs+pB3YYlX6NcF819sg5nDygQyhIGLUwAm8tqQ4Q9n1dv7n26Uf7Rl yRPlVYi+mRxfMc1G6Ezjx2WJM20EpXQZGZa1S74S4VUOkdFhtf87VyE3LbL7jFacEi+rbaKKT/U fNgA= X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 The generic resctrl header include/linux/resctrl.h includes linux/riscv_qos.h when CONFIG_ARCH_HAS_CPU_RESCTRL is set. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- MAINTAINERS | 1 + arch/riscv/include/asm/resctrl.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 31e536304972..96ead357a634 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22510,6 +22510,7 @@ M: Drew Fustini L: linux-riscv@lists.infradead.org S: Supported F: arch/riscv/include/asm/qos.h +F: arch/riscv/include/asm/resctrl.h F: arch/riscv/kernel/qos/ F: include/linux/riscv_qos.h =20 diff --git a/arch/riscv/include/asm/resctrl.h b/arch/riscv/include/asm/resc= trl.h new file mode 100644 index 000000000000..7d247d87dab9 --- /dev/null +++ b/arch/riscv/include/asm/resctrl.h @@ -0,0 +1,2 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include --=20 2.43.0 From nobody Sun Feb 8 15:53:51 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DED3A33B947; Tue, 20 Jan 2026 04:15:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768882524; cv=none; b=Wgq0xkHCC0aH5q5DO0pBaoXa3RgLgig53/HeueyJOKcSPS/gmFLrIngTwKAKYgNpIHtplF4X/aux2vxEjplQECkCxcEwhvdFpVnaiRzXhhCxmdFmaii/7Q/xFeR/713Jr+8vwuvlfG58C408TdrSWGmJmi0QxIpm9opn+Fk5L8M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768882524; c=relaxed/simple; bh=jw+AW2ohMGVwE01frppRYwsxi/H3/LBPifNRE5CWvac=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To; b=u5gTKhgEch3bIEdGSGtlcUNOQq1ltjQdQaGlDqxGb90Vt6N+wLuMrf4ff85i/vhN5bLn1a4HV+5i/z/JxqyWxqycJXkXmmADkL0FWGRfLXNuVZkzUBq9bEJ0lfAQq8xtVQ3+s4CAeQHMFusP7MKcFf2TARzn2bERB1jH/l5XKXk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tzHYKw8w; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tzHYKw8w" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C42B5C2BC87; Tue, 20 Jan 2026 04:15:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1768882523; bh=jw+AW2ohMGVwE01frppRYwsxi/H3/LBPifNRE5CWvac=; h=From:Date:Subject:References:In-Reply-To:To:From; b=tzHYKw8w0WWEHMf/ggC0mFgB6cU2ZV861rE5FmdcrE46pVUB/XCmIRYTNdMixY04b 85M6AqX5o5XEONNJ6yBsr4+2pJzacEqw1wIno0QTIdX6DIW09pHQ4ww/gi6MkcrAYS S+YP0bEzazZfcmDoNkx22MYjtsyoeAH66jnQeU0lxvhzQ8uhVISwqr38pDFePqlflM 5hpR4vta4fjkIYJsVTx3JiaTxL9LhalxXFMzAkTYxvG637Xmf/L74RyGoyUXYouwWL iVZCa3y93s0BEcpfUr9uK/lix93lw4SXzcLqj+e5ofYtdk9g9aJK0dCoc3UNMZX8s8 wXuVHKv6fGkEA== From: Drew Fustini Date: Mon, 19 Jan 2026 20:14:47 -0800 Subject: [PATCH RFC 10/19] RISC-V: QoS: add late_initcall to setup resctrl interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-ssqosid-cbqri-v1-10-aa2a75153832@kernel.org> References: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> In-Reply-To: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Conor Dooley , Krzysztof Kozlowski , Rob Herring , Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1362; i=fustini@kernel.org; h=from:subject:message-id; bh=jw+AW2ohMGVwE01frppRYwsxi/H3/LBPifNRE5CWvac=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTmMwbt1VgdKl0yuWPu/DSXozJXF/UK/H63O/t0Wr/xp iI5S+6AjlIWBjEuBlkxRZZNH/IuLPEK/bpg/ottMHNYmUCGMHBxCsBEVJcwMvz9s/up6g6nC4/W PWj9JvVAO+bjwya3LPWJfxQuLcmw7zzOyHAqtC9qwum584T99q85axFpJJOmsijkzLOkaYrfbGp 8azkA X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Add late_initcall which checks if the Ssqosid extension is present, and if so, calls resctrl setup and sets cpu hotplug state to "qos:online". Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- arch/riscv/kernel/qos/qos.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/riscv/kernel/qos/qos.c b/arch/riscv/kernel/qos/qos.c index 7b06f7ae9056..2cd5d7be1d10 100644 --- a/arch/riscv/kernel/qos/qos.c +++ b/arch/riscv/kernel/qos/qos.c @@ -1,5 +1,32 @@ // SPDX-License-Identifier: GPL-2.0-only +#include +#include +#include +#include +#include + +#include #include =20 +#include "internal.h" + /* cached value of sqoscfg csr for each cpu */ DEFINE_PER_CPU(u32, cpu_srmcfg); + +static int __init qos_arch_late_init(void) +{ + int err; + + if (!riscv_isa_extension_available(NULL, SSQOSID)) + return -ENODEV; + + err =3D qos_resctrl_setup(); + if (err !=3D 0) + return err; + + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "qos:online", qos_resctrl_online_c= pu, + qos_resctrl_offline_cpu); + + return err; +} +late_initcall(qos_arch_late_init); --=20 2.43.0 From nobody Sun Feb 8 15:53:51 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C3D133C538; Tue, 20 Jan 2026 04:15:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768882524; cv=none; b=rz4Q9a3aE9pGBgxZz4wKUCtY0S4ugNJxiC3MbMMy79xZ79V0w4rBwTYsEZsvIoGcu8pwUE2ekjgdTHe8lT8vCJWAbwrDap71i6MwykMq3/L9bYhK3bEW/scWgRxzpKr2kY3wHChuI1I8G3OKTHYU9yAxIYm7ztUloxtpQYtz01I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768882524; c=relaxed/simple; bh=LLcYCf8E3m+c3NEGM6PLVB/b2aK0eRa7uHCxUc0B8eM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To; b=SriRoQni/JDNdoZXJnEWagQbrZN2HQDK2ekb7eGCP77SOZ460JyBZysQt2ooetQ82hQIWs8bakor8E5Pm0H26O9G9X7xRt2LAnFBmmrNdtzW2ZWhw9/pfqVVBUW9305sWjtnK1MeH2sK+s9JnO/jAndcRf20/3BLATaiUh0QVsc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NjkctdjK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NjkctdjK" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 549EAC2BCC6; Tue, 20 Jan 2026 04:15:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1768882523; bh=LLcYCf8E3m+c3NEGM6PLVB/b2aK0eRa7uHCxUc0B8eM=; h=From:Date:Subject:References:In-Reply-To:To:From; b=NjkctdjKUn0SLqbTQurxBFfLInhgoQWsPREXXMtKwABJ/gYwDhLfCUs8qJtBs06rc EUaBhI2ahtDB8PBFbcHF5tCQl1GzV1TZdEqVEDdKoB4hJkz+LqtjEayxp6d+28gFE8 3ABLnRkLQPtnbfcmjEIIUs7xDEA+B4pluqyp1dkgwdmiqtqqtrMmERzCcuE3zeTV53 NoZia7WtAER7IlZZVsX/H+NT6nWzcWrp9vpmUzk7d0PbNOeq1moTRsUKI1lcK+6Vrh /lpV9aJzxiRiuX6iEMy0eT/YDrf8e9SePo2PA9hEHQ7H7RV8fEx8GeUbuUfigHfv0v G9hZ+ZbdjOglg== From: Drew Fustini Date: Mon, 19 Jan 2026 20:14:48 -0800 Subject: [PATCH RFC 11/19] RISC-V: QoS: add to build when CONFIG_RISCV_ISA_SSQOSID set Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-ssqosid-cbqri-v1-11-aa2a75153832@kernel.org> References: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> In-Reply-To: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Conor Dooley , Krzysztof Kozlowski , Rob Herring , Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=738; i=fustini@kernel.org; h=from:subject:message-id; bh=LLcYCf8E3m+c3NEGM6PLVB/b2aK0eRa7uHCxUc0B8eM=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTmMwbdjty3TG5LQAHrWZZdIf/E2jMXGsx4bdseHx+2s 0fuqKVwRykLgxgXg6yYIsumD3kXlniFfl0w/8U2mDmsTCBDGLg4BWAii20ZGd6Wzr7z0Wshw7Je jeDaqElRHatnO7xLi2dY+6hi7mvPLzsYGc7V2kZWJvycdatwx5ufb6pO+ChkSX88qvOua0PZlo8 +3/kB X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Add the srmcfg CSR handling and the resctrl interface to the build when CONFIG_RISCV_ISA_SSQOSID is set. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- arch/riscv/kernel/qos/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/qos/Makefile b/arch/riscv/kernel/qos/Makefile index 9f996263a86d..9ed0c13a854d 100644 --- a/arch/riscv/kernel/qos/Makefile +++ b/arch/riscv/kernel/qos/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_RISCV_ISA_SSQOSID) +=3D qos.o +obj-$(CONFIG_RISCV_ISA_SSQOSID) +=3D qos.o qos_resctrl.o --=20 2.43.0 From nobody Sun Feb 8 15:53:51 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0EB0633C1B7; Tue, 20 Jan 2026 04:15:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768882525; cv=none; b=Exu1DSWcBXqz3KtLB8jyu1J1shyw7OcEyDb7cTdhs7ipm3Yy30m2kQsFKL6a3j2uUAdPnOw6G/T4/x7KRj2peAKuUrIovNGcbdo48VhTrdYOKzcEr1XXpgHywHs8wMz1I+NfvJxh2V+jBbRD5Q/uWGedopOz7ssEh1sh/XLi5os= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768882525; c=relaxed/simple; bh=uFVTMJOPvCbobzJzlLLOywkmk/8YKf9YQOLxRrQYfB8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To; b=JGD44URNbZN0HRPhTM96PFxdds1fY6cav7v7ItNBmQmKJrwSaBD4vSvDWALOzKYpma432JaCrcA0h1QBavchsFYGL0gBAoSwdJuRbK+FgKJDecyyu1QsCAUkVDtm/pyJoDEIdO+O7Tdq694+7hTy7sjLgSd+NR39pJtRLJNxINY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=EjlSLzA7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="EjlSLzA7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EAC85C2BCB0; Tue, 20 Jan 2026 04:15:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1768882524; bh=uFVTMJOPvCbobzJzlLLOywkmk/8YKf9YQOLxRrQYfB8=; h=From:Date:Subject:References:In-Reply-To:To:From; b=EjlSLzA7PLfg5Brd4VelzPqUk2McwqgKEHr9LXbNSZS1+tB4h3R6KaBUUFgXrV3Pq NeRpnqofz2UV8XK4Muf+zWbpA0QXbXhZkcP/uKyzYuYhPJWyHrzvjL1SsOxEfTTsvO HXoDxTUh3eXXCg3X3F0nl/OBW3pE6FeK2JZDQH1ej1Xv/tm2CCPicpgkwwWl1zoynm +54/6E4DgDxiSdAgXcW9mGIg0ZX3VAqLhCuSkFZvbCMB84n0UQWlaMVAknhbyJmBuv IV9YxR1gpH3Zo8EZbJ88jv6A3QlFy8WZ3S91sbl/tpFrL1ZxQlOqCJbklLdbNzgDfF b3p/Co+to5Ddw== From: Drew Fustini Date: Mon, 19 Jan 2026 20:14:49 -0800 Subject: [PATCH RFC 12/19] RISC-V: QoS: make CONFIG_RISCV_ISA_SSQOSID select resctrl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-ssqosid-cbqri-v1-12-aa2a75153832@kernel.org> References: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> In-Reply-To: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Conor Dooley , Krzysztof Kozlowski , Rob Herring , Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=875; i=fustini@kernel.org; h=from:subject:message-id; bh=uFVTMJOPvCbobzJzlLLOywkmk/8YKf9YQOLxRrQYfB8=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTmMwb3zA5w3fvmloVYg6G7fU/96pqPs/8adhgHbkh+x mGT1XO7o5SFQYyLQVZMkWXTh7wLS7xCvy6Y/2IbzBxWJpAhDFycAjCRnkiG/2FrmKxCF/OkvLi5 21L3RcairRvZVMwv8r5v1n5XuNa3/AbDH76jCXrvFvms41hTJSsSMf2x4m2JNqVCL5Wq0j1yCtN n8gIA X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Make CONFIG_RISCV_ISA_SSQOSID select the config options for resctrl: ARCH_HAS_CPU_RESCTRL, RESCTRL_FS and MISC_FILESYSTEMS. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- arch/riscv/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 35a6238b02c5..8ff6d962b6b2 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -598,6 +598,9 @@ config RISCV_ISA_SVNAPOT config RISCV_ISA_SSQOSID bool "Ssqosid extension support for supervisor mode Quality of Service ID" default y + select ARCH_HAS_CPU_RESCTRL + select RESCTRL_FS + select MISC_FILESYSTEMS help Adds support for the Ssqosid ISA extension (Supervisor-mode Quality of Service ID). --=20 2.43.0 From nobody Sun Feb 8 15:53:51 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E53233DED0; Tue, 20 Jan 2026 04:15:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768882525; cv=none; b=oPoELGYRsS+YQ68+jFLaOeNijtVWU2rwsmR67zTVhWKmTUYR4jNz0gaJ87uChFMYlOTYEHnpynWBZQ9XcTrR9Nj9e1c/aYr6TLCi8KyzQagIzbzAfKVtklG84ft/TcVm/G/jiHWk5gnEwiLb1FssyrDfZRAXHj2NFsK6MKoEFa4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768882525; c=relaxed/simple; bh=RN9LOBb2Q5aHVScQAnVGdCBA9dhEyBoY6qpcRx7/gOs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To; b=rnd8jUTEu7kFFFsWNBL4rgfBjx4r6bv2qTjCxODky3QOW7Zdn0+nFLz6CtqMi3ieEhnjH9nqr9ZGBpcEhgijqHxDgKYPfIwKbYK8OKX4MH2ax5il4/9Hj00dJSw20JQidWfrFTCVS4ZzoTqvPqBNopax7vjF7jsPgMk9wRfej7A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ibALnT31; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ibALnT31" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 770D7C2BC86; Tue, 20 Jan 2026 04:15:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1768882524; bh=RN9LOBb2Q5aHVScQAnVGdCBA9dhEyBoY6qpcRx7/gOs=; h=From:Date:Subject:References:In-Reply-To:To:From; b=ibALnT31IaRWqMCGHNDwcHyS4zY3PSOEdYb8NpS5lFcY9V9AQeIfJA2MNUOWdVPtP wyj4P9oSyvIXD/15cPtpJwSySspLscah8p/lnpuHvXZEI85EKPrXpjLk+zD33TxEsw EHnQr6ea1HUSUyEiaNWdWHFBEMzPGqb7hEzz2cyMZnQXxYQOqA32mx0gxcMDD8ctGj U50pAXE51MWcZQQtDzQF951X0vIB//j+f/InQulIwnKdQXW3yZgzaG9oArYLSXu2pz Bpf4UF51bu52DKbecRmXPwjGMafftEKpEZa6YtZKZ/nCYIW5BinTsiwjTnFAmUHQCc cQsndQKaXlmKQ== From: Drew Fustini Date: Mon, 19 Jan 2026 20:14:50 -0800 Subject: [PATCH RFC 13/19] dt-bindings: riscv: add riscv,cbqri bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-ssqosid-cbqri-v1-13-aa2a75153832@kernel.org> References: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> In-Reply-To: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Conor Dooley , Krzysztof Kozlowski , Rob Herring , Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2066; i=fustini@kernel.org; h=from:subject:message-id; bh=RN9LOBb2Q5aHVScQAnVGdCBA9dhEyBoY6qpcRx7/gOs=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTmMwZvKFxgcutym03sq+CM7AXrjIVjpl3U/3o9LfXz/ danM1VvdJSyMIhxMciKKbJs+pB3YYlX6NcF819sg5nDygQyhIGLUwAm8rmO4X9BzN0toRZacQzf 96rcrT4tKfnC6njW3ZzSqS/jBRbaS51hZGiMPee4Z+38us9bFs7YbRN6YIFugjWX0duHVdEvGlX i1vADAA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Document properties that can be used in the bindings for controllers that implement the RISC-V CBQRI specification. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- .../devicetree/bindings/riscv/riscv,cbqri.yaml | 28 ++++++++++++++++++= ++++ MAINTAINERS | 1 + 2 files changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/riscv,cbqri.yaml b/Doc= umentation/devicetree/bindings/riscv/riscv,cbqri.yaml new file mode 100644 index 000000000000..7d0482c31a46 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/riscv,cbqri.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/riscv,cbqri.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V Capacity and Bandwidth Register Interface (CBQRI) properties + +description: | + Common properties for cache and memory controllers that implement the + RISC-V CBQRI specification: + https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0 + +maintainers: + - Drew Fustini + +properties: + riscv,cbqri-rcid: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The maximum number of RCIDs the controller supports + + riscv,cbqri-mcid: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The maximum number of MCIDs the controller supports + +additionalProperties: true + +... diff --git a/MAINTAINERS b/MAINTAINERS index 96ead357a634..2c9151e34d2b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22509,6 +22509,7 @@ RISC-V QOS RESCTRL SUPPORT M: Drew Fustini L: linux-riscv@lists.infradead.org S: Supported +F: Documentation/devicetree/bindings/riscv/riscv,cbqri.yaml F: arch/riscv/include/asm/qos.h F: arch/riscv/include/asm/resctrl.h F: arch/riscv/kernel/qos/ --=20 2.43.0 From nobody Sun Feb 8 15:53:51 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 273A433CEBC; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="o5O6wA2S" Received: by smtp.kernel.org (Postfix) with ESMTPSA id F2260C2BC87; Tue, 20 Jan 2026 04:15:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1768882525; bh=R1lDGdU7iIiekrd1oymtfCVNrLHfj85DdbG3x9sBksw=; h=From:Date:Subject:References:In-Reply-To:To:From; b=o5O6wA2Sa7mj9exOhlWMr60IUo9V+uZYDFgj/AhtuKNokK4T3QyFOibJGyRd/1tvh OlI8fL+nnGEs9NWYESHV2Ln6pnEEjX1xeBGGxoAFo6Yjtgv4DJxBR67E1V19Ji1w0T ru6gkzgY1nuC/RU8Nt7mQvtbTH1brAy6rmgME1DwHJBF7uTBQ/uheBfPdA85pqFZy0 TTpO4Ua/33Wtye91iWendEhluYKw7bEVDuNHZuECacmYeyVzJIQ8R7fPgk9c9Gsn5f QQJVQkom/0DVWSGuPP29AUkhY8ygZTpcvbJCaOZQeOJbb4SBneVreDS6c0YgELxqKh UtBt/nasszGpg== From: Drew Fustini Date: Mon, 19 Jan 2026 20:14:51 -0800 Subject: [PATCH NFU RFC 14/19] resctrl: riscv: add CBQRI cache controller driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-ssqosid-cbqri-v1-14-aa2a75153832@kernel.org> References: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> In-Reply-To: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Conor Dooley , Krzysztof Kozlowski , Rob Herring , Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3582; i=fustini@kernel.org; h=from:subject:message-id; bh=R1lDGdU7iIiekrd1oymtfCVNrLHfj85DdbG3x9sBksw=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTmMwbPd3m6brnUfHdzF68gA205o7A5f5Y/vX7961zf9 V6HTss+6yhlYRDjYpAVU2TZ9CHvwhKv0K8L5r/YBjOHlQlkCAMXpwBM5KMZI0NvyR13W+maSyv5 81fnPVsf/LTjXeQOW5t5nClJBgc62h4y/I/4cJxpakut2He/3U9mLlK4Eq8vvf2afgnHv7lGHCu mf2IDAA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 [NOT FOR UPSTREAM] Add example driver for a cache controller that implements CBQRI capacity allocation. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- drivers/resctrl/riscv/cbqri_cache.c | 106 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 106 insertions(+) diff --git a/drivers/resctrl/riscv/cbqri_cache.c b/drivers/resctrl/riscv/cb= qri_cache.c new file mode 100644 index 000000000000..0bee65eefb2d --- /dev/null +++ b/drivers/resctrl/riscv/cbqri_cache.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0-only +#define pr_fmt(fmt) "cbqri-cache: " fmt + +#include +#include +#include + +static const struct of_device_id cbqri_cache_ids[] =3D { + { .compatible =3D "riscv,cbqri-cache" }, + { } +}; + +static int __init cbqri_cache_init(void) +{ + struct cbqri_controller_info *ctrl_info; + struct device_node *np; + u32 value; + int err; + + for_each_matching_node(np, cbqri_cache_ids) { + if (!of_device_is_available(np)) { + of_node_put(np); + continue; + } + + ctrl_info =3D kzalloc(sizeof(*ctrl_info), GFP_KERNEL); + if (!ctrl_info) + goto err_node_put; + ctrl_info->type =3D CBQRI_CONTROLLER_TYPE_CAPACITY; + + err =3D of_property_read_u32_index(np, "reg", 1, &value); + if (err) { + pr_err("Failed to read reg base address (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->addr =3D value; + + err =3D of_property_read_u32_index(np, "reg", 3, &value); + if (err) { + pr_err("Failed to read reg size (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->size =3D value; + + err =3D of_property_read_u32(np, "cache-level", &value); + if (err) { + pr_err("Failed to read cache level (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->cache.cache_level =3D value; + + err =3D of_property_read_u32(np, "cache-size", &value); + if (err) { + pr_err("Failed to read cache size (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->cache.cache_size =3D value; + + err =3D of_property_read_u32(np, "riscv,cbqri-rcid", &value); + if (err) { + pr_err("Failed to read RCID count (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->rcid_count =3D value; + + err =3D of_property_read_u32(np, "riscv,cbqri-mcid", &value); + if (err) { + pr_err("Failed to read MCID count (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->mcid_count =3D value; + + /* + * For CBQRI, any cpu (technically a hart in RISC-V terms) + * can access the memory-mapped registers of any CBQRI + * controller in the system. Therefore, set the CPU mask + * to 'FF' to allow all 8 cores in the example Qemu SoC + */ + err =3D cpumask_parse("FF", &ctrl_info->cache.cpu_mask); + if (err) { + pr_err("Failed to convert cores mask string to cpumask (%d)", err); + goto err_kfree_ctrl_info; + } + + of_node_put(np); + + pr_debug("addr=3D0x%lx max-rcid=3D%u max-mcid=3D%u level=3D%d size=3D%u", + ctrl_info->addr, ctrl_info->rcid_count, ctrl_info->mcid_count, + ctrl_info->cache.cache_level, ctrl_info->cache.cache_size); + + /* Fill the list shared with RISC-V QoS resctrl */ + INIT_LIST_HEAD(&ctrl_info->list); + list_add_tail(&ctrl_info->list, &cbqri_controllers); + } + + return 0; + +err_kfree_ctrl_info: + kfree(ctrl_info); + +err_node_put: + of_node_put(np); + + return err; +} +device_initcall(cbqri_cache_init); --=20 2.43.0 From nobody Sun Feb 8 15:53:51 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A845D33E361; Tue, 20 Jan 2026 04:15:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768882526; cv=none; b=uYaZUUcgapSm71nmKdav02El5568Ok4XuIxEbVnXtqcHqNMkUBxVGl6WBxvQnRcDu8Fbtiksvs00/YTHi0n7bs22sKzDTSIOkhxap3IwPVGZaS8csPEjZtHmYn4vX7O7DaNt4lBMeALQejQx7vpoiXQM9bNQ9nE7VcivSgLAKmA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768882526; c=relaxed/simple; bh=3hAMXnvjLCvZuLkN0WdyCAoEU5EJcEF/iWW3PasfPck=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To; b=V3xnBaIalh1zYm7cJKMACe08SMHd7r6HNaxY/8RamAr/KGN3PVlR8CkYO3KOTnFdzDs5Ijwp3ZqOksgwwxHM1s2hYMW3YSKQIylja+rq3EI2lwPmp1P0FsdMAlcBVpYKbNHYPn8ZAAAYv4Suz8oa/xI6cUBQjf6g5UnX23jbBmk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NCOBNF3y; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NCOBNF3y" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7EBC7C2BCAF; Tue, 20 Jan 2026 04:15:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1768882526; bh=3hAMXnvjLCvZuLkN0WdyCAoEU5EJcEF/iWW3PasfPck=; h=From:Date:Subject:References:In-Reply-To:To:From; b=NCOBNF3y+UrdmyS49PT7n0srA8e8n9hSaC3seECAgp50Q29iJX+lJJju7IyABKaNj 0ZqtZ9RlOStNPHWd4U0F/H/+3qBxj1MEvFnwpC83RzNZyI78xb/vIWCC6hcAdw0VGD A9LpOmmSnUs8xiyo/SvLZXdalZM8F8a3wW7ipqqxUt5s6jBi/pW6cO4QlBWOyw4eJj 6nCT8Mrn7aTLKaDrmdjiI3xlLDYupPhtUXTNFcL1Htmjxhl1brpJKYaxjcyr/wB4uY o02xbB6cimgvS9YRjgUjSge82H2YfjV8Q/Tg4V5ETAKE2uLy99yyfoYy41NYyVx3d4 PR1IBl0ZWTMQw== From: Drew Fustini Date: Mon, 19 Jan 2026 20:14:52 -0800 Subject: [PATCH NFU RFC 15/19] resctrl: riscv: add CBQRI bandwidth controller driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-ssqosid-cbqri-v1-15-aa2a75153832@kernel.org> References: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> In-Reply-To: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Conor Dooley , Krzysztof Kozlowski , Rob Herring , Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2638; i=fustini@kernel.org; h=from:subject:message-id; bh=3hAMXnvjLCvZuLkN0WdyCAoEU5EJcEF/iWW3PasfPck=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTmMwbn/8v13chTdUpN9lEOU8TzUPZ6q5NPfpVN+XD97 YUp//+YdpSyMIhxMciKKbJs+pB3YYlX6NcF819sg5nDygQyhIGLUwAmcteKkeHIlWjJa+pxD7ce /vPsxKZFU05HrNv17dgzo74fFj9EzyhZMvzhbTQpOxrXseyb0cPUHecEewqvcl0Qmbft0sG+/uy 2viNMAA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 [NOT FOR UPSTREAM] Add example driver for a CBQRI bandwidth controller. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- drivers/resctrl/riscv/cbqri_bandwidth.c | 79 +++++++++++++++++++++++++++++= ++++ 1 file changed, 79 insertions(+) diff --git a/drivers/resctrl/riscv/cbqri_bandwidth.c b/drivers/resctrl/risc= v/cbqri_bandwidth.c new file mode 100644 index 000000000000..13649d56b7dc --- /dev/null +++ b/drivers/resctrl/riscv/cbqri_bandwidth.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-only +#define pr_fmt(fmt) "cbqri-bandwidth: " fmt + +#include +#include +#include + +static const struct of_device_id cbqri_mem_ctrl_ids[] =3D { + { .compatible =3D "riscv,cbqri-bandwidth" }, + { } +}; + +static int __init cbqri_mem_ctrl_init(void) +{ + struct cbqri_controller_info *ctrl_info; + struct device_node *np; + u32 value; + int err; + + for_each_matching_node(np, cbqri_mem_ctrl_ids) { + if (!of_device_is_available(np)) { + of_node_put(np); + continue; + } + + ctrl_info =3D kzalloc(sizeof(*ctrl_info), GFP_KERNEL); + if (!ctrl_info) + goto err_node_put; + ctrl_info->type =3D CBQRI_CONTROLLER_TYPE_BANDWIDTH; + + err =3D of_property_read_u32_index(np, "reg", 1, &value); + if (err) { + pr_err("Failed to read reg base address (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->addr =3D value; + + err =3D of_property_read_u32_index(np, "reg", 3, &value); + if (err) { + pr_err("Failed to read reg size (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->size =3D value; + + err =3D of_property_read_u32(np, "riscv,cbqri-rcid", &value); + if (err) { + pr_err("Failed to read RCID count (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->rcid_count =3D value; + + err =3D of_property_read_u32(np, "riscv,cbqri-mcid", &value); + if (err) { + pr_err("Failed to read MCID count (%d)", err); + goto err_kfree_ctrl_info; + } + ctrl_info->mcid_count =3D value; + + of_node_put(np); + + pr_debug("addr=3D0x%lx max-rcid=3D%u max-mcid=3D%u", ctrl_info->addr, + ctrl_info->rcid_count, ctrl_info->mcid_count); + + /* Fill the list shared with RISC-V QoS resctrl */ + INIT_LIST_HEAD(&ctrl_info->list); + list_add_tail(&ctrl_info->list, &cbqri_controllers); + } + + return 0; + +err_kfree_ctrl_info: + kfree(ctrl_info); + +err_node_put: + of_node_put(np); + + return err; +} +device_initcall(cbqri_mem_ctrl_init); --=20 2.43.0 From nobody Sun Feb 8 15:53:51 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8915133EAF9; Tue, 20 Jan 2026 04:15:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768882527; cv=none; b=rkraPCV+6Eq2uBgiZaVT2vQ6bMQk+NsGaS2G2VtRtaQ7lVgRf29xeL6LZOSZRMlLQ5+ZMnW6zdi+VeMFtjtLyqi6jNZGdWC7NouSnRTCBNKRlLDLqtqf9ptXobzvcl5HT4vbDKoP//udJH7BJozd1VEDdpRfnU8+gcGvMoiQM7s= ARC-Message-Signature: i=1; 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b=ZOPt/O0/lggO52Wdqgoyk4ZT7fSlplaFQFPkEmhmPi+Yz8LaLhlbmgALIJrx6Qxct KaJgNIlxfnALFw9h9mKpcDMv0npFxJbQTsaSXE1z6+TJG5qW7RX/5Cm48LHwRUVAL6 oSfR/TTp5nPBnVrA7wjOmqaaP4Fg5fiNXzUA3JIiL4BQUJjj4dF8Vidayyx+sleQjL hoqmDDtUXZlYKDnfd1AmALPWENyBoG6zcHMckXnN4pGLzDuVlAc6jxN+5q7ay93UWB G+1KaRwbhzTloc1xZrAsr+nW19jITSMDcC/WMPUbIAFRvyvmNVR4H2MJ6eKECnNq8t bL/1NqGjMLsZg== From: Drew Fustini Date: Mon, 19 Jan 2026 20:14:53 -0800 Subject: [PATCH NFU RFC 16/19] resctrl: riscv: build CBQRI drivers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-ssqosid-cbqri-v1-16-aa2a75153832@kernel.org> References: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> In-Reply-To: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Conor Dooley , Krzysztof Kozlowski , Rob Herring , Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2641; i=fustini@kernel.org; h=from:subject:message-id; bh=So9iUedCC3u+sUXH12Vr6tmS+PCHIo5F5wnJVHearb0=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTmMwafTDv76crDL4EMJi5SFdMX/G2vbLl3wN6i5O6Zk /I6Z9uCO0pZGMS4GGTFFFk2fci7sMQr9OuC+S+2wcxhZQIZwsDFKQATaTvLyHDgy++/e45OWiQf /TdkisrqDT/mH2b0m+xRqJT0/UqnT9xCRoajN+8bOG5XCGyRPTRt4gn+4FDLY0EdM+9l7zlpPV1 yXikjAA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 [NOT FOR UPSTREAM] Add RISC-V CBQRI cache and bandwidth controller drivers to the build. Link: https://github.com/riscv-non-isa/riscv-cbqri/releases/tag/v1.0 Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- drivers/resctrl/Kconfig | 2 ++ drivers/resctrl/Makefile | 2 ++ drivers/resctrl/riscv/Kconfig | 25 +++++++++++++++++++++++++ drivers/resctrl/riscv/Makefile | 4 ++++ 4 files changed, 33 insertions(+) diff --git a/drivers/resctrl/Kconfig b/drivers/resctrl/Kconfig index c808e0470394..6c1d909dd20c 100644 --- a/drivers/resctrl/Kconfig +++ b/drivers/resctrl/Kconfig @@ -22,3 +22,5 @@ config MPAM_KUNIT_TEST If unsure, say N. =20 endif + +source "drivers/resctrl/riscv/Kconfig" diff --git a/drivers/resctrl/Makefile b/drivers/resctrl/Makefile index 898199dcf80d..48fa4d69d76f 100644 --- a/drivers/resctrl/Makefile +++ b/drivers/resctrl/Makefile @@ -2,3 +2,5 @@ obj-$(CONFIG_ARM64_MPAM_DRIVER) +=3D mpam.o mpam-y +=3D mpam_devices.o =20 ccflags-$(CONFIG_ARM64_MPAM_DRIVER_DEBUG) +=3D -DDEBUG + +obj-y +=3D riscv/ diff --git a/drivers/resctrl/riscv/Kconfig b/drivers/resctrl/riscv/Kconfig new file mode 100644 index 000000000000..d9a774fb856b --- /dev/null +++ b/drivers/resctrl/riscv/Kconfig @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0 + +config RESCTRL_RISCV_CBQRI_CACHE + bool "RISC-V QoS cache controller (CBQRI)" + default y + depends on RISCV + select RISCV_ISA_SSQOSID + help + Support RISC-V platform which implements a QoS capacity + controller according to the RISC-V Capacity and Bandwidth QoS + Register Interface (CBQRI) specification. + + If you do not care about testing RISC-V CBQRI, then choose 'N'. + +config RESCTRL_RISCV_CBQRI_BANDWIDTH + bool "RISC-V QoS bandwidth controller (CBQRI)" + default y + depends on RISCV + select RISCV_ISA_SSQOSID + help + Support RISC-V platform which implements a QoS bandwidth + controller according to the RISC-V Capacity and Bandwidth QoS + Register Interface (CBQRI) specification. + + If you do not care about testing RISC-V CBQRI, then choose 'N'. diff --git a/drivers/resctrl/riscv/Makefile b/drivers/resctrl/riscv/Makefile new file mode 100644 index 000000000000..e6937a8632d6 --- /dev/null +++ b/drivers/resctrl/riscv/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_RESCTRL_RISCV_CBQRI_CACHE) +=3D cbqri_cache.o +obj-$(CONFIG_RESCTRL_RISCV_CBQRI_BANDWIDTH) +=3D cbqri_bandwidth.o --=20 2.43.0 From nobody Sun Feb 8 15:53:51 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C836833B6E7; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tRPacVIB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EE6D4C19424; Tue, 20 Jan 2026 04:15:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1768882527; bh=08+NoXyvW3Xk6Oo5KOcsUwbtLfO2FJFdCtJSOZ1Zuws=; h=From:Date:Subject:References:In-Reply-To:To:From; b=tRPacVIB4t2VbsUGJIO2a17wCy77QjWXAqYWwS+DmywWQ4CWeiln7CdoF7NgrS5WO QctBL5aVxNJi9c4/0f0XNETkCdcbkj5n0ztIYdU9Mbr0gJzs7QpYdlecRDZg9xYIe+ uE/TOVtnIlYqqra03dzwi5VJodv6Bhdk6Ky0sTFNwhoEU3aTMPuXGRURkPrgwkh0Vp 9nJo0cOP4H6KavTf6THwQiyeigZ17k9C4fnZx4rQPy1tYmDSAmaywdZv1CxvaxyEHa zlQbXvbGESSPyLfKcu5hgSEZDfutLFOyGI/vdAMsc2gc4QoK4BZhGE+rBO3g7wG/Ae 2xdke4ZtlmOdw== From: Drew Fustini Date: Mon, 19 Jan 2026 20:14:54 -0800 Subject: [PATCH NFU RFC 17/19] riscv: dts: qemu: add dump from virt machine Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-ssqosid-cbqri-v1-17-aa2a75153832@kernel.org> References: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> In-Reply-To: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Conor Dooley , Krzysztof Kozlowski , Rob Herring , Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=17006; i=fustini@kernel.org; h=from:subject:message-id; bh=08+NoXyvW3Xk6Oo5KOcsUwbtLfO2FJFdCtJSOZ1Zuws=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTmMwY3Jj7gXmZ++ZKKxNwG3X8sSgwn27sPfVXYGlV3e JL8woNPOkpZGMS4GGTFFFk2fci7sMQr9OuC+S+2wcxhZQIZwsDFKQATmWbFyLBL4M0U39MWP16x ZByefHHb1xbd//PaHiTNPVG+SO2xi1IXw//8Lc5J4SvPOkR0/vQxNpD/lTzvQqm8REaej170hLb 6RC4A X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 [NOT FOR UPSTREAM] Dumped dtb from qemu branch based on the v4 riscv-ssqosid-cbqri series. $ qemu-system-riscv64 -version QEMU emulator version 10.2.50 (v10.2.0-208-g087112467867) Copyright (c) 2003-2025 Fabrice Bellard and the QEMU Project developers $ qemu-system-riscv64 \ -M virt \ -nographic \ -smp 8 \ -bios output/images/fw_jump.elf \ -kernel $HOME/kernel/cbqri-linux/arch/riscv/boot/Image \ -append "root=3D/dev/vda ro" \ -drive file=3Doutput/images/rootfs.ext2,format=3Draw,id=3Dhd0 \ -device virtio-blk-device,drive=3Dhd0 \ -machine dumpdtb=3Dqemu.dtb Link: https://lore.kernel.org/all/20260105-riscv-ssqosid-cbqri-v4-0-9ad7671= dde78@kernel.org/ Link: https://github.com/tt-fustini/qemu/tree/b4/riscv-ssqosid-cbqri Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts | 399 +++++++++++++++++++++++= ++++ 1 file changed, 399 insertions(+) diff --git a/arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts b/arch/riscv/boot= /dts/qemu/qemu-virt-cbqri.dts new file mode 100644 index 000000000000..4c6257bec42d --- /dev/null +++ b/arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts @@ -0,0 +1,399 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/dts-v1/; + +/ { + #address-cells =3D <0x02>; + #size-cells =3D <0x02>; + compatible =3D "riscv-virtio"; + model =3D "riscv-virtio,qemu"; + + poweroff { + value =3D <0x5555>; + offset =3D <0x00>; + regmap =3D <0x12>; + compatible =3D "syscon-poweroff"; + }; + + reboot { + value =3D <0x7777>; + offset =3D <0x00>; + regmap =3D <0x12>; + compatible =3D "syscon-reboot"; + }; + + platform-bus@4000000 { + interrupt-parent =3D <0x11>; + ranges =3D <0x00 0x00 0x4000000 0x2000000>; + #address-cells =3D <0x01>; + #size-cells =3D <0x01>; + compatible =3D "qemu,platform\0simple-bus"; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x00 0x80000000 0x00 0x8000000>; + }; + + cpus { + #address-cells =3D <0x01>; + #size-cells =3D <0x00>; + timebase-frequency =3D <0x989680>; + + cpu@0 { + phandle =3D <0x0f>; + device_type =3D "cpu"; + reg =3D <0x00>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cbop-block-size =3D <0x40>; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa-extensions =3D "i\0m\0a\0f\0d\0c\0h\0zic64b\0zicbom\0zicbop\0= zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicntr\0zicsr\0zifencei\0zihint= ntl\0zihintpause\0zihpm\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zca\0zcd= \0zba\0zbb\0zbc\0zbs\0sdtrig\0shcounterenw\0shgatpa\0shtvala\0shvsatpa\0shv= stvala\0shvstvecd\0ssccptr\0sscounterenw\0ssqosid\0ssstrict\0sstc\0sstvala\= 0sstvecd\0ssu64xl\0svadu\0svvptc"; + riscv,isa-base =3D "rv64i"; + riscv,isa =3D "rv64imafdch_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_= zicclsm_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zmmul_za6= 4rs_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_sdtrig_shcounterenw_shga= tpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscounterenw_ssqosid_ssstr= ict_sstc_sstvala_sstvecd_ssu64xl_svadu_svvptc"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x10>; + }; + }; + + cpu@1 { + phandle =3D <0x0d>; + device_type =3D "cpu"; + reg =3D <0x01>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cbop-block-size =3D <0x40>; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa-extensions =3D "i\0m\0a\0f\0d\0c\0h\0zic64b\0zicbom\0zicbop\0= zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicntr\0zicsr\0zifencei\0zihint= ntl\0zihintpause\0zihpm\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zca\0zcd= \0zba\0zbb\0zbc\0zbs\0sdtrig\0shcounterenw\0shgatpa\0shtvala\0shvsatpa\0shv= stvala\0shvstvecd\0ssccptr\0sscounterenw\0ssqosid\0ssstrict\0sstc\0sstvala\= 0sstvecd\0ssu64xl\0svadu\0svvptc"; + riscv,isa-base =3D "rv64i"; + riscv,isa =3D "rv64imafdch_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_= zicclsm_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zmmul_za6= 4rs_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_sdtrig_shcounterenw_shga= tpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscounterenw_ssqosid_ssstr= ict_sstc_sstvala_sstvecd_ssu64xl_svadu_svvptc"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x0e>; + }; + }; + + cpu@2 { + phandle =3D <0x0b>; + device_type =3D "cpu"; + reg =3D <0x02>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cbop-block-size =3D <0x40>; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa-extensions =3D "i\0m\0a\0f\0d\0c\0h\0zic64b\0zicbom\0zicbop\0= zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicntr\0zicsr\0zifencei\0zihint= ntl\0zihintpause\0zihpm\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zca\0zcd= \0zba\0zbb\0zbc\0zbs\0sdtrig\0shcounterenw\0shgatpa\0shtvala\0shvsatpa\0shv= stvala\0shvstvecd\0ssccptr\0sscounterenw\0ssqosid\0ssstrict\0sstc\0sstvala\= 0sstvecd\0ssu64xl\0svadu\0svvptc"; + riscv,isa-base =3D "rv64i"; + riscv,isa =3D "rv64imafdch_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_= zicclsm_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zmmul_za6= 4rs_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_sdtrig_shcounterenw_shga= tpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscounterenw_ssqosid_ssstr= ict_sstc_sstvala_sstvecd_ssu64xl_svadu_svvptc"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x0c>; + }; + }; + + cpu@3 { + phandle =3D <0x09>; + device_type =3D "cpu"; + reg =3D <0x03>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cbop-block-size =3D <0x40>; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa-extensions =3D "i\0m\0a\0f\0d\0c\0h\0zic64b\0zicbom\0zicbop\0= zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicntr\0zicsr\0zifencei\0zihint= ntl\0zihintpause\0zihpm\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zca\0zcd= \0zba\0zbb\0zbc\0zbs\0sdtrig\0shcounterenw\0shgatpa\0shtvala\0shvsatpa\0shv= stvala\0shvstvecd\0ssccptr\0sscounterenw\0ssqosid\0ssstrict\0sstc\0sstvala\= 0sstvecd\0ssu64xl\0svadu\0svvptc"; + riscv,isa-base =3D "rv64i"; + riscv,isa =3D "rv64imafdch_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_= zicclsm_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zmmul_za6= 4rs_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_sdtrig_shcounterenw_shga= tpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscounterenw_ssqosid_ssstr= ict_sstc_sstvala_sstvecd_ssu64xl_svadu_svvptc"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x0a>; + }; + }; + + cpu@4 { + phandle =3D <0x07>; + device_type =3D "cpu"; + reg =3D <0x04>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cbop-block-size =3D <0x40>; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa-extensions =3D "i\0m\0a\0f\0d\0c\0h\0zic64b\0zicbom\0zicbop\0= zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicntr\0zicsr\0zifencei\0zihint= ntl\0zihintpause\0zihpm\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zca\0zcd= \0zba\0zbb\0zbc\0zbs\0sdtrig\0shcounterenw\0shgatpa\0shtvala\0shvsatpa\0shv= stvala\0shvstvecd\0ssccptr\0sscounterenw\0ssqosid\0ssstrict\0sstc\0sstvala\= 0sstvecd\0ssu64xl\0svadu\0svvptc"; + riscv,isa-base =3D "rv64i"; + riscv,isa =3D "rv64imafdch_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_= zicclsm_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zmmul_za6= 4rs_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_sdtrig_shcounterenw_shga= tpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscounterenw_ssqosid_ssstr= ict_sstc_sstvala_sstvecd_ssu64xl_svadu_svvptc"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x08>; + }; + }; + + cpu@5 { + phandle =3D <0x05>; + device_type =3D "cpu"; + reg =3D <0x05>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cbop-block-size =3D <0x40>; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa-extensions =3D "i\0m\0a\0f\0d\0c\0h\0zic64b\0zicbom\0zicbop\0= zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicntr\0zicsr\0zifencei\0zihint= ntl\0zihintpause\0zihpm\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zca\0zcd= \0zba\0zbb\0zbc\0zbs\0sdtrig\0shcounterenw\0shgatpa\0shtvala\0shvsatpa\0shv= stvala\0shvstvecd\0ssccptr\0sscounterenw\0ssqosid\0ssstrict\0sstc\0sstvala\= 0sstvecd\0ssu64xl\0svadu\0svvptc"; + riscv,isa-base =3D "rv64i"; + riscv,isa =3D "rv64imafdch_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_= zicclsm_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zmmul_za6= 4rs_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_sdtrig_shcounterenw_shga= tpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscounterenw_ssqosid_ssstr= ict_sstc_sstvala_sstvecd_ssu64xl_svadu_svvptc"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x06>; + }; + }; + + cpu@6 { + phandle =3D <0x03>; + device_type =3D "cpu"; + reg =3D <0x06>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cbop-block-size =3D <0x40>; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa-extensions =3D "i\0m\0a\0f\0d\0c\0h\0zic64b\0zicbom\0zicbop\0= zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicntr\0zicsr\0zifencei\0zihint= ntl\0zihintpause\0zihpm\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zca\0zcd= \0zba\0zbb\0zbc\0zbs\0sdtrig\0shcounterenw\0shgatpa\0shtvala\0shvsatpa\0shv= stvala\0shvstvecd\0ssccptr\0sscounterenw\0ssqosid\0ssstrict\0sstc\0sstvala\= 0sstvecd\0ssu64xl\0svadu\0svvptc"; + riscv,isa-base =3D "rv64i"; + riscv,isa =3D "rv64imafdch_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_= zicclsm_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zmmul_za6= 4rs_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_sdtrig_shcounterenw_shga= tpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscounterenw_ssqosid_ssstr= ict_sstc_sstvala_sstvecd_ssu64xl_svadu_svvptc"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x04>; + }; + }; + + cpu@7 { + phandle =3D <0x01>; + device_type =3D "cpu"; + reg =3D <0x07>; + status =3D "okay"; + compatible =3D "riscv"; + riscv,cbop-block-size =3D <0x40>; + riscv,cboz-block-size =3D <0x40>; + riscv,cbom-block-size =3D <0x40>; + riscv,isa-extensions =3D "i\0m\0a\0f\0d\0c\0h\0zic64b\0zicbom\0zicbop\0= zicboz\0ziccamoa\0ziccif\0zicclsm\0ziccrse\0zicntr\0zicsr\0zifencei\0zihint= ntl\0zihintpause\0zihpm\0zmmul\0za64rs\0zaamo\0zalrsc\0zawrs\0zfa\0zca\0zcd= \0zba\0zbb\0zbc\0zbs\0sdtrig\0shcounterenw\0shgatpa\0shtvala\0shvsatpa\0shv= stvala\0shvstvecd\0ssccptr\0sscounterenw\0ssqosid\0ssstrict\0sstc\0sstvala\= 0sstvecd\0ssu64xl\0svadu\0svvptc"; + riscv,isa-base =3D "rv64i"; + riscv,isa =3D "rv64imafdch_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_= zicclsm_ziccrse_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zmmul_za6= 4rs_zaamo_zalrsc_zawrs_zfa_zca_zcd_zba_zbb_zbc_zbs_sdtrig_shcounterenw_shga= tpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscounterenw_ssqosid_ssstr= ict_sstc_sstvala_sstvecd_ssu64xl_svadu_svvptc"; + mmu-type =3D "riscv,sv57"; + + interrupt-controller { + #interrupt-cells =3D <0x01>; + interrupt-controller; + compatible =3D "riscv,cpu-intc"; + phandle =3D <0x02>; + }; + }; + + cpu-map { + + cluster0 { + + core0 { + cpu =3D <0x0f>; + }; + + core1 { + cpu =3D <0x0d>; + }; + + core2 { + cpu =3D <0x0b>; + }; + + core3 { + cpu =3D <0x09>; + }; + + core4 { + cpu =3D <0x07>; + }; + + core5 { + cpu =3D <0x05>; + }; + + core6 { + cpu =3D <0x03>; + }; + + core7 { + cpu =3D <0x01>; + }; + }; + }; + }; + + pmu { + riscv,event-to-mhpmcounters =3D <0x01 0x01 0x7fff9 0x02 0x02 0x7fffc 0x1= 0019 0x10019 0x7fff8 0x1001b 0x1001b 0x7fff8 0x10021 0x10021 0x7fff8>; + compatible =3D "riscv,pmu"; + }; + + fw-cfg@10100000 { + dma-coherent; + reg =3D <0x00 0x10100000 0x00 0x18>; + compatible =3D "qemu,fw-cfg-mmio"; + }; + + flash@20000000 { + bank-width =3D <0x04>; + reg =3D <0x00 0x20000000 0x00 0x2000000 0x00 0x22000000 0x00 0x2000000>; + compatible =3D "cfi-flash"; + }; + + aliases { + serial0 =3D "/soc/serial@10000000"; + }; + + chosen { + bootargs =3D "root=3D/dev/vda ro loglevel=3D8"; + stdout-path =3D "/soc/serial@10000000"; + rng-seed =3D <0x56a2904d 0x281bbaec 0x55c405c1 0x602a34cd 0x3490edca 0x3= ed9ed5d 0xa98e5ed6 0xa663e102>; + }; + + soc { + #address-cells =3D <0x02>; + #size-cells =3D <0x02>; + compatible =3D "simple-bus"; + ranges; + + rtc@101000 { + interrupts =3D <0x0b>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x101000 0x00 0x1000>; + compatible =3D "google,goldfish-rtc"; + }; + + serial@10000000 { + interrupts =3D <0x0a>; + interrupt-parent =3D <0x11>; + clock-frequency =3D "\08@"; + reg =3D <0x00 0x10000000 0x00 0x100>; + compatible =3D "ns16550a"; + }; + + test@100000 { + phandle =3D <0x12>; + reg =3D <0x00 0x100000 0x00 0x1000>; + compatible =3D "sifive,test1\0sifive,test0\0syscon"; + }; + + virtio_mmio@10008000 { + interrupts =3D <0x08>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10008000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + virtio_mmio@10007000 { + interrupts =3D <0x07>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10007000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + virtio_mmio@10006000 { + interrupts =3D <0x06>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10006000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + virtio_mmio@10005000 { + interrupts =3D <0x05>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10005000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + virtio_mmio@10004000 { + interrupts =3D <0x04>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10004000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + virtio_mmio@10003000 { + interrupts =3D <0x03>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10003000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + virtio_mmio@10002000 { + interrupts =3D <0x02>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10002000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + virtio_mmio@10001000 { + interrupts =3D <0x01>; + interrupt-parent =3D <0x11>; + reg =3D <0x00 0x10001000 0x00 0x1000>; + compatible =3D "virtio,mmio"; + }; + + plic@c000000 { + phandle =3D <0x11>; + riscv,ndev =3D <0x5f>; + reg =3D <0x00 0xc000000 0x00 0x600000>; + interrupts-extended =3D <0x10 0x0b 0x10 0x09 0x0e 0x0b 0x0e 0x09 0x0c 0= x0b 0x0c 0x09 0x0a 0x0b 0x0a 0x09 0x08 0x0b 0x08 0x09 0x06 0x0b 0x06 0x09 0= x04 0x0b 0x04 0x09 0x02 0x0b 0x02 0x09>; + interrupt-controller; + compatible =3D "sifive,plic-1.0.0\0riscv,plic0"; + #address-cells =3D <0x00>; + #interrupt-cells =3D <0x01>; + }; + + clint@2000000 { + interrupts-extended =3D <0x10 0x03 0x10 0x07 0x0e 0x03 0x0e 0x07 0x0c 0= x03 0x0c 0x07 0x0a 0x03 0x0a 0x07 0x08 0x03 0x08 0x07 0x06 0x03 0x06 0x07 0= x04 0x03 0x04 0x07 0x02 0x03 0x02 0x07>; + reg =3D <0x00 0x2000000 0x00 0x10000>; + compatible =3D "sifive,clint0\0riscv,clint0"; + }; + + pci@30000000 { + interrupt-map-mask =3D <0x1800 0x00 0x00 0x07>; + interrupt-map =3D <0x00 0x00 0x00 0x01 0x11 0x20 0x00 0x00 0x00 0x02 0x= 11 0x21 0x00 0x00 0x00 0x03 0x11 0x22 0x00 0x00 0x00 0x04 0x11 0x23 0x800 0= x00 0x00 0x01 0x11 0x21 0x800 0x00 0x00 0x02 0x11 0x22 0x800 0x00 0x00 0x03= 0x11 0x23 0x800 0x00 0x00 0x04 0x11 0x20 0x1000 0x00 0x00 0x01 0x11 0x22 0= x1000 0x00 0x00 0x02 0x11 0x23 0x1000 0x00 0x00 0x03 0x11 0x20 0x1000 0x00 = 0x00 0x04 0x11 0x21 0x1800 0x00 0x00 0x01 0x11 0x23 0x1800 0x00 0x00 0x02 0= x11 0x20 0x1800 0x00 0x00 0x03 0x11 0x21 0x1800 0x00 0x00 0x04 0x11 0x22>; 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b=q9O4T3Iwp5YU9aTtmeJpgqm4DzAdGefVfEQ9vaci4fasVdHhxCtxtl06PwRBg9ERG h4nBCUYcBujNBC5VaUWllNPthZII8W19hZEeJqcnU3cXhADKEIYf43qj2Zw5g6iZQT 4IxMq95bY1ARP4MJGC/HikCdl+ip+UlakSpBKhDw0yU/aSRBfRzW0ME6L770zJ+EmK KL8Se3YCpBA+/ETMQAyiACgFGsljmdcS9hlV3ygaw3oBdg8ecLy6/zjUjYxezXL+Tq GiVchXxe9h9bw8OO0rmUuYaZma252RfrfXycAmNh4t+/ryn8mJXFugVqp8kRktGuAH o+5SG6ii9Ve1Q== From: Drew Fustini Date: Mon, 19 Jan 2026 20:14:55 -0800 Subject: [PATCH NFU RFC 18/19] riscv: dts: qemu: add CBQRI controller nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-ssqosid-cbqri-v1-18-aa2a75153832@kernel.org> References: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> In-Reply-To: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Conor Dooley , Krzysztof Kozlowski , Rob Herring , Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2591; i=fustini@kernel.org; h=from:subject:message-id; bh=udCB56ewUuBczR6ctM7up8XACViyJiWY/ibyZC1jejs=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTmMwZb8NY27P2ru04ycsMpxgV11wKXXXzt/+/TjxdWZ TE1O+tXd5SyMIhxMciKKbJs+pB3YYlX6NcF819sg5nDygQyhIGLUwAmknWb4X9CjeiBp9XGT/dk pz9Kmhp1gzl0e4QFn1Tk+51p269ymuoy/Ga5duGYup/rg52s59Ycknr2elF+qdEf8z9LK+1r/gj Lp/MBAA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 [NOT FOR UPSTREAM] Add nodes to for CBQRI-capable cache and bandwidth controllers. Link: https://github.com/tt-fustini/qemu/tree/b4/riscv-ssqosid-cbqri Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts | 59 ++++++++++++++++++++++++= ++++ 1 file changed, 59 insertions(+) diff --git a/arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts b/arch/riscv/boot= /dts/qemu/qemu-virt-cbqri.dts index 4c6257bec42d..9f65de65f758 100644 --- a/arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts +++ b/arch/riscv/boot/dts/qemu/qemu-virt-cbqri.dts @@ -395,5 +395,64 @@ pci@30000000 { #interrupt-cells =3D <0x01>; #address-cells =3D <0x03>; }; + + cluster0_l2: controller@4820000 { + compatible =3D "riscv,cbqri-cache"; + reg =3D <0x0 0x4820000 0x0 0x1000>; /* 4KB at 0x04820000 */ + cache-unified; + cache-line-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <1000>; + cache-size =3D <768000>; /* 750 KiB */ + next-level-cache =3D <&shared_llc>; + riscv,cbqri-rcid =3D <64>; + riscv,cbqri-mcid =3D <256>; + }; + + cluster1_l2: controller@4821000 { + compatible =3D "riscv,cbqri-cache"; + reg =3D <0x0 0x4821000 0x0 0x1000>; /* 4KB at 0x04821000 */ + cache-unified; + cache-line-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <1000>; + cache-size =3D <768000>; /* 750 KiB */ + next-level-cache =3D <&shared_llc>; + riscv,cbqri-rcid =3D <64>; + riscv,cbqri-mcid =3D <256>; + }; + + shared_llc: controller@482b000 { + compatible =3D "riscv,cbqri-cache"; + reg =3D <0x0 0x482b000 0x0 0x1000>; /* 4KB at 0x0482B000 */ + cache-unified; + cache-line-size =3D <64>; + cache-level =3D <3>; + cache-sets =3D <4096>; + cache-size =3D <3145728>; /* 3 MiB */ + riscv,cbqri-rcid =3D <64>; + riscv,cbqri-mcid =3D <256>; + }; + + mem0: controller@4828000 { + compatible =3D "riscv,cbqri-bandwidth"; + reg =3D <0x0 0x4828000 0x0 0x1000>; /* 4KB at 0x04828000 */ + riscv,cbqri-rcid =3D <64>; + riscv,cbqri-mcid =3D <256>; + }; + + mem1: controller@4829000 { + compatible =3D "riscv,cbqri-bandwidth"; + reg =3D <0x0 0x4829000 0x0 0x1000>; /* 4KB at 0x04829000 */ + riscv,cbqri-rcid =3D <64>; + riscv,cbqri-mcid =3D <256>; + }; + + mem2: controller@482a000 { + compatible =3D "riscv,cbqri-bandwidth"; + reg =3D <0x0 0x482a000 0x0 0x1000>; /* 4KB at 0x0482A000 */ + riscv,cbqri-rcid =3D <64>; + riscv,cbqri-mcid =3D <256>; + }; }; }; --=20 2.43.0 From nobody Sun Feb 8 15:53:51 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6E1A33F394; Tue, 20 Jan 2026 04:15:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768882528; cv=none; b=otwLAGRBWFUOeAL4unW87IiO2mDkvZE/nF6Q154wSBmHYPWIZLa+FlIwOzLNXghyKnlkkbeEbjcVgdJ0Mvh3EO1vfmB4soRj5TU2wcCll5be8F2NQZ40Y3yP5VuV0s1+aciApOVRZ3lQQiGAt8kHlwsg7bEgaV0VRgDwAYDLoNk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768882528; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-ssqosid-cbqri-v1-19-aa2a75153832@kernel.org> References: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> In-Reply-To: <20260119-ssqosid-cbqri-v1-0-aa2a75153832@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Conor Dooley , Krzysztof Kozlowski , Rob Herring , Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1198; i=fustini@kernel.org; h=from:subject:message-id; bh=vOomva/hR4ZN3wCiusAiE7WWWgswq+7ShOke7S7qUXU=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTmMwZb9fXLx8458y/0Pfe5tgalmf87g9JnbxHbYqs6L XJ21GyFjlIWBjEuBlkxRZZNH/IuLPEK/bpg/ottMHNYmUCGMHBxCsBEbqxl+O/57GxiscP8Tb3V knN/5t+90yOx1HDzHp+elU+MXJZnRSYwMnzd8TT9wTaPd2YLMy/lvH8bdczy/q5F/ZPdHptcYE8 9GMUCAA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 [NOT FOR UPSTREAM] Build DTB based on Qemu generated DTS when CONFIG_ARCH_VIRT is enabled. The resulting dtb will be consumed by qemu-system-riscv64. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/qemu/Makefile | 3 +++ 2 files changed, 4 insertions(+) diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index 69d8751fb17c..edd25cf000cc 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -5,6 +5,7 @@ subdir-y +=3D anlogic subdir-y +=3D canaan subdir-y +=3D eswin subdir-y +=3D microchip +subdir-y +=3D qemu subdir-y +=3D renesas subdir-y +=3D sifive subdir-y +=3D sophgo diff --git a/arch/riscv/boot/dts/qemu/Makefile b/arch/riscv/boot/dts/qemu/M= akefile new file mode 100644 index 000000000000..a6b06ef1a75a --- /dev/null +++ b/arch/riscv/boot/dts/qemu/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_VIRT) +=3D qemu-virt-cbqri.dtb +obj-$(CONFIG_BUILTIN_DTB) +=3D $(addsuffix .o, $(dtb-y)) --=20 2.43.0