From nobody Mon Feb 9 19:27:03 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86E6E37F74E; Mon, 19 Jan 2026 15:06:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768835197; cv=none; b=FoldHQS+1QYhC0iY6uqJhr9wqi7kaq+x7T/n/xk9eMk8Q2E0E2n+//aEWPBj9/wefG/6eRbGjMlNaGf5wS4ko2GWrANseTH1pr+Tl2QjueyEOfK1oR8U+As6ZpdNWnbkctSHYw+yFLJy3tHnNt/4emGPPGOOd6p3AO2IyCkavcM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768835197; c=relaxed/simple; bh=pasjO94/OvVqP2mPiNV/u3WQQo2v2cEH6cEjcMrCy14=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=uqxLYeZ8H1kXsetiSjGUD72LYxyTJ2947O8a73pQ7OHMZAj4fyHQxLfb+QNyBUCAshpcHThbbHVmnsB4tnRq48q1DQx22p8ciacu3XVCmYfdiDoS9vFUwQtzKBlA5ERgcAh6mbTciVpXE9m9oskvov2DpJPyYnrH956hXDYEZP4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=ZNlyYa1v; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="ZNlyYa1v" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1768835195; x=1800371195; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=pasjO94/OvVqP2mPiNV/u3WQQo2v2cEH6cEjcMrCy14=; b=ZNlyYa1vodH89XrPMgluofUbOboDANdjLTjRlODmqOgQ2Rf8zjmsG81O jSQcwi+Clrj6Rh1v6HFE8pYZ+r151touLyRBwQSw6pWjnvKO1emdLfB7x i/zoZDOibPZK62vJTOvXhi9QhoJ+/cdmkHY4vgOhVidkNxVEhga5p+6cw 9mkYrVgrywI+AOSNOes4VEf3yILxc4nBEyS4DPVkc0JxTtEbmPECOuqg7 /IUaZUSgsVaiw1xJk/3jr9VOfSAfrAnOvgfoEJtzJrwnpgkYVW2jUCbjd 704wai5pE+SP1biBEj96TwgXrn4u6iKCOO6JjQyAR67I/imaW0kKyi4Yw g==; X-CSE-ConnectionGUID: a45eXAL0QQeJgaK8l1tQlQ== X-CSE-MsgGUID: NdcRYvZHRk6Xu3z84wF1iQ== X-IronPort-AV: E=Sophos;i="6.21,238,1763449200"; d="scan'208";a="219391019" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 19 Jan 2026 08:06:34 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Mon, 19 Jan 2026 08:06:30 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 19 Jan 2026 08:06:27 -0700 From: =?utf-8?q?Jens_Emil_Schulz_=C3=98stergaard?= Date: Mon, 19 Jan 2026 16:06:09 +0100 Subject: [PATCH 1/3] dt-bindings: pinctrl: ocelot: Add LAN9645x SoC support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260119-pinctrl_ocelot_extend_support_for_lan9645x-v1-1-1228155ed0ee@microchip.com> References: <20260119-pinctrl_ocelot_extend_support_for_lan9645x-v1-0-1228155ed0ee@microchip.com> In-Reply-To: <20260119-pinctrl_ocelot_extend_support_for_lan9645x-v1-0-1228155ed0ee@microchip.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandre Belloni , Lars Povlsen , Bartosz Golaszewski , "Steen Hegelund" , Daniel Machon CC: , , , =?utf-8?q?Jens_Emil_Schulz_=C3=98stergaard?= X-Mailer: b4 0.15-dev Add documentation for the compatibles designated for the following SKUs in the LAN9645x family: lan96455f lan96457f lan96459f with fallback a compatible for the smallest 5-ported SKUs lan96455f. Reviewed-by: Steen Hegelund Reviewed-by: Daniel Machon Signed-off-by: Jens Emil Schulz =C3=98stergaard Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 6 +++= +++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.= yaml b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml index 31bc30a81752..930955caacd1 100644 --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml @@ -14,6 +14,7 @@ properties: compatible: oneOf: - enum: + - microchip,lan96455f-pinctrl - microchip,lan966x-pinctrl - microchip,lan9691-pinctrl - microchip,sparx5-pinctrl @@ -30,6 +31,11 @@ properties: - microchip,lan9693-pinctrl - microchip,lan9692-pinctrl - const: microchip,lan9691-pinctrl + - items: + - enum: + - microchip,lan96457f-pinctrl + - microchip,lan96459f-pinctrl + - const: microchip,lan96455f-pinctrl =20 reg: items: --=20 2.34.1 From nobody Mon Feb 9 19:27:03 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B70734FF59; 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X-CSE-ConnectionGUID: 1bDZ6aHwSTKUGtJlZF+cag== X-CSE-MsgGUID: nz/uRV0LRhGrJ/YBegxkCw== X-IronPort-AV: E=Sophos;i="6.21,238,1763449200"; d="scan'208";a="51363225" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 19 Jan 2026 08:06:44 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Mon, 19 Jan 2026 08:06:32 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 19 Jan 2026 08:06:30 -0700 From: =?utf-8?q?Jens_Emil_Schulz_=C3=98stergaard?= Date: Mon, 19 Jan 2026 16:06:10 +0100 Subject: [PATCH 2/3] pinctrl: ocelot: Update alt mode reg addr calculation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260119-pinctrl_ocelot_extend_support_for_lan9645x-v1-2-1228155ed0ee@microchip.com> References: <20260119-pinctrl_ocelot_extend_support_for_lan9645x-v1-0-1228155ed0ee@microchip.com> In-Reply-To: <20260119-pinctrl_ocelot_extend_support_for_lan9645x-v1-0-1228155ed0ee@microchip.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandre Belloni , Lars Povlsen , Bartosz Golaszewski , "Steen Hegelund" , Daniel Machon CC: , , , =?utf-8?q?Jens_Emil_Schulz_=C3=98stergaard?= X-Mailer: b4 0.15-dev Lan9645x is the first chip supported by this driver where the pin stride is different from the alt mode stride. With 51 pins and up to 7 alt modes, we have stride =3D 2 and alt_mode_stride =3D 3. The current REG_ALT macro has the implicit assumption that these numbers are equal, so it does not work for lan9645x. The pin stride is the 'stride' variable in the driver. It is the size of certain register groups which depends on the number of pins supported by the device. Generally we have stride =3D DIV_ROUND_UP(npins, 32). E.g: GPIO_OUT_SET0 GPIO_OUT_SET1 ... GPIO_OUT_SETn The alt mode registers are further replicated by the number of bits necessary to represent the alt mode. For instance if we need 3 bits to represent the alt mode: GPIO_ALT0[0-2] GPIO_ALT1[0-2] To set alt mode 3 on pin 12, it is necessary to perform writes GPIO_ALT0[0] |=3D BIT(12) GPIO_ALT0[1] |=3D BIT(12) GPIO_ALT0[2] &=3D ~BIT(12) The stride and alt mode stride are used by the REG_ALT macro to calculate the alt mode register address for a given pin. This adds the option to specify n_alt_modes, which is used to set info->altm_stride. The default value is info->stride, to make sure existing devices are unaffected by this change. Reviewed-by: Steen Hegelund Reviewed-by: Daniel Machon Signed-off-by: Jens Emil Schulz =C3=98stergaard Reviewed-by: Alexandre Belloni --- drivers/pinctrl/pinctrl-ocelot.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-oce= lot.c index 70da3f37567a..4db0439ca8c4 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -358,12 +358,14 @@ struct ocelot_pinctrl { const struct ocelot_pincfg_data *pincfg_data; struct ocelot_pmx_func func[FUNC_MAX]; u8 stride; + u8 altm_stride; struct workqueue_struct *wq; }; =20 struct ocelot_match_data { struct pinctrl_desc desc; struct ocelot_pincfg_data pincfg_data; + unsigned int n_alt_modes; }; =20 struct ocelot_irq_work { @@ -1362,7 +1364,7 @@ static int ocelot_pin_function_idx(struct ocelot_pinc= trl *info, return -1; } =20 -#define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((m= sb) + ((info)->stride * ((p) / 32)))) +#define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((m= sb) + ((info)->altm_stride * ((p) / 32)))) =20 static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, unsigned int group) @@ -2294,6 +2296,9 @@ static int ocelot_pinctrl_probe(struct platform_devic= e *pdev) reset_control_reset(reset); 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Mon, 19 Jan 2026 08:06:35 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 19 Jan 2026 08:06:32 -0700 From: =?utf-8?q?Jens_Emil_Schulz_=C3=98stergaard?= Date: Mon, 19 Jan 2026 16:06:11 +0100 Subject: [PATCH 3/3] pinctrl: ocelot: Extend support for lan9645xf family Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260119-pinctrl_ocelot_extend_support_for_lan9645x-v1-3-1228155ed0ee@microchip.com> References: <20260119-pinctrl_ocelot_extend_support_for_lan9645x-v1-0-1228155ed0ee@microchip.com> In-Reply-To: <20260119-pinctrl_ocelot_extend_support_for_lan9645x-v1-0-1228155ed0ee@microchip.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandre Belloni , Lars Povlsen , Bartosz Golaszewski , "Steen Hegelund" , Daniel Machon CC: , , , =?utf-8?q?Jens_Emil_Schulz_=C3=98stergaard?= X-Mailer: b4 0.15-dev Extend pinctrl-ocelot driver to support the lan9645xf chip family. Reviewed-by: Steen Hegelund Reviewed-by: Daniel Machon Signed-off-by: Jens Emil Schulz =C3=98stergaard --- drivers/pinctrl/pinctrl-ocelot.c | 177 +++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 177 insertions(+) diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-oce= lot.c index 4db0439ca8c4..6ea9544ddd06 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -97,6 +97,8 @@ enum { FUNC_FC_SHRD20, FUNC_FUSA, FUNC_GPIO, + FUNC_I2C, + FUNC_I2C_Sa, FUNC_IB_TRG_a, FUNC_IB_TRG_b, FUNC_IB_TRG_c, @@ -112,9 +114,11 @@ enum { FUNC_IRQ1, FUNC_IRQ1_IN, FUNC_IRQ1_OUT, + FUNC_IRQ2, FUNC_IRQ3, FUNC_IRQ4, FUNC_EXT_IRQ, + FUNC_MACLED, FUNC_MIIM, FUNC_MIIM_a, FUNC_MIIM_b, @@ -126,6 +130,7 @@ enum { FUNC_OB_TRG_a, FUNC_OB_TRG_b, FUNC_PHY_LED, + FUNC_PHY_DBG, FUNC_PCI_WAKE, FUNC_MD, FUNC_PCIE_PERST, @@ -156,10 +161,12 @@ enum { FUNC_SG0, FUNC_SG1, FUNC_SG2, + FUNC_SPI, FUNC_SGPIO_a, FUNC_SGPIO_b, FUNC_SI, FUNC_SI2, + FUNC_SI_Sa, FUNC_SYNCE, FUNC_TACHO, FUNC_TACHO_a, @@ -188,6 +195,7 @@ enum { FUNC_EMMC_SD, FUNC_REF_CLK, FUNC_RCVRD_CLK, + FUNC_RGMII, FUNC_MAX }; =20 @@ -237,6 +245,8 @@ static const char *const ocelot_function_names[] =3D { [FUNC_FC_SHRD20] =3D "fc_shrd20", [FUNC_FUSA] =3D "fusa", [FUNC_GPIO] =3D "gpio", + [FUNC_I2C] =3D "i2c", + [FUNC_I2C_Sa] =3D "i2c_slave_a", [FUNC_IB_TRG_a] =3D "ib_trig_a", [FUNC_IB_TRG_b] =3D "ib_trig_b", [FUNC_IB_TRG_c] =3D "ib_trig_c", @@ -252,9 +262,11 @@ static const char *const ocelot_function_names[] =3D { [FUNC_IRQ1] =3D "irq1", [FUNC_IRQ1_IN] =3D "irq1_in", [FUNC_IRQ1_OUT] =3D "irq1_out", + [FUNC_IRQ2] =3D "irq2", [FUNC_IRQ3] =3D "irq3", [FUNC_IRQ4] =3D "irq4", [FUNC_EXT_IRQ] =3D "ext_irq", + [FUNC_MACLED] =3D "mac_led", [FUNC_MIIM] =3D "miim", [FUNC_MIIM_a] =3D "miim_a", [FUNC_MIIM_b] =3D "miim_b", @@ -263,6 +275,7 @@ static const char *const ocelot_function_names[] =3D { [FUNC_MIIM_Sb] =3D "miim_slave_b", [FUNC_MIIM_IRQ] =3D "miim_irq", [FUNC_PHY_LED] =3D "phy_led", + [FUNC_PHY_DBG] =3D "phy_dbg", [FUNC_PCI_WAKE] =3D "pci_wake", [FUNC_PCIE_PERST] =3D "pcie_perst", [FUNC_MD] =3D "md", @@ -300,6 +313,8 @@ static const char *const ocelot_function_names[] =3D { [FUNC_SGPIO_b] =3D "sgpio_b", [FUNC_SI] =3D "si", [FUNC_SI2] =3D "si2", + [FUNC_SI_Sa] =3D "si_slave_a", + [FUNC_SPI] =3D "spi", [FUNC_SYNCE] =3D "synce", [FUNC_TACHO] =3D "tacho", [FUNC_TACHO_a] =3D "tacho_a", @@ -328,6 +343,7 @@ static const char *const ocelot_function_names[] =3D { [FUNC_EMMC_SD] =3D "emmc_sd", [FUNC_REF_CLK] =3D "ref_clk", [FUNC_RCVRD_CLK] =3D "rcvrd_clk", + [FUNC_RGMII] =3D "rgmii", }; =20 struct ocelot_pmx_func { @@ -1323,6 +1339,132 @@ static const struct pinctrl_pin_desc lan969x_pins[]= =3D { LAN969X_PIN(66), }; =20 +#define LAN9645X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \ +static struct ocelot_pin_caps lan9645x_pin_##p =3D { \ + .pin =3D p, \ + .functions =3D { \ + FUNC_##f0, FUNC_##f1, FUNC_##f2, \ + FUNC_##f3 \ + }, \ + .a_functions =3D { \ + FUNC_##f4, FUNC_##f5, FUNC_##f6, \ + FUNC_##f7 \ + }, \ +} + +/* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 F= UNC5 FUNC6 FUNC7 */ +LAN9645X_P(0, GPIO, SPI, SI_Sa, I2C_Sa, MIIM_Sa, = UART, MIIM, PHY_DBG); +LAN9645X_P(1, GPIO, SPI, SI_Sa, I2C_Sa, MIIM_Sa, = UART, MIIM, PHY_DBG); +LAN9645X_P(2, GPIO, SPI, SI_Sa, I2C, NONE, = NONE, NONE, PHY_DBG); +LAN9645X_P(3, GPIO, SPI, SI_Sa, I2C, MIIM_Sa, = NONE, NONE, PHY_DBG); +LAN9645X_P(4, GPIO, RGMII, TWI_SCL_M, I2C, NONE, = NONE, SI_Sa, PHY_DBG); +LAN9645X_P(5, GPIO, RGMII, TWI_SCL_M, I2C, NONE, = NONE, SI_Sa, PHY_DBG); +LAN9645X_P(6, GPIO, RGMII, TWI_SCL_M, NONE, NONE, = NONE, SI_Sa, PHY_DBG); +LAN9645X_P(7, GPIO, RGMII, TWI_SCL_M, SFP, SGPIO_a, = MIIM, SI_Sa, PHY_DBG); +LAN9645X_P(8, GPIO, RGMII, TWI_SCL_M, SFP, SGPIO_a, = MIIM, NONE, PHY_DBG); +LAN9645X_P(9, GPIO, RGMII, TWI_SCL_M, RECO_CLK, SGPIO_a, = IRQ1, UART, PHY_DBG); +LAN9645X_P(10, GPIO, RGMII, TWI_SCL_M, RECO_CLK, SGPIO_a, = IRQ2, UART, PHY_DBG); +LAN9645X_P(11, GPIO, RGMII, TWI_SCL_M, MIIM, NONE, = IRQ3, NONE, PHY_DBG); +LAN9645X_P(12, GPIO, RGMII, TWI_SCL_M, MIIM, PTP0, = NONE, NONE, PHY_DBG); +LAN9645X_P(13, GPIO, RGMII, TWI_SCL_M, CLKMON, PTP1, = MACLED, NONE, PHY_DBG); +LAN9645X_P(14, GPIO, RGMII, TWI_SCL_M, CLKMON, PTP2, = MACLED, NONE, PHY_DBG); +LAN9645X_P(15, GPIO, RGMII, TWI_SCL_M, CLKMON, PTP3, = NONE, NONE, PHY_DBG); +LAN9645X_P(16, GPIO, RGMII, NONE, NONE, NONE, = NONE, NONE, PHY_DBG); +LAN9645X_P(17, GPIO, RGMII, NONE, NONE, NONE, = NONE, NONE, PHY_DBG); +LAN9645X_P(18, GPIO, RGMII, NONE, NONE, NONE, = NONE, NONE, PHY_DBG); +LAN9645X_P(19, GPIO, RGMII, NONE, NONE, NONE, = NONE, NONE, PHY_DBG); +LAN9645X_P(20, GPIO, RGMII, NONE, NONE, NONE, = NONE, NONE, PHY_DBG); +LAN9645X_P(21, GPIO, RGMII, NONE, NONE, NONE, = NONE, NONE, PHY_DBG); +LAN9645X_P(22, GPIO, RGMII, NONE, NONE, NONE, = NONE, NONE, PHY_DBG); +LAN9645X_P(23, GPIO, RGMII, NONE, NONE, NONE, = NONE, NONE, PHY_DBG); +LAN9645X_P(24, GPIO, RGMII, NONE, NONE, NONE, = NONE, NONE, PHY_DBG); +LAN9645X_P(25, GPIO, RGMII, NONE, NONE, NONE, = NONE, NONE, PHY_DBG); +LAN9645X_P(26, GPIO, RGMII, NONE, NONE, NONE, = NONE, NONE, PHY_DBG); +LAN9645X_P(27, GPIO, RGMII, NONE, NONE, NONE, = NONE, NONE, PHY_DBG); +LAN9645X_P(28, GPIO, RECO_CLK, MIIM, NONE, NONE, = NONE, NONE, R); +LAN9645X_P(29, GPIO, RECO_CLK, MIIM, NONE, NONE, = NONE, NONE, R); +LAN9645X_P(30, GPIO, PTP0, I2C, UART, NONE, = NONE, NONE, R); +LAN9645X_P(31, GPIO, PTP1, TWI_SCL_M, UART, NONE, = NONE, NONE, R); +LAN9645X_P(32, GPIO, PTP2, TWI_SCL_M, NONE, NONE, = NONE, NONE, R); +LAN9645X_P(33, GPIO, PTP3, IRQ0, NONE, NONE, = NONE, NONE, R); +LAN9645X_P(34, GPIO, RECO_CLK, PHY_LED, PHY_LED, NONE, = NONE, NONE, R); +LAN9645X_P(35, GPIO, RECO_CLK, PHY_LED, PHY_LED, NONE, = MACLED, NONE, R); +LAN9645X_P(36, GPIO, PTP0, PHY_LED, PHY_LED, NONE, = MACLED, NONE, R); +LAN9645X_P(37, GPIO, PTP1, PHY_LED, PHY_LED, NONE, = MACLED, NONE, R); +LAN9645X_P(38, GPIO, NONE, PHY_LED, PHY_LED, NONE, = MACLED, NONE, R); +LAN9645X_P(39, GPIO, UART, PHY_LED, NONE, NONE, = MACLED, NONE, R); +LAN9645X_P(40, GPIO, SPI, PHY_LED, SGPIO_a, NONE, = MACLED, NONE, R); +LAN9645X_P(41, GPIO, SPI, PHY_LED, SGPIO_a, IRQ1, = MACLED, NONE, R); +LAN9645X_P(42, GPIO, SPI, PHY_LED, SGPIO_a, IRQ2, = MACLED, SFP, R); +LAN9645X_P(43, GPIO, SPI, PHY_LED, SGPIO_a, IRQ3, = MACLED, SFP, R); +LAN9645X_P(44, GPIO, MIIM, I2C, NONE, NONE, = NONE, NONE, R); +LAN9645X_P(45, GPIO, MIIM, I2C, NONE, NONE, = NONE, NONE, R); +LAN9645X_P(46, GPIO, NONE, PHY_LED, NONE, NONE, = NONE, NONE, R); +LAN9645X_P(47, GPIO, NONE, PHY_LED, NONE, NONE, = NONE, NONE, R); +LAN9645X_P(48, GPIO, MIIM_Sa, PHY_LED, NONE, NONE, = NONE, NONE, R); +LAN9645X_P(49, GPIO, MIIM_Sa, PHY_LED, I2C_Sa, NONE, = NONE, NONE, R); +LAN9645X_P(50, GPIO, MIIM_Sa, PHY_LED, I2C_Sa, NONE, = NONE, NONE, R); + +#define LAN9645X_PIN(n) { \ + .number =3D n, \ + .name =3D "GPIO_"#n, \ + .drv_data =3D &lan9645x_pin_##n \ +} + +static const struct pinctrl_pin_desc lan9645x_pins[] =3D { + LAN9645X_PIN(0), + LAN9645X_PIN(1), + LAN9645X_PIN(2), + LAN9645X_PIN(3), + LAN9645X_PIN(4), + LAN9645X_PIN(5), + LAN9645X_PIN(6), + LAN9645X_PIN(7), + LAN9645X_PIN(8), + LAN9645X_PIN(9), + LAN9645X_PIN(10), + LAN9645X_PIN(11), + LAN9645X_PIN(12), + LAN9645X_PIN(13), + LAN9645X_PIN(14), + LAN9645X_PIN(15), + LAN9645X_PIN(16), + LAN9645X_PIN(17), + LAN9645X_PIN(18), + LAN9645X_PIN(19), + LAN9645X_PIN(20), + LAN9645X_PIN(21), + LAN9645X_PIN(22), + LAN9645X_PIN(23), + LAN9645X_PIN(24), + LAN9645X_PIN(25), + LAN9645X_PIN(26), + LAN9645X_PIN(27), + LAN9645X_PIN(28), + LAN9645X_PIN(29), + LAN9645X_PIN(30), + LAN9645X_PIN(31), + LAN9645X_PIN(32), + LAN9645X_PIN(33), + LAN9645X_PIN(34), + LAN9645X_PIN(35), + LAN9645X_PIN(36), + LAN9645X_PIN(37), + LAN9645X_PIN(38), + LAN9645X_PIN(39), + LAN9645X_PIN(40), + LAN9645X_PIN(41), + LAN9645X_PIN(42), + LAN9645X_PIN(43), + LAN9645X_PIN(44), + LAN9645X_PIN(45), + LAN9645X_PIN(46), + LAN9645X_PIN(47), + LAN9645X_PIN(48), + LAN9645X_PIN(49), + LAN9645X_PIN(50), +}; + static int ocelot_get_functions_count(struct pinctrl_dev *pctldev) { return ARRAY_SIZE(ocelot_function_names); @@ -1471,6 +1613,13 @@ static int lan966x_gpio_request_enable(struct pinctr= l_dev *pctldev, return 0; } =20 +static int lan9645x_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + return 0; +} + static const struct pinmux_ops ocelot_pmx_ops =3D { .get_functions_count =3D ocelot_get_functions_count, .get_function_name =3D ocelot_get_function_name, @@ -1489,6 +1638,15 @@ static const struct pinmux_ops lan966x_pmx_ops =3D { .gpio_request_enable =3D lan966x_gpio_request_enable, }; =20 +static const struct pinmux_ops lan9645x_pmx_ops =3D { + .get_functions_count =3D ocelot_get_functions_count, + .get_function_name =3D ocelot_get_function_name, + .get_function_groups =3D ocelot_get_function_groups, + .set_mux =3D lan966x_pinmux_set_mux, + .gpio_set_direction =3D ocelot_gpio_set_direction, + .gpio_request_enable =3D lan9645x_gpio_request_enable, +}; + static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev) { struct ocelot_pinctrl *info =3D pinctrl_dev_get_drvdata(pctldev); @@ -1886,6 +2044,24 @@ static const struct ocelot_match_data lan969x_desc = =3D { }, }; =20 +static struct ocelot_match_data lan9645xf_desc =3D { + .desc =3D { + .name =3D "lan9645xf-pinctrl", + .pins =3D lan9645x_pins, + .npins =3D ARRAY_SIZE(lan9645x_pins), + .pctlops =3D &ocelot_pctl_ops, + .pmxops =3D &lan9645x_pmx_ops, + .confops =3D &ocelot_confops, + .owner =3D THIS_MODULE, + }, + .pincfg_data =3D { + .pd_bit =3D BIT(3), + .pu_bit =3D BIT(2), + .drive_bits =3D GENMASK(1, 0), + }, + .n_alt_modes =3D 7, +}; + static int ocelot_create_group_func_map(struct device *dev, struct ocelot_pinctrl *info) { @@ -2220,6 +2396,7 @@ static const struct of_device_id ocelot_pinctrl_of_ma= tch[] =3D { { .compatible =3D "microchip,sparx5-pinctrl", .data =3D &sparx5_desc }, { .compatible =3D "microchip,lan966x-pinctrl", .data =3D &lan966x_desc }, { .compatible =3D "microchip,lan9691-pinctrl", .data =3D &lan969x_desc }, + { .compatible =3D "microchip,lan96455f-pinctrl", .data =3D &lan9645xf_des= c }, {}, }; MODULE_DEVICE_TABLE(of, ocelot_pinctrl_of_match); --=20 2.34.1