From nobody Tue Feb 10 03:37:30 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 643CB244660 for ; Mon, 19 Jan 2026 12:17:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768825046; cv=none; b=DvqQ38NL871FMxuQ1gth867B34OJpDSP19QJlMuMlfyDRpJqHS0ASakK9TWNUAfAbmhKluHYTWyS1KFr0JccIVjusCgzJbOrdmVSMyJpzlr1hUq9FVDquaIuwlkdAoe4wy35g+pZ8u0yzp3u/sfB2Xwa+DtzlwM8N85h/IVWrK0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768825046; c=relaxed/simple; bh=j7ALa2ZclhoGMQnJoj7aJ1Do0/fMTZqp4zi/tvC4Yrs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rAOPXgSkuwaVJ3LG5yU7LoGuiMmitHON4I6Ft89vQNmm2lhnxDlTWch7wGXoXkO8ajCl3d/Auuqbe3RfpwevOx8XN5AeJSbNgGM9DG/6ecpDQQH7S3mbtiU/TB0e3kvMb+nDpSm8wxK7+UQOkfM85txZ1yIiISestsq3JZhQxX8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=IPZpVwLJ; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=RRbMKvxJ; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="IPZpVwLJ"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="RRbMKvxJ" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 60JBDMCW1440838 for ; Mon, 19 Jan 2026 12:17:23 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= ODvajz5k+1YRXA6Nwokuzw/VMyW4/mE+fTtWqbu7rKg=; b=IPZpVwLJPuvCjP68 EoXnbOX2bzoU+tuQhq/IuETuOxfpvrvxHmSzbWOd+1epPb4wsI9ioMpvcVHF+Gnc Y28i1c2a6s/MklK5LDwOThlPLmtp4ZB8S5C0NYqVb0IPq1OmEvnlI4dKgK9bCWaJ +wDybahgZcE4bCioOW5d8zAg88TuEQ7JCFj6L/uNEvNCYsdo59GVICPx9/FMnupk oeCmOU33uP2A37xAG8cyG+TZizK8MZpEyBrt3zcHmqxqEaeRuGPnCIkrjy0lJ1Ne NUDKH99bzopgButMyP8nllor5LJN4uNloTCHWKzDoWuivzUOwCAfkrjzbg2KY/6K Q+yGKA== Received: from mail-qv1-f69.google.com (mail-qv1-f69.google.com [209.85.219.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4bskj3g5h2-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 19 Jan 2026 12:17:23 +0000 (GMT) Received: by mail-qv1-f69.google.com with SMTP id 6a1803df08f44-88a2d8b7ea5so47432996d6.0 for ; Mon, 19 Jan 2026 04:17:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1768825043; x=1769429843; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ODvajz5k+1YRXA6Nwokuzw/VMyW4/mE+fTtWqbu7rKg=; b=RRbMKvxJMc5FLLOwDeDe//3MVExAp8xSYMI9xmEH8TAtjdSoctyRxnNGO9FlqzPKin oW1gA/WIKov9bTREPD4CoULwRToM1jMDZwV1NSK0XvcU2zWyVkDv+qiuPgMeopnWaePl S+T457YGVv22a9lFHEVhpto3j9ncbGVpLWtVHObLz2yZzgBGGV3LTyeESJMu96Xtk7YI EAgvneDdZ9BYNllsol5VpBkyTRp4xNSWGFcXPmZ3nAt7M4P9E1iU12zEI00RORTZazmJ novDUzSm/vBDbyZ6LKacUSolaAeap0XE5RahfjdMiAB5r0E1nGAkFtXgiExN3BCnNdMN BZvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768825043; x=1769429843; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=ODvajz5k+1YRXA6Nwokuzw/VMyW4/mE+fTtWqbu7rKg=; b=p/bc0bbECqVaWRvxfAJ0L7v7QZB3hmZuv59NPC4doMgFPu0xlDTCEqlHKKgwW0ku6E 47evsAT28g+0mUsT8EzOyVUtDCQbhPzCmr7I0Q48Y0//Qw26pCTp+aNe1wUDQgBo00/+ QuYm46hQ/Bh/GSDaiI5mt1HYe5d5ofBAkagjJ6AftdLQGuzBCFwddtqKvvW5/ECHDKvO dDisR+0QUxm2eXwDqidPMXogh8tClMZ2L+BjtX5y+B6eU1e+61U71v7NdapdX3OdaR1U F1cokI3Gfekdd8iqzc0iIGorLf9fUFdroPicH2CkA+ByK0rPga2QemcZ4HG3QBm8620V VgZQ== X-Forwarded-Encrypted: i=1; AJvYcCW5wSnHK/VfDMpIy3+Z809DZPVIZuVXqtbhdVdX/ta2LYQoyMotE7ZpybZ8boeuF8lMBL+FyckLUB3zDuo=@vger.kernel.org X-Gm-Message-State: AOJu0Yyhr+BTKoWGVoUPv2AEoJuee9PZudL9HjdBvymmmQf4F3d/DmX8 dQgbN7pqw0ERUIh/IpVjVndsjRVAdHCv1sj4JZN84qYm7ItgPGe2/iMflwlTmdY/5NSgXK/xCfK 3pWQNxDQuL8u6DjGN4KTPAwkyg3LEmTV+/YYwfvh4Zcgim0KkErymtTM6/9ShUxljBGQ= X-Gm-Gg: AZuq6aJz02PFNbUtBDWFjECbNLljG5ax+xBhVPJB/rfoWoxUUQXK8enLbbl4RvFxIu4 SRuGEx4+skGvgVHITPMQMJtrzZBpAP9O3vvbdP+dVnH0ZYazPhRqEJllsPoT0kfJNsc13DIyWcq kQ6WD8SoIS4K0tuSjL1lscFTGnxavvkqo+HAjO5VwBRb54htmMZnJn3QNn+hriSiDrSrdSEZtOx l3F0XoekAgI4/mNpQyXWn5SviY0lHD35nGN60tbKKAmGKqMbAi1DJkF4XDEenFvTeUlh7/LKz7V DMvR1T+WusCP76PBY+D2ATm8qJ27Fs8VYhCKk7tx5GM5T2F1rgT/5lKD0PNZVTL4cO//kUmc8q3 t3KmFq2yUUUg7QZWjxiyxDJeNZeGhEJDaSiA31v7vuvqkNAzhBF9LYp7Rm7GvLdU5mKCeQ7KLoM k/AC2q5Fb8CxkPvN95Mr5mfW4= X-Received: by 2002:a05:6214:629:b0:88a:3113:3abf with SMTP id 6a1803df08f44-8942dd8e7c8mr153078956d6.52.1768825042395; Mon, 19 Jan 2026 04:17:22 -0800 (PST) X-Received: by 2002:a05:6214:629:b0:88a:3113:3abf with SMTP id 6a1803df08f44-8942dd8e7c8mr153078406d6.52.1768825041762; Mon, 19 Jan 2026 04:17:21 -0800 (PST) Received: from umbar.lan (2001-14ba-a073-af00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-59baf3a17b9sm3274641e87.92.2026.01.19.04.17.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jan 2026 04:17:20 -0800 (PST) From: Dmitry Baryshkov Date: Mon, 19 Jan 2026 14:16:39 +0200 Subject: [PATCH v4 3/4] drm/msm/dpu: program correct register for UBWC config on DPU 8.x+ Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-msm-ubwc-fixes-v4-3-0987acc0427f@oss.qualcomm.com> References: <20260119-msm-ubwc-fixes-v4-0-0987acc0427f@oss.qualcomm.com> In-Reply-To: <20260119-msm-ubwc-fixes-v4-0-0987acc0427f@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Konrad Dybcio , Konrad Dybcio , Vinod Koul , Stephan Gerhold Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Val Packett X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3623; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=j7ALa2ZclhoGMQnJoj7aJ1Do0/fMTZqp4zi/tvC4Yrs=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ2aewum/G+1ffRMqUL0xI39LiBqH4eGkfwYP4uNeMlc7/ S5hLmHoZDRmYWDkYpAVU2TxKWiZGrMpOezDjqn1MINYmUCmMHBxCsBEumvY//C9Wblebvp1pYT4 f/e736Zn70xWNo+XX//xTPn9j+902Riu1Sh1PjXZKhafFfiq66f3AgmX3aqLbfqv/90pNmnOgwL 3z9ZCoUJNqqF1LE38ebs6pBwnMTcfMJHWfuC/hWnJEr3sG5PNdXgcs8vdS7fE1cm2bKu2m744/X +HZMceuU7PNLV3U4JfTTRV4zSMOct1pOp148FjgR1Nqwtta7bsfd7CydyfOlt/26942WfT/jNmH +X1Wvbh8etzXPus1FwuTrV4N52DIXiexss3leUCOp/F9umznX9jWLw2uu9kdY7pgRnrjhg9j757 RuhPrV+hZL6qs9O7C/oBr5u5XvcfEFkc+db9o5SEfkU9AA== X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Authority-Analysis: v=2.4 cv=ds7Wylg4 c=1 sm=1 tr=0 ts=696e20d3 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=BEO5sv_cWZf0Vc4k7EUA:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTE5MDEwMiBTYWx0ZWRfX2GWzcpZT8N/R XhvC4qPbwurxu1kj9hMZ+rNbGijee8UEK0jIqpVoqYUvz4IuDuhb2agGzaraesz0sM4iQ1TZc2s E24sxCJORtlb+HtwZvqRckAIFtnEPq+SL/B4farbTmXzu5bWkw8+aqEUambAjKtg5meiLFV5BCc e6WfjsorsjWaB7FmvggFZgcLrC0uZxdjqaPu61XI9PY1BsvYl3QEKxdR2PiFbnqWKyOU9qRPQDf G6Ta7T4DCdqSfaDYkO7wFM10WsbL4Fm/3ikBtaQ+OFh6p97daux0biquApg01CEM+nRGsU/Vj6H EZahp0s8q385nUmP3PMYUoRHyRh7LhOgwfy9ahdbQPOT6N+UC8zU11PiXC80oeqlCjmyKHPQ6I3 C+MTll+9xpwSe+2nFjhj33T33FRoRajl7OCexLpxCVLGIpetf9OfcQpF0jU8yO0lUtDbtKGQ2jO sRnDl5uElpORh5WBj8w== X-Proofpoint-ORIG-GUID: oS7Q-4bV1pJMsCqZ_kHYPLe-Irv_N8dV X-Proofpoint-GUID: oS7Q-4bV1pJMsCqZ_kHYPLe-Irv_N8dV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-19_02,2026-01-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 phishscore=0 priorityscore=1501 spamscore=0 clxscore=1015 adultscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601190102 Since DPU 8.0 there is a separate register for the second rectangle, which needs to be programmed with the UBWC config if multirect is being used. Write pipe's UBWC configuration to the correct register. Fixes: 100d7ef6995d ("drm/msm/dpu: add support for SM8450") Tested-by: Val Packett # x1e80100-dell-latitude-7455 Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_sspp.c index b66c4cb5760c..6ff4902fce08 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -72,6 +72,8 @@ #define SSPP_EXCL_REC_XY_REC1 0x188 #define SSPP_EXCL_REC_SIZE 0x1B4 #define SSPP_EXCL_REC_XY 0x1B8 +#define SSPP_UBWC_STATIC_CTRL_REC1 0x1c0 +#define SSPP_UBWC_ERROR_STATUS_REC1 0x1c8 #define SSPP_CLK_CTRL 0x330 =20 /* SSPP_SRC_OP_MODE & OP_MODE_REC1 */ @@ -215,7 +217,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe= *pipe, u32 chroma_samp, unpack, src_format; u32 opmode =3D 0; u32 fast_clear =3D 0; - u32 op_mode_off, unpack_pat_off, format_off; + u32 op_mode_off, unpack_pat_off, format_off, ubwc_ctrl_off, ubwc_error_of= f; =20 if (!ctx || !fmt) return; @@ -225,10 +227,21 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pi= pe *pipe, op_mode_off =3D SSPP_SRC_OP_MODE; unpack_pat_off =3D SSPP_SRC_UNPACK_PATTERN; format_off =3D SSPP_SRC_FORMAT; + ubwc_ctrl_off =3D SSPP_UBWC_STATIC_CTRL; + ubwc_error_off =3D SSPP_UBWC_ERROR_STATUS; } else { op_mode_off =3D SSPP_SRC_OP_MODE_REC1; unpack_pat_off =3D SSPP_SRC_UNPACK_PATTERN_REC1; format_off =3D SSPP_SRC_FORMAT_REC1; + + /* reg wasn't present before DPU 8.0 */ + if (ctx->mdss_ver->core_major_ver >=3D 8) { + ubwc_ctrl_off =3D SSPP_UBWC_STATIC_CTRL_REC1; + ubwc_error_off =3D SSPP_UBWC_ERROR_STATUS_REC1; + } else { + ubwc_ctrl_off =3D SSPP_UBWC_STATIC_CTRL; + ubwc_error_off =3D SSPP_UBWC_ERROR_STATUS; + } } =20 c =3D &ctx->hw; @@ -281,24 +294,24 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pi= pe *pipe, switch (ctx->ubwc->ubwc_enc_version) { case UBWC_1_0: fast_clear =3D fmt->alpha_enable ? BIT(31) : 0; - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, + DPU_REG_WRITE(c, ubwc_ctrl_off, fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) | BIT(8) | (hbb << 4)); break; case UBWC_2_0: fast_clear =3D fmt->alpha_enable ? BIT(31) : 0; - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, + DPU_REG_WRITE(c, ubwc_ctrl_off, fast_clear | (ctx->ubwc->ubwc_swizzle) | (hbb << 4)); break; case UBWC_3_0: - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, + DPU_REG_WRITE(c, ubwc_ctrl_off, BIT(30) | (ctx->ubwc->ubwc_swizzle) | (hbb << 4)); break; case UBWC_4_0: - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, + DPU_REG_WRITE(c, ubwc_ctrl_off, MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30)); break; } @@ -327,7 +340,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe= *pipe, DPU_REG_WRITE(c, op_mode_off, opmode); =20 /* clear previous UBWC error */ - DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS, BIT(31)); + DPU_REG_WRITE(c, ubwc_error_off, BIT(31)); } =20 static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx, --=20 2.47.3