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[35.240.102.164]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4356997e664sm20698421f8f.30.2026.01.19.04.08.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jan 2026 04:08:57 -0800 (PST) From: Tudor Ambarus Date: Mon, 19 Jan 2026 12:08:52 +0000 Subject: [PATCH v2 6/7] arm64: dts: exynos: gs101: Add thermal management unit Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-acpm-tmu-v2-6-e02a834f04c6@linaro.org> References: <20260119-acpm-tmu-v2-0-e02a834f04c6@linaro.org> In-Reply-To: <20260119-acpm-tmu-v2-0-e02a834f04c6@linaro.org> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Alim Akhtar , Bartlomiej Zolnierkiewicz , Kees Cook , "Gustavo A. R. Silva" , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= Cc: willmcvicker@google.com, jyescas@google.com, shin.son@samsung.com, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-hardening@vger.kernel.org, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768824532; l=8775; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=FbDNXAgPAAbLgVJFNLv0wQaisif895tAwODlc1nDIio=; b=qx+povYGdT0SCFv279IfjgdUWsxoqkhWF6qHZZALvaE22fhrYKhuXAxLzfU98oDlk5mXUiVBU t7OehfZc22vAY1BC+MzyyBUIR9n0Zis/U51nv9beTQD7+vsnuAuPZdD X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add the Thermal Management Unit (TMU) support for the Google GS101 SoC. Describe the TMU using a consolidated SoC node that includes memory resources for interrupt identification and a phandle to the ACPM IPC interface for functional control. Define thermal zones for the little, mid, and big CPU clusters, including associated trip points and cooling-device maps to enable thermal mitigation. Signed-off-by: Tudor Ambarus --- arch/arm64/boot/dts/exynos/google/gs101-tmu.dtsi | 209 +++++++++++++++++++= ++++ arch/arm64/boot/dts/exynos/google/gs101.dtsi | 18 ++ 2 files changed, 227 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101-tmu.dtsi b/arch/arm64/= boot/dts/exynos/google/gs101-tmu.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..6262c3b890aa2f7ad572c32b30b= f926df804ec1e --- /dev/null +++ b/arch/arm64/boot/dts/exynos/google/gs101-tmu.dtsi @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Google GS101 TMU configurations device tree source + * + * Copyright 2020 Samsung Electronics Co., Ltd. + * Copyright 2020 Google LLC. + * Copyright 2026 Linaro Ltd. + */ + +#include + +/ { + thermal-zones { + cpucl2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 0>; + + trips { + big_cold: big-cold { + temperature =3D <20000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + big_switch_on: big-switch-on { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + + big_control_temp: big-control-temp { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + big_pre_switch_on: big-pre-switch-on { + temperature =3D <55000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + + big_alert2: big-alert2 { + temperature =3D <95000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + big_hw_throttling: big-hw-throttling { + temperature =3D <103000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + big_pause: big-pause { + temperature =3D <108000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + big_hot: big-hot { + temperature =3D <115000>; + hysteresis =3D <3000>; + type =3D "hot"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&big_control_temp>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpucl1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 1>; + + trips { + mid_cold: mid-cold { + temperature =3D <20000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + mid_switch_on: mid-switch-on { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + + mid_control_temp: mid-control-temp { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + mid_pre_switch_on: mid-pre-switch-on { + temperature =3D <55000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + + mid_alert2: mid-alert2 { + temperature =3D <95000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + mid_hw_throttling: mid-hw-throttling { + temperature =3D <98000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + mid_pause: mid-pause { + temperature =3D <108000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + mid_hot: mid-hot { + temperature =3D <115000>; + hysteresis =3D <3000>; + type =3D "hot"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&mid_control_temp>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpucl0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 2>; + + trips { + little_cold: little-cold { + temperature =3D <20000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + little_switch_on: little-switch-on { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + + little_control_temp: little-control-temp { + temperature =3D <95000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + little_pre_switch_on: little-pre-switch-on { + temperature =3D <55000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + + little_alert2: little-alert2 { + temperature =3D <100000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + little_alert5: little-alert5 { + temperature =3D <103000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + little_alert6: little-alert6 { + temperature =3D <110000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + little_hot: little-hot { + temperature =3D <115000>; + hysteresis =3D <3000>; + type =3D "hot"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&little_control_temp>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + }; +}; diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index d085f9fb0f62ac2f57b104c20880e64d885d0bee..4b8c7edaddb6fd49e61496f2f21= f348db0b58f10 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -74,6 +74,7 @@ cpu0: cpu@0 { compatible =3D "arm,cortex-a55"; reg =3D <0x0000>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -86,6 +87,7 @@ cpu1: cpu@100 { compatible =3D "arm,cortex-a55"; reg =3D <0x0100>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -98,6 +100,7 @@ cpu2: cpu@200 { compatible =3D "arm,cortex-a55"; reg =3D <0x0200>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -110,6 +113,7 @@ cpu3: cpu@300 { compatible =3D "arm,cortex-a55"; reg =3D <0x0300>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -122,6 +126,7 @@ cpu4: cpu@400 { compatible =3D "arm,cortex-a76"; reg =3D <0x0400>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&enyo_cpu_sleep>; capacity-dmips-mhz =3D <620>; @@ -134,6 +139,7 @@ cpu5: cpu@500 { compatible =3D "arm,cortex-a76"; reg =3D <0x0500>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&enyo_cpu_sleep>; capacity-dmips-mhz =3D <620>; @@ -146,6 +152,7 @@ cpu6: cpu@600 { compatible =3D "arm,cortex-x1"; reg =3D <0x0600>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL2>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&hera_cpu_sleep>; capacity-dmips-mhz =3D <1024>; @@ -158,6 +165,7 @@ cpu7: cpu@700 { compatible =3D "arm,cortex-x1"; reg =3D <0x0700>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL2>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&hera_cpu_sleep>; capacity-dmips-mhz =3D <1024>; @@ -639,6 +647,15 @@ watchdog_cl1: watchdog@10070000 { status =3D "disabled"; }; =20 + tmu_top: thermal-sensor@100a0000 { + compatible =3D "google,gs101-tmu-top"; + reg =3D <0x100a0000 0x800>; + clocks =3D <&cmu_misc CLK_GOUT_MISC_TMU_TOP_PCLK>; + interrupts =3D ; + samsung,acpm-ipc =3D <&acpm_ipc>; + #thermal-sensor-cells =3D <1>; + }; + trng: rng@10141400 { compatible =3D "google,gs101-trng", "samsung,exynos850-trng"; @@ -1861,3 +1878,4 @@ timer { }; =20 #include "gs101-pinctrl.dtsi" +#include "gs101-tmu.dtsi" --=20 2.52.0.457.g6b5491de43-goog