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[35.240.102.164]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4356997e664sm20698421f8f.30.2026.01.19.04.08.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jan 2026 04:08:53 -0800 (PST) From: Tudor Ambarus Date: Mon, 19 Jan 2026 12:08:47 +0000 Subject: [PATCH v2 1/7] dt-bindings: thermal: Add Google GS101 TMU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-acpm-tmu-v2-1-e02a834f04c6@linaro.org> References: <20260119-acpm-tmu-v2-0-e02a834f04c6@linaro.org> In-Reply-To: <20260119-acpm-tmu-v2-0-e02a834f04c6@linaro.org> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Alim Akhtar , Bartlomiej Zolnierkiewicz , Kees Cook , "Gustavo A. R. Silva" , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= Cc: willmcvicker@google.com, jyescas@google.com, shin.son@samsung.com, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-hardening@vger.kernel.org, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768824532; l=3157; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=NSnDjeYXDKXRwPd3DPQdyVTKpEJbKoAyXp1JmfIwRDo=; b=dtDJDuEZ8DzLjZa7229oBMQmNZpRgOy1kXud/+4ry809hpk1wR2EYaj7pZfffGZmlWn/aR34X iStwRKVu+IWANL5Tdx/kQfLXBZ9N9QrNnyHAcG5rsHW5rDnJDO2waeq X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Document the Thermal Management Unit (TMU) found on the Google GS101 SoC. The GS101 TMU utilizes a hybrid control model shared between the Application Processor (AP) and the ACPM (Alive Clock and Power Manager) firmware. While the TMU is a standard memory-mapped IP block, on this platform the AP's direct register access is restricted to the interrupt pending (INTPEND) registers for event identification. High-level functional tasks, such as sensor initialization, threshold programming, and temperature reads, are delegated to the ACPM firmware. Signed-off-by: Tudor Ambarus Reviewed-by: Krzysztof Kozlowski --- .../bindings/thermal/google,gs101-tmu-top.yaml | 67 ++++++++++++++++++= ++++ 1 file changed, 67 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/google,gs101-tmu-top= .yaml b/Documentation/devicetree/bindings/thermal/google,gs101-tmu-top.yaml new file mode 100644 index 0000000000000000000000000000000000000000..b09e1ff5d89194b570810a042c7= 5836ca2e53950 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/google,gs101-tmu-top.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/google,gs101-tmu-top.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google GS101 Thermal Management Unit (TMU) + +maintainers: + - Tudor Ambarus + +description: + The Google GS101 TMU is a thermal sensor block that supports both direct + register-level access and firmware-mediated management via the ACPM + (Alive Clock and Power Manager) firmware. + + On this platform, the hardware is managed in a hybrid fashion. The + Application Processor (AP) maintains direct memory-mapped access + exclusively to the interrupt pending registers to identify thermal + events. All other functional aspects - including sensor + initialization, threshold configuration, and temperature acquisition + - are handled by the ACPM firmware. The AP coordinates these + operations through the ACPM IPC protocol. + +properties: + compatible: + const: google,gs101-tmu-top + + reg: + maxItems: 1 + + clocks: + items: + - description: APB peripheral clock (PCLK) for TMU register access. + + interrupts: + maxItems: 1 + + "#thermal-sensor-cells": + const: 1 + + samsung,acpm-ipc: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to the ACPM IPC node. + +required: + - compatible + - reg + - clocks + - interrupts + - "#thermal-sensor-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + thermal-sensor@100a0000 { + compatible =3D "google,gs101-tmu-top"; + reg =3D <0x100a0000 0x800>; + clocks =3D <&cmu_misc CLK_GOUT_MISC_TMU_TOP_PCLK>; + interrupts =3D ; + #thermal-sensor-cells =3D <1>; + samsung,acpm-ipc =3D <&acpm_ipc>; + }; --=20 2.52.0.457.g6b5491de43-goog From nobody Sun Feb 8 13:53:09 2026 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4EB823590DA for ; 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[35.240.102.164]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4356997e664sm20698421f8f.30.2026.01.19.04.08.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jan 2026 04:08:53 -0800 (PST) From: Tudor Ambarus Date: Mon, 19 Jan 2026 12:08:48 +0000 Subject: [PATCH v2 2/7] firmware: samsung: acpm: Add TMU protocol support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-acpm-tmu-v2-2-e02a834f04c6@linaro.org> References: <20260119-acpm-tmu-v2-0-e02a834f04c6@linaro.org> In-Reply-To: <20260119-acpm-tmu-v2-0-e02a834f04c6@linaro.org> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Alim Akhtar , Bartlomiej Zolnierkiewicz , Kees Cook , "Gustavo A. R. Silva" , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= Cc: willmcvicker@google.com, jyescas@google.com, shin.son@samsung.com, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-hardening@vger.kernel.org, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768824532; l=11506; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=xm2Bk0tp2/dYXXAn7n3eVAFPnJF+Lc6bvpH8padRGcg=; b=rK0SJyctMob1vdqVS1D3IM9jdQOu7BrB06o+UuhUxD6Fa9dPj+HX2X3tOmK6b3Z9riwIfmBH8 25iPEkXpzD/Ccb0PKShVmQz+ixWvGYzX5PWtpZj5zVaHXf8pMfbSn/E X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= The Thermal Management Unit (TMU) on the Google GS101 SoC is managed through a hybrid model shared between the kernel and the Alive Clock and Power Manager (ACPM) firmware. Add the protocol helpers required to communicate with the ACPM for thermal operations, including initialization, threshold configuration, temperature reading, and system suspend/resume handshakes. Signed-off-by: Tudor Ambarus --- drivers/firmware/samsung/Makefile | 1 + drivers/firmware/samsung/exynos-acpm-tmu.c | 212 +++++++++++++++++= ++++ drivers/firmware/samsung/exynos-acpm-tmu.h | 33 ++++ drivers/firmware/samsung/exynos-acpm.c | 12 ++ .../linux/firmware/samsung/exynos-acpm-protocol.h | 24 +++ 5 files changed, 282 insertions(+) diff --git a/drivers/firmware/samsung/Makefile b/drivers/firmware/samsung/M= akefile index 80d4f89b33a9558b68c9083da675c70ec3d05f19..5a6f72bececfd98ba5af37d1d65= fed48a3d8f912 100644 --- a/drivers/firmware/samsung/Makefile +++ b/drivers/firmware/samsung/Makefile @@ -3,4 +3,5 @@ acpm-protocol-objs :=3D exynos-acpm.o acpm-protocol-objs +=3D exynos-acpm-pmic.o acpm-protocol-objs +=3D exynos-acpm-dvfs.o +acpm-protocol-objs +=3D exynos-acpm-tmu.o obj-$(CONFIG_EXYNOS_ACPM_PROTOCOL) +=3D acpm-protocol.o diff --git a/drivers/firmware/samsung/exynos-acpm-tmu.c b/drivers/firmware/= samsung/exynos-acpm-tmu.c new file mode 100644 index 0000000000000000000000000000000000000000..7ec4b48074eb8b4e569b39d4bb5= 963d887aa9521 --- /dev/null +++ b/drivers/firmware/samsung/exynos-acpm-tmu.c @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2020 Samsung Electronics Co., Ltd. + * Copyright 2020 Google LLC. + * Copyright 2026 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include + +#include "exynos-acpm.h" +#include "exynos-acpm-tmu.h" + +/* IPC Request Types */ +#define ACPM_TMU_INIT 0x01 +#define ACPM_TMU_READ_TEMP 0x02 +#define ACPM_TMU_SUSPEND 0x04 +#define ACPM_TMU_RESUME 0x10 +#define ACPM_TMU_THRESHOLD 0x11 +#define ACPM_TMU_INTEN 0x12 +#define ACPM_TMU_CONTROL 0x13 +#define ACPM_TMU_IRQ_CLEAR 0x14 +#define ACPM_TMU_HYSTERESIS 0x16 + +#define ACPM_TMU_TX_DATA_LEN 8 +#define ACPM_TMU_RX_DATA_LEN 7 + +struct acpm_tmu_tx { + u16 ctx; + u16 fw_use; + u8 type; + u8 rsvd0; + u8 tzid; + u8 rsvd1; + u8 data[ACPM_TMU_TX_DATA_LEN]; +} __packed; + +struct acpm_tmu_rx { + u16 ctx; + u16 fw_use; + u8 type; + s8 ret; + u8 tzid; + s8 temp; + u8 rsvd; + u8 data[ACPM_TMU_RX_DATA_LEN]; +} __packed; + +union acpm_tmu_msg { + u32 data[4]; + struct acpm_tmu_tx tx; + struct acpm_tmu_rx rx; +} __packed; + +static void acpm_tmu_set_xfer(struct acpm_xfer *xfer, u32 *cmd, size_t cmd= len, + unsigned int acpm_chan_id) +{ + xfer->acpm_chan_id =3D acpm_chan_id; + xfer->txd =3D cmd; + xfer->txlen =3D cmdlen; + xfer->rxd =3D cmd; + xfer->rxlen =3D cmdlen; +} + +int acpm_tmu_init(const struct acpm_handle *handle, unsigned int acpm_chan= _id) +{ + union acpm_tmu_msg msg =3D {0}; + struct acpm_xfer xfer; + + msg.tx.type =3D ACPM_TMU_INIT; + acpm_tmu_set_xfer(&xfer, msg.data, sizeof(msg.data), acpm_chan_id); + + return acpm_do_xfer(handle, &xfer); +} + +int acpm_tmu_read_temp(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, int *temp) +{ + union acpm_tmu_msg msg =3D {0}; + struct acpm_xfer xfer; + int ret; + + msg.tx.type =3D ACPM_TMU_READ_TEMP; + msg.tx.tzid =3D tz; + + acpm_tmu_set_xfer(&xfer, msg.data, sizeof(msg.data), acpm_chan_id); + + ret =3D acpm_do_xfer(handle, &xfer); + if (ret) + return ret; + + *temp =3D msg.rx.temp; + + return 0; +} + +int acpm_tmu_set_threshold(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, + const u8 temperature[8], size_t tlen) +{ + union acpm_tmu_msg msg =3D {0}; + struct acpm_xfer xfer; + int i; + + if (tlen > ACPM_TMU_TX_DATA_LEN) + return -EINVAL; + + msg.tx.type =3D ACPM_TMU_THRESHOLD; + msg.tx.tzid =3D tz; + + for (i =3D 0; i < tlen; i++) + msg.tx.data[i] =3D temperature[i]; + + acpm_tmu_set_xfer(&xfer, msg.data, sizeof(msg.data), acpm_chan_id); + + return acpm_do_xfer(handle, &xfer); +} + +int acpm_tmu_set_hysteresis(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, + const u8 hysteresis[8], size_t hlen) +{ + union acpm_tmu_msg msg =3D {0}; + struct acpm_xfer xfer; + int i; + + if (hlen > ACPM_TMU_TX_DATA_LEN) + return -EINVAL; + + msg.tx.type =3D ACPM_TMU_HYSTERESIS; + msg.tx.tzid =3D tz; + + for (i =3D 0; i < hlen; i++) + msg.tx.data[i] =3D hysteresis[i]; + + acpm_tmu_set_xfer(&xfer, msg.data, sizeof(msg.data), acpm_chan_id); + + return acpm_do_xfer(handle, &xfer); +} + +int acpm_tmu_set_interrupt_enable(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, u8 inten) +{ + union acpm_tmu_msg msg =3D {0}; + struct acpm_xfer xfer; + + msg.tx.type =3D ACPM_TMU_INTEN; + msg.tx.tzid =3D tz; + msg.tx.data[0] =3D inten; + + acpm_tmu_set_xfer(&xfer, msg.data, sizeof(msg.data), acpm_chan_id); + + return acpm_do_xfer(handle, &xfer); +} + +int acpm_tmu_tz_control(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, bool enable) +{ + union acpm_tmu_msg msg =3D {0}; + struct acpm_xfer xfer; + + msg.tx.type =3D ACPM_TMU_CONTROL; + msg.tx.tzid =3D tz; + msg.tx.data[0] =3D enable ? 1 : 0; + + acpm_tmu_set_xfer(&xfer, msg.data, sizeof(msg.data), acpm_chan_id); + + return acpm_do_xfer(handle, &xfer); +} + +int acpm_tmu_clear_tz_irq(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz) +{ + union acpm_tmu_msg msg =3D {0}; + struct acpm_xfer xfer; + + msg.tx.type =3D ACPM_TMU_IRQ_CLEAR; + msg.tx.tzid =3D tz; + + acpm_tmu_set_xfer(&xfer, msg.data, sizeof(msg.data), acpm_chan_id); + + return acpm_do_xfer(handle, &xfer); +} + +int acpm_tmu_suspend(const struct acpm_handle *handle, + unsigned int acpm_chan_id) +{ + union acpm_tmu_msg msg =3D {0}; + struct acpm_xfer xfer; + + msg.tx.type =3D ACPM_TMU_SUSPEND; + + acpm_tmu_set_xfer(&xfer, msg.data, sizeof(msg.data), acpm_chan_id); + + return acpm_do_xfer(handle, &xfer); +} + +int acpm_tmu_resume(const struct acpm_handle *handle, unsigned int acpm_ch= an_id) +{ + union acpm_tmu_msg msg =3D {0}; + struct acpm_xfer xfer; + + msg.tx.type =3D ACPM_TMU_RESUME; + + acpm_tmu_set_xfer(&xfer, msg.data, sizeof(msg.data), acpm_chan_id); + + return acpm_do_xfer(handle, &xfer); +} diff --git a/drivers/firmware/samsung/exynos-acpm-tmu.h b/drivers/firmware/= samsung/exynos-acpm-tmu.h new file mode 100644 index 0000000000000000000000000000000000000000..f1a1ac21736d52bea0ad2a7cb3b= 280201fa74ffe --- /dev/null +++ b/drivers/firmware/samsung/exynos-acpm-tmu.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2020 Samsung Electronics Co., Ltd. + * Copyright 2020 Google LLC. + * Copyright 2026 Linaro Ltd. + */ +#ifndef __EXYNOS_ACPM_TMU_H__ +#define __EXYNOS_ACPM_TMU_H__ + +#include + +struct acpm_handle; + +int acpm_tmu_init(const struct acpm_handle *handle, unsigned int acpm_chan= _id); +int acpm_tmu_read_temp(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, int *temp); +int acpm_tmu_set_threshold(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, + const u8 temperature[8], size_t tlen); +int acpm_tmu_set_hysteresis(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, + const u8 hysteresis[8], size_t hlen); +int acpm_tmu_set_interrupt_enable(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, u8 inten); +int acpm_tmu_tz_control(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, bool enable); +int acpm_tmu_clear_tz_irq(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz); +int acpm_tmu_suspend(const struct acpm_handle *handle, + unsigned int acpm_chan_id); +int acpm_tmu_resume(const struct acpm_handle *handle, + unsigned int acpm_chan_id); +#endif /* __EXYNOS_ACPM_TMU_H__ */ diff --git a/drivers/firmware/samsung/exynos-acpm.c b/drivers/firmware/sams= ung/exynos-acpm.c index 0cb269c7046015d4c5fe5731ba0d61d48dcaeee1..cc045370f4b0dc6ccea99e3c2d6= f86a43b2e9671 100644 --- a/drivers/firmware/samsung/exynos-acpm.c +++ b/drivers/firmware/samsung/exynos-acpm.c @@ -31,6 +31,7 @@ #include "exynos-acpm.h" #include "exynos-acpm-dvfs.h" #include "exynos-acpm-pmic.h" +#include "exynos-acpm-tmu.h" =20 #define ACPM_PROTOCOL_SEQNUM GENMASK(21, 16) =20 @@ -595,6 +596,7 @@ static void acpm_setup_ops(struct acpm_info *acpm) { struct acpm_dvfs_ops *dvfs_ops =3D &acpm->handle.ops.dvfs_ops; struct acpm_pmic_ops *pmic_ops =3D &acpm->handle.ops.pmic_ops; + struct acpm_tmu_ops *tmu_ops =3D &acpm->handle.ops.tmu; =20 dvfs_ops->set_rate =3D acpm_dvfs_set_rate; dvfs_ops->get_rate =3D acpm_dvfs_get_rate; @@ -604,6 +606,16 @@ static void acpm_setup_ops(struct acpm_info *acpm) pmic_ops->write_reg =3D acpm_pmic_write_reg; pmic_ops->bulk_write =3D acpm_pmic_bulk_write; pmic_ops->update_reg =3D acpm_pmic_update_reg; + + tmu_ops->init =3D acpm_tmu_init; + tmu_ops->read_temp =3D acpm_tmu_read_temp; + tmu_ops->set_threshold =3D acpm_tmu_set_threshold; + tmu_ops->set_hysteresis =3D acpm_tmu_set_hysteresis; + tmu_ops->set_interrupt_enable =3D acpm_tmu_set_interrupt_enable; + tmu_ops->tz_control =3D acpm_tmu_tz_control; + tmu_ops->clear_tz_irq =3D acpm_tmu_clear_tz_irq; + tmu_ops->suspend =3D acpm_tmu_suspend; + tmu_ops->resume =3D acpm_tmu_resume; } =20 static void acpm_clk_pdev_unregister(void *data) diff --git a/include/linux/firmware/samsung/exynos-acpm-protocol.h b/includ= e/linux/firmware/samsung/exynos-acpm-protocol.h index 2091da965a5ad238b5e16c567a72fe88fafe6095..43d41e11ad2eb985e27a918ce3f= 9e9ac15a194ee 100644 --- a/include/linux/firmware/samsung/exynos-acpm-protocol.h +++ b/include/linux/firmware/samsung/exynos-acpm-protocol.h @@ -40,9 +40,33 @@ struct acpm_pmic_ops { u8 value, u8 mask); }; =20 +struct acpm_tmu_ops { + int (*init)(const struct acpm_handle *handle, + unsigned int acpm_chan_id); + int (*read_temp)(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, int *temp); + int (*set_threshold)(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, + const u8 temperature[8], size_t tlen); + int (*set_hysteresis)(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, + const u8 hysteresis[8], size_t hlen); + int (*set_interrupt_enable)(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, u8 inten); + int (*tz_control)(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, bool enable); + int (*clear_tz_irq)(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz); + int (*suspend)(const struct acpm_handle *handle, + unsigned int acpm_chan_id); + int (*resume)(const struct acpm_handle *handle, + unsigned int acpm_chan_id); +}; + struct acpm_ops { struct acpm_dvfs_ops dvfs_ops; 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[35.240.102.164]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4356997e664sm20698421f8f.30.2026.01.19.04.08.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jan 2026 04:08:54 -0800 (PST) From: Tudor Ambarus Date: Mon, 19 Jan 2026 12:08:49 +0000 Subject: [PATCH v2 3/7] firmware: samsung: acpm: Add devm_acpm_get_by_phandle helper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-acpm-tmu-v2-3-e02a834f04c6@linaro.org> References: <20260119-acpm-tmu-v2-0-e02a834f04c6@linaro.org> In-Reply-To: <20260119-acpm-tmu-v2-0-e02a834f04c6@linaro.org> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Alim Akhtar , Bartlomiej Zolnierkiewicz , Kees Cook , "Gustavo A. R. Silva" , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= Cc: willmcvicker@google.com, jyescas@google.com, shin.son@samsung.com, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-hardening@vger.kernel.org, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768824532; l=2702; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=pykdip+kkXufUlfCYLkhdMwhxg3VFd8rMtL8HJrLcEc=; b=mq6tHfgFD5v+dBnv9e/9P/zH0n4O+kG2DeWw28a7k1Ie25bdm6byhx1O/Jsmir3D59rhSmRB2 PCtjiH30SmtCASeMud922mbZVmChdLaD2MzvcIIs6KDlOrDaN2jrrTO X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Introduce devm_acpm_get_by_phandle() to standardize how consumer drivers acquire a handle to the ACPM IPC interface. Enforce the use of the "samsung,acpm-ipc" property name across the SoC and simplify the boilerplate code in client drivers. Signed-off-by: Tudor Ambarus --- drivers/firmware/samsung/exynos-acpm.c | 23 ++++++++++++++++++= ++++ .../linux/firmware/samsung/exynos-acpm-protocol.h | 6 ++++++ 2 files changed, 29 insertions(+) diff --git a/drivers/firmware/samsung/exynos-acpm.c b/drivers/firmware/sams= ung/exynos-acpm.c index cc045370f4b0dc6ccea99e3c2d6f86a43b2e9671..cf849ba23f09d8b1e7f91734a0a= 1cc064f7407c7 100644 --- a/drivers/firmware/samsung/exynos-acpm.c +++ b/drivers/firmware/samsung/exynos-acpm.c @@ -776,6 +776,29 @@ const struct acpm_handle *devm_acpm_get_by_node(struct= device *dev, } EXPORT_SYMBOL_GPL(devm_acpm_get_by_node); =20 +/** + * devm_acpm_get_by_phandle - Resource managed lookup of the standardized + * "samsung,acpm-ipc" handle. + * @dev: consumer device + * + * Returns a pointer to the acpm_handle on success, or an ERR_PTR on failu= re. + */ +const struct acpm_handle *devm_acpm_get_by_phandle(struct device *dev) +{ + const struct acpm_handle *handle; + struct device_node *np; + + np =3D of_parse_phandle(dev->of_node, "samsung,acpm-ipc", 0); + if (!np) + return ERR_PTR(-ENODEV); + + handle =3D devm_acpm_get_by_node(dev, np); + of_node_put(np); + + return handle; +} +EXPORT_SYMBOL_GPL(devm_acpm_get_by_phandle); + static const struct acpm_match_data acpm_gs101 =3D { .initdata_base =3D ACPM_GS101_INITDATA_BASE, .acpm_clk_dev_name =3D "gs101-acpm-clk", diff --git a/include/linux/firmware/samsung/exynos-acpm-protocol.h b/includ= e/linux/firmware/samsung/exynos-acpm-protocol.h index 43d41e11ad2eb985e27a918ce3f9e9ac15a194ee..9485cdc1d91e86f9a9a8fc00722= f3313e3000c6a 100644 --- a/include/linux/firmware/samsung/exynos-acpm-protocol.h +++ b/include/linux/firmware/samsung/exynos-acpm-protocol.h @@ -82,6 +82,7 @@ struct device; #if IS_ENABLED(CONFIG_EXYNOS_ACPM_PROTOCOL) const struct acpm_handle *devm_acpm_get_by_node(struct device *dev, struct device_node *np); +const struct acpm_handle *devm_acpm_get_by_phandle(struct device *dev); #else =20 static inline const struct acpm_handle *devm_acpm_get_by_node(struct devic= e *dev, @@ -89,6 +90,11 @@ static inline const struct acpm_handle *devm_acpm_get_by= _node(struct device *dev { return NULL; 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[35.240.102.164]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4356997e664sm20698421f8f.30.2026.01.19.04.08.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jan 2026 04:08:55 -0800 (PST) From: Tudor Ambarus Date: Mon, 19 Jan 2026 12:08:50 +0000 Subject: [PATCH v2 4/7] thermal: samsung: Add support for GS101 TMU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-acpm-tmu-v2-4-e02a834f04c6@linaro.org> References: <20260119-acpm-tmu-v2-0-e02a834f04c6@linaro.org> In-Reply-To: <20260119-acpm-tmu-v2-0-e02a834f04c6@linaro.org> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Alim Akhtar , Bartlomiej Zolnierkiewicz , Kees Cook , "Gustavo A. R. Silva" , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= Cc: willmcvicker@google.com, jyescas@google.com, shin.son@samsung.com, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-hardening@vger.kernel.org, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768824532; l=19921; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=zoQOnSwC+2Ihs8FPFbdS+lFq+c7kQwUN5grvaAYMLVE=; b=k7IsR2vUDbTq2YdFfmnkeeIWwUNgT0gN4qYdJBp+6ioS3docBgUAkv219LIlo3k1Vfz1BeN/D /J3XFzhzYcjCWg5D0cQ6M/HMJt+A65j/jZxjSQIqUcz7MkwqfWbHxr9 X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add the thermal driver for the Google GS101 SoC. The GS101 TMU utilizes a hybrid management model shared between the Application Processor (AP) and the ACPM (Alive Clock and Power Manager) firmware. The driver maintains direct memory-mapped access to the TMU interrupt pending registers to identify thermal events, while delegating functional tasks - such as sensor initialization, threshold configuration, and temperature acquisition - to the ACPM firmware via the ACPM IPC protocol. Signed-off-by: Tudor Ambarus --- drivers/thermal/samsung/Kconfig | 16 + drivers/thermal/samsung/Makefile | 2 + drivers/thermal/samsung/acpm-tmu.c | 643 +++++++++++++++++++++++++++++++++= ++++ 3 files changed, 661 insertions(+) diff --git a/drivers/thermal/samsung/Kconfig b/drivers/thermal/samsung/Kcon= fig index f4eff5a41a84ce02b12abb85d6a0f8818031d0dc..5679dfa85f4079c7d40317ac231= bd6a1af93c7e7 100644 --- a/drivers/thermal/samsung/Kconfig +++ b/drivers/thermal/samsung/Kconfig @@ -9,3 +9,19 @@ config EXYNOS_THERMAL the TMU, reports temperature and handles cooling action if defined. This driver uses the Exynos core thermal APIs and TMU configuration data from the supported SoCs. + +config EXYNOS_ACPM_THERMAL + tristate "Exynos ACPM thermal management unit driver" + depends on THERMAL_OF + depends on EXYNOS_ACPM_PROTOCOL || (COMPILE_TEST && !EXYNOS_ACPM_PROTOCOL) + help + Support for the Thermal Management Unit (TMU) on Google GS101 SoC. + + The TMU on GS101 is managed through a hybrid architecture. This driver + handles direct register access for thermal interrupt status monitoring + and communicates with the Alive Clock and Power Manager (ACPM) + firmware via the ACPM IPC protocol for functional sensor control and + configuration. + + Select this if you want to monitor device temperature and enable + thermal mitigation on GS101 based devices. diff --git a/drivers/thermal/samsung/Makefile b/drivers/thermal/samsung/Mak= efile index f139407150d26940fc9ffcf000505cea4866223f..daed80647c349ba4f937ed8fbe6= be9df06c34aac 100644 --- a/drivers/thermal/samsung/Makefile +++ b/drivers/thermal/samsung/Makefile @@ -4,3 +4,5 @@ # obj-$(CONFIG_EXYNOS_THERMAL) +=3D exynos_thermal.o exynos_thermal-y :=3D exynos_tmu.o +obj-$(CONFIG_EXYNOS_ACPM_THERMAL) +=3D exynos_acpm_thermal.o +exynos_acpm_thermal-y :=3D acpm-tmu.o diff --git a/drivers/thermal/samsung/acpm-tmu.c b/drivers/thermal/samsung/a= cpm-tmu.c new file mode 100644 index 0000000000000000000000000000000000000000..9fbac174e554284ff0b8c0b188a= 44dcceee4c440 --- /dev/null +++ b/drivers/thermal/samsung/acpm-tmu.c @@ -0,0 +1,643 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2019 Samsung Electronics Co., Ltd. + * Copyright 2025 Google LLC. + * Copyright 2026 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../thermal_hwmon.h" + +#define EXYNOS_TMU_SENSOR(i) BIT(i) +#define EXYNOS_TMU_SENSORS_MAX_COUNT 16 + +#define GS101_CPUCL2_SENSOR_MASK (EXYNOS_TMU_SENSOR(0) | \ + EXYNOS_TMU_SENSOR(6) | \ + EXYNOS_TMU_SENSOR(7) | \ + EXYNOS_TMU_SENSOR(8) | \ + EXYNOS_TMU_SENSOR(9)) +#define GS101_CPUCL1_SENSOR_MASK (EXYNOS_TMU_SENSOR(4) | \ + EXYNOS_TMU_SENSOR(5)) +#define GS101_CPUCL0_SENSOR_MASK (EXYNOS_TMU_SENSOR(1) | \ + EXYNOS_TMU_SENSOR(2)) + +#define GS101_REG_INTPEND(i) ((i) * 0x50 + 0xf8) + +enum { + P0_INTPEND, + P1_INTPEND, + P2_INTPEND, + P3_INTPEND, + P4_INTPEND, + P5_INTPEND, + P6_INTPEND, + P7_INTPEND, + P8_INTPEND, + P9_INTPEND, + P10_INTPEND, + P11_INTPEND, + P12_INTPEND, + P13_INTPEND, + P14_INTPEND, + P15_INTPEND, + REG_INTPEND_COUNT, +}; + +struct acpm_tmu_sensor_group { + u16 mask; + u8 id; +}; + +struct acpm_tmu_sensor { + const struct acpm_tmu_sensor_group *group; + struct thermal_zone_device *tzd; + struct acpm_tmu_priv *priv; + struct mutex lock; /* protects sensor state */ + bool enabled; +}; + +struct acpm_tmu_priv { + struct regmap_field *regmap_fields[REG_INTPEND_COUNT]; + const struct acpm_handle *handle; + struct device *dev; + struct clk *clk; + unsigned int mbox_chan_id; + unsigned int num_sensors; + int irq; + struct acpm_tmu_sensor sensors[] __counted_by(num_sensors); +}; + +struct acpm_tmu_driver_data { + const struct reg_field *reg_fields; + const struct acpm_tmu_sensor_group *sensor_groups; + unsigned int num_sensor_groups; + unsigned int mbox_chan_id; +}; + +struct acpm_tmu_initialize_tripwalkdata { + unsigned char threshold[8]; + unsigned char hysteresis[8]; + unsigned char inten; + int i; +}; + +struct acpm_tmu_trip_temp_tripwalkdata { + const struct thermal_trip *trip; + unsigned char threshold[8]; + int temperature; + int i; +}; + +#define ACPM_TMU_SENSOR_GROUP(_mask, _id) \ + { \ + .mask =3D _mask, \ + .id =3D _id, \ + } + +static const struct acpm_tmu_sensor_group gs101_sensor_groups[] =3D { + ACPM_TMU_SENSOR_GROUP(GS101_CPUCL2_SENSOR_MASK, 0), + ACPM_TMU_SENSOR_GROUP(GS101_CPUCL1_SENSOR_MASK, 1), + ACPM_TMU_SENSOR_GROUP(GS101_CPUCL0_SENSOR_MASK, 2), +}; + +static const struct reg_field gs101_reg_fields[REG_INTPEND_COUNT] =3D { + [P0_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(0), 0, 31), + [P1_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(1), 0, 31), + [P2_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(2), 0, 31), + [P3_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(3), 0, 31), + [P4_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(4), 0, 31), + [P5_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(5), 0, 31), + [P6_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(6), 0, 31), + [P7_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(7), 0, 31), + [P8_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(8), 0, 31), + [P9_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(9), 0, 31), + [P10_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(10), 0, 31), + [P11_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(11), 0, 31), + [P12_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(12), 0, 31), + [P13_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(13), 0, 31), + [P14_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(14), 0, 31), + [P15_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(15), 0, 31), +}; + +static const struct regmap_config gs101_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .use_relaxed_mmio =3D true, + .max_register =3D GS101_REG_INTPEND(15), +}; + +static const struct acpm_tmu_driver_data acpm_tmu_gs101 =3D { + .reg_fields =3D gs101_reg_fields, + .sensor_groups =3D gs101_sensor_groups, + .num_sensor_groups =3D ARRAY_SIZE(gs101_sensor_groups), + .mbox_chan_id =3D 9, +}; + +static int acpm_tmu_op_tz_control(struct acpm_tmu_sensor *sensor, bool on) +{ + struct acpm_tmu_priv *priv =3D sensor->priv; + const struct acpm_handle *handle =3D priv->handle; + const struct acpm_tmu_ops *ops =3D &handle->ops.tmu; + int ret; + + ret =3D ops->tz_control(handle, priv->mbox_chan_id, sensor->group->id, + on); + if (ret) + return ret; + + sensor->enabled =3D on; + + return 0; +} + +static int acpm_tmu_control(struct acpm_tmu_priv *priv, bool on) +{ + struct device *dev =3D priv->dev; + int i, ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) + return ret; + + for (i =3D 0; i < priv->num_sensors; i++) { + struct acpm_tmu_sensor *sensor =3D &priv->sensors[i]; + + /* Skip sensors that weren't found in DT */ + if (!sensor->tzd) + continue; + + scoped_guard(mutex, &sensor->lock) { + ret =3D acpm_tmu_op_tz_control(sensor, on); + } + + if (ret) + goto out; + } + +out: + pm_runtime_put_autosuspend(dev); + return ret; +} + +static int acpm_tmu_get_temp(struct thermal_zone_device *tz, int *temp) +{ + struct acpm_tmu_sensor *sensor =3D thermal_zone_device_priv(tz); + struct acpm_tmu_priv *priv =3D sensor->priv; + const struct acpm_handle *handle =3D priv->handle; + const struct acpm_tmu_ops *ops =3D &handle->ops.tmu; + struct device *dev =3D priv->dev; + int acpm_temp, ret; + + if (!sensor->enabled) + return -EAGAIN; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) + return ret; + + scoped_guard(mutex, &sensor->lock) { + ret =3D ops->read_temp(handle, priv->mbox_chan_id, + sensor->group->id, &acpm_temp); + } + + pm_runtime_put_autosuspend(dev); + + if (ret) + return ret; + + *temp =3D acpm_temp * MILLIDEGREE_PER_DEGREE; + + return 0; +} + +static int acpm_tmu_trip_temp_walk_cb(struct thermal_trip *trip, void *dat= a) +{ + struct acpm_tmu_trip_temp_tripwalkdata * const twd =3D data; + int temperature; + + if (twd->i >=3D ARRAY_SIZE(twd->threshold)) + return -ERANGE; + + if (trip->type =3D=3D THERMAL_TRIP_PASSIVE) + goto out; + + temperature =3D (trip =3D=3D twd->trip) ? twd->temperature : trip->temper= ature; + + twd->threshold[twd->i] =3D temperature / MILLIDEGREE_PER_DEGREE; + +out: + ++twd->i; + return 0; +} + +static int acpm_tmu_set_trip_temp(struct thermal_zone_device *tz, + const struct thermal_trip *trip, int temperature) +{ + struct acpm_tmu_sensor *sensor =3D thermal_zone_device_priv(tz); + struct acpm_tmu_priv *priv =3D sensor->priv; + const struct acpm_handle *handle =3D priv->handle; + const struct acpm_tmu_ops *ops =3D &handle->ops.tmu; + struct device *dev =3D priv->dev; + struct acpm_tmu_trip_temp_tripwalkdata twd =3D { + .trip =3D trip, + .temperature =3D temperature, + }; + int ret; + + if (trip->type =3D=3D THERMAL_TRIP_PASSIVE) + return 0; + + for_each_thermal_trip(tz, acpm_tmu_trip_temp_walk_cb, &twd); + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + guard(mutex)(&sensor->lock); + + if (!sensor->enabled) { + ret =3D ops->set_threshold(handle, priv->mbox_chan_id, + sensor->group->id, twd.threshold, + ARRAY_SIZE(twd.threshold)); + goto out; + } + + ret =3D acpm_tmu_op_tz_control(sensor, false); + if (ret) + goto out; + + ret =3D ops->set_threshold(handle, priv->mbox_chan_id, sensor->group->id, + twd.threshold, ARRAY_SIZE(twd.threshold)); + if (ret) + goto out; + + ret =3D acpm_tmu_op_tz_control(sensor, true); + +out: + pm_runtime_put_autosuspend(dev); + return ret; +} + +static const struct thermal_zone_device_ops acpm_tmu_sensor_ops =3D { + .get_temp =3D acpm_tmu_get_temp, + .set_trip_temp =3D acpm_tmu_set_trip_temp, +}; + +static int acpm_tmu_has_pending_irq(struct acpm_tmu_sensor *sensor, + bool *pending_irq) +{ + struct acpm_tmu_priv *priv =3D sensor->priv; + unsigned long mask =3D sensor->group->mask; + int i, ret; + u32 val; + + guard(mutex)(&sensor->lock); + + for_each_set_bit(i, &mask, EXYNOS_TMU_SENSORS_MAX_COUNT) { + ret =3D regmap_field_read(priv->regmap_fields[i], &val); + if (ret) + return ret; + + if (val) { + *pending_irq =3D true; + break; + } + } + + return 0; +} + +static irqreturn_t acpm_tmu_thread_fn(int irq, void *id) +{ + struct acpm_tmu_priv *priv =3D id; + const struct acpm_handle *handle =3D priv->handle; + const struct acpm_tmu_ops *ops =3D &handle->ops.tmu; + struct device *dev =3D priv->dev; + int i, ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) { + dev_err(dev, "Failed to resume: %d\n", ret); + return IRQ_NONE; + } + + for (i =3D 0; i < priv->num_sensors; i++) { + struct acpm_tmu_sensor *sensor =3D &priv->sensors[i]; + bool pending_irq =3D false; + + if (!sensor->tzd) + continue; + + ret =3D acpm_tmu_has_pending_irq(sensor, &pending_irq); + if (ret || !pending_irq) + continue; + + thermal_zone_device_update(sensor->tzd, + THERMAL_EVENT_UNSPECIFIED); + + scoped_guard(mutex, &sensor->lock) { + ret =3D ops->clear_tz_irq(handle, priv->mbox_chan_id, + sensor->group->id); + if (ret) + dev_err(priv->dev, "Sensor %d: failed to clear IRQ (%d)\n", + i, ret); + } + } + + pm_runtime_put_autosuspend(dev); + + return IRQ_HANDLED; +} + +static int acpm_tmu_init_sensor(struct acpm_tmu_sensor *sensor, + const struct acpm_tmu_initialize_tripwalkdata *twd) +{ + struct acpm_tmu_priv *priv =3D sensor->priv; + const struct acpm_handle *handle =3D priv->handle; + const struct acpm_tmu_ops *ops =3D &handle->ops.tmu; + unsigned int mbox_chan_id =3D priv->mbox_chan_id; + u8 acpm_sensor_id =3D sensor->group->id; + int ret; + + guard(mutex)(&sensor->lock); + + ret =3D ops->set_threshold(handle, mbox_chan_id, acpm_sensor_id, + twd->threshold, + ARRAY_SIZE(twd->threshold)); + if (ret) + return ret; + + ret =3D ops->set_hysteresis(handle, mbox_chan_id, acpm_sensor_id, + twd->hysteresis, + ARRAY_SIZE(twd->threshold)); + if (ret) + return ret; + + ret =3D ops->set_interrupt_enable(handle, mbox_chan_id, acpm_sensor_id, + twd->inten); + return ret; +} + +static int acpm_tmu_initialize_walk_cb(struct thermal_trip *trip, void *da= ta) +{ + struct acpm_tmu_initialize_tripwalkdata * const twd =3D data; + int i; + + if (twd->i >=3D ARRAY_SIZE(twd->threshold)) + return -ERANGE; + + if (trip->type =3D=3D THERMAL_TRIP_PASSIVE) + goto out; + + i =3D twd->i; + + twd->threshold[i] =3D trip->temperature / MILLIDEGREE_PER_DEGREE; + twd->hysteresis[i] =3D trip->hysteresis / MILLIDEGREE_PER_DEGREE; + + twd->inten |=3D BIT(i); + +out: + ++twd->i; + return 0; +} + +static int acpm_tmu_init_sensors(struct acpm_tmu_priv *priv) +{ + int i, ret; + + for (i =3D 0; i < priv->num_sensors; i++) { + struct acpm_tmu_sensor *sensor =3D &priv->sensors[i]; + struct acpm_tmu_initialize_tripwalkdata twd =3D {}; + + /* Skip sensors that weren't found in DT */ + if (!sensor->tzd) + continue; + + thermal_zone_for_each_trip(sensor->tzd, + acpm_tmu_initialize_walk_cb, &twd); + + ret =3D acpm_tmu_init_sensor(sensor, &twd); + if (ret) + return ret; + } + + return 0; +} + +static const struct of_device_id acpm_tmu_match[] =3D { + { .compatible =3D "google,gs101-tmu-top" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, acpm_tmu_match); + +static int acpm_tmu_probe(struct platform_device *pdev) +{ + const struct acpm_tmu_driver_data *data =3D &acpm_tmu_gs101; + const struct acpm_handle *acpm_handle; + struct device *dev =3D &pdev->dev; + struct acpm_tmu_priv *priv; + struct regmap *regmap; + void __iomem *base; + int i, ret; + + acpm_handle =3D devm_acpm_get_by_phandle(dev); + if (IS_ERR(acpm_handle)) + return dev_err_probe(dev, PTR_ERR(acpm_handle), + "Failed to get ACPM handle\n"); + + priv =3D devm_kzalloc(dev, + struct_size(priv, sensors, data->num_sensor_groups), + GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev =3D dev; + priv->handle =3D acpm_handle; + priv->mbox_chan_id =3D data->mbox_chan_id; + priv->num_sensors =3D data->num_sensor_groups; + + platform_set_drvdata(pdev, priv); + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return dev_err_probe(dev, PTR_ERR(base), "Failed to ioremap resource\n"); + + regmap =3D devm_regmap_init_mmio(dev, base, &gs101_regmap_config); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), "Failed to init regmap\n"); + + ret =3D devm_regmap_field_bulk_alloc(dev, regmap, priv->regmap_fields, + data->reg_fields, REG_INTPEND_COUNT); + if (ret) + return dev_err_probe(dev, ret, + "Unable to map syscon registers\n"); + + priv->clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) + return dev_err_probe(dev, PTR_ERR(priv->clk), + "Failed to get the clock\n"); + + priv->irq =3D platform_get_irq(pdev, 0); + if (priv->irq < 0) + return dev_err_probe(dev, priv->irq, "Failed to get irq\n"); + + ret =3D devm_request_threaded_irq(dev, priv->irq, NULL, + acpm_tmu_thread_fn, IRQF_ONESHOT, + dev_name(dev), priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to request irq\n"); + + pm_runtime_set_autosuspend_delay(dev, 100); + pm_runtime_use_autosuspend(dev); + + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable runtime PM\n"); + + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to resume device\n"); + + ret =3D acpm_handle->ops.tmu.init(acpm_handle, priv->mbox_chan_id); + if (ret) { + ret =3D dev_err_probe(dev, ret, "Failed to init TMU\n"); + goto err_pm_put; + } + + for (i =3D 0; i < priv->num_sensors; i++) { + struct acpm_tmu_sensor *sensor =3D &priv->sensors[i]; + + mutex_init(&sensor->lock); + sensor->group =3D &data->sensor_groups[i]; + sensor->priv =3D priv; + + sensor->tzd =3D devm_thermal_of_zone_register(dev, i, sensor, + &acpm_tmu_sensor_ops); + if (IS_ERR(sensor->tzd)) { + ret =3D PTR_ERR(sensor->tzd); + if (ret =3D=3D -ENODEV) { + sensor->tzd =3D NULL; + dev_dbg(dev, "Sensor %d not used in DT, skipping\n", i); + continue; + } + + ret =3D dev_err_probe(dev, ret, "Failed to register sensor %d\n", i); + goto err_pm_put; + } + + ret =3D devm_thermal_add_hwmon_sysfs(dev, sensor->tzd); + if (ret) + dev_warn(dev, "Failed to add hwmon sysfs!\n"); + } + + ret =3D acpm_tmu_init_sensors(priv); + if (ret) { + ret =3D dev_err_probe(dev, ret, "Failed to init sensors\n"); + goto err_pm_put; + } + + ret =3D acpm_tmu_control(priv, true); + if (ret) { + ret =3D dev_err_probe(dev, ret, "Failed to enable TMU\n"); + goto err_pm_put; + } + + pm_runtime_put_autosuspend(&pdev->dev); + + return 0; + +err_pm_put: + pm_runtime_put_sync(dev); + return ret; +} + +static void acpm_tmu_remove(struct platform_device *pdev) +{ + struct acpm_tmu_priv *priv =3D platform_get_drvdata(pdev); + + /* Stop IRQ first to prevent race with thread_fn */ + disable_irq(priv->irq); + + acpm_tmu_control(priv, false); +} + +static int acpm_tmu_suspend(struct device *dev) +{ + struct acpm_tmu_priv *priv =3D dev_get_drvdata(dev); + const struct acpm_handle *handle =3D priv->handle; + const struct acpm_tmu_ops *ops =3D &handle->ops.tmu; + int ret; + + ret =3D acpm_tmu_control(priv, false); + if (ret) + return ret; + + /* APB clock not required for this specific msg */ + return ops->suspend(handle, priv->mbox_chan_id); +} + +static int acpm_tmu_resume(struct device *dev) +{ + struct acpm_tmu_priv *priv =3D dev_get_drvdata(dev); + const struct acpm_handle *handle =3D priv->handle; + const struct acpm_tmu_ops *ops =3D &handle->ops.tmu; + int ret; + + /* APB clock not required for this specific msg */ + ret =3D ops->resume(handle, priv->mbox_chan_id); + if (ret) + return ret; + + return acpm_tmu_control(priv, true); +} + +static int acpm_tmu_runtime_suspend(struct device *dev) +{ + struct acpm_tmu_priv *priv =3D dev_get_drvdata(dev); + + clk_disable_unprepare(priv->clk); + + return 0; +} + +static int acpm_tmu_runtime_resume(struct device *dev) +{ + struct acpm_tmu_priv *priv =3D dev_get_drvdata(dev); + + return clk_prepare_enable(priv->clk); +} + +static const struct dev_pm_ops acpm_tmu_pm_ops =3D { + SYSTEM_SLEEP_PM_OPS(acpm_tmu_suspend, acpm_tmu_resume) + RUNTIME_PM_OPS(acpm_tmu_runtime_suspend, acpm_tmu_runtime_resume, NULL) +}; + +static struct platform_driver acpm_tmu_driver =3D { + .driver =3D { + .name =3D "gs-tmu", + .pm =3D pm_ptr(&acpm_tmu_pm_ops), + .of_match_table =3D acpm_tmu_match, + }, + .probe =3D acpm_tmu_probe, + .remove =3D acpm_tmu_remove, +}; +module_platform_driver(acpm_tmu_driver); + +MODULE_AUTHOR("Tudor Ambarus "); +MODULE_DESCRIPTION("Samsung Exynos ACPM TMU Driver"); +MODULE_LICENSE("GPL"); --=20 2.52.0.457.g6b5491de43-goog From nobody Sun Feb 8 13:53:09 2026 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C916435A928 for ; Mon, 19 Jan 2026 12:08:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768824541; cv=none; b=fz34z6YVKPGuJOTh+3Y1xDsCrr7kCTAAeE/76h7K4M/JTi05rQ3Z2eXbFEQFNjotFecjSnVX08tbxVDLeFFZL5p+bWGyAD4gikvk1/lmJm/RysMVEJp8+Q7i0lNde/iOWMWj9dzAFUpSglTfZrlDyFjI4UBdOgpgHdgNm5bVX1c= ARC-Message-Signature: i=1; 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Silva" , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= Cc: willmcvicker@google.com, jyescas@google.com, shin.son@samsung.com, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-hardening@vger.kernel.org, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768824532; l=971; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=7HVJFrG3U/QwDFKx95QyYbsMuRfAm1hbMd+GcbM229I=; b=TlBEnMuauOll69kA3Iht1mp8Vn36O+nZ27Yqrrl+ucAF9TVN0wbdHvi0EFHd/dHU17mHdXaSU xi2wLoqH9f+D/9H1BB1EA+6a5jaXfj1M4JXToWWKa7JZ7HltBPIb1du X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add a MAINTAINERS entry for the Samsung Exynos ACPM thermal driver. Signed-off-by: Tudor Ambarus --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5b11839cba9de1e9e43f63787578edd8c429ca39..ab44f2de8e8e03ad9bb022ebdf1= b6c0058fb0425 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23171,6 +23171,14 @@ F: drivers/clk/samsung/clk-acpm.c F: drivers/firmware/samsung/exynos-acpm* F: include/linux/firmware/samsung/exynos-acpm-protocol.h =20 +SAMSUNG EXYNOS ACPM THERMAL DRIVER +M: Tudor Ambarus +L: linux-kernel@vger.kernel.org +L: linux-samsung-soc@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/thermal/google,gs101-tmu-top.yaml +F: drivers/thermal/samsung/acpm-tmu.c + SAMSUNG EXYNOS MAILBOX DRIVER M: Tudor Ambarus L: linux-kernel@vger.kernel.org --=20 2.52.0.457.g6b5491de43-goog From nobody Sun Feb 8 13:53:09 2026 Received: from mail-wr1-f68.google.com (mail-wr1-f68.google.com [209.85.221.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13FC7359FBB for ; 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[35.240.102.164]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4356997e664sm20698421f8f.30.2026.01.19.04.08.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jan 2026 04:08:57 -0800 (PST) From: Tudor Ambarus Date: Mon, 19 Jan 2026 12:08:52 +0000 Subject: [PATCH v2 6/7] arm64: dts: exynos: gs101: Add thermal management unit Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-acpm-tmu-v2-6-e02a834f04c6@linaro.org> References: <20260119-acpm-tmu-v2-0-e02a834f04c6@linaro.org> In-Reply-To: <20260119-acpm-tmu-v2-0-e02a834f04c6@linaro.org> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Alim Akhtar , Bartlomiej Zolnierkiewicz , Kees Cook , "Gustavo A. R. Silva" , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= Cc: willmcvicker@google.com, jyescas@google.com, shin.son@samsung.com, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-hardening@vger.kernel.org, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768824532; l=8775; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=FbDNXAgPAAbLgVJFNLv0wQaisif895tAwODlc1nDIio=; b=qx+povYGdT0SCFv279IfjgdUWsxoqkhWF6qHZZALvaE22fhrYKhuXAxLzfU98oDlk5mXUiVBU t7OehfZc22vAY1BC+MzyyBUIR9n0Zis/U51nv9beTQD7+vsnuAuPZdD X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add the Thermal Management Unit (TMU) support for the Google GS101 SoC. Describe the TMU using a consolidated SoC node that includes memory resources for interrupt identification and a phandle to the ACPM IPC interface for functional control. Define thermal zones for the little, mid, and big CPU clusters, including associated trip points and cooling-device maps to enable thermal mitigation. Signed-off-by: Tudor Ambarus --- arch/arm64/boot/dts/exynos/google/gs101-tmu.dtsi | 209 +++++++++++++++++++= ++++ arch/arm64/boot/dts/exynos/google/gs101.dtsi | 18 ++ 2 files changed, 227 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101-tmu.dtsi b/arch/arm64/= boot/dts/exynos/google/gs101-tmu.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..6262c3b890aa2f7ad572c32b30b= f926df804ec1e --- /dev/null +++ b/arch/arm64/boot/dts/exynos/google/gs101-tmu.dtsi @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Google GS101 TMU configurations device tree source + * + * Copyright 2020 Samsung Electronics Co., Ltd. + * Copyright 2020 Google LLC. + * Copyright 2026 Linaro Ltd. + */ + +#include + +/ { + thermal-zones { + cpucl2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 0>; + + trips { + big_cold: big-cold { + temperature =3D <20000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + big_switch_on: big-switch-on { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + + big_control_temp: big-control-temp { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + big_pre_switch_on: big-pre-switch-on { + temperature =3D <55000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + + big_alert2: big-alert2 { + temperature =3D <95000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + big_hw_throttling: big-hw-throttling { + temperature =3D <103000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + big_pause: big-pause { + temperature =3D <108000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + big_hot: big-hot { + temperature =3D <115000>; + hysteresis =3D <3000>; + type =3D "hot"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&big_control_temp>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpucl1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 1>; + + trips { + mid_cold: mid-cold { + temperature =3D <20000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + mid_switch_on: mid-switch-on { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + + mid_control_temp: mid-control-temp { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + mid_pre_switch_on: mid-pre-switch-on { + temperature =3D <55000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + + mid_alert2: mid-alert2 { + temperature =3D <95000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + mid_hw_throttling: mid-hw-throttling { + temperature =3D <98000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + mid_pause: mid-pause { + temperature =3D <108000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + mid_hot: mid-hot { + temperature =3D <115000>; + hysteresis =3D <3000>; + type =3D "hot"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&mid_control_temp>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpucl0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 2>; + + trips { + little_cold: little-cold { + temperature =3D <20000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + little_switch_on: little-switch-on { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + + little_control_temp: little-control-temp { + temperature =3D <95000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + little_pre_switch_on: little-pre-switch-on { + temperature =3D <55000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + + little_alert2: little-alert2 { + temperature =3D <100000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + little_alert5: little-alert5 { + temperature =3D <103000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + little_alert6: little-alert6 { + temperature =3D <110000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + little_hot: little-hot { + temperature =3D <115000>; + hysteresis =3D <3000>; + type =3D "hot"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&little_control_temp>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + }; +}; diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index d085f9fb0f62ac2f57b104c20880e64d885d0bee..4b8c7edaddb6fd49e61496f2f21= f348db0b58f10 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -74,6 +74,7 @@ cpu0: cpu@0 { compatible =3D "arm,cortex-a55"; reg =3D <0x0000>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -86,6 +87,7 @@ cpu1: cpu@100 { compatible =3D "arm,cortex-a55"; reg =3D <0x0100>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -98,6 +100,7 @@ cpu2: cpu@200 { compatible =3D "arm,cortex-a55"; reg =3D <0x0200>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -110,6 +113,7 @@ cpu3: cpu@300 { compatible =3D "arm,cortex-a55"; reg =3D <0x0300>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -122,6 +126,7 @@ cpu4: cpu@400 { compatible =3D "arm,cortex-a76"; reg =3D <0x0400>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&enyo_cpu_sleep>; capacity-dmips-mhz =3D <620>; @@ -134,6 +139,7 @@ cpu5: cpu@500 { compatible =3D "arm,cortex-a76"; reg =3D <0x0500>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&enyo_cpu_sleep>; capacity-dmips-mhz =3D <620>; @@ -146,6 +152,7 @@ cpu6: cpu@600 { compatible =3D "arm,cortex-x1"; reg =3D <0x0600>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL2>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&hera_cpu_sleep>; capacity-dmips-mhz =3D <1024>; @@ -158,6 +165,7 @@ cpu7: cpu@700 { compatible =3D "arm,cortex-x1"; reg =3D <0x0700>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL2>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&hera_cpu_sleep>; capacity-dmips-mhz =3D <1024>; @@ -639,6 +647,15 @@ watchdog_cl1: watchdog@10070000 { status =3D "disabled"; }; =20 + tmu_top: thermal-sensor@100a0000 { + compatible =3D "google,gs101-tmu-top"; + reg =3D <0x100a0000 0x800>; + clocks =3D <&cmu_misc CLK_GOUT_MISC_TMU_TOP_PCLK>; + interrupts =3D ; + samsung,acpm-ipc =3D <&acpm_ipc>; + #thermal-sensor-cells =3D <1>; + }; + trng: rng@10141400 { compatible =3D "google,gs101-trng", "samsung,exynos850-trng"; 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[35.240.102.164]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4356997e664sm20698421f8f.30.2026.01.19.04.08.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jan 2026 04:08:57 -0800 (PST) From: Tudor Ambarus Date: Mon, 19 Jan 2026 12:08:53 +0000 Subject: [PATCH v2 7/7] arm64: defconfig: enable Exynos ACPM thermal support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260119-acpm-tmu-v2-7-e02a834f04c6@linaro.org> References: <20260119-acpm-tmu-v2-0-e02a834f04c6@linaro.org> In-Reply-To: <20260119-acpm-tmu-v2-0-e02a834f04c6@linaro.org> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Alim Akhtar , Bartlomiej Zolnierkiewicz , Kees Cook , "Gustavo A. R. Silva" , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= Cc: willmcvicker@google.com, jyescas@google.com, shin.son@samsung.com, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-hardening@vger.kernel.org, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768824532; l=868; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=glFQ4Oo7aFXvg4qCxUzDyhw63Eric2ZNI22jQtPmJhg=; b=jGWmIQ3VJe/OIr58mGBQinzVZCX659HJK8MtuuaHM01fhgkcacEuB8bWVtLq4hLL7aAt8CY7o ND/UZrRnDGbDYAMpf2MIYS7MwKUlOKLihzJnMnIfQ6vWHwzkx5s2HTQ X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Enable the Exynos ACPM thermal driver (CONFIG_EXYNOS_ACPM_THERMAL) to allow temperature monitoring and thermal management on Samsung Exynos SoCs that use the Alive Clock and Power Manager (ACPM) protocol. Signed-off-by: Tudor Ambarus --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 45288ec9eaf7365427d98195c48e2f8065a8bb1b..68fefe4bf49501500362fcb0b49= 0a684ea469b26 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -752,6 +752,7 @@ CONFIG_BCM2711_THERMAL=3Dm CONFIG_BCM2835_THERMAL=3Dm CONFIG_BRCMSTB_THERMAL=3Dm CONFIG_EXYNOS_THERMAL=3Dy +CONFIG_EXYNOS_ACPM_THERMAL=3Dm CONFIG_TEGRA_SOCTHERM=3Dm CONFIG_TEGRA_BPMP_THERMAL=3Dm CONFIG_GENERIC_ADC_THERMAL=3Dm --=20 2.52.0.457.g6b5491de43-goog