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[94.59.215.181]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4801e879542sm112402295e9.4.2026.01.17.12.19.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Jan 2026 12:19:26 -0800 (PST) From: "Anton D. Stavinskii" Date: Sun, 18 Jan 2026 00:18:53 +0400 Subject: [PATCH v2 1/7] dt-bindings: sound: sophgo: add CV1800B I2S/TDM controller binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260118-cv1800b-i2s-driver-v2-1-d10055f68368@gmail.com> References: <20260118-cv1800b-i2s-driver-v2-0-d10055f68368@gmail.com> In-Reply-To: <20260118-cv1800b-i2s-driver-v2-0-d10055f68368@gmail.com> To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Jaroslav Kysela , Takashi Iwai , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-sound@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, "Anton D. Stavinskii" X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768681160; l=2586; i=stavinsky@gmail.com; s=20260115; h=from:subject:message-id; bh=xkpcY06T5wFRQA45eU8MgJ1mdP3AEvbYjLzx5NAKsb4=; b=pC6DV7GcI29FzrC3Bw4ofC67X6yqQvXg4mNStfo506jWw3oV/KO8EwPu9xuatoEK/rpgZTG54 zNxte7NQmWECIAwaPL6+eJ/2yQ9EfbdX8Lgg30Tihx77gEimpIQSPnn X-Developer-Key: i=stavinsky@gmail.com; a=ed25519; pk=2WxGZ1zd1vQwSPFCSks6zrADqUDBUdtq39lElk4ZE7Q= Purpose: introduce DT schema for the CPU driver The driver uses dma to transfer data. The dma it self has 8 channels. Each channel can be connected only to a specific i2s node. But each of dma channel can have multiple purposes so in order to save dma channels the configurations allows to use tx and rx, only rx, only tx or none channels. I2S controller without channels can be useful in configuration where I2S is used as clock source only and doesn't produce any data. Signed-off-by: Anton D. Stavinskii --- .../bindings/sound/sophgo,cv1800b-i2s.yaml | 75 ++++++++++++++++++= ++++ 1 file changed, 75 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/sophgo,cv1800b-i2s.yam= l b/Documentation/devicetree/bindings/sound/sophgo,cv1800b-i2s.yaml new file mode 100644 index 000000000000..cf30880a62da --- /dev/null +++ b/Documentation/devicetree/bindings/sound/sophgo,cv1800b-i2s.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/sophgo,cv1800b-i2s.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo CV1800B I2S/TDM controller + +maintainers: + - Anton D. Stavinskii + +description: | + I2S/TDM controller found in CV1800B / Sophgo SG2002/SG2000 SoCs. + +properties: + compatible: + const: sophgo,cv1800b-i2s + + reg: + maxItems: 1 + + "#sound-dai-cells": + const: 0 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + items: + - const: i2s + - const: mclk + + dmas: + maxItems: 2 + + dma-names: + description: | + Names of DMA channels. May be omitted. If present, one entry + selects a single direction, while two entries select RX and TX. + minItems: 1 + maxItems: 2 + items: + enum: [rx, tx] + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - "#sound-dai-cells" + +additionalProperties: false + +examples: + - | + #include + + i2s1: i2s@4110000 { + compatible =3D "sophgo,cv1800b-i2s"; + reg =3D <0x04110000 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk CLK_APB_I2S1>, <&clk CLK_SDMA_AUD1>; + clock-names =3D "i2s", "mclk"; + dmas =3D <&dmamux 2 1>, <&dmamux 3 1>; + dma-names =3D "rx", "tx"; + }; +... --=20 2.43.0 From nobody Sun Feb 8 12:20:22 2026 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 421322E6CDF for ; Sat, 17 Jan 2026 20:19:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768681176; cv=none; b=gRiXeW65dA1FJ6WRTt9vaCn5kz6/Ay7mw2MVlBdP9MlAuHRMd3qhxIPrFN5Ppm5wxI1ydWslocw57if+u6p4tyDHKWgqFWueuEJc2Ygv8SYqUWisYWfXfNOjc0J0oNYgjr1ucNc/UjtHX0QlTAr2N7g2iRkDsANO33/+3gkveCM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768681176; c=relaxed/simple; bh=YK8sOyjxEj2clVOTBQVKHJUKu6xazJnb6+5ewohsv7w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VVgGBEMEmr2bDoi9uG3ImGtGsG1Lh9kHDKAy8waC1K+k8pzpLtKHRxahSbJabzfemucK4pDHRKyTYqCNGYA6oDrhcZs5KHK9X8kX419PjOJKr3yiroLf7W0yZow6A0TCx+3tdYcsF31UlQv/5sdo+cn0PV1/bdQBrO9sTnKJRZ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Y3MMEeQ8; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Y3MMEeQ8" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-4801eb2c0a5so14211585e9.3 for ; Sat, 17 Jan 2026 12:19:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1768681170; x=1769285970; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=qdtTggWtSnqWuzAEcucgKQmIhwVjy7+q/2HYsV8qzdU=; b=Y3MMEeQ82Xs0Edr2X40kCzsa30AQGEvmOsPTKjxm6fQyxPw/+GTJVV8ZUHl6rkUwfj hBxFuifjuGzm7xm/DdyUZw6wn/XaFx8aIxy2Fg85uZ33iDm9+g8DNAsueI2IInxAFn9t 0R0/magN5nlUmg+anjmFpw89MxE7Oktu77ksGRwa/BUG/uiCdpMul+8+pDAAKVYA2hUF N4VDWtstJi3payoL0IwJqzoReS8zzexAbrQvP7IG8rt6Iqtf/JPimd3R1SUDkGdADVYS FtS7SJDEj8PrwPnJ4NksajVGgzi1Z3+XRWyovJLirEZ6p9U4IAro93EdVM4WqtYVXa70 H0bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768681170; x=1769285970; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=qdtTggWtSnqWuzAEcucgKQmIhwVjy7+q/2HYsV8qzdU=; b=f+0JfMVS0MX+R1PtuQB7X0vg2iFaeN4Q9/XmJA7END8sDBPCE57uefyLIn3hWdvD3n ssqbdr/OdEb9tisoKeXwtj8U7X5iE/DJwVNgasZlrc6hoD6vgPKlUKw43mDR1NWegSEJ VHqJ5GPmUni8v8lZK9W2TfkJEUdJXLaBNoIhVVxuqjoTj5LqH1l3vV06lmV06wpfNTcK 6qX+D0NO0rlolOrI/BU9WXIaGJDS5GT9lBurhkEZI3zzXh+9JoBFWoy7zLmTxrJo6p/D An0QlkkybXAsIpGdWzp/EAjdTi+fBal39PZmB2dM7B91ZQb8aGemXdeUKtxyWMiwnwpZ EwZw== X-Forwarded-Encrypted: i=1; AJvYcCURaPekPSnuBYRd4wjjibX1PRRZWWHE0GiyNbapi9CoywoVYNAVFl2iXIofptjoc7SyiTWrkE6rpjP2q9U=@vger.kernel.org X-Gm-Message-State: AOJu0Ywkh9eqFlk8+8iVNfO5fccaoW51YfSsXVEaoTjYs3NIFKHkBllA b3EgVxU2B8jMLui0S15NJfRrpTv8FBZxUx/v2nVlsoe6xLdc67y3cUfq77U4PCXZ X-Gm-Gg: AY/fxX6lTt5IupMDGWSYBDUaJ3eiluAZFv3Zd5EQpa/Gv4m0EkHq0lNUYIovjVqkLv6 DDuDvwGnRDVgNxD3YPi76sipWX6JqC4um52rp/z4IX/2IUUHooVsTixKYcbYEggRBnzX6qNkjV5 9z2fhD7IC8pjyyxrLr352/EvGvWh6kTHPYSvVyvAmhTLZPGepGbA6ow/TXi104XYuO7w/lVh8Gm iWVSgwWCi/cE/2iHs0TC/lOYJFsl499Wtb5rZvx5osDTW1kclfM1ZaD9fwCBOBfDTtBVPHpGW5u ZZdMqR5LckbH6CJi07d2TmEfTzWiH76ewNi2QqDzYMJZZqUhTkeoaPdNTP3d+ToRGz6s51dW+eg CBA3ZGbUlWGo46hiRdVAITIzI2yctohxpJonnZQGSZn1I+H6ek6d28Zh5AJU3i97T5SrLVNnvH3 UF4r7bh7g2q4gYXwxALrcgQIbQ2bBXqVOzLfhmBtxLOYFU X-Received: by 2002:a05:600c:4695:b0:477:b734:8c52 with SMTP id 5b1f17b1804b1-4801e2fec26mr94737935e9.14.1768681170061; Sat, 17 Jan 2026 12:19:30 -0800 (PST) Received: from [127.0.1.1] (bba-94-59-215-181.alshamil.net.ae. [94.59.215.181]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4801e879542sm112402295e9.4.2026.01.17.12.19.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Jan 2026 12:19:29 -0800 (PST) From: "Anton D. Stavinskii" Date: Sun, 18 Jan 2026 00:18:54 +0400 Subject: [PATCH v2 2/7] ASoC: sophgo: add CV1800B I2S/TDM controller driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260118-cv1800b-i2s-driver-v2-2-d10055f68368@gmail.com> References: <20260118-cv1800b-i2s-driver-v2-0-d10055f68368@gmail.com> In-Reply-To: <20260118-cv1800b-i2s-driver-v2-0-d10055f68368@gmail.com> To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Jaroslav Kysela , Takashi Iwai , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-sound@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, "Anton D. Stavinskii" X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768681160; l=24524; i=stavinsky@gmail.com; s=20260115; h=from:subject:message-id; bh=YK8sOyjxEj2clVOTBQVKHJUKu6xazJnb6+5ewohsv7w=; b=JKBx/zbgf8UC7YFMY6pof1lkp3fPalOXNP33M97Zu70ELTqjnOFe8pMEWQYPJ/VYGQjSCHaS3 eJuEFxTd5jQCm3aIS074BOqLrjdKZuchNPgam0rZBvouD2zxktPSUU5 X-Developer-Key: i=stavinsky@gmail.com; a=ed25519; pk=2WxGZ1zd1vQwSPFCSks6zrADqUDBUdtq39lElk4ZE7Q= The actual CPU DAI controller. The driver can be used with simple-audio-card. It respects fixed clock configuration from simple-audio-card. The card driver can request direction out, this will be interpreted as mclk out, the clock which can be used in other CPU or codecs. For example I2S3 generates clock for ADC. I2S was tested in S24_32 and S16 dual channel formats. Signed-off-by: Anton D. Stavinskii --- sound/soc/Kconfig | 1 + sound/soc/Makefile | 1 + sound/soc/sophgo/Kconfig | 20 ++ sound/soc/sophgo/Makefile | 3 + sound/soc/sophgo/cv1800b-tdm.c | 714 +++++++++++++++++++++++++++++++++++++= ++++ 5 files changed, 739 insertions(+) diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig index 36e0d443ba0e..edfdcbf734fe 100644 --- a/sound/soc/Kconfig +++ b/sound/soc/Kconfig @@ -127,6 +127,7 @@ source "sound/soc/renesas/Kconfig" source "sound/soc/rockchip/Kconfig" source "sound/soc/samsung/Kconfig" source "sound/soc/sdca/Kconfig" +source "sound/soc/sophgo/Kconfig" source "sound/soc/spacemit/Kconfig" source "sound/soc/spear/Kconfig" source "sound/soc/sprd/Kconfig" diff --git a/sound/soc/Makefile b/sound/soc/Makefile index 8c0480e6484e..21d8406767fc 100644 --- a/sound/soc/Makefile +++ b/sound/soc/Makefile @@ -70,6 +70,7 @@ obj-$(CONFIG_SND_SOC) +=3D rockchip/ obj-$(CONFIG_SND_SOC) +=3D samsung/ obj-$(CONFIG_SND_SOC) +=3D sdca/ obj-$(CONFIG_SND_SOC) +=3D sof/ +obj-$(CONFIG_SND_SOC) +=3D sophgo/ obj-$(CONFIG_SND_SOC) +=3D spacemit/ obj-$(CONFIG_SND_SOC) +=3D spear/ obj-$(CONFIG_SND_SOC) +=3D sprd/ diff --git a/sound/soc/sophgo/Kconfig b/sound/soc/sophgo/Kconfig new file mode 100644 index 000000000000..70f07d46c810 --- /dev/null +++ b/sound/soc/sophgo/Kconfig @@ -0,0 +1,20 @@ +menu "Sophgo" + depends on COMPILE_TEST || ARCH_SOPHGO + +config SND_SOC_CV1800B_TDM + tristate "Sophgo CV1800B I2S/TDM support" + depends on SND_SOC && OF + select SND_SOC_GENERIC_DMAENGINE_PCM + help + This option enables the I2S/TDM audio controller found in Sophgo + CV1800B / SG2002 SoCs. The controller supports standard I2S + audio modes for playback and capture. + + The driver integrates with the ASoC framework and uses the DMA + engine for audio data transfer. It is intended to be configured + via Device Tree along with simple-audio-card module. + + To compile the driver as a module, choose M here: the module will + be called cv1800b_tdm. + +endmenu diff --git a/sound/soc/sophgo/Makefile b/sound/soc/sophgo/Makefile new file mode 100644 index 000000000000..3f9f1d07227a --- /dev/null +++ b/sound/soc/sophgo/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +# Sophgo Platform Support +obj-$(CONFIG_SND_SOC_CV1800B_TDM) +=3D cv1800b-tdm.o diff --git a/sound/soc/sophgo/cv1800b-tdm.c b/sound/soc/sophgo/cv1800b-tdm.c new file mode 100644 index 000000000000..5bd9236ef3b9 --- /dev/null +++ b/sound/soc/sophgo/cv1800b-tdm.c @@ -0,0 +1,714 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define TX_FIFO_SIZE (1024) +#define RX_FIFO_SIZE (1024) +#define TX_MAX_BURST (8) +#define RX_MAX_BURST (8) + +#define CV1800B_DEF_FREQ 24576000 +#define CV1800B_DEF_MCLK_FS_RATIO 256 + +/* tdm registers */ +#define CV1800B_BLK_MODE_SETTING 0x000 +#define CV1800B_FRAME_SETTING 0x004 +#define CV1800B_SLOT_SETTING1 0x008 +#define CV1800B_SLOT_SETTING2 0x00C +#define CV1800B_DATA_FORMAT 0x010 +#define CV1800B_BLK_CFG 0x014 +#define CV1800B_I2S_ENABLE 0x018 +#define CV1800B_I2S_RESET 0x01C +#define CV1800B_I2S_INT_EN 0x020 +#define CV1800B_I2S_INT 0x024 +#define CV1800B_FIFO_THRESHOLD 0x028 +#define CV1800B_LRCK_MASTER 0x02C /* special clock only mode */ +#define CV1800B_FIFO_RESET 0x030 +#define CV1800B_RX_STATUS 0x040 +#define CV1800B_TX_STATUS 0x048 +#define CV1800B_CLK_CTRL0 0x060 +#define CV1800B_CLK_CTRL1 0x064 +#define CV1800B_PCM_SYNTH 0x068 +#define CV1800B_RX_RD_PORT 0x080 +#define CV1800B_TX_WR_PORT 0x0C0 + +/* CV1800B_BLK_MODE_SETTING (0x000) */ +#define BLK_TX_MODE_MASK GENMASK(0, 0) +#define BLK_MASTER_MODE_MASK GENMASK(1, 1) +#define BLK_DMA_MODE_MASK GENMASK(7, 7) + +/* CV1800B_CLK_CTRL1 (0x064) */ +#define CLK_MCLK_DIV_MASK GENMASK(15, 0) +#define CLK_BCLK_DIV_MASK GENMASK(31, 16) + +/* CV1800B_CLK_CTRL0 (0x060) */ +#define CLK_AUD_CLK_SEL_MASK GENMASK(0, 0) +#define CLK_BCLK_OUT_CLK_FORCE_EN_MASK GENMASK(6, 6) +#define CLK_MCLK_OUT_EN_MASK GENMASK(7, 7) +#define CLK_AUD_EN_MASK GENMASK(8, 8) + +/* CV1800B_I2S_RESET (0x01C) */ +#define RST_I2S_RESET_RX_MASK GENMASK(0, 0) +#define RST_I2S_RESET_TX_MASK GENMASK(1, 1) + +/* CV1800B_FIFO_RESET (0x030) */ +#define FIFO_RX_RESET_MASK GENMASK(0, 0) +#define FIFO_TX_RESET_MASK GENMASK(16, 16) + +/* CV1800B_I2S_ENABLE (0x018) */ +#define I2S_ENABLE_MASK GENMASK(0, 0) + +/* CV1800B_BLK_CFG (0x014) */ +#define BLK_AUTO_DISABLE_WITH_CH_EN_MASK GENMASK(4, 4) +#define BLK_RX_BLK_CLK_FORCE_EN_MASK GENMASK(8, 8) +#define BLK_RX_FIFO_DMA_CLK_FORCE_EN_MASK GENMASK(9, 9) +#define BLK_TX_BLK_CLK_FORCE_EN_MASK GENMASK(16, 16) +#define BLK_TX_FIFO_DMA_CLK_FORCE_EN_MASK GENMASK(17, 17) + +/* CV1800B_FRAME_SETTING (0x004) */ +#define FRAME_LENGTH_MASK GENMASK(8, 0) +#define FS_ACTIVE_LENGTH_MASK GENMASK(23, 16) + +/* CV1800B_I2S_INT_EN (0x020) */ +#define INT_I2S_INT_EN_MASK GENMASK(8, 8) + +/* CV1800B_SLOT_SETTING2 (0x00C) */ +#define SLOT_EN_MASK GENMASK(15, 0) + +/* CV1800B_LRCK_MASTER (0x02C) */ +#define LRCK_MASTER_ENABLE_MASK GENMASK(0, 0) + +/* CV1800B_DATA_FORMAT (0x010) */ +#define DF_WORD_LENGTH_MASK GENMASK(2, 1) +#define DF_TX_SOURCE_LEFT_ALIGN_MASK GENMASK(6, 6) + +/* CV1800B_FIFO_THRESHOLD (0x028) */ +#define FIFO_RX_THRESHOLD_MASK GENMASK(4, 0) +#define FIFO_TX_THRESHOLD_MASK GENMASK(20, 16) +#define FIFO_TX_HIGH_THRESHOLD_MASK GENMASK(28, 24) + +/* CV1800B_SLOT_SETTING1 (0x008) */ +#define SLOT_NUM_MASK GENMASK(3, 0) +#define SLOT_SIZE_MASK GENMASK(13, 8) +#define DATA_SIZE_MASK GENMASK(20, 16) +#define FB_OFFSET_MASK GENMASK(28, 24) + +enum cv1800b_tdm_word_length { + CV1800B_WORD_LENGTH_8_BIT =3D 0, + CV1800B_WORD_LENGTH_16_BIT =3D 1, + CV1800B_WORD_LENGTH_32_BIT =3D 2, +}; + +struct cv1800b_i2s { + void __iomem *base; + struct clk *clk; + struct clk *sysclk; + struct device *dev; + struct snd_dmaengine_dai_dma_data playback_dma; + struct snd_dmaengine_dai_dma_data capture_dma; + u32 mclk_rate; + bool bclk_ratio_fixed; + u32 bclk_ratio; + +}; + +static void cv1800b_setup_dma_struct(struct cv1800b_i2s *i2s, + phys_addr_t phys_base) +{ + i2s->playback_dma.addr =3D phys_base + CV1800B_TX_WR_PORT; + i2s->playback_dma.addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; + i2s->playback_dma.fifo_size =3D TX_FIFO_SIZE; + i2s->playback_dma.maxburst =3D TX_MAX_BURST; + + i2s->capture_dma.addr =3D phys_base + CV1800B_RX_RD_PORT; + i2s->capture_dma.addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; + i2s->capture_dma.fifo_size =3D RX_FIFO_SIZE; + i2s->capture_dma.maxburst =3D RX_MAX_BURST; +} + +static const struct snd_dmaengine_pcm_config cv1800b_i2s_pcm_config =3D { + .prepare_slave_config =3D snd_dmaengine_pcm_prepare_slave_config, +}; + +static void cv1800b_reset_fifo(struct cv1800b_i2s *i2s) +{ + u32 val; + + val =3D readl(i2s->base + CV1800B_FIFO_RESET); + val =3D u32_replace_bits(val, 1, FIFO_RX_RESET_MASK); + val =3D u32_replace_bits(val, 1, FIFO_TX_RESET_MASK); + writel(val, i2s->base + CV1800B_FIFO_RESET); + + usleep_range(10, 20); + + val =3D readl(i2s->base + CV1800B_FIFO_RESET); + val =3D u32_replace_bits(val, 0, FIFO_RX_RESET_MASK); + val =3D u32_replace_bits(val, 0, FIFO_TX_RESET_MASK); + writel(val, i2s->base + CV1800B_FIFO_RESET); +} + +static void cv1800b_reset_i2s(struct cv1800b_i2s *i2s) +{ + u32 val; + + val =3D readl(i2s->base + CV1800B_I2S_RESET); + val =3D u32_replace_bits(val, 1, RST_I2S_RESET_RX_MASK); + val =3D u32_replace_bits(val, 1, RST_I2S_RESET_TX_MASK); + writel(val, i2s->base + CV1800B_I2S_RESET); + + usleep_range(10, 20); + + val =3D readl(i2s->base + CV1800B_I2S_RESET); + val =3D u32_replace_bits(val, 0, RST_I2S_RESET_RX_MASK); + val =3D u32_replace_bits(val, 0, RST_I2S_RESET_TX_MASK); + writel(val, i2s->base + CV1800B_I2S_RESET); +} + +static void cv1800b_set_mclk_div(struct cv1800b_i2s *i2s, u32 mclk_div) +{ + u32 val; + + val =3D readl(i2s->base + CV1800B_CLK_CTRL1); + val =3D u32_replace_bits(val, mclk_div, CLK_MCLK_DIV_MASK); + writel(val, i2s->base + CV1800B_CLK_CTRL1); + dev_dbg(i2s->dev, "mclk_div is set to %u\n", mclk_div); +} + +static void cv1800b_set_tx_mode(struct cv1800b_i2s *i2s, bool is_tx) +{ + u32 val; + + val =3D readl(i2s->base + CV1800B_BLK_MODE_SETTING); + val =3D u32_replace_bits(val, is_tx, BLK_TX_MODE_MASK); + writel(val, i2s->base + CV1800B_BLK_MODE_SETTING); + dev_dbg(i2s->dev, "tx_mode is set to %u\n", is_tx); +} + +static int cv1800b_set_bclk_div(struct cv1800b_i2s *i2s, u32 bclk_div) +{ + u32 val; + + if (bclk_div =3D=3D 0 || bclk_div > 0xFFFF) + return -EINVAL; + + val =3D readl(i2s->base + CV1800B_CLK_CTRL1); + val =3D u32_replace_bits(val, bclk_div, CLK_BCLK_DIV_MASK); + writel(val, i2s->base + CV1800B_CLK_CTRL1); + dev_dbg(i2s->dev, "bclk_div is set to %u\n", bclk_div); + return 0; +} + +/* set memory width of audio data , reg word_length */ +static int cv1800b_set_word_length(struct cv1800b_i2s *i2s, + unsigned int physical_width) +{ + u8 word_length_val; + u32 val; + + switch (physical_width) { + case 8: + word_length_val =3D CV1800B_WORD_LENGTH_8_BIT; + break; + case 16: + word_length_val =3D CV1800B_WORD_LENGTH_16_BIT; + break; + case 32: + word_length_val =3D CV1800B_WORD_LENGTH_32_BIT; + break; + default: + dev_dbg(i2s->dev, "can't set word_length field\n"); + return -EINVAL; + } + + val =3D readl(i2s->base + CV1800B_DATA_FORMAT); + val =3D u32_replace_bits(val, word_length_val, DF_WORD_LENGTH_MASK); + writel(val, i2s->base + CV1800B_DATA_FORMAT); + return 0; +} + +static void cv1800b_enable_clocks(struct cv1800b_i2s *i2s, bool enabled) +{ + u32 val; + + val =3D readl(i2s->base + CV1800B_CLK_CTRL0); + val =3D u32_replace_bits(val, enabled, CLK_AUD_EN_MASK); + writel(val, i2s->base + CV1800B_CLK_CTRL0); +} + +static int cv1800b_set_slot_settings(struct cv1800b_i2s *i2s, u32 slots, + u32 physical_width, u32 data_size) +{ + u32 slot_num; + u32 slot_size; + u32 frame_length; + u32 frame_active_length; + u32 val; + + if (!slots || !physical_width || !data_size) { + dev_err(i2s->dev, "frame or slot settings are not valid\n"); + return -EINVAL; + } + if (slots > 16 || physical_width > 64 || data_size > 32) { + dev_err(i2s->dev, "frame or slot settings are not valid\n"); + return -EINVAL; + } + + slot_num =3D slots - 1; + slot_size =3D physical_width - 1; + frame_length =3D (physical_width * slots) - 1; + frame_active_length =3D physical_width - 1; + + if (frame_length > 511 || frame_active_length > 255) { + dev_err(i2s->dev, "frame or slot settings are not valid\n"); + return -EINVAL; + } + + val =3D readl(i2s->base + CV1800B_SLOT_SETTING1); + val =3D u32_replace_bits(val, slot_size, SLOT_SIZE_MASK); + val =3D u32_replace_bits(val, data_size - 1, DATA_SIZE_MASK); + val =3D u32_replace_bits(val, slot_num, SLOT_NUM_MASK); + writel(val, i2s->base + CV1800B_SLOT_SETTING1); + + val =3D readl(i2s->base + CV1800B_FRAME_SETTING); + val =3D u32_replace_bits(val, frame_length, FRAME_LENGTH_MASK); + val =3D u32_replace_bits(val, frame_active_length, FS_ACTIVE_LENGTH_MASK); + writel(val, i2s->base + CV1800B_FRAME_SETTING); + + dev_dbg(i2s->dev, "slot settings num: %u width: %u\n", slots, physical_wi= dth); + return 0; +} + +/* + * calculate mclk_div. + * if requested value is bigger than optimal + * leave mclk_div as 1. cff clock is capable + * to handle it + */ +static int cv1800b_calc_mclk_div(unsigned int target_mclk, u32 *mclk_div) +{ + *mclk_div =3D 1; + + if (target_mclk =3D=3D 0) + return -EINVAL; + + /* optimal parent frequency is close to CV1800B_DEF_FREQ */ + if (target_mclk < CV1800B_DEF_FREQ) { + *mclk_div =3D DIV_ROUND_CLOSEST(CV1800B_DEF_FREQ, target_mclk); + if (!*mclk_div || *mclk_div > 0xFFFF) + return -EINVAL; + } + return 0; +} + +/* + * set CCF clock and divider for this clock + * mclk_clock =3D ccf_clock / mclk_div + */ +static int cv1800b_i2s_set_rate_for_mclk(struct cv1800b_i2s *i2s, + unsigned int target_mclk) +{ + u32 mclk_div =3D 1; + u64 tmp; + int ret; + unsigned long clk_rate; + unsigned long actual; + + ret =3D cv1800b_calc_mclk_div(target_mclk, &mclk_div); + if (ret) { + dev_dbg(i2s->dev, "can't calc mclk_div for freq %u\n", + target_mclk); + return ret; + } + + tmp =3D (u64)target_mclk * mclk_div; + if (tmp > ULONG_MAX) { + dev_err(i2s->dev, "clk_rate overflow: freq=3D%u div=3D%u\n", + target_mclk, mclk_div); + return -ERANGE; + } + + clk_rate =3D (unsigned long)tmp; + + cv1800b_enable_clocks(i2s, false); + + ret =3D clk_set_rate(i2s->sysclk, clk_rate); + if (ret) + return ret; + + actual =3D clk_get_rate(i2s->sysclk); + if (clk_rate !=3D actual) { + dev_err_ratelimited(i2s->dev, + "clk_set_rate failed %lu, actual is %lu\n", + clk_rate, actual); + } + + cv1800b_set_mclk_div(i2s, mclk_div); + cv1800b_enable_clocks(i2s, true); + + return 0; +} + +static int cv1800b_i2s_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct cv1800b_i2s *i2s =3D snd_soc_dai_get_drvdata(dai); + unsigned int rate =3D params_rate(params); + unsigned int channels =3D params_channels(params); + unsigned int physical_width =3D params_physical_width(params); + int data_width =3D params_width(params); + bool tx_mode =3D (substream->stream =3D=3D SNDRV_PCM_STREAM_PLAYBACK) ? 1= : 0; + int ret; + u32 bclk_div; + u32 bclk_ratio; + u32 mclk_rate; + u64 tmp; + + if (data_width < 0) + return data_width; + + if (!channels || !rate || !physical_width) + return -EINVAL; + + ret =3D cv1800b_set_slot_settings(i2s, channels, physical_width, data_wid= th); + if (ret) + return ret; + + if (i2s->mclk_rate) { + mclk_rate =3D i2s->mclk_rate; + } else { + dev_dbg(i2s->dev, "mclk is not set by machine driver\n"); + ret =3D cv1800b_i2s_set_rate_for_mclk(i2s, + rate * CV1800B_DEF_MCLK_FS_RATIO); + if (ret) + return ret; + mclk_rate =3D rate * CV1800B_DEF_MCLK_FS_RATIO; + } + + bclk_ratio =3D (i2s->bclk_ratio_fixed) ? i2s->bclk_ratio : + (physical_width * channels); + + tmp =3D (u64)rate * bclk_ratio; + if (!tmp) + return -EINVAL; + if (mclk_rate % tmp) + dev_warn(i2s->dev, "mclk rate is not aligned to bclk or rate\n"); + + bclk_div =3D DIV_ROUND_CLOSEST((u64)mclk_rate, tmp); + + ret =3D cv1800b_set_bclk_div(i2s, bclk_div); + if (ret) + return ret; + + ret =3D cv1800b_set_word_length(i2s, physical_width); + if (ret) + return ret; + + cv1800b_set_tx_mode(i2s, tx_mode); + + cv1800b_reset_fifo(i2s); + cv1800b_reset_i2s(i2s); + return 0; +} + +static int cv1800b_i2s_trigger(struct snd_pcm_substream *substream, int cm= d, + struct snd_soc_dai *dai) +{ + struct cv1800b_i2s *i2s =3D snd_soc_dai_get_drvdata(dai); + u32 val; + + val =3D readl(i2s->base + CV1800B_I2S_ENABLE); + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + val =3D u32_replace_bits(val, 1, I2S_ENABLE_MASK); + break; + + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + val =3D u32_replace_bits(val, 0, I2S_ENABLE_MASK); + break; + default: + return -EINVAL; + } + writel(val, i2s->base + CV1800B_I2S_ENABLE); + return 0; +} + +static int cv1800b_i2s_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd =3D snd_soc_substream_to_rtd(substream); + struct cv1800b_i2s *i2s =3D snd_soc_dai_get_drvdata(dai); + struct snd_soc_dai_link *dai_link =3D rtd->dai_link; + + dev_dbg(i2s->dev, "%s: dai=3D%s substream=3D%d\n", __func__, dai->name, + substream->stream); + /** + * Ensure DMA is stopped before DAI + * shutdown (prevents DW AXI DMAC stop/busy on next open). + */ + dai_link->trigger_stop =3D SND_SOC_TRIGGER_ORDER_LDC; + return 0; +} + +static int cv1800b_i2s_dai_probe(struct snd_soc_dai *dai) +{ + struct cv1800b_i2s *i2s =3D snd_soc_dai_get_drvdata(dai); + + if (!i2s) { + dev_err(dai->dev, "no drvdata in DAI probe\n"); + return -ENODEV; + } + + snd_soc_dai_init_dma_data(dai, &i2s->playback_dma, &i2s->capture_dma); + return 0; +} + +static int cv1800b_i2s_dai_set_fmt(struct snd_soc_dai *dai, unsigned int f= mt) +{ + struct cv1800b_i2s *i2s =3D snd_soc_dai_get_drvdata(dai); + u32 val; + u32 master; + + /* only i2s format is supported */ + if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) !=3D SND_SOC_DAIFMT_I2S) + return -EINVAL; + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBP_CFP: + dev_dbg(i2s->dev, "set to master mode\n"); + master =3D 1; + break; + + case SND_SOC_DAIFMT_CBC_CFC: + dev_dbg(i2s->dev, "set to slave mode\n"); + master =3D 0; + break; + default: + return -EINVAL; + } + + val =3D readl(i2s->base + CV1800B_BLK_MODE_SETTING); + val =3D u32_replace_bits(val, master, BLK_MASTER_MODE_MASK); + writel(val, i2s->base + CV1800B_BLK_MODE_SETTING); + return 0; +} + +static int cv1800b_i2s_dai_set_bclk_ratio(struct snd_soc_dai *dai, + unsigned int ratio) +{ + struct cv1800b_i2s *i2s =3D snd_soc_dai_get_drvdata(dai); + + if (ratio =3D=3D 0) + return -EINVAL; + i2s->bclk_ratio =3D ratio; + i2s->bclk_ratio_fixed =3D true; + return 0; +} + +static int cv1800b_i2s_dai_set_sysclk(struct snd_soc_dai *dai, int clk_id, + unsigned int freq, int dir) +{ + struct cv1800b_i2s *i2s =3D snd_soc_dai_get_drvdata(dai); + int ret; + u32 val; + bool output_enable =3D (dir =3D=3D SND_SOC_CLOCK_OUT) ? true : false; + + dev_dbg(i2s->dev, "%s called with %u\n", __func__, freq); + ret =3D cv1800b_i2s_set_rate_for_mclk(i2s, freq); + if (ret) + return ret; + + val =3D readl(i2s->base + CV1800B_CLK_CTRL0); + val =3D u32_replace_bits(val, output_enable, CLK_MCLK_OUT_EN_MASK); + writel(val, i2s->base + CV1800B_CLK_CTRL0); + + i2s->mclk_rate =3D freq; + return 0; +} + +static const struct snd_soc_dai_ops cv1800b_i2s_dai_ops =3D { + .probe =3D cv1800b_i2s_dai_probe, + .startup =3D cv1800b_i2s_startup, + .hw_params =3D cv1800b_i2s_hw_params, + .trigger =3D cv1800b_i2s_trigger, + .set_fmt =3D cv1800b_i2s_dai_set_fmt, + .set_bclk_ratio =3D cv1800b_i2s_dai_set_bclk_ratio, + .set_sysclk =3D cv1800b_i2s_dai_set_sysclk, +}; + +static struct snd_soc_dai_driver cv1800b_i2s_dai_template =3D { + .name =3D "cv1800b-i2s", + .playback =3D { + .stream_name =3D "Playback", + .channels_min =3D 1, + .channels_max =3D 2, + .rates =3D SNDRV_PCM_RATE_8000_192000, + .formats =3D SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE, + }, + .capture =3D { + .stream_name =3D "Capture", + .channels_min =3D 1, + .channels_max =3D 2, + .rates =3D SNDRV_PCM_RATE_8000_192000, + .formats =3D SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE, + }, + .ops =3D &cv1800b_i2s_dai_ops, +}; + +static const struct snd_soc_component_driver cv1800b_i2s_component =3D { + .name =3D "cv1800b-i2s", +}; + +static void cv1800b_i2s_hw_disable(struct cv1800b_i2s *i2s) +{ + u32 val; + + val =3D readl(i2s->base + CV1800B_I2S_ENABLE); + val =3D u32_replace_bits(val, 0, I2S_ENABLE_MASK); + writel(val, i2s->base + CV1800B_I2S_ENABLE); + + val =3D readl(i2s->base + CV1800B_CLK_CTRL0); + val =3D u32_replace_bits(val, 0, CLK_AUD_EN_MASK); + val =3D u32_replace_bits(val, 0, CLK_MCLK_OUT_EN_MASK); + writel(val, i2s->base + CV1800B_CLK_CTRL0); + + val =3D readl(i2s->base + CV1800B_I2S_RESET); + val =3D u32_replace_bits(val, 1, RST_I2S_RESET_RX_MASK); + val =3D u32_replace_bits(val, 1, RST_I2S_RESET_TX_MASK); + writel(val, i2s->base + CV1800B_I2S_RESET); + + val =3D readl(i2s->base + CV1800B_FIFO_RESET); + val =3D u32_replace_bits(val, 1, FIFO_RX_RESET_MASK); + val =3D u32_replace_bits(val, 1, FIFO_TX_RESET_MASK); + writel(val, i2s->base + CV1800B_FIFO_RESET); +} + +static void cv1800b_i2s_setup_tdm(struct cv1800b_i2s *i2s) +{ + u32 val; + + val =3D readl(i2s->base + CV1800B_BLK_MODE_SETTING); + val =3D u32_replace_bits(val, 1, BLK_DMA_MODE_MASK); + writel(val, i2s->base + CV1800B_BLK_MODE_SETTING); + + val =3D readl(i2s->base + CV1800B_CLK_CTRL0); + val =3D u32_replace_bits(val, 0, CLK_AUD_CLK_SEL_MASK); + val =3D u32_replace_bits(val, 0, CLK_MCLK_OUT_EN_MASK); + val =3D u32_replace_bits(val, 0, CLK_AUD_EN_MASK); + writel(val, i2s->base + CV1800B_CLK_CTRL0); + + val =3D readl(i2s->base + CV1800B_FIFO_THRESHOLD); + val =3D u32_replace_bits(val, 4, FIFO_RX_THRESHOLD_MASK); + val =3D u32_replace_bits(val, 4, FIFO_TX_THRESHOLD_MASK); + val =3D u32_replace_bits(val, 4, FIFO_TX_HIGH_THRESHOLD_MASK); + writel(val, i2s->base + CV1800B_FIFO_THRESHOLD); + + val =3D readl(i2s->base + CV1800B_I2S_ENABLE); + val =3D u32_replace_bits(val, 0, I2S_ENABLE_MASK); + writel(val, i2s->base + CV1800B_I2S_ENABLE); +} + +static int cv1800b_i2s_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct cv1800b_i2s *i2s; + struct resource *res; + void __iomem *regs; + struct snd_soc_dai_driver *dai; + int ret; + + i2s =3D devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL); + if (!i2s) + return -ENOMEM; + + regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) + return PTR_ERR(regs); + i2s->dev =3D &pdev->dev; + i2s->base =3D regs; + + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + cv1800b_setup_dma_struct(i2s, res->start); + + i2s->clk =3D devm_clk_get_enabled(dev, "i2s"); + if (IS_ERR(i2s->clk)) + return dev_err_probe(dev, PTR_ERR(i2s->clk), + "failed to get+enable i2s\n"); + i2s->sysclk =3D devm_clk_get_enabled(dev, "mclk"); + if (IS_ERR(i2s->sysclk)) + return dev_err_probe(dev, PTR_ERR(i2s->sysclk), + "failed to get+enable mclk\n"); + + platform_set_drvdata(pdev, i2s); + cv1800b_i2s_setup_tdm(i2s); + + dai =3D devm_kmemdup(dev, &cv1800b_i2s_dai_template, sizeof(*dai), + GFP_KERNEL); + if (!dai) + return -ENOMEM; + + ret =3D devm_snd_soc_register_component(dev, &cv1800b_i2s_component, dai, + 1); + if (ret) + return ret; + + ret =3D devm_snd_dmaengine_pcm_register(dev, &cv1800b_i2s_pcm_config, 0); + if (ret) { + dev_err(dev, "dmaengine_pcm_register failed: %d\n", ret); + return ret; + } + + dev_dbg(dev, "cv1800b I2S probed:\n"); + return 0; +} + +static void cv1800b_i2s_remove(struct platform_device *pdev) +{ + struct cv1800b_i2s *i2s =3D platform_get_drvdata(pdev); + + if (!i2s) + return; + cv1800b_i2s_hw_disable(i2s); +} + +static const struct of_device_id cv1800b_i2s_of_match[] =3D { + { .compatible =3D "sophgo,cv1800b-i2s" }, + { /* sentinel */ } +}; + +MODULE_DEVICE_TABLE(of, cv1800b_i2s_of_match); + +static struct platform_driver cv1800b_i2s_driver =3D { + .probe =3D cv1800b_i2s_probe, + .remove =3D cv1800b_i2s_remove, + .driver =3D { + .name =3D "cv1800b-i2s", + .of_match_table =3D cv1800b_i2s_of_match, + }, +}; +module_platform_driver(cv1800b_i2s_driver); + +MODULE_DESCRIPTION("Sophgo cv1800b I2S/TDM driver"); +MODULE_AUTHOR("Anton D. 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[94.59.215.181]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4801e879542sm112402295e9.4.2026.01.17.12.19.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Jan 2026 12:19:32 -0800 (PST) From: "Anton D. Stavinskii" Date: Sun, 18 Jan 2026 00:18:55 +0400 Subject: [PATCH v2 3/7] dt-bindings: sound: sophgo: add CV1800B internal ADC codec Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260118-cv1800b-i2s-driver-v2-3-d10055f68368@gmail.com> References: <20260118-cv1800b-i2s-driver-v2-0-d10055f68368@gmail.com> In-Reply-To: <20260118-cv1800b-i2s-driver-v2-0-d10055f68368@gmail.com> To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Jaroslav Kysela , Takashi Iwai , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-sound@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, "Anton D. Stavinskii" X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768681160; l=1630; i=stavinsky@gmail.com; s=20260115; h=from:subject:message-id; bh=dLNnA22RKAohaAguDDfnNkXyaGGOSbGYv0h2Zz9YQM0=; b=EeFcn+GCVjQQk9AlKztuSLRvUBU20OcxJTOUV5Zv62e8woM+6/UmsJtbuI2XJHrjfsIZYIG4g pEFujRYgLMPBsgyOGXn6+QLsWcx6nO8e2+oHmZSTG4XSGcGekrlC1RN X-Developer-Key: i=stavinsky@gmail.com; a=ed25519; pk=2WxGZ1zd1vQwSPFCSks6zrADqUDBUdtq39lElk4ZE7Q= Document the internal ADC audio codec integrated in the Sophgo CV1800B SoC. Signed-off-by: Anton D. Stavinskii --- .../bindings/sound/sophgo,cv1800b-sound-adc.yaml | 43 ++++++++++++++++++= ++++ 1 file changed, 43 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/sophgo,cv1800b-sound-a= dc.yaml b/Documentation/devicetree/bindings/sound/sophgo,cv1800b-sound-adc.= yaml new file mode 100644 index 000000000000..339b60e317e8 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/sophgo,cv1800b-sound-adc.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/sophgo,cv1800b-sound-adc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo CV1800B Internal ADC Codec + +maintainers: + - Anton D. Stavinskii + +description: | + Internal ADC audio codec integrated in the Sophgo CV1800B SoC. + The codec exposes a single DAI and is intended to be connected + to an I2S/TDM controller via an ASoC machine driver. + +properties: + compatible: + const: sophgo,cv1800b-sound-adc + + reg: + maxItems: 1 + description: + Base address and size of the ADC register block. + + "#sound-dai-cells": + const: 0 + +required: + - compatible + - reg + - "#sound-dai-cells" + +additionalProperties: false + +examples: + - | + audio-codec@300a100 { + compatible =3D "sophgo,cv1800b-sound-adc"; + reg =3D <0x0300a100 0x100>; + #sound-dai-cells =3D <0>; + }; +... --=20 2.43.0 From nobody Sun Feb 8 12:20:22 2026 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0EA82E7F0A for ; Sat, 17 Jan 2026 20:19:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768681183; cv=none; b=e37S2vBcnQpZdXmB6NY5Z60RQaHBgUAAzqfsQ7oIasWd/6AuQrg7yoyNLM01fuHg3Y7nUMfcXLcE6jIv8G5IOOFowgfwSsjZvs0ZKmaBVegF3hJH4YBfVIpbCsXsFQ5KgaP8qKilZQ2lB1A65cfBzqDTKARZEv+VPMWnXoWFwG4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768681183; c=relaxed/simple; bh=yoqDZc5ZVlZgdU+bd4E5tzHezHO66wUqbgpf8bFY4E4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hSHImcaVq521V1Rmsjcsg/veoUZxNFkEdW19fS6i4daQs7P4iHP3JIKh1UtpsnB1qvJPsuRxuQKv1TBcW8gUwPPuKBRzHAeBabIKS+YiijwEgC52Y4N0c/4rUdDJcoFSTRlTB7rHwCxUwKiAjpLmCgnTq71KIHUpiYMwV0MiWSA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=nNZWdZi8; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="nNZWdZi8" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-4801d98cf39so11815765e9.1 for ; Sat, 17 Jan 2026 12:19:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1768681177; x=1769285977; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=M+UkR1HZFum2uQlZYRs91yhhWbIXUBFNThSz2GGApOk=; b=nNZWdZi8SU/dlCIEuO1egPGoswDy6CucbgOha+hOqot0PrXtLwsTMAvO03eTxkAG9O BdtP15FrlHbvUnZJULJSCLh5v9S7hxJ/PSXgVZt3l3zlC2Z8dQ2FHnmC5vv+0PCpgAKl Rt1Hu6iwp+BkLcmy8SN0OV3Ftipr7/bEZyMTUIrvVtCyjqopO8T8/kUbcI6Zoghb6e5i kOOqutUGyT2+3Xctjuw/0bfQqUDfA7PT4cuIuMUcEk+f7fJ5NYZGYiwgtYjjpK6/nzdb 650Z41sG03inwm3Otku9nkkRSyia0Sir2ftLnoeiTBZ818hY83wfvmojzbmPpR0l0Vw3 Yi/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768681177; x=1769285977; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=M+UkR1HZFum2uQlZYRs91yhhWbIXUBFNThSz2GGApOk=; b=PE81cw0Cnd8dj0y2U3wG0ORVn39Jo7wtnWB++ZLRgSKvZ3jToeKWbRYF/520DefvqW phwpXpnJFHfODhjZmBIVKvRJih/wOca5Du/wJn3mQ8p3iMfofGwfEePN6qQ+m2FATB2H 4xNoZpGR12gNNvW64ODe5uC8LrTEjPQScKGVTxogcmR0noCpDT4It3Zwv3ilkjF3WfPk /zBOlWOn/7joIcozzS/zSDvTIK2G113ZZezRlYQLSCb6bu8L7WMFfA0inhLunpk/nJ/G Ldxt12OQiVPRq9+SNLqcnXsWX0DpcW6WHCNK3FLq5m2y3ud0bGt0pyOR0yUMtiBix0NQ lE1g== X-Forwarded-Encrypted: i=1; AJvYcCVQQ3c7zyKTkke2uFnRxRVQuzUEYX3zPElJzJQCNDjBC7Xvw/DWw9mQrOdqDt+VKg1I+2dBz+LCLaojW1w=@vger.kernel.org X-Gm-Message-State: AOJu0Yw3HPYvyJjnVqIgXlSL4Se/8Nj2geYOJplAUfIjd76rpZbLXiw0 G+8IMRap9zTw9QHRPhPRZQ2DQzdd8eqBuDsNlU3pClh9bXxeoH/CkPJUDXstyDjw X-Gm-Gg: AY/fxX5BE/r6cEkYu9Yr5vPuMRU1fQ6rHMD+D7iFoWWeFtEzMvb8j6hlX1zHMIpMHSF x5An9IKbyOinQ0ednk+L1V8eMx974uW0fH8KkoUh5TxxCXTvMAZitwh5T/GQuLxmpjgZzNqL0Zf TZ+XHiim5AfNStX0fY5MehTDVP5MsAMoXWmyORuXIPVvm86oIa94KkyLUpILDwtDW/5CIuSCcqL FaiIyfRf4OIttAp0bsGWDlh5DrQUf0kDv5wmyzdSbCchum/pyk/cBOjR8yZUjraf0XPa8dR5rGD Rsl3Wdxyh3LzYgCrwD8ucowXA0vMTVRJ+U79Baixy9urpVONyfsURJVBHzJHCv5xT9/qkFQtxss PdcsfoO9iCT9/IyxoEO5mnU8JNMvRhWXeDTE1Q6dYocHBhsuzx5waKlUeIX6CNqmSOAuiwKOljA dPa+h/joagRXvBrXhfD4rzespqQhitKzyj9/0AwymBIii35i4QZME+Q1A= X-Received: by 2002:a05:600c:a009:b0:475:dd9a:f791 with SMTP id 5b1f17b1804b1-4801eb0ef0bmr62487135e9.28.1768681176483; Sat, 17 Jan 2026 12:19:36 -0800 (PST) Received: from [127.0.1.1] (bba-94-59-215-181.alshamil.net.ae. [94.59.215.181]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4801e879542sm112402295e9.4.2026.01.17.12.19.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Jan 2026 12:19:36 -0800 (PST) From: "Anton D. Stavinskii" Date: Sun, 18 Jan 2026 00:18:56 +0400 Subject: [PATCH v2 4/7] ASoC: sophgo: add CV1800B internal ADC codec driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260118-cv1800b-i2s-driver-v2-4-d10055f68368@gmail.com> References: <20260118-cv1800b-i2s-driver-v2-0-d10055f68368@gmail.com> In-Reply-To: <20260118-cv1800b-i2s-driver-v2-0-d10055f68368@gmail.com> To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Jaroslav Kysela , Takashi Iwai , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-sound@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, "Anton D. Stavinskii" X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768681160; l=11247; i=stavinsky@gmail.com; s=20260115; h=from:subject:message-id; bh=yoqDZc5ZVlZgdU+bd4E5tzHezHO66wUqbgpf8bFY4E4=; b=Kh3fdLaX4mnHZSrSNmx5C/yL+afTAzTi84PHGn/Q2uCiR3cSfuRe7KJiZvTBMw0s+/RANKNEz qLuXaWzmsl8CQcS8U2Xh8OCgN/Ht/G5jgeywp1j+hpJtSs2i2nBGF5Y X-Developer-Key: i=stavinsky@gmail.com; a=ed25519; pk=2WxGZ1zd1vQwSPFCSks6zrADqUDBUdtq39lElk4ZE7Q= Codec DAI endpoint for RXADC + basic controls. THe codec have basic volume control. Which is imlemented by lookup table for simplicity. The codec expects set_sysclk callback to adjust internal mclk divider. Signed-off-by: Anton D. Stavinskii --- sound/soc/sophgo/Kconfig | 12 ++ sound/soc/sophgo/Makefile | 1 + sound/soc/sophgo/cv1800b-sound-adc.c | 322 +++++++++++++++++++++++++++++++= ++++ 3 files changed, 335 insertions(+) diff --git a/sound/soc/sophgo/Kconfig b/sound/soc/sophgo/Kconfig index 70f07d46c810..813ab30d6da3 100644 --- a/sound/soc/sophgo/Kconfig +++ b/sound/soc/sophgo/Kconfig @@ -17,4 +17,16 @@ config SND_SOC_CV1800B_TDM To compile the driver as a module, choose M here: the module will be called cv1800b_tdm. =20 +config SND_SOC_CV1800B_ADC_CODEC + tristate "Sophgo CV1800B/SG2002 internal ADC codec" + depends on SND_SOC + help + This driver provides an ASoC codec DAI for capture and basic + control of the RXADC registers. + + Say Y or M to build support for the Sophgo CV1800B + internal analog ADC codec block (RXADC). + The module will be called cv1800b-sound-adc + + endmenu diff --git a/sound/soc/sophgo/Makefile b/sound/soc/sophgo/Makefile index 3f9f1d07227a..c654d6059cbd 100644 --- a/sound/soc/sophgo/Makefile +++ b/sound/soc/sophgo/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 # Sophgo Platform Support obj-$(CONFIG_SND_SOC_CV1800B_TDM) +=3D cv1800b-tdm.o +obj-$(CONFIG_SND_SOC_CV1800B_ADC_CODEC) +=3D cv1800b-sound-adc.o diff --git a/sound/soc/sophgo/cv1800b-sound-adc.c b/sound/soc/sophgo/cv1800= b-sound-adc.c new file mode 100644 index 000000000000..794030b713e9 --- /dev/null +++ b/sound/soc/sophgo/cv1800b-sound-adc.c @@ -0,0 +1,322 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Internal adc codec for cv1800b compatible SoC + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CV1800B_RXADC_WORD_LEN 16 +#define CV1800B_RXADC_CHANNELS 2 + +#define CV1800B_RXADC_CTRL0 0x00 +#define CV1800B_RXADCC_CTRL1 0x04 +#define CV1800B_RXADC_STATUS 0x08 +#define CV1800B_RXADC_CLK 0x0c +#define CV1800B_RXADC_ANA0 0x10 +#define CV1800B_RXADC_ANA1 0x14 +#define CV1800B_RXADC_ANA2 0x18 +#define CV1800B_RXADC_ANA3 0x1c +#define CV1800B_RXADC_ANA4 0x20 + +/* CV1800B_RXADC_CTRL0 */ +#define REG_RXADC_EN GENMASK(0, 0) +#define REG_I2S_TX_EN GENMASK(1, 1) + +/* CV1800B_RXADCC_CTRL1 */ +#define REG_RXADC_CIC_OPT GENMASK(1, 0) +#define REG_RXADC_IGR_INIT GENMASK(8, 8) + +/* CV1800B_RXADC_ANA0 */ +#define REG_GSTEPL_RXPGA GENMASK(12, 0) +#define REG_G6DBL_RXPGA GENMASK(13, 13) +#define REG_GAINL_RXADC GENMASK(15, 14) +#define REG_GSTEPR_RXPGA GENMASK(28, 16) +#define REG_G6DBR_RXPGA GENMASK(29, 29) +#define REG_GAINR_RXADC GENMASK(31, 30) +#define REG_COMB_LEFT_VOLUME GENMASK(15, 0) +#define REG_COMB_RIGHT_VOLUME GENMASK(31, 16) + +/* CV1800B_RXADC_ANA2 */ +#define REG_MUTEL_RXPGA GENMASK(0, 0) +#define REG_MUTER_RXPGA GENMASK(1, 1) + +/* CV1800B_RXADC_CLK */ +#define REG_RXADC_CLK_INV GENMASK(0, 0) +#define REG_RXADC_SCK_DIV GENMASK(15, 8) +#define REG_RXADC_DLYEN GENMASK(23, 16) + +enum decimation_values { + DECIMATION_64 =3D 0, + DECIMATION_128, + DECIMATION_256, + DECIMATION_512, +}; + +static const u32 cv1800b_gains[] =3D { + 0x0001, /* 0dB */ + 0x0002, /* 2dB */ + 0x0004, /* 4dB */ + 0x0008, /* 6dB */ + 0x0010, /* 8dB */ + 0x0020, /* 10dB */ + 0x0040, /* 12dB */ + 0x0080, /* 14dB */ + 0x0100, /* 16dB */ + 0x0200, /* 18dB */ + 0x0400, /* 20dB */ + 0x0800, /* 22dB */ + 0x1000, /* 24dB */ + 0x2400, /* 26dB */ + 0x2800, /* 28dB */ + 0x3000, /* 30dB */ + 0x6400, /* 32dB */ + 0x6800, /* 34dB */ + 0x7000, /* 36dB */ + 0xA400, /* 38dB */ + 0xA800, /* 40dB */ + 0xB000, /* 42dB */ + 0xE400, /* 44dB */ + 0xE800, /* 46dB */ + 0xF000, /* 48dB */ +}; + +struct cv1800b_priv { + void __iomem *regs; + struct device *dev; + unsigned int mclk_rate; +}; + +static int cv1800b_adc_setbclk_div(struct cv1800b_priv *priv, unsigned int= rate) +{ + u32 val; + u32 bclk_div; + u64 tmp; + + if (!priv->mclk_rate || !rate) + return -EINVAL; + + tmp =3D priv->mclk_rate; + tmp /=3D CV1800B_RXADC_WORD_LEN; + tmp /=3D CV1800B_RXADC_CHANNELS; + tmp /=3D rate; + tmp /=3D 2; + + if (!tmp) { + dev_err(priv->dev, "computed BCLK divider is zero\n"); + return -EINVAL; + } + + if (tmp > 256) { + dev_err(priv->dev, "BCLK divider %llu out of range\n", tmp); + return -EINVAL; + } + + bclk_div =3D tmp - 1; + val =3D readl(priv->regs + CV1800B_RXADC_CLK); + val =3D u32_replace_bits(val, bclk_div, REG_RXADC_SCK_DIV); + /* Vendor value for 48kHz, tested on SG2000/SG2002 */ + val =3D u32_replace_bits(val, 0x19, REG_RXADC_DLYEN); + writel(val, priv->regs + CV1800B_RXADC_CLK); + + return 0; +} + +static void cv1800b_adc_enable(struct cv1800b_priv *priv, bool enable) +{ + u32 val; + + val =3D readl(priv->regs + CV1800B_RXADC_CTRL0); + val =3D u32_replace_bits(val, enable, REG_RXADC_EN); + val =3D u32_replace_bits(val, enable, REG_I2S_TX_EN); + writel(val, priv->regs + CV1800B_RXADC_CTRL0); +} + +static unsigned int cv1800b_adc_calc_db(u32 ana0, bool right) +{ + u32 step_mask =3D right ? FIELD_GET(REG_GSTEPR_RXPGA, ana0) : + FIELD_GET(REG_GSTEPL_RXPGA, ana0); + u32 coarse =3D right ? FIELD_GET(REG_GAINR_RXADC, ana0) : + FIELD_GET(REG_GAINL_RXADC, ana0); + bool g6db =3D right ? FIELD_GET(REG_G6DBR_RXPGA, ana0) : + FIELD_GET(REG_G6DBL_RXPGA, ana0); + + u32 step =3D step_mask ? __ffs(step_mask) : 0; + + step =3D min(step, 12U); + coarse =3D min(coarse, 3U); + + return 2 * step + 6 * coarse + (g6db ? 6 : 0); +} + +static int cv1800b_adc_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct cv1800b_priv *priv =3D snd_soc_dai_get_drvdata(dai); + unsigned int rate =3D params_rate(params); + u32 val; + int ret; + + ret =3D cv1800b_adc_setbclk_div(priv, rate); + if (ret) { + dev_err(priv->dev, + "could not set rate, check DT node for fixed clock\n"); + return ret; + } + + /* init adc */ + val =3D readl(priv->regs + CV1800B_RXADCC_CTRL1); + val =3D u32_replace_bits(val, 1, REG_RXADC_IGR_INIT); + val =3D u32_replace_bits(val, DECIMATION_64, REG_RXADC_CIC_OPT); + writel(val, priv->regs + CV1800B_RXADCC_CTRL1); + return 0; +} + +static int cv1800b_adc_dai_trigger(struct snd_pcm_substream *substream, in= t cmd, + struct snd_soc_dai *dai) +{ + struct cv1800b_priv *priv =3D snd_soc_dai_get_drvdata(dai); + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + cv1800b_adc_enable(priv, true); + break; + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + cv1800b_adc_enable(priv, false); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int cv1800b_adc_dai_set_sysclk(struct snd_soc_dai *dai, int clk_id, + unsigned int freq, int dir) +{ + struct cv1800b_priv *priv =3D snd_soc_dai_get_drvdata(dai); + + priv->mclk_rate =3D freq; + dev_dbg(priv->dev, "mclk is set to %u\n", freq); + return 0; +} + +static const struct snd_soc_dai_ops cv1800b_adc_dai_ops =3D { + .hw_params =3D cv1800b_adc_hw_params, + .set_sysclk =3D cv1800b_adc_dai_set_sysclk, + .trigger =3D cv1800b_adc_dai_trigger, +}; + +static struct snd_soc_dai_driver cv1800b_adc_dai =3D { + .name =3D "adc-hifi", + .capture =3D { .stream_name =3D "ADC Capture", + .channels_min =3D 1, + .channels_max =3D 2, + .rates =3D SNDRV_PCM_RATE_48000, + .formats =3D SNDRV_PCM_FMTBIT_S16_LE }, + .ops =3D &cv1800b_adc_dai_ops, +}; + +static int cv1800b_adc_volume_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component =3D snd_kcontrol_chip(kcontrol); + struct cv1800b_priv *priv =3D snd_soc_component_get_drvdata(component); + u32 ana0 =3D readl(priv->regs + CV1800B_RXADC_ANA0); + + unsigned int left =3D cv1800b_adc_calc_db(ana0, false); + unsigned int right =3D cv1800b_adc_calc_db(ana0, true); + + ucontrol->value.integer.value[0] =3D min(left / 2, 24U); + ucontrol->value.integer.value[1] =3D min(right / 2, 24U); + return 0; +} + +static int cv1800b_adc_volume_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component =3D snd_kcontrol_chip(kcontrol); + struct cv1800b_priv *priv =3D snd_soc_component_get_drvdata(component); + + u32 v_left =3D clamp_t(u32, ucontrol->value.integer.value[0], 0, 24); + u32 v_right =3D clamp_t(u32, ucontrol->value.integer.value[1], 0, 24); + u32 val; + + val =3D readl(priv->regs + CV1800B_RXADC_ANA0); + val =3D u32_replace_bits(val, cv1800b_gains[v_left], + REG_COMB_LEFT_VOLUME); + val =3D u32_replace_bits(val, cv1800b_gains[v_right], + REG_COMB_RIGHT_VOLUME); + writel(val, priv->regs + CV1800B_RXADC_ANA0); + + return 0; +} + +static DECLARE_TLV_DB_SCALE(cv1800b_volume_tlv, 0, 200, 0); + +static const struct snd_kcontrol_new cv1800b_adc_controls[] =3D { + SOC_DOUBLE_EXT_TLV("Internal I2S Capture Volume", SND_SOC_NOPM, 0, 16, 24= , false, + cv1800b_adc_volume_get, cv1800b_adc_volume_set, + cv1800b_volume_tlv), +}; + +static const struct snd_soc_component_driver cv1800b_adc_component =3D { + .name =3D "cv1800b-adc-codec", + .controls =3D cv1800b_adc_controls, + .num_controls =3D ARRAY_SIZE(cv1800b_adc_controls), +}; + +static int cv1800b_adc_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct cv1800b_priv *priv; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev =3D dev; + priv->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->regs)) + return PTR_ERR(priv->regs); + + platform_set_drvdata(pdev, priv); + return devm_snd_soc_register_component(&pdev->dev, + &cv1800b_adc_component, + &cv1800b_adc_dai, 1); +} + +static const struct of_device_id cv1800b_adc_of_match[] =3D { + { .compatible =3D "sophgo,cv1800b-sound-adc" }, + { /* sentinel */ } +}; + +MODULE_DEVICE_TABLE(of, cv1800b_adc_of_match); + +static struct platform_driver cv1800b_adc_driver =3D { + .probe =3D cv1800b_adc_probe, + .driver =3D { + .name =3D "cv1800b-sound-adc", + .of_match_table =3D cv1800b_adc_of_match, + }, +}; + +module_platform_driver(cv1800b_adc_driver); + +MODULE_DESCRIPTION("ADC codec for CV1800B"); +MODULE_AUTHOR("Anton D. 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[94.59.215.181]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4801e879542sm112402295e9.4.2026.01.17.12.19.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Jan 2026 12:19:39 -0800 (PST) From: "Anton D. Stavinskii" Date: Sun, 18 Jan 2026 00:18:57 +0400 Subject: [PATCH v2 5/7] dt-bindings: sound: sophgo: add CV1800B internal DAC codec Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260118-cv1800b-i2s-driver-v2-5-d10055f68368@gmail.com> References: <20260118-cv1800b-i2s-driver-v2-0-d10055f68368@gmail.com> In-Reply-To: <20260118-cv1800b-i2s-driver-v2-0-d10055f68368@gmail.com> To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Jaroslav Kysela , Takashi Iwai , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-sound@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, "Anton D. Stavinskii" X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768681160; l=1737; i=stavinsky@gmail.com; s=20260115; h=from:subject:message-id; bh=GwTIVlGCDzAackWj5fM/XVH5Lb9iGR97dcSVgftL+2Q=; b=gWseGCnVm2/lclbG2rn3qTW1KAMRYhjwJ6KXzgLpr24RyIRTPhxiEifZ6rXedoHGg4b2rRBJg 0zD6SVMzvkUDOAMuPw4nvoWJS0mMvRtfBHAbR4UhgEvE/VkxZzHvzq7 X-Developer-Key: i=stavinsky@gmail.com; a=ed25519; pk=2WxGZ1zd1vQwSPFCSks6zrADqUDBUdtq39lElk4ZE7Q= Document the internal DAC audio codec integrated in the Sophgo CV1800B SoC. The codec doesn't have any special configuration at the moment. Signed-off-by: Anton D. Stavinskii --- .../bindings/sound/sophgo,cv1800b-sound-dac.yaml | 43 ++++++++++++++++++= ++++ 1 file changed, 43 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/sophgo,cv1800b-sound-d= ac.yaml b/Documentation/devicetree/bindings/sound/sophgo,cv1800b-sound-dac.= yaml new file mode 100644 index 000000000000..2a35e38dc7f9 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/sophgo,cv1800b-sound-dac.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/sophgo,cv1800b-sound-dac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo CV1800B internal DAC audio codec + +maintainers: + - Anton D. Stavinskii + +description: | + Internal DAC audio codec integrated in the Sophgo CV1800B SoC. + The codec exposes a single playback DAI and is intended to be connected = to an + I2S/TDM controller via an ASoC machine driver. + +properties: + compatible: + const: sophgo,cv1800b-sound-dac + + reg: + maxItems: 1 + description: | + Register base address and size of the internal DAC codec register bl= ock. + + "#sound-dai-cells": + const: 0 + +required: + - compatible + - reg + - "#sound-dai-cells" + +additionalProperties: false + +examples: + - | + audio-codec@300A000 { + compatible =3D "sophgo,cv1800b-sound-dac"; + #sound-dai-cells =3D <0>; + reg =3D <0x0300A000 0x100>; + }; +... --=20 2.43.0 From nobody Sun Feb 8 12:20:22 2026 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 207422E6CC8 for ; Sat, 17 Jan 2026 20:19:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768681187; cv=none; b=bQQyDkcoDvSj4KNx2KfO4w/38m5r1is7C4qlZXUPG0HM4cp5/PBSSsyjigUHpbZPhJZs+x+yhGHLFeEl0CIDlDV5TbFLvdSZGpDTBYBbzLffpSqOfVJqP/NnzB4CspO5Ikq/xkeATTYP5zwtk00wwOxRUu0UzyIIaHXCQVF3eUQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768681187; c=relaxed/simple; bh=Ry87fypYvNiXf2Do52FZjUNG5N0BLDgHQy32QFRln+Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hMRj01MTBrQ7rbKTNTrsrpbtVB84kaevLc+n8uGwzn0FNvBBF3ffMko2WDJzG3LKApvbCElWF2QZd0hyW0mlynaVQC4UJzynaAEA3Czziv+nt+Fj4ZMYVyFOseZBAUhfpltLVT/DaMtR1PIIeOQ2KIs99EsWTVqS2RXIgaZph04= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=CYLsQchZ; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="CYLsQchZ" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-47edd6111b4so26636875e9.1 for ; Sat, 17 Jan 2026 12:19:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1768681183; x=1769285983; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=3M3zoQ0I/C+HXol0UHjaWQx8Rj1QNDs6zFN2pCrPidA=; b=CYLsQchZXDmQs3gUNksldC6Z5eFx3My7lElNOBxXPzz+1MKzbpN4BSNfjOHn3G17wS dhy2PRRtovuM25pyKppj7db12rU0OXjr/NLRAWBxqOgsAVVRMMBYcNBks/u4eYRzPBsn 16sHg3GDExmjpOI1X7GhsmBrCgVEHzPaqO+zj8n2nNc0/irpBVSG6VoirKLfnV+En2af LF2pLx9I5jJAXdoPhvsNovxof3GG6LXg0YNoZu0DcoIgDqbR4zKyybXJ6HjZZJAgGCoE 2MkACEpJHypuZLXokcR6/jlAxuTOHLasoHYOM/NOjiZAak3BFF/ATflKm7yxI2VVTfA/ 0KEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768681183; x=1769285983; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=3M3zoQ0I/C+HXol0UHjaWQx8Rj1QNDs6zFN2pCrPidA=; b=Y4GKdQddDdnGdGfljUoznxgJYjgRjBoYr/LBJTJLb6EIL6IdjbNJ6OMFKh8S9eXTm3 ivsMp+BmblW+ZsgUlqXS4WuuuGv+XbUohpWtPqvPBIRpz4ZcWEQEFz6GfrKQi4Yp9QGG K4MjQjNDY05QR+Jg0OlvkeTlmWpIwmAueolZ/zjbddYP2JEhy4ad8QtYKpxrD5B5o4lV ZS2x88qt5vowjYytszHcI+Kl2fY+XYNWJQK4uLTLQ3csG9qhaWQ3qcGfDQf2rcXXsi8b +1rZQC/vrQCLW59ldGBz0hZe3Y2UnBZWQU5QNbGoZmXY07Q/zqQRfPxKN7bf4UKBfXLj /rmQ== X-Forwarded-Encrypted: i=1; AJvYcCXZB+npzhK+7YlsXymH1nA0dkIlUjxIcWPqxUhmToJlsM20+tXgoBkwr83EpvMFVlTtp3kLTzjytDNl4cc=@vger.kernel.org X-Gm-Message-State: AOJu0Yx9XqPVX2xJDYLvQrAETKYVBE9sVSD8wdZ5nT65bC7uJavpyTBz tPko5iE1A8aXOcegTb/yog4DSUyQuoaujHro89rDZPLzuIbr6nWAHAaq7h2Tmhzx X-Gm-Gg: AY/fxX41F8TNyyMita3+cFoAqKAwHwBqINlUvI/gOxi3CivyzvHOedXH2b91my4lw5r MWrJHnPmqIrh5uudhJDPqIMc0h8rUXf0VNsHRxat/Zp0CrpD74lKR+R47tHH4H09TlSxk7tbRZn vw4Uz+mOKkXBPqwGMr319w5z9ChY+xZQbgsMLfCdcBWL4aJLdhTR32x1v6h2Qs4U5ADHrQI4VT2 O2xBrvR79hQJ9ZhIO461L2roANmzEg98V5y2P3tmkE1lsE8eIg19bCFdN3kDFx2dPtSoelv94uI ss8o+mrlVc9qKHzEdlO8JU9FQXqPZnQ2WgqkI+PXxEMQJeYXu42WDvlBRRUEAhuYxlmwZ5yEQYk A2v567dhBmyHEnspVWQJw30xL5WEUN9++GkJT2wLz+Lv6PjkFOeXDlAVTe+i9NUhsH0JwyhMu0y OOCXldvmZLJfo4PlW9qv1yuKjETKzGiXxyMpuzBL+6lXtu X-Received: by 2002:a05:600c:3e08:b0:46e:3550:9390 with SMTP id 5b1f17b1804b1-4801e334384mr69858765e9.20.1768681182725; Sat, 17 Jan 2026 12:19:42 -0800 (PST) Received: from [127.0.1.1] (bba-94-59-215-181.alshamil.net.ae. [94.59.215.181]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4801e879542sm112402295e9.4.2026.01.17.12.19.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Jan 2026 12:19:42 -0800 (PST) From: "Anton D. Stavinskii" Date: Sun, 18 Jan 2026 00:18:58 +0400 Subject: [PATCH v2 6/7] ASoC: sophgo: add CV1800B internal DAC codec driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260118-cv1800b-i2s-driver-v2-6-d10055f68368@gmail.com> References: <20260118-cv1800b-i2s-driver-v2-0-d10055f68368@gmail.com> In-Reply-To: <20260118-cv1800b-i2s-driver-v2-0-d10055f68368@gmail.com> To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Jaroslav Kysela , Takashi Iwai , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-sound@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, "Anton D. Stavinskii" X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768681160; l=7443; i=stavinsky@gmail.com; s=20260115; h=from:subject:message-id; bh=Ry87fypYvNiXf2Do52FZjUNG5N0BLDgHQy32QFRln+Q=; b=ued2nn31acFQjJYgLWHNrDxR3FILxTIpgxb6K2yEjB+F26VPN42E7lrSrcEeInLf/U2ajKXuG PIiF0Fe5pktDSQClDtzLM9pjs3BWDtuXax/hEcgbzJQoeLZj2Ou9qkU X-Developer-Key: i=stavinsky@gmail.com; a=ed25519; pk=2WxGZ1zd1vQwSPFCSks6zrADqUDBUdtq39lElk4ZE7Q= Codec DAI endpoint for TXDAC. The codec does only a few things - set up decimation - enable codec and I2S output - ensures the driver doesn't have dac overwrite enabled. (unmute the output) Signed-off-by: Anton D. Stavinskii --- sound/soc/sophgo/Kconfig | 11 +- sound/soc/sophgo/Makefile | 1 + sound/soc/sophgo/cv1800b-sound-dac.c | 204 +++++++++++++++++++++++++++++++= ++++ 3 files changed, 215 insertions(+), 1 deletion(-) diff --git a/sound/soc/sophgo/Kconfig b/sound/soc/sophgo/Kconfig index 813ab30d6da3..e7c617b44db6 100644 --- a/sound/soc/sophgo/Kconfig +++ b/sound/soc/sophgo/Kconfig @@ -23,10 +23,19 @@ config SND_SOC_CV1800B_ADC_CODEC help This driver provides an ASoC codec DAI for capture and basic control of the RXADC registers. - Say Y or M to build support for the Sophgo CV1800B internal analog ADC codec block (RXADC). The module will be called cv1800b-sound-adc =20 +config SND_SOC_CV1800B_DAC_CODEC + tristate "Sophgo CV1800B/SG2002 internal DAC codec" + depends on SND_SOC + help + This driver provides an ASoC codec DAI for playback and basic + control of the TXDAC registers. + + Say Y or M to build support for the Sophgo CV1800B + internal analog DAC codec block (TXDAC). + The module will be called cv1800b-sound-dac =20 endmenu diff --git a/sound/soc/sophgo/Makefile b/sound/soc/sophgo/Makefile index c654d6059cbd..ec8dd31efddd 100644 --- a/sound/soc/sophgo/Makefile +++ b/sound/soc/sophgo/Makefile @@ -2,3 +2,4 @@ # Sophgo Platform Support obj-$(CONFIG_SND_SOC_CV1800B_TDM) +=3D cv1800b-tdm.o obj-$(CONFIG_SND_SOC_CV1800B_ADC_CODEC) +=3D cv1800b-sound-adc.o +obj-$(CONFIG_SND_SOC_CV1800B_DAC_CODEC) +=3D cv1800b-sound-dac.o diff --git a/sound/soc/sophgo/cv1800b-sound-dac.c b/sound/soc/sophgo/cv1800= b-sound-dac.c new file mode 100644 index 000000000000..ccf386174639 --- /dev/null +++ b/sound/soc/sophgo/cv1800b-sound-dac.c @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Internal DAC codec for cv1800b based CPUs + */ + +#include +#include +#include +#include +#include +#include + +#define CV1800B_TXDAC_CTRL0 0x00 +#define CV1800B_TXDAC_CTRL1 0x04 +#define CV1800B_TXDAC_STATUS 0x08 +#define CV1800B_TXDAC_AFE0 0x0c +#define CV1800B_TXDAC_AFE1 0x10 +#define CV1800B_TXDAC_ANA0 0x20 +#define CV1800B_TXDAC_ANA1 0x24 +#define CV1800B_TXDAC_ANA2 0x28 + +/* cv1800b_TXDAC_CTRL0 */ +#define REG_TXDAC_EN GENMASK(0, 0) +#define REG_I2S_RX_EN GENMASK(1, 1) + +/* cv1800b_TXDAC_CTRL1 */ +#define REG_TXDAC_CIC_OPT GENMASK(1, 0) + +/* cv1800b_TXDAC_AFE0 */ +#define REG_TXDAC_INIT_DLY_CNT GENMASK(5, 0) + +/* cv1800b_TXDAC_ANA2 */ +#define TXDAC_OW_VAL_L_MASK GENMASK(7, 0) +#define TXDAC_OW_VAL_R_MASK GENMASK(15, 8) +#define TXDAC_OW_EN_L_MASK GENMASK(16, 16) +#define TXDAC_OW_EN_R_MASK GENMASK(17, 17) + +struct cv1800b_priv { + void __iomem *regs; + struct device *dev; +}; + +enum decimation_values { + DECIMATION_64 =3D 0, + DECIMATION_128, + DECIMATION_256, + DECIMATION_512, +}; + +static void cv1800b_dac_enable(struct cv1800b_priv *priv, bool enable) +{ + u32 val; + + val =3D readl(priv->regs + CV1800B_TXDAC_CTRL0); + val =3D u32_replace_bits(val, enable, REG_TXDAC_EN); + val =3D u32_replace_bits(val, enable, REG_I2S_RX_EN); + writel(val, priv->regs + CV1800B_TXDAC_CTRL0); +} + +static void cv1800b_dac_mute(struct cv1800b_priv *priv, bool enable) +{ + u32 val; + + val =3D readl(priv->regs + CV1800B_TXDAC_ANA2); + val =3D u32_replace_bits(val, enable, TXDAC_OW_EN_L_MASK); + val =3D u32_replace_bits(val, enable, TXDAC_OW_EN_R_MASK); + writel(val, priv->regs + CV1800B_TXDAC_ANA2); +} + +static int cv1800b_dac_decimation(struct cv1800b_priv *priv, u8 dec) +{ + u32 val; + + if (dec > 3) + return -EINVAL; + + val =3D readl(priv->regs + CV1800B_TXDAC_CTRL1); + val =3D u32_replace_bits(val, dec, REG_TXDAC_CIC_OPT); + writel(val, priv->regs + CV1800B_TXDAC_CTRL1); + return 0; +} + +static int cv1800b_dac_dly(struct cv1800b_priv *priv, u32 dly) +{ + u32 val; + + if (dly > 63) + return -EINVAL; + + val =3D readl(priv->regs + CV1800B_TXDAC_AFE0); + val =3D u32_replace_bits(val, dly, REG_TXDAC_INIT_DLY_CNT); + writel(val, priv->regs + CV1800B_TXDAC_AFE0); + return 0; +} + +static int cv1800b_dac_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct cv1800b_priv *priv =3D snd_soc_dai_get_drvdata(dai); + int ret; + unsigned int rate =3D params_rate(params); + + if (rate !=3D 48000) { + dev_err(priv->dev, "rate %u is not supported\n", rate); + return -EINVAL; + } + + cv1800b_dac_mute(priv, false); + /* minimal decimation for 48kHz is 64*/ + ret =3D cv1800b_dac_decimation(priv, DECIMATION_64); + if (ret) + return ret; + + /* value is taken from vendors driver 48kHz + * tested on sg2000 and sg2002. + */ + ret =3D cv1800b_dac_dly(priv, 0x19); + if (ret) + return ret; + + return 0; +} + +static int cv1800b_dac_dai_trigger(struct snd_pcm_substream *substream, in= t cmd, + struct snd_soc_dai *dai) +{ + struct cv1800b_priv *priv =3D snd_soc_dai_get_drvdata(dai); + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + cv1800b_dac_enable(priv, true); + break; + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + cv1800b_dac_enable(priv, false); + break; + default: + return -EINVAL; + } + + return 0; +} + +static const struct snd_soc_dai_ops cv1800b_dac_dai_ops =3D { + .hw_params =3D cv1800b_dac_hw_params, + .trigger =3D cv1800b_dac_dai_trigger, +}; + +static struct snd_soc_dai_driver cv1800b_dac_dai =3D { + .name =3D "dac-hifi", + .playback =3D { .stream_name =3D "DAC Playback", + .channels_min =3D 2, + .channels_max =3D 2, + .rates =3D SNDRV_PCM_RATE_48000, + .formats =3D SNDRV_PCM_FMTBIT_S16_LE }, + .ops =3D &cv1800b_dac_dai_ops, +}; + +static const struct snd_soc_component_driver cv1800b_dac_component =3D { + .name =3D "cv1800b-dac-codec", +}; + +static int cv1800b_dac_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct cv1800b_priv *priv; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev =3D dev; + priv->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->regs)) + return PTR_ERR(priv->regs); + + platform_set_drvdata(pdev, priv); + return devm_snd_soc_register_component(&pdev->dev, + &cv1800b_dac_component, + &cv1800b_dac_dai, 1); +} + +static const struct of_device_id cv1800b_dac_of_match[] =3D { + { .compatible =3D "sophgo,cv1800b-sound-dac" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, cv1800b_dac_of_match); + +static struct platform_driver cv1800b_dac_driver =3D { + .probe =3D cv1800b_dac_probe, + .driver =3D { + .name =3D "cv1800b-dac-codec", + .of_match_table =3D cv1800b_dac_of_match, + }, +}; +module_platform_driver(cv1800b_dac_driver); + +MODULE_DESCRIPTION("DAC codec for CV1800B"); +MODULE_AUTHOR("Anton D. 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[94.59.215.181]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4801e879542sm112402295e9.4.2026.01.17.12.19.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Jan 2026 12:19:45 -0800 (PST) From: "Anton D. Stavinskii" Date: Sun, 18 Jan 2026 00:18:59 +0400 Subject: [PATCH v2 7/7] riscv: dts: sophgo: dts nodes for i2s tdm modules Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260118-cv1800b-i2s-driver-v2-7-d10055f68368@gmail.com> References: <20260118-cv1800b-i2s-driver-v2-0-d10055f68368@gmail.com> In-Reply-To: <20260118-cv1800b-i2s-driver-v2-0-d10055f68368@gmail.com> To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Jaroslav Kysela , Takashi Iwai , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-sound@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, "Anton D. Stavinskii" X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768681160; l=4478; i=stavinsky@gmail.com; s=20260115; h=from:subject:message-id; bh=g4t3ASBfpTD6MsKZ16mnOZXRVvOWIeS8pZgY3yatJ+k=; b=IP/61jcli7ye+ePhqXMU/dvjwgiJnBsZKE2W1q/UjFBh0BZ0qWBFmNKibfoStAitWRS+TSq1X s+qHIH+9TLWA4M+O7mS88p7iE9XRfRSp62cdieG5oTFmNQ5FOulvhvx X-Developer-Key: i=stavinsky@gmail.com; a=ed25519; pk=2WxGZ1zd1vQwSPFCSks6zrADqUDBUdtq39lElk4ZE7Q= Introduced I2S nodes and internal dac and adc nodes as well The new header file provided in order to make DMA channel names more readable. Signed-off-by: Anton D. Stavinskii --- arch/riscv/boot/dts/sophgo/cv180x-dmamux.h | 57 +++++++++++++++++++++++++++ arch/riscv/boot/dts/sophgo/cv180x.dtsi | 63 ++++++++++++++++++++++++++= ++++ 2 files changed, 120 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/cv180x-dmamux.h b/arch/riscv/boot/d= ts/sophgo/cv180x-dmamux.h new file mode 100644 index 000000000000..6314bf6e9dc8 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/cv180x-dmamux.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2025 Inochi Amaoto + */ + +#ifndef _SOPHGO_CV18XX_DMAMUX +#define _SOPHGO_CV18XX_DMAMUX + +#define DMA_I2S0_RX 0 +#define DMA_I2S0_TX 1 +#define DMA_I2S1_RX 2 +#define DMA_I2S1_TX 3 +#define DMA_I2S2_RX 4 +#define DMA_I2S2_TX 5 +#define DMA_I2S3_RX 6 +#define DMA_I2S3_TX 7 +#define DMA_UART0_RX 8 +#define DMA_UART0_TX 9 +#define DMA_UART1_RX 10 +#define DMA_UART1_TX 11 +#define DMA_UART2_RX 12 +#define DMA_UART2_TX 13 +#define DMA_UART3_RX 14 +#define DMA_UART3_TX 15 +#define DMA_SPI0_RX 16 +#define DMA_SPI0_TX 17 +#define DMA_SPI1_RX 18 +#define DMA_SPI1_TX 19 +#define DMA_SPI2_RX 20 +#define DMA_SPI2_TX 21 +#define DMA_SPI3_RX 22 +#define DMA_SPI3_TX 23 +#define DMA_I2C0_RX 24 +#define DMA_I2C0_TX 25 +#define DMA_I2C1_RX 26 +#define DMA_I2C1_TX 27 +#define DMA_I2C2_RX 28 +#define DMA_I2C2_TX 29 +#define DMA_I2C3_RX 30 +#define DMA_I2C3_TX 31 +#define DMA_I2C4_RX 32 +#define DMA_I2C4_TX 33 +#define DMA_TDM0_RX 34 +#define DMA_TDM0_TX 35 +#define DMA_TDM1_RX 36 +#define DMA_AUDSRC 37 +#define DMA_SPI_NAND 38 +#define DMA_SPI_NOR 39 +#define DMA_UART4_RX 40 +#define DMA_UART4_TX 41 +#define DMA_SPI_NOR1 42 + +#define DMA_CPU_A53 0 +#define DMA_CPU_C906_0 1 +#define DMA_CPU_C906_1 2 + +#endif // _SOPHGO_CV18XX_DMAMUX diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/s= ophgo/cv180x.dtsi index 06b0ce5a2db7..5a56951f7e4c 100644 --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi @@ -8,6 +8,7 @@ #include #include #include "cv18xx-reset.h" +#include "cv180x-dmamux.h" =20 / { #address-cells =3D <1>; @@ -448,6 +449,68 @@ usb: usb@4340000 { status =3D "disabled"; }; =20 + i2s0: i2s@4100000 { + compatible =3D "sophgo,cv1800b-i2s"; + reg =3D <0x04100000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk CLK_APB_I2S0>, <&clk CLK_SDMA_AUD0>; + clock-names =3D "i2s", "mclk"; + dmas =3D <&dmamux DMA_I2S0_RX 1>, <&dmamux DMA_I2S0_TX 1>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; + + i2s1: i2s@4110000 { + compatible =3D "sophgo,cv1800b-i2s"; + reg =3D <0x04110000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk CLK_APB_I2S1>, <&clk CLK_SDMA_AUD1>; + clock-names =3D "i2s", "mclk"; + dmas =3D <&dmamux DMA_I2S1_RX 1>, <&dmamux DMA_I2S1_TX 1>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; + + i2s2: i2s@4120000 { + compatible =3D "sophgo,cv1800b-i2s"; + reg =3D <0x04120000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk CLK_APB_I2S2>, <&clk CLK_SDMA_AUD2>; + clock-names =3D "i2s", "mclk"; + dmas =3D <&dmamux DMA_I2S2_RX 1>, <&dmamux DMA_I2S2_TX 1>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; + + i2s3: i2s@4130000 { + compatible =3D "sophgo,cv1800b-i2s"; + reg =3D <0x04130000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk CLK_APB_I2S3>, <&clk CLK_SDMA_AUD3>; + clock-names =3D "i2s", "mclk"; + dmas =3D <&dmamux DMA_I2S3_RX 1>, <&dmamux DMA_I2S3_TX 1>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; + + int_adc: codec@300a100 { + compatible =3D "sophgo,cv1800b-sound-adc"; + #sound-dai-cells =3D <0>; + reg =3D <0x300a100 0x100>; + status =3D "disabled"; + }; + + int_dac: codec@300a000 { + compatible =3D "sophgo,cv1800b-sound-dac"; + #sound-dai-cells =3D <0>; + reg =3D <0x300a000 0x100>; + status =3D "disabled"; + }; + rtc@5025000 { compatible =3D "sophgo,cv1800b-rtc", "syscon"; reg =3D <0x5025000 0x2000>; --=20 2.43.0