From nobody Sun Feb 8 20:32:39 2026 Received: from out-178.mta1.migadu.com (out-178.mta1.migadu.com [95.215.58.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A540197A7D for ; Sat, 17 Jan 2026 23:48:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768693703; cv=none; b=KTVCRouXWbE0AUkdzONMx9w48nPN9u1gf50kIS8UHgqz1LR7XzK0BQwXKRLToXA5ArxwmLO8vpK4PZTsLMb8oLcg7Yv5CcgvGF+rXrhhcqK3BwPB1fkzdAaLjo1o4X7gOD4ffAs/W3Ra+Q3ekhmXWYQRyPr9sn1ea3jGPhB1fV4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768693703; c=relaxed/simple; bh=u2RW7j3wp4dVjPImpC/IXWdc6WnGy6Q2lSvJkCeYBPU=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=r9OHVHwL67rmE0ObyT7w17CVOD9vcNl+lSB1U53oBygIfsMHW73oPOZjO42rEi8ILlLNOqp+npefOcjIi+m62gGg8IS8XQCyawdPvf/6ISM0YEcTi/zg14zrx8iipfGdolXsoD/oiYo5zUwwWDTQmHq5IIXe0i0wDWZbX+JvgjM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=xa0kXggA; arc=none smtp.client-ip=95.215.58.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="xa0kXggA" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1768693690; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=+5niUaeixLKbgx0rFYLIxVy+7xWVWWGUdpqZii7CbFo=; b=xa0kXggAJPXhDTj9WesIFXjoF/bD3lbsmfmf/5jYUUGS5cm7b29NWLXgpfh+qV9UJsHRyR yzI5bV46YZz8y/Ps8RtgpVWhFeDsTzBplJo/eppjuEYPvsNPVKJgH5DXK5k35T4Qp9DK3M +xdAmVB1SHkylL7dLwbz0mOoAR9yp7w= From: Matthew Schwartz To: Adrian Hunter , Ulf Hansson , Ben Chuang , Victor Shih Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Matthew Schwartz Subject: [RFC PATCH] mmc: sdhci-pci-gli: fix GL9750 DMA write corruption Date: Sat, 17 Jan 2026 15:48:00 -0800 Message-ID: <20260117234800.931664-1-matthew.schwartz@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" The GL9750 SD host controller has intermittent data corruption during DMA write operations, which has been traced to an incorrect burst configuration. This was discovered by comparing initialization sequences between the working GL9767 controller and GL9750 and seeing that the GM_BURST register was handled differently. Clearing bits 16-17 eliminates the corruption with f3write/f3read tests while maintaining full DMA write/read performance. Fixes: e51df6ce668a ("mmc: host: sdhci-pci: Add Genesys Logic GL975x suppor= t") Closes: https://lore.kernel.org/linux-mmc/33d12807-5c72-41ce-8679-57aa11831= fad@linux.dev/ Signed-off-by: Matthew Schwartz --- Hi all, I arrived at this after a whole bunch of guesswork based on the other Genesys card readers in the kernel that do work, like GL9767. I landed on register 0x510 which appears to be "GM_BURST_SIZE" and ended up going through each bit and either setting it or masking it. Eventually, I arrived at masking bits 16-17 which seemed to stabilize writes completely. Could someone at Genesys confirm what this register is for on GL9750, and what those bits are? At least locally, I have been able to run 50GB of f3write/f3read without any corruption while before even 1GB would corrupt. This also maintains the same read/write speed as before this change. I tried searching online but was unable to find any relevant docs, and I'd like to confirm the purpose of those bits before sending this out as v1. Thanks, Matt --- drivers/mmc/host/sdhci-pci-gli.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-= gli.c index b0f91cc9e40e4..a06b0cf11f12d 100644 --- a/drivers/mmc/host/sdhci-pci-gli.c +++ b/drivers/mmc/host/sdhci-pci-gli.c @@ -26,6 +26,9 @@ #define GLI_9750_WT_EN_ON 0x1 #define GLI_9750_WT_EN_OFF 0x0 =20 +#define SDHCI_GLI_9750_GM_BURST_SIZE 0x510 +#define SDHCI_GLI_9750_GM_BURST_SIZE_MASK GENMASK(17, 16) + #define SDHCI_GLI_9750_CFG2 0x848 #define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24) #define GLI_9750_CFG2_L1DLY_VALUE 0x1F @@ -629,6 +632,11 @@ static void gl9750_hw_setting(struct sdhci_host *host) =20 gl9750_wt_on(host); =20 + /* clear GM_BURST bits to avoid corruption with DMA writes */ + value =3D sdhci_readl(host, SDHCI_GLI_9750_GM_BURST_SIZE); + value &=3D ~SDHCI_GLI_9750_GM_BURST_SIZE_MASK; + sdhci_writel(host, value, SDHCI_GLI_9750_GM_BURST_SIZE); + value =3D sdhci_readl(host, SDHCI_GLI_9750_CFG2); value &=3D ~SDHCI_GLI_9750_CFG2_L1DLY; /* set ASPM L1 entry delay to 7.9us */ --=20 2.52.0