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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , linux-kernel@vger.kernel.org Subject: [PATCH net-next v2] net: dsa: yt921x: Add LAG offloading support Date: Sun, 18 Jan 2026 00:21:11 +0800 Message-ID: <20260117162116.1063043-1-mmyangfl@gmail.com> X-Mailer: git-send-email 2.51.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add offloading for a link aggregation group supported by the YT921x switches. Signed-off-by: David Yang --- v1: https://lore.kernel.org/r/20260114151448.253238-1-mmyangfl@gmail.com - fix malfunctionality of port_lag_leave Picked from: https://lore.kernel.org/r/20251126093240.2853294-5-mmyangfl@gm= ail.com drivers/net/dsa/yt921x.c | 186 +++++++++++++++++++++++++++++++++++++++ drivers/net/dsa/yt921x.h | 20 +++++ 2 files changed, 206 insertions(+) diff --git a/drivers/net/dsa/yt921x.c b/drivers/net/dsa/yt921x.c index 0b3df732c0d1..a4b346ddf8dd 100644 --- a/drivers/net/dsa/yt921x.c +++ b/drivers/net/dsa/yt921x.c @@ -1117,6 +1117,188 @@ yt921x_dsa_port_mirror_add(struct dsa_switch *ds, i= nt port, return res; } =20 +static int yt921x_lag_hash(struct yt921x_priv *priv, u32 ctrl, bool unique= _lag, + struct netlink_ext_ack *extack) +{ + u32 val; + int res; + + /* Hash Mode is global. Make sure the same Hash Mode is set to all the + * 2 possible lags. + * If we are the unique LAG we can set whatever hash mode we want. + * To change hash mode it's needed to remove all LAG and change the mode + * with the latest. + */ + if (unique_lag) { + res =3D yt921x_reg_write(priv, YT921X_LAG_HASH, ctrl); + if (res) + return res; + } else { + res =3D yt921x_reg_read(priv, YT921X_LAG_HASH, &val); + if (res) + return res; + + if (val !=3D ctrl) { + NL_SET_ERR_MSG_MOD(extack, + "Mismatched Hash Mode across different lags is not supported"); + return -EOPNOTSUPP; + } + } + + return 0; +} + +static int yt921x_lag_set(struct yt921x_priv *priv, u8 index, u16 ports_ma= sk) +{ + unsigned long targets_mask =3D ports_mask; + unsigned int cnt; + u32 ctrl; + int port; + int res; + + cnt =3D 0; + for_each_set_bit(port, &targets_mask, YT921X_PORT_NUM) { + ctrl =3D YT921X_LAG_MEMBER_PORT(port); + res =3D yt921x_reg_write(priv, YT921X_LAG_MEMBERnm(index, cnt), + ctrl); + if (res) + return res; + + cnt++; + } + + ctrl =3D YT921X_LAG_GROUP_PORTS(ports_mask) | + YT921X_LAG_GROUP_MEMBER_NUM(cnt); + return yt921x_reg_write(priv, YT921X_LAG_GROUPn(index), ctrl); +} + +static int +yt921x_dsa_port_lag_leave(struct dsa_switch *ds, int port, struct dsa_lag = lag) +{ + struct yt921x_priv *priv =3D to_yt921x_priv(ds); + struct dsa_port *dp; + u32 ctrl; + int res; + + if (!lag.id) + return -EINVAL; + + ctrl =3D 0; + dsa_lag_foreach_port(dp, ds->dst, &lag) + ctrl |=3D BIT(dp->index); + + mutex_lock(&priv->reg_lock); + res =3D yt921x_lag_set(priv, lag.id - 1, ctrl); + mutex_unlock(&priv->reg_lock); + + return res; +} + +static int +yt921x_dsa_port_lag_check(struct dsa_switch *ds, struct dsa_lag lag, + struct netdev_lag_upper_info *info, + struct netlink_ext_ack *extack) +{ + unsigned int members; + struct dsa_port *dp; + + if (!lag.id) + return -EINVAL; + + members =3D 0; + dsa_lag_foreach_port(dp, ds->dst, &lag) + /* Includes the port joining the LAG */ + members++; + + if (members > YT921X_LAG_PORT_NUM) { + NL_SET_ERR_MSG_MOD(extack, + "Cannot offload more than 4 LAG ports"); + return -EOPNOTSUPP; + } + + if (info->tx_type !=3D NETDEV_LAG_TX_TYPE_HASH) { + NL_SET_ERR_MSG_MOD(extack, + "Can only offload LAG using hash TX type"); + return -EOPNOTSUPP; + } + + if (info->hash_type !=3D NETDEV_LAG_HASH_L2 && + info->hash_type !=3D NETDEV_LAG_HASH_L23 && + info->hash_type !=3D NETDEV_LAG_HASH_L34) { + NL_SET_ERR_MSG_MOD(extack, + "Can only offload L2 or L2+L3 or L3+L4 TX hash"); + return -EOPNOTSUPP; + } + + return 0; +} + +static int +yt921x_dsa_port_lag_join(struct dsa_switch *ds, int port, struct dsa_lag l= ag, + struct netdev_lag_upper_info *info, + struct netlink_ext_ack *extack) +{ + struct yt921x_priv *priv =3D to_yt921x_priv(ds); + struct dsa_port *dp; + bool unique_lag; + unsigned int i; + u32 ctrl; + int res; + + res =3D yt921x_dsa_port_lag_check(ds, lag, info, extack); + if (res) + return res; + + ctrl =3D 0; + switch (info->hash_type) { + case NETDEV_LAG_HASH_L34: + ctrl |=3D YT921X_LAG_HASH_IP_DST; + ctrl |=3D YT921X_LAG_HASH_IP_SRC; + ctrl |=3D YT921X_LAG_HASH_IP_PROTO; + + ctrl |=3D YT921X_LAG_HASH_L4_DPORT; + ctrl |=3D YT921X_LAG_HASH_L4_SPORT; + break; + case NETDEV_LAG_HASH_L23: + ctrl |=3D YT921X_LAG_HASH_MAC_DA; + ctrl |=3D YT921X_LAG_HASH_MAC_SA; + + ctrl |=3D YT921X_LAG_HASH_IP_DST; + ctrl |=3D YT921X_LAG_HASH_IP_SRC; + ctrl |=3D YT921X_LAG_HASH_IP_PROTO; + break; + case NETDEV_LAG_HASH_L2: + ctrl |=3D YT921X_LAG_HASH_MAC_DA; + ctrl |=3D YT921X_LAG_HASH_MAC_SA; + break; + default: + return -EOPNOTSUPP; + } + + /* Check if we are the unique configured LAG */ + unique_lag =3D true; + dsa_lags_foreach_id(i, ds->dst) + if (i !=3D lag.id && dsa_lag_by_id(ds->dst, i)) { + unique_lag =3D false; + break; + } + + mutex_lock(&priv->reg_lock); + do { + res =3D yt921x_lag_hash(priv, ctrl, unique_lag, extack); + if (res) + break; + + ctrl =3D 0; + dsa_lag_foreach_port(dp, ds->dst, &lag) + ctrl |=3D BIT(dp->index); + res =3D yt921x_lag_set(priv, lag.id - 1, ctrl); + } while (0); + mutex_unlock(&priv->reg_lock); + + return res; +} + static int yt921x_fdb_wait(struct yt921x_priv *priv, u32 *valp) { struct device *dev =3D to_device(priv); @@ -2881,6 +3063,9 @@ static const struct dsa_switch_ops yt921x_dsa_switch_= ops =3D { /* mirror */ .port_mirror_del =3D yt921x_dsa_port_mirror_del, .port_mirror_add =3D yt921x_dsa_port_mirror_add, + /* lag */ + .port_lag_leave =3D yt921x_dsa_port_lag_leave, + .port_lag_join =3D yt921x_dsa_port_lag_join, /* fdb */ .port_fdb_dump =3D yt921x_dsa_port_fdb_dump, .port_fast_age =3D yt921x_dsa_port_fast_age, @@ -2977,6 +3162,7 @@ static int yt921x_mdio_probe(struct mdio_device *mdio= dev) ds->ageing_time_min =3D 1 * 5000; ds->ageing_time_max =3D U16_MAX * 5000; ds->phylink_mac_ops =3D &yt921x_phylink_mac_ops; + ds->num_lag_ids =3D YT921X_LAG_NUM; ds->num_ports =3D YT921X_PORT_NUM; =20 mdiodev_set_drvdata(mdiodev, priv); diff --git a/drivers/net/dsa/yt921x.h b/drivers/net/dsa/yt921x.h index 61bb0ab3b09a..bacd4ccaa8e5 100644 --- a/drivers/net/dsa/yt921x.h +++ b/drivers/net/dsa/yt921x.h @@ -370,6 +370,14 @@ #define YT921X_FILTER_PORTn(port) BIT(port) #define YT921X_VLAN_EGR_FILTER 0x180598 #define YT921X_VLAN_EGR_FILTER_PORTn(port) BIT(port) +#define YT921X_LAG_GROUPn(n) (0x1805a8 + 4 * (n)) +#define YT921X_LAG_GROUP_PORTS_M GENMASK(13, 3) +#define YT921X_LAG_GROUP_PORTS(x) FIELD_PREP(YT921X_LAG_GROUP_PORTS_M,= (x)) +#define YT921X_LAG_GROUP_MEMBER_NUM_M GENMASK(2, 0) +#define YT921X_LAG_GROUP_MEMBER_NUM(x) FIELD_PREP(YT921X_LAG_GROUP_MEMB= ER_NUM_M, (x)) +#define YT921X_LAG_MEMBERnm(n, m) (0x1805b0 + 4 * (4 * (n) + (m))) +#define YT921X_LAG_MEMBER_PORT_M GENMASK(3, 0) +#define YT921X_LAG_MEMBER_PORT(x) FIELD_PREP(YT921X_LAG_MEMBER_PORT_M,= (x)) #define YT921X_CPU_COPY 0x180690 #define YT921X_CPU_COPY_FORCE_INT_PORT BIT(2) #define YT921X_CPU_COPY_TO_INT_CPU BIT(1) @@ -414,6 +422,15 @@ #define YT921X_PORT_IGR_TPIDn_STAG(x) BIT((x) + 4) #define YT921X_PORT_IGR_TPIDn_CTAG_M GENMASK(3, 0) #define YT921X_PORT_IGR_TPIDn_CTAG(x) BIT(x) +#define YT921X_LAG_HASH 0x210090 +#define YT921X_LAG_HASH_L4_SPORT BIT(7) +#define YT921X_LAG_HASH_L4_DPORT BIT(6) +#define YT921X_LAG_HASH_IP_PROTO BIT(5) +#define YT921X_LAG_HASH_IP_SRC BIT(4) +#define YT921X_LAG_HASH_IP_DST BIT(3) +#define YT921X_LAG_HASH_MAC_SA BIT(2) +#define YT921X_LAG_HASH_MAC_DA BIT(1) +#define YT921X_LAG_HASH_SRC_PORT BIT(0) =20 #define YT921X_PORTn_VLAN_CTRL(port) (0x230010 + 4 * (port)) #define YT921X_PORT_VLAN_CTRL_SVLAN_PRI_EN BIT(31) @@ -458,6 +475,9 @@ enum yt921x_fdb_entry_status { =20 #define YT921X_MSTI_NUM 16 =20 +#define YT921X_LAG_NUM 2 +#define YT921X_LAG_PORT_NUM 4 + #define YT9215_MAJOR 0x9002 #define YT9218_MAJOR 0x9001 =20 --=20 2.51.0