From nobody Sun Feb 8 09:27:32 2026 Received: from canpmsgout04.his.huawei.com (canpmsgout04.his.huawei.com [113.46.200.219]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 966792FD69D; Sat, 17 Jan 2026 10:18:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.219 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768645099; cv=none; b=pxopMBPfocgV1HcVyo/Mla/B4YAYJuGsKMGtmsf4ZaESsI/FOam+6annvZFoBMRZYnz6eJciTuijGstwhQMg33pY9eDhZUaLQ7EYi5IL+0/YZPV3/KK/Ixs9GXkJAwbupeqcODMZRhFkQxW/d2DSWnsp+WO+Dowq15+B6N3D6h0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768645099; c=relaxed/simple; bh=CjY4Xtz6sxrD7XMVBv1z2sA/eG+BwJjKAgN66jAEEnw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gNjvNGW6wncRngDsk/lOk3mlPK+QEB3iij7H1Qo8XsFPkd7Peey4I/alJb7PuIOnMysD8nFc7EFDeo7nEs/WJZDeFDYCB3cEF0PsHlzEuPIgg8x+pzkB0QMx0gV714EGOT9jv8wlyHbcfxSteKLvAockqxptVwqJEcnXHIFovcU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=HwN3pU93; arc=none smtp.client-ip=113.46.200.219 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="HwN3pU93" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=QQ77zNzJ28/hhg5JXu4D2DvZ7Ug9oghseuWjWMWInxw=; b=HwN3pU93uqHlri0bFASI7BPliv6+ghX8CviM1VnJI9xtJs+cf/oQaWbkJYLt0rHnPEA1K2J66 HfN83Dn0kT7twgzZ6qzOF6zMy0UNjU4sec3uIwiC1HRWBy1x+mFfTHOUBRcaFfh+bSnmK4mjm53 bPSXfcFpUDRLCSNSLHDx90I= Received: from mail.maildlp.com (unknown [172.19.163.104]) by canpmsgout04.his.huawei.com (SkyGuard) with ESMTPS id 4dtXdc4Ny5z1prLJ; Sat, 17 Jan 2026 18:14:44 +0800 (CST) Received: from dggemv712-chm.china.huawei.com (unknown [10.1.198.32]) by mail.maildlp.com (Postfix) with ESMTPS id F2FAC404AD; Sat, 17 Jan 2026 18:18:07 +0800 (CST) Received: from kwepemq200001.china.huawei.com (7.202.195.16) by dggemv712-chm.china.huawei.com (10.1.198.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Sat, 17 Jan 2026 18:18:07 +0800 Received: from localhost.huawei.com (10.90.31.46) by kwepemq200001.china.huawei.com (7.202.195.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Sat, 17 Jan 2026 18:18:07 +0800 From: Chenghai Huang To: , CC: , , , , , Subject: [PATCH 1/4] crypto: hisilicon/qm - move the barrier before writing to the mailbox register Date: Sat, 17 Jan 2026 18:18:03 +0800 Message-ID: <20260117101806.2172918-2-huangchenghai2@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260117101806.2172918-1-huangchenghai2@huawei.com> References: <20260117101806.2172918-1-huangchenghai2@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100001.china.huawei.com (7.221.188.238) To kwepemq200001.china.huawei.com (7.202.195.16) Content-Type: text/plain; charset="utf-8" Before sending the data via the mailbox to the hardware, to ensure that the data accessed by the hardware is the most up-to-date, a write barrier should be added before writing to the mailbox register. The current memory barrier is placed after writing to the register, the barrier order should be modified to be before writing to the register. Signed-off-by: Chenghai Huang --- drivers/crypto/hisilicon/qm.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c index 700fc1b8318e..49c1c78ff600 100644 --- a/drivers/crypto/hisilicon/qm.c +++ b/drivers/crypto/hisilicon/qm.c @@ -609,9 +609,13 @@ static void qm_mb_write(struct hisi_qm *qm, const void= *src) } =20 #if IS_ENABLED(CONFIG_ARM64) + /* + * The dmb oshst instruction ensures that the data in the + * mailbox is written before it is sent to the hardware. + */ asm volatile("ldp %0, %1, %3\n" - "stp %0, %1, %2\n" "dmb oshst\n" + "stp %0, %1, %2\n" : "=3D&r" (tmp0), "=3D&r" (tmp1), "+Q" (*((char __iomem *)fun_base)) --=20 2.33.0 From nobody Sun Feb 8 09:27:32 2026 Received: from canpmsgout05.his.huawei.com (canpmsgout05.his.huawei.com [113.46.200.220]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 871172AF1D; Sat, 17 Jan 2026 10:18:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.220 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768645095; cv=none; b=CsbD5v1cuKbFG4FJ7Xshp5LIb+OxVQwayOXfO8GlJYV9p8xUDfLUCEG/Lw5e29TkMTyFTQVsMKFwXrhFhyYxs1kvVC12k8fn158pCayhpzPQzoaHNLO7o13BrHPUMkTYzC7ctJwL42FmExt8+00IVhtjYOmrQWUZHLh9CgIRaGQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768645095; c=relaxed/simple; bh=BJVbyWOA+j0i2Rk7nSVAaqdwldI7WS4lQR6iKpnGcVk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Ap/dMez2z7F1LKy8w6UK0cY6RHDNy+syXsFIj6e8PZALrx6f17ds56WrewITSZXCt6JPd7rDUnfDdTOPyEbGJx+0UwmI+kMNFVUh+wsoU7PVZ3gO3QKDlCRCAZuc5A4k/NFD5Kr40oV4KChlpgwgCAmxXnHJS1sVXSR/4vXS1Mo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=4xHhsV/9; arc=none smtp.client-ip=113.46.200.220 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="4xHhsV/9" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=MsIWqJASqMqIr/uzMIQ8zwSd5DhPTPgNnwliRnUhuw4=; b=4xHhsV/9Mjo+CjrwwRKce4KLLdp4ytBFmq6zWNsIhf8XgMOKsLgeE0yd2T4B8/0PAcc9SDkaX Z7AFeQ6o6je8oGKtWqEfLxDPo92vLDrRZzChk4Dgc5Xi3kF8Ze671PeOvAbxoYXlPsJyRNuvqqa gCfkHW78//oUzBDSIuYN4sk= Received: from mail.maildlp.com (unknown [172.19.162.223]) by canpmsgout05.his.huawei.com (SkyGuard) with ESMTPS id 4dtXcv6Y2gz12LFm; Sat, 17 Jan 2026 18:14:07 +0800 (CST) Received: from dggemv705-chm.china.huawei.com (unknown [10.3.19.32]) by mail.maildlp.com (Postfix) with ESMTPS id 94F0240569; Sat, 17 Jan 2026 18:18:08 +0800 (CST) Received: from kwepemq200001.china.huawei.com (7.202.195.16) by dggemv705-chm.china.huawei.com (10.3.19.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Sat, 17 Jan 2026 18:18:08 +0800 Received: from localhost.huawei.com (10.90.31.46) by kwepemq200001.china.huawei.com (7.202.195.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Sat, 17 Jan 2026 18:18:07 +0800 From: Chenghai Huang To: , CC: , , , , , Subject: [PATCH 2/4] crypto: hisilicon/qm - remove unnecessary code in qm_mb_write() Date: Sat, 17 Jan 2026 18:18:04 +0800 Message-ID: <20260117101806.2172918-3-huangchenghai2@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260117101806.2172918-1-huangchenghai2@huawei.com> References: <20260117101806.2172918-1-huangchenghai2@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100001.china.huawei.com (7.221.188.238) To kwepemq200001.china.huawei.com (7.202.195.16) Content-Type: text/plain; charset="utf-8" From: Weili Qian Since the HiSilicon accelerator is used only on the ARM64 architectures, the implementations for other architectures are not needed, so remove the unnecessary code. Signed-off-by: Weili Qian Signed-off-by: Chenghai Huang --- drivers/crypto/hisilicon/qm.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c index 49c1c78ff600..2bb94e8c6a07 100644 --- a/drivers/crypto/hisilicon/qm.c +++ b/drivers/crypto/hisilicon/qm.c @@ -596,19 +596,9 @@ EXPORT_SYMBOL_GPL(hisi_qm_wait_mb_ready); /* 128 bit should be written to hardware at one time to trigger a mailbox = */ static void qm_mb_write(struct hisi_qm *qm, const void *src) { - void __iomem *fun_base =3D qm->io_base + QM_MB_CMD_SEND_BASE; - -#if IS_ENABLED(CONFIG_ARM64) - unsigned long tmp0 =3D 0, tmp1 =3D 0; -#endif - - if (!IS_ENABLED(CONFIG_ARM64)) { - memcpy_toio(fun_base, src, 16); - dma_wmb(); - return; - } - #if IS_ENABLED(CONFIG_ARM64) + void __iomem *fun_base =3D qm->io_base + QM_MB_CMD_SEND_BASE; + unsigned long tmp0, tmp1; /* * The dmb oshst instruction ensures that the data in the * mailbox is written before it is sent to the hardware. --=20 2.33.0 From nobody Sun Feb 8 09:27:32 2026 Received: from canpmsgout07.his.huawei.com (canpmsgout07.his.huawei.com [113.46.200.222]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A8872AF1D; Sat, 17 Jan 2026 10:18:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.222 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768645101; cv=none; b=Bc9XtDrxxq+tUnAyGe/Y7Pi8sALL3jAnFQNUaW9SD4jibZntgEf+1S+Zlx50h7+ugcSsXfkti630vHkBszJZ/3g9Am4xQYaHqNdrnTvN+atIrvQS6CTKKstrs0hXC61r6gY2PuQkTsSa8tUJianp9Y8nYrNckV3K1jXflbqkzb8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768645101; c=relaxed/simple; bh=F3CQ2i9mOChIGfbAlz+e4RLo3NyiwFFF4GlGfb+Hv3s=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=a8RDq3bhzNkBMcwKSR2zy5EOleAEr3xICjFGIEPFa9uIVq5WsrW5jslxn7iYphcQ8lJmDU9XA319UpYpEhUfSedaWQa7VhKZBxDZqXFKwjhiZodZX39GQ2VBdCk+FPuyqjel/yxfz0HVxq/F5dsawZFK0XFP2nyQ4EBR1uL8Xow= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=SLUqDFDW; arc=none smtp.client-ip=113.46.200.222 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="SLUqDFDW" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=XWirnVW4RmGYF9aGx8Ms/Q30Z3xEEHjfbD9aXL6YKGQ=; b=SLUqDFDW7r90NaqS1yfquhHNdau6zNrUrCmWKOp9n25cAOxbsYcZgIJ5tMdriKDiB0YPrGqkU c3/heG7awGVAR28YsnkGVV6g555Z6TPfLJ4JoLxoNqo2gvcpQ0Uy3nJXhwqbzjGANb+J+P+RFGW Zfgu2iOMNoKxjzA0CdoY0I0= Received: from mail.maildlp.com (unknown [172.19.162.92]) by canpmsgout07.his.huawei.com (SkyGuard) with ESMTPS id 4dtXdh09X0zLlSk; Sat, 17 Jan 2026 18:14:48 +0800 (CST) Received: from dggemv705-chm.china.huawei.com (unknown [10.3.19.32]) by mail.maildlp.com (Postfix) with ESMTPS id BE36B40565; Sat, 17 Jan 2026 18:18:08 +0800 (CST) Received: from kwepemq200001.china.huawei.com (7.202.195.16) by dggemv705-chm.china.huawei.com (10.3.19.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Sat, 17 Jan 2026 18:18:08 +0800 Received: from localhost.huawei.com (10.90.31.46) by kwepemq200001.china.huawei.com (7.202.195.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Sat, 17 Jan 2026 18:18:08 +0800 From: Chenghai Huang To: , CC: , , , , , Subject: [PATCH 3/4] crypto: hisilicon/qm - obtain the mailbox configuration at one time Date: Sat, 17 Jan 2026 18:18:05 +0800 Message-ID: <20260117101806.2172918-4-huangchenghai2@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260117101806.2172918-1-huangchenghai2@huawei.com> References: <20260117101806.2172918-1-huangchenghai2@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100001.china.huawei.com (7.221.188.238) To kwepemq200001.china.huawei.com (7.202.195.16) Content-Type: text/plain; charset="utf-8" From: Weili Qian The malibox needs to be triggered by a 128bit atomic operation. The reason is that the PF and VFs of the device share the mmio memory of the mailbox, and the mutex cannot lock mailbox operations in different functions, especially when passing through VFs to virtual machines. Currently, the write operation to the mailbox is already a 128-bit atomic write. The read operation also needs to be modified to a 128-bit atomic read. Since there is no general 128-bit IO memory access API in the current ARM64 architecture, and the stp and ldp instructions do not guarantee atomic access to device memory, they cannot be extracted as a general API. Therefore, the 128-bit atomic read and write operations need to be implemented in the driver. Signed-off-by: Weili Qian Signed-off-by: Chenghai Huang --- drivers/crypto/hisilicon/qm.c | 133 ++++++++++++++++++++++------------ include/linux/hisi_acc_qm.h | 1 + 2 files changed, 87 insertions(+), 47 deletions(-) diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c index 2bb94e8c6a07..94f96b6b38f5 100644 --- a/drivers/crypto/hisilicon/qm.c +++ b/drivers/crypto/hisilicon/qm.c @@ -31,6 +31,7 @@ /* mailbox */ #define QM_MB_PING_ALL_VFS 0xffff #define QM_MB_STATUS_MASK GENMASK(12, 9) +#define QM_MB_BUSY_MASK BIT(13) =20 /* sqc shift */ #define QM_SQ_HOP_NUM_SHIFT 0 @@ -582,16 +583,30 @@ static void qm_mb_pre_init(struct qm_mailbox *mailbox= , u8 cmd, mailbox->rsvd =3D 0; } =20 -/* return 0 mailbox ready, -ETIMEDOUT hardware timeout */ -int hisi_qm_wait_mb_ready(struct hisi_qm *qm) +/* + * The mailbox is 128 bits and requires a single read/write operation. + * Since there is no general 128-bit IO memory access API in the current + * ARM64 architecture, this needs to be implemented in the driver. + */ +static struct qm_mailbox qm_mb_read(struct hisi_qm *qm) { - u32 val; + struct qm_mailbox mailbox =3D {0}; + +#if IS_ENABLED(CONFIG_ARM64) + const void __iomem *fun_base =3D qm->io_base + QM_MB_CMD_SEND_BASE; + unsigned long tmp0, tmp1; =20 - return readl_relaxed_poll_timeout(qm->io_base + QM_MB_CMD_SEND_BASE, - val, !((val >> QM_MB_BUSY_SHIFT) & - 0x1), POLL_PERIOD, POLL_TIMEOUT); + asm volatile("ldp %0, %1, %3\n" + "stp %0, %1, %2\n" + : "=3D&r" (tmp0), + "=3D&r" (tmp1), + "+Q" (mailbox) + : "Q" (*((char __iomem *)fun_base)) + : "memory"); +#endif + + return mailbox; } -EXPORT_SYMBOL_GPL(hisi_qm_wait_mb_ready); =20 /* 128 bit should be written to hardware at one time to trigger a mailbox = */ static void qm_mb_write(struct hisi_qm *qm, const void *src) @@ -614,35 +629,61 @@ static void qm_mb_write(struct hisi_qm *qm, const voi= d *src) #endif } =20 -static int qm_mb_nolock(struct hisi_qm *qm, struct qm_mailbox *mailbox) +int hisi_qm_wait_mb_ready(struct hisi_qm *qm) { + struct qm_mailbox mailbox =3D {0}; int ret; - u32 val; =20 - if (unlikely(hisi_qm_wait_mb_ready(qm))) { + ret =3D read_poll_timeout(qm_mb_read, mailbox, + !(le16_to_cpu(mailbox.w0) & QM_MB_BUSY_MASK), + POLL_PERIOD, POLL_TIMEOUT, + true, qm); + if (ret) dev_err(&qm->pdev->dev, "QM mailbox is busy to start!\n"); - ret =3D -EBUSY; - goto mb_busy; - } =20 - qm_mb_write(qm, mailbox); + return ret; +} +EXPORT_SYMBOL_GPL(hisi_qm_wait_mb_ready); + +static int qm_wait_mb_finish(struct hisi_qm *qm, struct qm_mailbox *mailbo= x) +{ + struct device *dev =3D &qm->pdev->dev; + int ret; =20 - if (unlikely(hisi_qm_wait_mb_ready(qm))) { - dev_err(&qm->pdev->dev, "QM mailbox operation timeout!\n"); - ret =3D -ETIMEDOUT; - goto mb_busy; + ret =3D read_poll_timeout(qm_mb_read, *mailbox, + !(le16_to_cpu(mailbox->w0) & QM_MB_BUSY_MASK), + POLL_PERIOD, POLL_TIMEOUT, + true, qm); + if (ret) { + dev_err(dev, "QM mailbox operation timeout!\n"); + return ret; } =20 - val =3D readl(qm->io_base + QM_MB_CMD_SEND_BASE); - if (val & QM_MB_STATUS_MASK) { - dev_err(&qm->pdev->dev, "QM mailbox operation failed!\n"); - ret =3D -EIO; - goto mb_busy; + if (le16_to_cpu(mailbox->w0) & QM_MB_STATUS_MASK) { + dev_err(dev, "QM mailbox operation failed!\n"); + return -EIO; } =20 return 0; +} + +static int qm_mb_nolock(struct hisi_qm *qm, struct qm_mailbox *mailbox) +{ + int ret; + + ret =3D hisi_qm_wait_mb_ready(qm); + if (ret) + goto mb_err_cnt_increase; + + qm_mb_write(qm, mailbox); + + ret =3D qm_wait_mb_finish(qm, mailbox); + if (ret) + goto mb_err_cnt_increase; + + return 0; =20 -mb_busy: +mb_err_cnt_increase: atomic64_inc(&qm->debug.dfx.mb_err_cnt); return ret; } @@ -663,6 +704,25 @@ int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t = dma_addr, u16 queue, } EXPORT_SYMBOL_GPL(hisi_qm_mb); =20 +int hisi_qm_mb_read(struct hisi_qm *qm, u64 *base, u8 cmd, u16 queue) +{ + struct qm_mailbox mailbox; + int ret; + + qm_mb_pre_init(&mailbox, cmd, 0, queue, 1); + mutex_lock(&qm->mailbox_lock); + ret =3D qm_mb_nolock(qm, &mailbox); + mutex_unlock(&qm->mailbox_lock); + if (ret) + return ret; + + *base =3D le32_to_cpu(mailbox.base_l) | + ((u64)le32_to_cpu(mailbox.base_h) << 32); + + return 0; +} +EXPORT_SYMBOL_GPL(hisi_qm_mb_read); + /* op 0: set xqc information to hardware, 1: get xqc information from hard= ware. */ int qm_set_and_get_xqc(struct hisi_qm *qm, u8 cmd, void *xqc, u32 qp_id, b= ool op) { @@ -1379,12 +1439,10 @@ static int qm_get_vft_v2(struct hisi_qm *qm, u32 *b= ase, u32 *number) u64 sqc_vft; int ret; =20 - ret =3D hisi_qm_mb(qm, QM_MB_CMD_SQC_VFT_V2, 0, 0, 1); + ret =3D hisi_qm_mb_read(qm, &sqc_vft, QM_MB_CMD_SQC_VFT_V2, 0); if (ret) return ret; =20 - sqc_vft =3D readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) | - ((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) << 32); *base =3D QM_SQC_VFT_BASE_MASK_V2 & (sqc_vft >> QM_SQC_VFT_BASE_SHIFT_V2); *number =3D (QM_SQC_VFT_NUM_MASK_V2 & (sqc_vft >> QM_SQC_VFT_NUM_SHIFT_V2)) + 1; @@ -1524,25 +1582,6 @@ static enum acc_err_result qm_hw_error_handle_v2(str= uct hisi_qm *qm) return ACC_ERR_RECOVERED; } =20 -static int qm_get_mb_cmd(struct hisi_qm *qm, u64 *msg, u16 fun_num) -{ - struct qm_mailbox mailbox; - int ret; - - qm_mb_pre_init(&mailbox, QM_MB_CMD_DST, 0, fun_num, 0); - mutex_lock(&qm->mailbox_lock); - ret =3D qm_mb_nolock(qm, &mailbox); - if (ret) - goto err_unlock; - - *msg =3D readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) | - ((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) << 32); - -err_unlock: - mutex_unlock(&qm->mailbox_lock); - return ret; -} - static void qm_clear_cmd_interrupt(struct hisi_qm *qm, u64 vf_mask) { u32 val; @@ -1871,7 +1910,7 @@ static int qm_get_ifc_v3(struct hisi_qm *qm, enum qm_= ifc_cmd *cmd, u32 *data, u3 u64 msg; int ret; =20 - ret =3D qm_get_mb_cmd(qm, &msg, fun_num); + ret =3D hisi_qm_mb_read(qm, &msg, QM_MB_CMD_DST, fun_num); if (ret) return ret; =20 diff --git a/include/linux/hisi_acc_qm.h b/include/linux/hisi_acc_qm.h index f517b9db8392..51a6dc2b97e9 100644 --- a/include/linux/hisi_acc_qm.h +++ b/include/linux/hisi_acc_qm.h @@ -571,6 +571,7 @@ void hisi_qm_reset_done(struct pci_dev *pdev); int hisi_qm_wait_mb_ready(struct hisi_qm *qm); int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue, bool op); +int hisi_qm_mb_read(struct hisi_qm *qm, u64 *base, u8 cmd, u16 queue); =20 struct hisi_acc_sgl_pool; struct hisi_acc_hw_sgl *hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev, --=20 2.33.0 From nobody Sun Feb 8 09:27:32 2026 Received: from canpmsgout10.his.huawei.com (canpmsgout10.his.huawei.com [113.46.200.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2AD0B29E114; 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Sat, 17 Jan 2026 18:18:09 +0800 Received: from localhost.huawei.com (10.90.31.46) by kwepemq200001.china.huawei.com (7.202.195.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Sat, 17 Jan 2026 18:18:08 +0800 From: Chenghai Huang To: , CC: , , , , , Subject: [PATCH 4/4] crypto: hisilicon/qm - increase wait time for mailbox Date: Sat, 17 Jan 2026 18:18:06 +0800 Message-ID: <20260117101806.2172918-5-huangchenghai2@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260117101806.2172918-1-huangchenghai2@huawei.com> References: <20260117101806.2172918-1-huangchenghai2@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100001.china.huawei.com (7.221.188.238) To kwepemq200001.china.huawei.com (7.202.195.16) Content-Type: text/plain; charset="utf-8" From: Weili Qian The device requires more time to process queue stop and function stop mailbox commands compared to other mailbox commands . In the current driver, the mailbox processing wait time for queue stop and function stop is less than the device timeout, which may cause the driver to incorrectly assume that the mailbox processing has failed. Therefore, the driver wait time for queue stop and function stop should be set to be greater than the device timeout. And PF and VF communication relies on mailbox, the communication wait time should also be modified. Signed-off-by: Weili Qian Signed-off-by: Chenghai Huang --- drivers/crypto/hisilicon/qm.c | 34 ++++++++++++++++++++++++---------- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c index 94f96b6b38f5..571d0d250242 100644 --- a/drivers/crypto/hisilicon/qm.c +++ b/drivers/crypto/hisilicon/qm.c @@ -32,6 +32,8 @@ #define QM_MB_PING_ALL_VFS 0xffff #define QM_MB_STATUS_MASK GENMASK(12, 9) #define QM_MB_BUSY_MASK BIT(13) +#define QM_MB_MAX_WAIT_TIMEOUT USEC_PER_SEC +#define QM_MB_MAX_STOP_TIMEOUT (5 * USEC_PER_SEC) =20 /* sqc shift */ #define QM_SQ_HOP_NUM_SHIFT 0 @@ -189,8 +191,8 @@ #define QM_IFC_INT_DISABLE BIT(0) #define QM_IFC_INT_STATUS_MASK BIT(0) #define QM_IFC_INT_SET_MASK BIT(0) -#define QM_WAIT_DST_ACK 10 -#define QM_MAX_PF_WAIT_COUNT 10 +#define QM_WAIT_DST_ACK 1000 +#define QM_MAX_PF_WAIT_COUNT 20 #define QM_MAX_VF_WAIT_COUNT 40 #define QM_VF_RESET_WAIT_US 20000 #define QM_VF_RESET_WAIT_CNT 3000 @@ -645,14 +647,14 @@ int hisi_qm_wait_mb_ready(struct hisi_qm *qm) } EXPORT_SYMBOL_GPL(hisi_qm_wait_mb_ready); =20 -static int qm_wait_mb_finish(struct hisi_qm *qm, struct qm_mailbox *mailbo= x) +static int qm_wait_mb_finish(struct hisi_qm *qm, struct qm_mailbox *mailbo= x, u32 wait_timeout) { struct device *dev =3D &qm->pdev->dev; int ret; =20 ret =3D read_poll_timeout(qm_mb_read, *mailbox, !(le16_to_cpu(mailbox->w0) & QM_MB_BUSY_MASK), - POLL_PERIOD, POLL_TIMEOUT, + POLL_PERIOD, wait_timeout, true, qm); if (ret) { dev_err(dev, "QM mailbox operation timeout!\n"); @@ -667,7 +669,7 @@ static int qm_wait_mb_finish(struct hisi_qm *qm, struct= qm_mailbox *mailbox) return 0; } =20 -static int qm_mb_nolock(struct hisi_qm *qm, struct qm_mailbox *mailbox) +static int qm_mb_nolock(struct hisi_qm *qm, struct qm_mailbox *mailbox, u3= 2 wait_timeout) { int ret; =20 @@ -677,7 +679,7 @@ static int qm_mb_nolock(struct hisi_qm *qm, struct qm_m= ailbox *mailbox) =20 qm_mb_write(qm, mailbox); =20 - ret =3D qm_wait_mb_finish(qm, mailbox); + ret =3D qm_wait_mb_finish(qm, mailbox, wait_timeout); if (ret) goto mb_err_cnt_increase; =20 @@ -692,12 +694,24 @@ int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t= dma_addr, u16 queue, bool op) { struct qm_mailbox mailbox; + u32 wait_timeout; int ret; =20 + if (cmd =3D=3D QM_MB_CMD_STOP_QP || cmd =3D=3D QM_MB_CMD_FLUSH_QM) + wait_timeout =3D QM_MB_MAX_STOP_TIMEOUT; + else + wait_timeout =3D QM_MB_MAX_WAIT_TIMEOUT; + + /* No need to judge if master OOO is blocked. */ + if (qm_check_dev_error(qm)) { + dev_err(&qm->pdev->dev, "QM mailbox operation failed since qm is stop!\n= "); + return -EIO; + } + qm_mb_pre_init(&mailbox, cmd, dma_addr, queue, op); =20 mutex_lock(&qm->mailbox_lock); - ret =3D qm_mb_nolock(qm, &mailbox); + ret =3D qm_mb_nolock(qm, &mailbox, wait_timeout); mutex_unlock(&qm->mailbox_lock); =20 return ret; @@ -711,7 +725,7 @@ int hisi_qm_mb_read(struct hisi_qm *qm, u64 *base, u8 c= md, u16 queue) =20 qm_mb_pre_init(&mailbox, cmd, 0, queue, 1); mutex_lock(&qm->mailbox_lock); - ret =3D qm_mb_nolock(qm, &mailbox); + ret =3D qm_mb_nolock(qm, &mailbox, QM_MB_MAX_WAIT_TIMEOUT); mutex_unlock(&qm->mailbox_lock); if (ret) return ret; @@ -769,7 +783,7 @@ int qm_set_and_get_xqc(struct hisi_qm *qm, u8 cmd, void= *xqc, u32 qp_id, bool op memcpy(tmp_xqc, xqc, size); =20 qm_mb_pre_init(&mailbox, cmd, xqc_dma, qp_id, op); - ret =3D qm_mb_nolock(qm, &mailbox); + ret =3D qm_mb_nolock(qm, &mailbox, QM_MB_MAX_WAIT_TIMEOUT); if (!ret && op) memcpy(xqc, tmp_xqc, size); =20 @@ -1897,7 +1911,7 @@ static int qm_set_ifc_begin_v3(struct hisi_qm *qm, en= um qm_ifc_cmd cmd, u32 data =20 qm_mb_pre_init(&mailbox, QM_MB_CMD_SRC, msg, fun_num, 0); mutex_lock(&qm->mailbox_lock); - return qm_mb_nolock(qm, &mailbox); + return qm_mb_nolock(qm, &mailbox, QM_MB_MAX_WAIT_TIMEOUT); } =20 static void qm_set_ifc_end_v3(struct hisi_qm *qm) --=20 2.33.0