From nobody Sun Feb 8 04:57:28 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B80F032D0CC; Sat, 17 Jan 2026 11:17:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768648651; cv=none; b=OiwbsBZEeImMKxyDK5HOSD9eNkfsVWAN37KGQmeUMCJMiLAhBZXUa0sYTfSdCZdJ6+r2l84hhxYbOQIFl1o+JmmvR3NRSW8TApodUQYinPUirlPAbzaPkrCjRorFLhf9vhvO7k5hmQKjAG+0eNdTIh0oniAsm3zIlnMubosloaU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768648651; c=relaxed/simple; bh=fMFjNVfJUJK5VN+Q6Q9ptUJYcET4fbirvqq7Y5jOHoc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=QM7l7AdZiLopmeN8z6LC16XvhDQs89VDazxrxz9ifXSfFYTUcF6sA6bNcvbUvmS+EzQnZvY4ZOX9j1I02rs/LdQvo4dQtqZfib9qvGY/hsmIVGtrPSQwtDAuyS3ZsviAfZnSBIFTXajMwBp0tfCVyFBdNwTEcyd2idq1PAd5/fc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Sat, 17 Jan 2026 19:17:17 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Sat, 17 Jan 2026 19:17:17 +0800 From: Billy Tsai Date: Sat, 17 Jan 2026 19:17:08 +0800 Subject: [PATCH 1/5] gpio: aspeed-sgpio: Change the macro to support deferred probe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260117-upstream_sgpio-v1-1-850ef3ffb680@aspeedtech.com> References: <20260117-upstream_sgpio-v1-0-850ef3ffb680@aspeedtech.com> In-Reply-To: <20260117-upstream_sgpio-v1-0-850ef3ffb680@aspeedtech.com> To: Linus Walleij , Bartosz Golaszewski , Joel Stanley , Andrew Jeffery , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , "Andrew Jeffery" , , , Billy Tsai X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768648637; l=1688; i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id; bh=fMFjNVfJUJK5VN+Q6Q9ptUJYcET4fbirvqq7Y5jOHoc=; b=9EIQUzfuyfySwb/EFm0C5bcEqwAY3UXvUjcFnygWmMjnJ9uNZVYEsKiAmq1MeqA0pabJ5y1C7 Sezf7nTpx/uBfCjf5VmGZshvDdXvfx21ty7qHiy4b3i4NzUtCqDRkjE X-Developer-Key: i=billy_tsai@aspeedtech.com; a=ed25519; pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ= Use module_platform_driver() to replace module_platform_driver_probe(). The former utilizes platform_driver_register(), which allows the driver to defer probing when it doesn't acquire the necessary resources due to probe order. In contrast, the latter uses __platform_driver_probe(), which includes the comment "Note that this is incompatible with deferred probing." Since our SGPIO driver requires access to the clock resource, the former is more suitable. Signed-off-by: Billy Tsai Reviewed-by: Linus Walleij --- drivers/gpio/gpio-aspeed-sgpio.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sg= pio.c index 7622f9e9f54a..318cd0e39741 100644 --- a/drivers/gpio/gpio-aspeed-sgpio.c +++ b/drivers/gpio/gpio-aspeed-sgpio.c @@ -516,7 +516,7 @@ static const struct of_device_id aspeed_sgpio_of_table[= ] =3D { =20 MODULE_DEVICE_TABLE(of, aspeed_sgpio_of_table); =20 -static int __init aspeed_sgpio_probe(struct platform_device *pdev) +static int aspeed_sgpio_probe(struct platform_device *pdev) { u32 nr_gpios, sgpio_freq, sgpio_clk_div, gpio_cnt_regval, pin_mask; const struct aspeed_sgpio_pdata *pdata; @@ -611,11 +611,12 @@ static int __init aspeed_sgpio_probe(struct platform_= device *pdev) } =20 static struct platform_driver aspeed_sgpio_driver =3D { + .probe =3D aspeed_sgpio_probe, .driver =3D { .name =3D KBUILD_MODNAME, .of_match_table =3D aspeed_sgpio_of_table, }, }; =20 -module_platform_driver_probe(aspeed_sgpio_driver, aspeed_sgpio_probe); +module_platform_driver(aspeed_sgpio_driver); MODULE_DESCRIPTION("Aspeed Serial GPIO Driver"); --=20 2.34.1 From nobody Sun Feb 8 04:57:28 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACD273314DC; Sat, 17 Jan 2026 11:17:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768648654; cv=none; b=qOKqynPtdYlZsyZVOkLWd2IytJ9kid73e8M/Irbcxv7rnfMw/s1o7gxoXOY3krpuYfdYpcuNTJdIr7dvNgkGnDB68z01ArdMW2ft5PxSvJGn7zC6yTznvBzQFhEvXHftKe3os4MOdIK7uYO/0kLA2ql/TzUoLvrSdhujHMn+Rp0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768648654; c=relaxed/simple; bh=SKQ0UCfpVZsXx1vqEVOZz/+nmvbJAsfFSAPsnOZxtWk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=W+i/qesPFnrpf5kKlfqEzO0ROvlPFvy3+mwvK34uUMx4fEXjltetd/4RWC+OeMjqY0MDphG7qxnkKfjB7/er3RJd4a3dOjjMatuezbv91KFPCOLGToQlFYdCuNgJHKd1Q/LfLBM1ynGqynrTNL1zQEugEsed9MsXviKdHaTDxkM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Sat, 17 Jan 2026 19:17:17 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Sat, 17 Jan 2026 19:17:17 +0800 From: Billy Tsai Date: Sat, 17 Jan 2026 19:17:09 +0800 Subject: [PATCH 2/5] gpio: aspeed-sgpio: Remove unused bank name field Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260117-upstream_sgpio-v1-2-850ef3ffb680@aspeedtech.com> References: <20260117-upstream_sgpio-v1-0-850ef3ffb680@aspeedtech.com> In-Reply-To: <20260117-upstream_sgpio-v1-0-850ef3ffb680@aspeedtech.com> To: Linus Walleij , Bartosz Golaszewski , Joel Stanley , Andrew Jeffery , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , "Andrew Jeffery" , , , Billy Tsai X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768648637; l=1279; i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id; bh=SKQ0UCfpVZsXx1vqEVOZz/+nmvbJAsfFSAPsnOZxtWk=; b=k2LVCG2VagQD1eIDaRMgFRwUurzQ/Cu9gfgS0o7/bRo9EEg1cVDQLuXQVxNFVa9668aEDQGiM v1qVLcFLYU2A7S/oafjJLDbd7aJj7CZ/YNHfOOIZlxD/6wjXE3hp/RQ X-Developer-Key: i=billy_tsai@aspeedtech.com; a=ed25519; pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ= Drops the names array from the bank struct and its initializers, as it is unused in the driver. Signed-off-by: Billy Tsai Reviewed-by: Linus Walleij --- drivers/gpio/gpio-aspeed-sgpio.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sg= pio.c index 318cd0e39741..a96ed6d8a55d 100644 --- a/drivers/gpio/gpio-aspeed-sgpio.c +++ b/drivers/gpio/gpio-aspeed-sgpio.c @@ -43,7 +43,6 @@ struct aspeed_sgpio_bank { u16 rdata_reg; u16 irq_regs; u16 tolerance_regs; - const char names[4][3]; }; =20 /* @@ -59,28 +58,24 @@ static const struct aspeed_sgpio_bank aspeed_sgpio_bank= s[] =3D { .rdata_reg =3D 0x0070, .irq_regs =3D 0x0004, .tolerance_regs =3D 0x0018, - .names =3D { "A", "B", "C", "D" }, }, { .val_regs =3D 0x001C, .rdata_reg =3D 0x0074, .irq_regs =3D 0x0020, .tolerance_regs =3D 0x0034, - .names =3D { "E", "F", "G", "H" }, }, { .val_regs =3D 0x0038, .rdata_reg =3D 0x0078, .irq_regs =3D 0x003C, .tolerance_regs =3D 0x0050, - .names =3D { "I", "J", "K", "L" }, }, { .val_regs =3D 0x0090, .rdata_reg =3D 0x007C, .irq_regs =3D 0x0094, .tolerance_regs =3D 0x00A8, - .names =3D { "M", "N", "O", "P" }, }, }; =20 --=20 2.34.1 From nobody Sun Feb 8 04:57:28 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6822A331A79; Sat, 17 Jan 2026 11:17:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768648658; cv=none; b=cMQUtbH+0bhlMEK9ixLs3R8h490+iI1BFzCQyJ0tkikicilHsj4GU5JAoHXlGTo9VKYaRWk0Y3g/YC8PU6KwfFazq/LfHyh9ypxrsApwJGR15OHeP7gKvcAKxPRpUfovUH9re6hYKT4IuhvDyj/zV1whQ0Z/H4rYv3FSTFLE1fY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768648658; c=relaxed/simple; bh=waDaV8apJ6t/c4i0hcqNZDcoMEOmxJAN2etTE7z0YVY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=ATeiAlX3H9IEA9eD5DVrYiEKNijhtPUIY5qsOH8kQpQfuauMIA6RIQX0RDmg7htVXP9BSW9b+fGYzpXpFtWke3ISIeZMPzMRbv6vwC3rvSE3VPzfevjb3GWmhj4rI0Fgv8gD7PUDvyHVmTZ9Dp4fAn0+0bqV7AmjC6Za1Ns5PaM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Sat, 17 Jan 2026 19:17:17 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Sat, 17 Jan 2026 19:17:17 +0800 From: Billy Tsai Date: Sat, 17 Jan 2026 19:17:10 +0800 Subject: [PATCH 3/5] gpio: aspeed-sgpio: Create llops to handle hardware access Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260117-upstream_sgpio-v1-3-850ef3ffb680@aspeedtech.com> References: <20260117-upstream_sgpio-v1-0-850ef3ffb680@aspeedtech.com> In-Reply-To: <20260117-upstream_sgpio-v1-0-850ef3ffb680@aspeedtech.com> To: Linus Walleij , Bartosz Golaszewski , Joel Stanley , Andrew Jeffery , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , "Andrew Jeffery" , , , Billy Tsai X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768648637; l=13990; i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id; bh=waDaV8apJ6t/c4i0hcqNZDcoMEOmxJAN2etTE7z0YVY=; b=WK3cp1IIzqzbmV2my4CSbK3wCzTSC1LiMoaGVO5pfflzPb+If8ydHApY7Pa2elknQnQ/m4T4O /wzSxBxZMCuACyPS53E0NqkJXTW36CaB1KVdf8GOBiz1ds3hrzWBsbT X-Developer-Key: i=billy_tsai@aspeedtech.com; a=ed25519; pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ= Add low-level operations (llops) to abstract the register access for SGPIO registers. With this abstraction layer, the driver can separate the hardware and software logic, making it easier to extend the driver to support different hardware register layouts. Signed-off-by: Billy Tsai Reviewed-by: Linus Walleij --- drivers/gpio/gpio-aspeed-sgpio.c | 239 ++++++++++++++++++-----------------= ---- 1 file changed, 111 insertions(+), 128 deletions(-) diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sg= pio.c index a96ed6d8a55d..a2401f4e8e37 100644 --- a/drivers/gpio/gpio-aspeed-sgpio.c +++ b/drivers/gpio/gpio-aspeed-sgpio.c @@ -27,6 +27,7 @@ =20 struct aspeed_sgpio_pdata { const u32 pin_mask; + const struct aspeed_sgpio_llops *llops; }; =20 struct aspeed_sgpio { @@ -36,6 +37,7 @@ struct aspeed_sgpio { raw_spinlock_t lock; void __iomem *base; int irq; + const struct aspeed_sgpio_pdata *pdata; }; =20 struct aspeed_sgpio_bank { @@ -90,6 +92,15 @@ enum aspeed_sgpio_reg { reg_tolerance, }; =20 +struct aspeed_sgpio_llops { + void (*reg_bit_set)(struct aspeed_sgpio *gpio, unsigned int offset, + const enum aspeed_sgpio_reg reg, bool val); + bool (*reg_bit_get)(struct aspeed_sgpio *gpio, unsigned int offset, + const enum aspeed_sgpio_reg reg); + int (*reg_bank_get)(struct aspeed_sgpio *gpio, unsigned int offset, + const enum aspeed_sgpio_reg reg); +}; + #define GPIO_VAL_VALUE 0x00 #define GPIO_IRQ_ENABLE 0x00 #define GPIO_IRQ_TYPE0 0x04 @@ -97,9 +108,9 @@ enum aspeed_sgpio_reg { #define GPIO_IRQ_TYPE2 0x0C #define GPIO_IRQ_STATUS 0x10 =20 -static void __iomem *bank_reg(struct aspeed_sgpio *gpio, - const struct aspeed_sgpio_bank *bank, - const enum aspeed_sgpio_reg reg) +static void __iomem *aspeed_sgpio_g4_bank_reg(struct aspeed_sgpio *gpio, + const struct aspeed_sgpio_bank *bank, + const enum aspeed_sgpio_reg reg) { switch (reg) { case reg_val: @@ -165,14 +176,13 @@ static bool aspeed_sgpio_is_input(unsigned int offset) static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset) { struct aspeed_sgpio *gpio =3D gpiochip_get_data(gc); - const struct aspeed_sgpio_bank *bank =3D to_bank(offset); enum aspeed_sgpio_reg reg; int rc =3D 0; =20 guard(raw_spinlock_irqsave)(&gpio->lock); =20 reg =3D aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata; - rc =3D !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset)); + rc =3D gpio->pdata->llops->reg_bit_get(gpio, offset, reg); =20 return rc; } @@ -180,26 +190,11 @@ static int aspeed_sgpio_get(struct gpio_chip *gc, uns= igned int offset) static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int = val) { struct aspeed_sgpio *gpio =3D gpiochip_get_data(gc); - const struct aspeed_sgpio_bank *bank =3D to_bank(offset); - void __iomem *addr_r, *addr_w; - u32 reg =3D 0; =20 if (aspeed_sgpio_is_input(offset)) return -EINVAL; =20 - /* Since this is an output, read the cached value from rdata, then - * update val. */ - addr_r =3D bank_reg(gpio, bank, reg_rdata); - addr_w =3D bank_reg(gpio, bank, reg_val); - - reg =3D ioread32(addr_r); - - if (val) - reg |=3D GPIO_BIT(offset); - else - reg &=3D ~GPIO_BIT(offset); - - iowrite32(reg, addr_w); + gpio->pdata->llops->reg_bit_set(gpio, offset, reg_val, val); =20 return 0; } @@ -238,69 +233,34 @@ static int aspeed_sgpio_get_direction(struct gpio_chi= p *gc, unsigned int offset) return !!aspeed_sgpio_is_input(offset); } =20 -static void irqd_to_aspeed_sgpio_data(struct irq_data *d, - struct aspeed_sgpio **gpio, - const struct aspeed_sgpio_bank **bank, - u32 *bit, int *offset) -{ - struct aspeed_sgpio *internal; - - *offset =3D irqd_to_hwirq(d); - internal =3D irq_data_get_irq_chip_data(d); - WARN_ON(!internal); - - *gpio =3D internal; - *bank =3D to_bank(*offset); - *bit =3D GPIO_BIT(*offset); -} =20 static void aspeed_sgpio_irq_ack(struct irq_data *d) { - const struct aspeed_sgpio_bank *bank; - struct aspeed_sgpio *gpio; - void __iomem *status_addr; - int offset; - u32 bit; - - irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset); - - status_addr =3D bank_reg(gpio, bank, reg_irq_status); + struct aspeed_sgpio *gpio =3D irq_data_get_irq_chip_data(d); + int offset =3D irqd_to_hwirq(d); =20 guard(raw_spinlock_irqsave)(&gpio->lock); =20 - iowrite32(bit, status_addr); + gpio->pdata->llops->reg_bit_set(gpio, offset, reg_irq_status, 1); } =20 static void aspeed_sgpio_irq_set_mask(struct irq_data *d, bool set) { - const struct aspeed_sgpio_bank *bank; - struct aspeed_sgpio *gpio; - u32 reg, bit; - void __iomem *addr; - int offset; - - irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset); - addr =3D bank_reg(gpio, bank, reg_irq_enable); + struct aspeed_sgpio *gpio =3D irq_data_get_irq_chip_data(d); + int offset =3D irqd_to_hwirq(d); =20 /* Unmasking the IRQ */ if (set) - gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(d)); - - scoped_guard(raw_spinlock_irqsave, &gpio->lock) { - reg =3D ioread32(addr); - if (set) - reg |=3D bit; - else - reg &=3D ~bit; - - iowrite32(reg, addr); + gpiochip_enable_irq(&gpio->chip, offset); + scoped_guard(raw_spinlock_irqsave, &gpio->lock) + { + gpio->pdata->llops->reg_bit_set(gpio, offset, reg_irq_enable, + set); } =20 /* Masking the IRQ */ if (!set) - gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(d)); - - + gpiochip_disable_irq(&gpio->chip, offset); } =20 static void aspeed_sgpio_irq_mask(struct irq_data *d) @@ -318,30 +278,25 @@ static int aspeed_sgpio_set_type(struct irq_data *d, = unsigned int type) u32 type0 =3D 0; u32 type1 =3D 0; u32 type2 =3D 0; - u32 bit, reg; - const struct aspeed_sgpio_bank *bank; irq_flow_handler_t handler; - struct aspeed_sgpio *gpio; - void __iomem *addr; - int offset; - - irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset); + struct aspeed_sgpio *gpio =3D irq_data_get_irq_chip_data(d); + int offset =3D irqd_to_hwirq(d); =20 switch (type & IRQ_TYPE_SENSE_MASK) { case IRQ_TYPE_EDGE_BOTH: - type2 |=3D bit; + type2 =3D 1; fallthrough; case IRQ_TYPE_EDGE_RISING: - type0 |=3D bit; + type0 =3D 1; fallthrough; case IRQ_TYPE_EDGE_FALLING: handler =3D handle_edge_irq; break; case IRQ_TYPE_LEVEL_HIGH: - type0 |=3D bit; + type0 =3D 1; fallthrough; case IRQ_TYPE_LEVEL_LOW: - type1 |=3D bit; + type1 =3D 1; handler =3D handle_level_irq; break; default: @@ -349,20 +304,9 @@ static int aspeed_sgpio_set_type(struct irq_data *d, u= nsigned int type) } =20 scoped_guard(raw_spinlock_irqsave, &gpio->lock) { - addr =3D bank_reg(gpio, bank, reg_irq_type0); - reg =3D ioread32(addr); - reg =3D (reg & ~bit) | type0; - iowrite32(reg, addr); - - addr =3D bank_reg(gpio, bank, reg_irq_type1); - reg =3D ioread32(addr); - reg =3D (reg & ~bit) | type1; - iowrite32(reg, addr); - - addr =3D bank_reg(gpio, bank, reg_irq_type2); - reg =3D ioread32(addr); - reg =3D (reg & ~bit) | type2; - iowrite32(reg, addr); + gpio->pdata->llops->reg_bit_set(gpio, offset, reg_irq_type0, type0); + gpio->pdata->llops->reg_bit_set(gpio, offset, reg_irq_type1, type1); + gpio->pdata->llops->reg_bit_set(gpio, offset, reg_irq_type2, type2); } =20 irq_set_handler_locked(d, handler); @@ -374,16 +318,14 @@ static void aspeed_sgpio_irq_handler(struct irq_desc = *desc) { struct gpio_chip *gc =3D irq_desc_get_handler_data(desc); struct irq_chip *ic =3D irq_desc_get_chip(desc); - struct aspeed_sgpio *data =3D gpiochip_get_data(gc); + struct aspeed_sgpio *gpio =3D gpiochip_get_data(gc); unsigned int i, p; unsigned long reg; =20 chained_irq_enter(ic, desc); =20 for (i =3D 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) { - const struct aspeed_sgpio_bank *bank =3D &aspeed_sgpio_banks[i]; - - reg =3D ioread32(bank_reg(data, bank, reg_irq_status)); + reg =3D gpio->pdata->llops->reg_bank_get(gpio, i << 6, reg_irq_status); =20 for_each_set_bit(p, ®, 32) generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2); @@ -394,12 +336,8 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *= desc) =20 static void aspeed_sgpio_irq_print_chip(struct irq_data *d, struct seq_fil= e *p) { - const struct aspeed_sgpio_bank *bank; - struct aspeed_sgpio *gpio; - u32 bit; - int offset; + struct aspeed_sgpio *gpio =3D irq_data_get_irq_chip_data(d); =20 - irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset); seq_puts(p, dev_name(gpio->dev)); } =20 @@ -417,7 +355,6 @@ static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio = *gpio, struct platform_device *pdev) { int rc, i; - const struct aspeed_sgpio_bank *bank; struct gpio_irq_chip *irq; =20 rc =3D platform_get_irq(pdev, 0); @@ -427,12 +364,11 @@ static int aspeed_sgpio_setup_irqs(struct aspeed_sgpi= o *gpio, gpio->irq =3D rc; =20 /* Disable IRQ and clear Interrupt status registers for all SGPIO Pins. */ - for (i =3D 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) { - bank =3D &aspeed_sgpio_banks[i]; + for (i =3D 0; i < gpio->chip.ngpio; i +=3D 2) { /* disable irq enable bits */ - iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_enable)); + gpio->pdata->llops->reg_bit_set(gpio, i, reg_irq_enable, 0); /* clear status bits */ - iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_status)); + gpio->pdata->llops->reg_bit_set(gpio, i, reg_irq_status, 1); } =20 irq =3D &gpio->chip.irq; @@ -446,42 +382,90 @@ static int aspeed_sgpio_setup_irqs(struct aspeed_sgpi= o *gpio, irq->num_parents =3D 1; =20 /* Apply default IRQ settings */ - for (i =3D 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) { - bank =3D &aspeed_sgpio_banks[i]; + for (i =3D 0; i < gpio->chip.ngpio; i +=3D 2) { /* set falling or level-low irq */ - iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type0)); + gpio->pdata->llops->reg_bit_set(gpio, i, reg_irq_type0, 0); /* trigger type is edge */ - iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type1)); + gpio->pdata->llops->reg_bit_set(gpio, i, reg_irq_type1, 0); /* single edge trigger */ - iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type2)); + gpio->pdata->llops->reg_bit_set(gpio, i, reg_irq_type2, 0); } =20 return 0; } =20 +static void aspeed_sgpio_g4_reg_bit_set(struct aspeed_sgpio *gpio, unsigne= d int offset, + const enum aspeed_sgpio_reg reg, bool val) +{ + const struct aspeed_sgpio_bank *bank =3D to_bank(offset); + void __iomem *addr =3D aspeed_sgpio_g4_bank_reg(gpio, bank, reg); + u32 temp; + + if (reg =3D=3D reg_val) { + /* Since this is an output, read the cached value from rdata, then updat= e val. */ + addr =3D aspeed_sgpio_g4_bank_reg(gpio, bank, reg_rdata); + temp =3D ioread32(addr); + if (val) + temp |=3D GPIO_BIT(offset); + else + temp &=3D ~GPIO_BIT(offset); + + addr =3D aspeed_sgpio_g4_bank_reg(gpio, bank, reg_val); + iowrite32(temp, addr); + } else if (reg =3D=3D reg_irq_status) { + if (val) + iowrite32(GPIO_BIT(offset), addr); + } else { + /* When setting other registers, we read from the register itself */ + temp =3D ioread32(addr); + if (val) + temp |=3D GPIO_BIT(offset); + else + temp &=3D ~GPIO_BIT(offset); + iowrite32(temp, addr); + } +} + +static bool aspeed_sgpio_g4_reg_bit_get(struct aspeed_sgpio *gpio, unsigne= d int offset, + const enum aspeed_sgpio_reg reg) +{ + const struct aspeed_sgpio_bank *bank =3D to_bank(offset); + void __iomem *addr =3D aspeed_sgpio_g4_bank_reg(gpio, bank, reg); + + return !!(ioread32(addr) & GPIO_BIT(offset)); +} + +static int aspeed_sgpio_g4_reg_bank_get(struct aspeed_sgpio *gpio, unsigne= d int offset, + const enum aspeed_sgpio_reg reg) +{ + const struct aspeed_sgpio_bank *bank =3D to_bank(offset); + void __iomem *addr =3D aspeed_sgpio_g4_bank_reg(gpio, bank, reg); + + if (reg =3D=3D reg_irq_status) + return ioread32(addr); + else + return -EOPNOTSUPP; +} + +static const struct aspeed_sgpio_llops aspeed_sgpio_g4_llops =3D { + .reg_bit_set =3D aspeed_sgpio_g4_reg_bit_set, + .reg_bit_get =3D aspeed_sgpio_g4_reg_bit_get, + .reg_bank_get =3D aspeed_sgpio_g4_reg_bank_get, +}; + static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata =3D { .pin_mask =3D GENMASK(9, 6), + .llops =3D &aspeed_sgpio_g4_llops, }; =20 static int aspeed_sgpio_reset_tolerance(struct gpio_chip *chip, unsigned int offset, bool enable) { struct aspeed_sgpio *gpio =3D gpiochip_get_data(chip); - void __iomem *reg; - u32 val; - - reg =3D bank_reg(gpio, to_bank(offset), reg_tolerance); =20 guard(raw_spinlock_irqsave)(&gpio->lock); =20 - val =3D readl(reg); - - if (enable) - val |=3D GPIO_BIT(offset); - else - val &=3D ~GPIO_BIT(offset); - - writel(val, reg); + gpio->pdata->llops->reg_bit_set(gpio, offset, reg_tolerance, enable); =20 return 0; } @@ -500,6 +484,7 @@ static int aspeed_sgpio_set_config(struct gpio_chip *ch= ip, unsigned int offset, =20 static const struct aspeed_sgpio_pdata ast2600_sgpiom_pdata =3D { .pin_mask =3D GENMASK(10, 6), + .llops =3D &aspeed_sgpio_g4_llops, }; =20 static const struct of_device_id aspeed_sgpio_of_table[] =3D { @@ -514,7 +499,6 @@ MODULE_DEVICE_TABLE(of, aspeed_sgpio_of_table); static int aspeed_sgpio_probe(struct platform_device *pdev) { u32 nr_gpios, sgpio_freq, sgpio_clk_div, gpio_cnt_regval, pin_mask; - const struct aspeed_sgpio_pdata *pdata; struct aspeed_sgpio *gpio; unsigned long apb_freq; int rc; @@ -529,12 +513,11 @@ static int aspeed_sgpio_probe(struct platform_device = *pdev) =20 gpio->dev =3D &pdev->dev; =20 - pdata =3D device_get_match_data(&pdev->dev); - if (!pdata) + gpio->pdata =3D device_get_match_data(&pdev->dev); + if (!gpio->pdata) return -EINVAL; =20 - pin_mask =3D pdata->pin_mask; - + pin_mask =3D gpio->pdata->pin_mask; rc =3D device_property_read_u32(&pdev->dev, "ngpios", &nr_gpios); if (rc < 0) { dev_err(&pdev->dev, "Could not read ngpios property\n"); --=20 2.34.1 From nobody Sun Feb 8 04:57:28 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D45DF33507B; Sat, 17 Jan 2026 11:17:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; 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spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Sat, 17 Jan 2026 19:17:17 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Sat, 17 Jan 2026 19:17:17 +0800 From: Billy Tsai Date: Sat, 17 Jan 2026 19:17:11 +0800 Subject: [PATCH 4/5] dt-bindings: gpio: aspeed,sgpio: Support ast2700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260117-upstream_sgpio-v1-4-850ef3ffb680@aspeedtech.com> References: <20260117-upstream_sgpio-v1-0-850ef3ffb680@aspeedtech.com> In-Reply-To: <20260117-upstream_sgpio-v1-0-850ef3ffb680@aspeedtech.com> To: Linus Walleij , Bartosz Golaszewski , Joel Stanley , Andrew Jeffery , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , "Andrew Jeffery" , , , Billy Tsai X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768648637; l=1334; i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id; bh=XG7pFsnR1EluRR+EFdEVQzRXxWGFIGc/mPiruNMQ0xs=; b=fBUpqWXZ3gZbvVmGZDnwQESir3BVUnInQZVNigV+6h1dREc3oa9lSK1yJ/gLlHqEIx3FesdjB wD22J7LklN4BMVLJoVCp4EMHEn3ZEOSfWnSTK3dZGETbOg7O5CMSz5d X-Developer-Key: i=billy_tsai@aspeedtech.com; a=ed25519; pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ= The AST2700 is the 7th generation SoC from Aspeed, featuring two SGPIO master controllers: both with 256 serial inputs and outputs. Signed-off-by: Billy Tsai Acked-by: Krzysztof Kozlowski Reviewed-by: Linus Walleij --- Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml b/Doc= umentation/devicetree/bindings/gpio/aspeed,sgpio.yaml index 1046f0331c09..974185e3478f 100644 --- a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml +++ b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml @@ -10,7 +10,8 @@ maintainers: - Andrew Jeffery =20 description: - This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC, + This SGPIO controller is for ASPEED AST2400, AST2500, AST2600 and AST270= 0 SoC, + AST2700 have two sgpio master both with 256 pins, AST2600 have two sgpio master one with 128 pins another one with 80 pins, AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial GPIO pins can be programmed to support the following options @@ -27,6 +28,7 @@ properties: - aspeed,ast2400-sgpio - aspeed,ast2500-sgpio - aspeed,ast2600-sgpiom + - aspeed,ast2700-sgpiom =20 reg: maxItems: 1 --=20 2.34.1 From nobody Sun Feb 8 04:57:28 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1CAD335573; Sat, 17 Jan 2026 11:17:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768648666; cv=none; b=oUSvj5GdjsthHvFUlcSFaPne7Tn8tnxM1vZTnL0AYnjAt8LWZeboqnQ/vFLVmCbdNk0Up3P1xU6/qnF+PjVfTK/41UEgRk4UilzqVv0fUuQXobV9HtEI1X7owV5HzoPBvKnYzuTIuumE3B/DFMRAkk72ymoad0nqUZF/s0NuLrU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768648666; c=relaxed/simple; bh=7Fu2o997lanr8Aykv8Nr8m2+OkvdinLwokWjAcgDTaQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=EtmwPO5IPopqXs+qzk3sC25VZceXNQjY8oKlunmCdJl+bHwaXqFJQP/qpITDa6Vh9NxoZ9N4z40JG4Tyy7u2rPMVPzx/JB27E4RnPBcB/MOqEl3/su2UYLyPXA1KY0CvfpyGA3Gcto52B5zOmqHlHZHzlexzUO+5O18grybYaw0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Sat, 17 Jan 2026 19:17:17 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Sat, 17 Jan 2026 19:17:17 +0800 From: Billy Tsai Date: Sat, 17 Jan 2026 19:17:12 +0800 Subject: [PATCH 5/5] gpio: aspeed-sgpio: Support G7 Aspeed sgpiom controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260117-upstream_sgpio-v1-5-850ef3ffb680@aspeedtech.com> References: <20260117-upstream_sgpio-v1-0-850ef3ffb680@aspeedtech.com> In-Reply-To: <20260117-upstream_sgpio-v1-0-850ef3ffb680@aspeedtech.com> To: Linus Walleij , Bartosz Golaszewski , Joel Stanley , Andrew Jeffery , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , "Andrew Jeffery" , , , Billy Tsai X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768648637; l=6430; i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id; bh=7Fu2o997lanr8Aykv8Nr8m2+OkvdinLwokWjAcgDTaQ=; b=gMBbmy9iHd2sG7jfiVUJa54edrL9tfbnS070gbokV3OCF06CNh2XPTWutGMCgFTG5PSZ5UTUD M8fNNAbsTKNDPQEj2lwbnlOGwFOM2ADZR1zjAymioUfKmJDTRo+YxZl X-Developer-Key: i=billy_tsai@aspeedtech.com; a=ed25519; pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ= In the 7th generation of the SoC from Aspeed, the control logic of the SGPIO controller has been updated to support per-pin control. Each pin now has its own 32-bit register, allowing for individual control of the pin's value, interrupt type, and other settings. Signed-off-by: Billy Tsai Reviewed-by: Linus Walleij --- drivers/gpio/gpio-aspeed-sgpio.c | 115 +++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 111 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sg= pio.c index a2401f4e8e37..840a2486e3de 100644 --- a/drivers/gpio/gpio-aspeed-sgpio.c +++ b/drivers/gpio/gpio-aspeed-sgpio.c @@ -19,7 +19,31 @@ #include #include =20 -#define ASPEED_SGPIO_CTRL 0x54 +#define SGPIO_G7_IRQ_STS_BASE 0x40 +#define SGPIO_G7_IRQ_STS_OFFSET(x) (SGPIO_G7_IRQ_STS_BASE + (x) * 0x4) +#define SGPIO_G7_CTRL_REG_BASE 0x80 +#define SGPIO_G7_CTRL_REG_OFFSET(x) (SGPIO_G7_CTRL_REG_BASE + (x) * 0x4) +#define SGPIO_G7_OUT_DATA BIT(0) +#define SGPIO_G7_PARALLEL_OUT_DATA BIT(1) +#define SGPIO_G7_IRQ_EN BIT(2) +#define SGPIO_G7_IRQ_TYPE0 BIT(3) +#define SGPIO_G7_IRQ_TYPE1 BIT(4) +#define SGPIO_G7_IRQ_TYPE2 BIT(5) +#define SGPIO_G7_RST_TOLERANCE BIT(6) +#define SGPIO_G7_INPUT_MASK BIT(9) +#define SGPIO_G7_HW_BYPASS_EN BIT(10) +#define SGPIO_G7_HW_IN_SEL BIT(11) +#define SGPIO_G7_IRQ_STS BIT(12) +#define SGPIO_G7_IN_DATA BIT(13) +#define SGPIO_G7_PARALLEL_IN_DATA BIT(14) +#define SGPIO_G7_SERIAL_OUT_SEL GENMASK(17, 16) +#define SGPIO_G7_PARALLEL_OUT_SEL GENMASK(19, 18) +#define SELECT_FROM_CSR 0 +#define SELECT_FROM_PARALLEL_IN 1 +#define SELECT_FROM_SERIAL_IN 2 + +#define ASPEED_SGPIO_G4_CFG_OFFSET 0x54 +#define ASPEED_SGPIO_G7_CFG_OFFSET 0x0 =20 #define ASPEED_SGPIO_CLK_DIV_MASK GENMASK(31, 16) #define ASPEED_SGPIO_ENABLE BIT(0) @@ -28,6 +52,7 @@ struct aspeed_sgpio_pdata { const u32 pin_mask; const struct aspeed_sgpio_llops *llops; + const u32 cfg_offset; }; =20 struct aspeed_sgpio { @@ -135,6 +160,30 @@ static void __iomem *aspeed_sgpio_g4_bank_reg(struct a= speed_sgpio *gpio, } } =20 +static u32 aspeed_sgpio_g7_reg_mask(const enum aspeed_sgpio_reg reg) +{ + switch (reg) { + case reg_val: + case reg_rdata: + return SGPIO_G7_OUT_DATA; + case reg_irq_enable: + return SGPIO_G7_IRQ_EN; + case reg_irq_type0: + return SGPIO_G7_IRQ_TYPE0; + case reg_irq_type1: + return SGPIO_G7_IRQ_TYPE1; + case reg_irq_type2: + return SGPIO_G7_IRQ_TYPE2; + case reg_irq_status: + return SGPIO_G7_IRQ_STS; + case reg_tolerance: + return SGPIO_G7_RST_TOLERANCE; + default: + WARN_ON_ONCE(1); + return 0; + } +} + #define GPIO_BANK(x) ((x) >> 6) #define GPIO_OFFSET(x) ((x) & GENMASK(5, 0)) #define GPIO_BIT(x) BIT(GPIO_OFFSET(x) >> 1) @@ -319,12 +368,13 @@ static void aspeed_sgpio_irq_handler(struct irq_desc = *desc) struct gpio_chip *gc =3D irq_desc_get_handler_data(desc); struct irq_chip *ic =3D irq_desc_get_chip(desc); struct aspeed_sgpio *gpio =3D gpiochip_get_data(gc); - unsigned int i, p; + unsigned int i, p, banks; unsigned long reg; =20 chained_irq_enter(ic, desc); =20 - for (i =3D 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) { + banks =3D DIV_ROUND_UP(gpio->chip.ngpio, 64); + for (i =3D 0; i < banks; i++) { reg =3D gpio->pdata->llops->reg_bank_get(gpio, i << 6, reg_irq_status); =20 for_each_set_bit(p, ®, 32) @@ -456,6 +506,7 @@ static const struct aspeed_sgpio_llops aspeed_sgpio_g4_= llops =3D { static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata =3D { .pin_mask =3D GENMASK(9, 6), .llops =3D &aspeed_sgpio_g4_llops, + .cfg_offset =3D ASPEED_SGPIO_G4_CFG_OFFSET, }; =20 static int aspeed_sgpio_reset_tolerance(struct gpio_chip *chip, @@ -485,12 +536,68 @@ static int aspeed_sgpio_set_config(struct gpio_chip *= chip, unsigned int offset, static const struct aspeed_sgpio_pdata ast2600_sgpiom_pdata =3D { .pin_mask =3D GENMASK(10, 6), .llops =3D &aspeed_sgpio_g4_llops, + .cfg_offset =3D ASPEED_SGPIO_G4_CFG_OFFSET, +}; + +static void aspeed_sgpio_g7_reg_bit_set(struct aspeed_sgpio *gpio, unsigne= d int offset, + const enum aspeed_sgpio_reg reg, bool val) +{ + u32 mask =3D aspeed_sgpio_g7_reg_mask(reg); + void __iomem *addr =3D gpio->base + SGPIO_G7_CTRL_REG_OFFSET(offset >> 1); + u32 write_val; + + if (mask) { + write_val =3D (ioread32(addr) & ~(mask)) | field_prep(mask, val); + iowrite32(write_val, addr); + } +} + +static bool aspeed_sgpio_g7_reg_bit_get(struct aspeed_sgpio *gpio, unsigne= d int offset, + const enum aspeed_sgpio_reg reg) +{ + u32 mask =3D aspeed_sgpio_g7_reg_mask(reg); + void __iomem *addr; + + addr =3D gpio->base + SGPIO_G7_CTRL_REG_OFFSET(offset >> 1); + if (reg =3D=3D reg_val) + mask =3D SGPIO_G7_IN_DATA; + + if (mask) + return field_get(mask, ioread32(addr)); + else + return 0; +} + +static int aspeed_sgpio_g7_reg_bank_get(struct aspeed_sgpio *gpio, unsigne= d int offset, + const enum aspeed_sgpio_reg reg) +{ + void __iomem *addr; + + if (reg =3D=3D reg_irq_status) { + addr =3D gpio->base + SGPIO_G7_IRQ_STS_OFFSET(offset >> 6); + return ioread32(addr); + } else { + return -EOPNOTSUPP; + } +} + +static const struct aspeed_sgpio_llops aspeed_sgpio_g7_llops =3D { + .reg_bit_set =3D aspeed_sgpio_g7_reg_bit_set, + .reg_bit_get =3D aspeed_sgpio_g7_reg_bit_get, + .reg_bank_get =3D aspeed_sgpio_g7_reg_bank_get, +}; + +static const struct aspeed_sgpio_pdata ast2700_sgpiom_pdata =3D { + .pin_mask =3D GENMASK(11, 6), + .llops =3D &aspeed_sgpio_g7_llops, + .cfg_offset =3D ASPEED_SGPIO_G7_CFG_OFFSET, }; =20 static const struct of_device_id aspeed_sgpio_of_table[] =3D { { .compatible =3D "aspeed,ast2400-sgpio", .data =3D &ast2400_sgpio_pdata,= }, { .compatible =3D "aspeed,ast2500-sgpio", .data =3D &ast2400_sgpio_pdata,= }, { .compatible =3D "aspeed,ast2600-sgpiom", .data =3D &ast2600_sgpiom_pdat= a, }, + { .compatible =3D "aspeed,ast2700-sgpiom", .data =3D &ast2700_sgpiom_pdat= a, }, {} }; =20 @@ -561,7 +668,7 @@ static int aspeed_sgpio_probe(struct platform_device *p= dev) =20 gpio_cnt_regval =3D ((nr_gpios / 8) << ASPEED_SGPIO_PINS_SHIFT) & pin_mas= k; iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) | gpio_cnt= _regval | - ASPEED_SGPIO_ENABLE, gpio->base + ASPEED_SGPIO_CTRL); + ASPEED_SGPIO_ENABLE, gpio->base + gpio->pdata->cfg_offset); =20 raw_spin_lock_init(&gpio->lock); =20 --=20 2.34.1