From nobody Sun Feb 8 05:20:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1397E221FC6; Sat, 17 Jan 2026 15:36:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768664182; cv=none; b=O1Joupagjl0l++8PLr3eA4Ku+gLis5r8b5FvwcJNMQlAHc4t3h1SUKjU8y4XvYHnISUH54RSL/JQXvVKx96Hfl9vRhVwUkjFAhDAuTNfDXTYyZ9F1Wy53g3KePQlPqe9SRkJteuJByn2zfk8GSUfjbbJ0Sby6PTctI1+uIm4QOY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768664182; c=relaxed/simple; bh=/uadSS85/MPVjwqxP7KTAwdkLax6oKXXxEdPj9V+T9A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qHAa/qzKGmvdbuSuhSjUqKEXp4Etbif1AkLVr42hXHAG+27eZja1fKTy9LzYgoMbt/pHm2+bfpy6b2D7sIDjzdiaYyhOh04/fJWBipZ4Mk7nfhyy5h0qfqwDUYPn/gwooT4KV6LU9TzcZ+2Gzc9edjUOjhPwSnXZJnyFAwFQNF4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=c0232HHI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="c0232HHI" Received: by smtp.kernel.org (Postfix) with ESMTPS id 9EEABC19423; Sat, 17 Jan 2026 15:36:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1768664181; bh=/uadSS85/MPVjwqxP7KTAwdkLax6oKXXxEdPj9V+T9A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=c0232HHIOwJglfX7dHf5f6iXvkifN62mZ3sQXXHDsvIMVgTOp4qZWzpeYj+v32J4w 7mN5n0wjHZP0W/vX8tO1moRSPcSex3+44OaFdWegsjNqjxT9L2yfkn3PsDV0o+ZqFR JdBbY3XXfN2ml/rXjWFJG5B7Pn0d81xijcvRZpMy/w/6m2Ikaw8phrcxBApIjEFsBP 6wIYwYVz/1JpPhkFSLSHQNDZx8pJV7PEzc2PZ0iONqFebF45YP4/Xg/JglVViGMhyu flyuzAZVUGiLMEub/VAXWxLCVrhgV7vmwsQu3uWl+J6Wm26A1lFgYGbr0PPV1XGdsQ 9BXsS5+YVNzxw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8BE68C98315; Sat, 17 Jan 2026 15:36:21 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Sat, 17 Jan 2026 16:36:16 +0100 Subject: [PATCH v3 1/8] media: qcom: camss: csiphy: Introduce PHY configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260117-qcom-cphy-v3-1-8ce76a06f7db@ixit.cz> References: <20260117-qcom-cphy-v3-0-8ce76a06f7db@ixit.cz> In-Reply-To: <20260117-qcom-cphy-v3-0-8ce76a06f7db@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , Casey Connolly , "Dr. Git" Cc: Konrad Dybcio , Joel Selvaraj , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2436; i=david@ixit.cz; h=from:subject:message-id; bh=mQVMyUAqZChIt7A9c/SYnHbFFHnHmz7GAPKyVmtGOoM=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBpa6xzxGDJZ3mmtQVncbRDgsQ27+lgn37KiiyGu wyjz8yF7bOJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaWuscwAKCRBgAj/E00kg crN+EACuLya4+/XMUY4t0rfm29bG8EUuGEpch/rxS82NT+XxNaLj4lhD0FAb6GHnIfaC8s7U0pa G3cvhmXPilXzTwV4C9F5cS2s4kcr4Rsu35IHb4UnTqO60NPdqzkQiCpg/PLE/mlFCcKa7vb1kb8 lWxk307bhFzbXxsEV47dF8uB2u0LgowgLOk2jU6DZ+XE1CzEBXgM7a8BsUvmDEnxzCkA7RzYdVM +HdXzsgaFhmmBdRT+3pUsAEtBbWfuX2LH6Utnc/y24UxFKeDwuz8maKARdEx7fbcxCwuv8UTC3a +mCzj5v7uHcPCBCrz8Eqhl4MiIg4PkjnzO7DuI6rJ00y4aEnb/VI9vFx7hhJO6h79c4zLSbRRtD Z4HneoGvQ6kOczplakt6N4/FwVui0KEdzcF/IQhzHXHyUA8alJBRK8t86u7OFYgEmK1326UtJx+ XFrikQGY8F9lZQSU4ccExX9gzrBK4DlgHisaQ29MywbxLfjrAPHAGke7uSb5z7q/t+hZ2UWG9cA H7cbiQVeZNfLt9MQPVcjt1cRYpFxn2pBNyIfatSCCv2qs3xBeaetLivDTApxGI5vmWK/u3AUyie vqurtHIIMboXc9M8FITR6Q8LZLITjq/hRNXt4lxUxmJkk/iQaJR8nzu8fMGq0ZpDtSskVn7BM1H 2AlR2FYn/k1Yggw== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg Read PHY configuration from the device-tree bus-type and save it into the c= siphy structure for later use. For C-PHY, skip clock line configuration, as there is none. Signed-off-by: David Heidelberg --- drivers/media/platform/qcom/camss/camss-csiphy.h | 2 ++ drivers/media/platform/qcom/camss/camss.c | 18 +++++++++++------- 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/med= ia/platform/qcom/camss/camss-csiphy.h index 2d5054819df7f..d198171700e73 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.h +++ b/drivers/media/platform/qcom/camss/camss-csiphy.h @@ -28,11 +28,13 @@ struct csiphy_lane { =20 /** * struct csiphy_lanes_cfg - CSIPHY lanes configuration + * @phy_cfg: interface selection (C-PHY or D-PHY) * @num_data: number of data lanes * @data: data lanes configuration * @clk: clock lane configuration (only for D-PHY) */ struct csiphy_lanes_cfg { + enum v4l2_mbus_type phy_cfg; int num_data; struct csiphy_lane *data; struct csiphy_lane clk; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 00b87fd9afbd8..ea0c8cf3cd806 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -4411,11 +4411,11 @@ static int camss_parse_endpoint_node(struct device = *dev, if (ret) return ret; =20 - /* - * Most SoCs support both D-PHY and C-PHY standards, but currently only - * D-PHY is supported in the driver. - */ - if (vep.bus_type !=3D V4L2_MBUS_CSI2_DPHY) { + switch (vep.bus_type) { + case V4L2_MBUS_CSI2_CPHY: + case V4L2_MBUS_CSI2_DPHY: + break; + default: dev_err(dev, "Unsupported bus type %d\n", vep.bus_type); return -EINVAL; } @@ -4423,9 +4423,13 @@ static int camss_parse_endpoint_node(struct device *= dev, csd->interface.csiphy_id =3D vep.base.port; =20 mipi_csi2 =3D &vep.bus.mipi_csi2; - lncfg->clk.pos =3D mipi_csi2->clock_lane; - lncfg->clk.pol =3D mipi_csi2->lane_polarities[0]; lncfg->num_data =3D mipi_csi2->num_data_lanes; + lncfg->phy_cfg =3D vep.bus_type; + + if (lncfg->phy_cfg !=3D V4L2_MBUS_CSI2_CPHY) { + lncfg->clk.pos =3D mipi_csi2->clock_lane; + lncfg->clk.pol =3D mipi_csi2->lane_polarities[0]; + } =20 lncfg->data =3D devm_kcalloc(dev, lncfg->num_data, sizeof(*lncfg->data), --=20 2.51.0 From nobody Sun Feb 8 05:20:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8221139579; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260117-qcom-cphy-v3-2-8ce76a06f7db@ixit.cz> References: <20260117-qcom-cphy-v3-0-8ce76a06f7db@ixit.cz> In-Reply-To: <20260117-qcom-cphy-v3-0-8ce76a06f7db@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , Casey Connolly , "Dr. Git" Cc: Konrad Dybcio , Joel Selvaraj , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=6047; i=david@ixit.cz; h=from:subject:message-id; bh=Py+ahC8+QgtZhaEyxSnmQ4ggve0to/vdi/NPYJPgPjU=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBpa6xzkeqxPfoPvfQNSlRy35pNpn6GzYk/l+1Iw rpbFRRNniiJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaWuscwAKCRBgAj/E00kg cguFD/9Jscq5HuwYUTFSnYxmXsRZmR2JgZmSUmdtOgoHmYLjWqPJ1NiNczdHUsEGQSQpKlYdQ8A khqUAPktuwV7lH81wGsijrLCsucFats1lslH2AURPJS4e3kuMMtwgKPZDCsyA+X+BWO/yqrxp6P eppzY0mRbO/75BeRJKDcwwgzwftRpauP3vivVU1/YpUxu6npWMm+JOpWSnznOPH54gAc73J176A ZUDcMfAUJ1UoH7dmgaoySnzaeIHo52Gr1tWKT8SDcbRyPP4KYYDNY6Z+R98O70FGd+Fy13f/gw3 lca6QgpuEsMwpCgXTI1RFrDuWSUB22NqUpgpqQV9nqKuBZRFYNhZFjgxiV26ZHX6G5K6/5h9DmG e8vRnSJ7B3UuVmwtVUczJE5WmiysrZFkJXF/7hyNqVtGcwb5DJYPUtJCZd6mLrDkMBb4yN4lxSc 1ZoHdwWG6nCm7mcAnTWaQaTupE6VfsSdIL2g/DsexMFkn3cN/Yqv9B23g5n82CIkndfEM3V9XLR ZFyRLPT4vrHHHNDPQ6qmbka45o+LRm0fAgruWUwnwvAlKZGhzmg3z4Q40a2YH7OH/LY+1boCjMY XbqEESdyzeYKalU9dVRQ6Flqjq8sLlFKpiY1/aVK69LBtEdRP9mssWOZCfztbt+Lh1Y9Www+JyI oVj2LVSh2g3b9LA== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg So far, only D-PHY mode was supported, which uses even bits when enabling or masking lanes. For C-PHY configuration, the hardware instead requires using the odd bits. Since there can be unrecognized configuration allow returning failure. Signed-off-by: David Heidelberg Reviewed-by: Bryan O'Donoghue --- .../platform/qcom/camss/camss-csiphy-2ph-1-0.c | 8 ++-- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 49 +++++++++++++++++-= ---- drivers/media/platform/qcom/camss/camss-csiphy.c | 4 +- drivers/media/platform/qcom/camss/camss-csiphy.h | 6 +-- 4 files changed, 47 insertions(+), 20 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c index 9d67e7fa6366a..bb4b91f69616b 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c @@ -94,9 +94,9 @@ static u8 csiphy_settle_cnt_calc(s64 link_freq, u32 timer= _clk_rate) return settle_cnt; } =20 -static void csiphy_lanes_enable(struct csiphy_device *csiphy, - struct csiphy_config *cfg, - s64 link_freq, u8 lane_mask) +static int csiphy_lanes_enable(struct csiphy_device *csiphy, + struct csiphy_config *cfg, + s64 link_freq, u8 lane_mask) { struct csiphy_lanes_cfg *c =3D &cfg->csi2->lane_cfg; u8 settle_cnt; @@ -132,6 +132,8 @@ static void csiphy_lanes_enable(struct csiphy_device *c= siphy, writel_relaxed(0x3f, csiphy->base + CAMSS_CSI_PHY_INTERRUPT_CLEARn(l)); } + + return 0; } =20 static void csiphy_lanes_disable(struct csiphy_device *csiphy, diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index 4154832745525..f3a8625511e1e 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -14,6 +14,7 @@ #include #include #include +#include =20 #define CSIPHY_3PH_LNn_CFG1(n) (0x000 + 0x100 * (n)) #define CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG (BIT(7) | BIT(6)) @@ -993,13 +994,22 @@ static void csiphy_gen2_config_lanes(struct csiphy_de= vice *csiphy, =20 static u8 csiphy_get_lane_mask(struct csiphy_lanes_cfg *lane_cfg) { - u8 lane_mask; - int i; + u8 lane_mask =3D 0; =20 - lane_mask =3D CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; + switch (lane_cfg->phy_cfg) { + case V4L2_MBUS_CSI2_CPHY: + for (int i =3D 0; i < lane_cfg->num_data; i++) + lane_mask |=3D (1 << lane_cfg->data[i].pos) + 1; + break; + case V4L2_MBUS_CSI2_DPHY: + lane_mask =3D CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; =20 - for (i =3D 0; i < lane_cfg->num_data; i++) - lane_mask |=3D 1 << lane_cfg->data[i].pos; + for (int i =3D 0; i < lane_cfg->num_data; i++) + lane_mask |=3D 1 << lane_cfg->data[i].pos; + break; + default: + break; + } =20 return lane_mask; } @@ -1027,10 +1037,11 @@ static bool csiphy_is_gen2(u32 version) return ret; } =20 -static void csiphy_lanes_enable(struct csiphy_device *csiphy, - struct csiphy_config *cfg, - s64 link_freq, u8 lane_mask) +static int csiphy_lanes_enable(struct csiphy_device *csiphy, + struct csiphy_config *cfg, + s64 link_freq, u8 lane_mask) { + struct device *dev =3D csiphy->camss->dev; struct csiphy_lanes_cfg *c =3D &cfg->csi2->lane_cfg; struct csiphy_device_regs *regs =3D csiphy->regs; u8 settle_cnt; @@ -1039,9 +1050,23 @@ static void csiphy_lanes_enable(struct csiphy_device= *csiphy, =20 settle_cnt =3D csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate); =20 - val =3D CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; - for (i =3D 0; i < c->num_data; i++) - val |=3D BIT(c->data[i].pos * 2); + val =3D 0; + + switch (c->phy_cfg) { + case V4L2_MBUS_CSI2_CPHY: + for (i =3D 0; i < c->num_data; i++) + val |=3D BIT((c->data[i].pos * 2) + 1); + break; + case V4L2_MBUS_CSI2_DPHY: + val =3D CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; + + for (i =3D 0; i < c->num_data; i++) + val |=3D BIT(c->data[i].pos * 2); + break; + default: + dev_err(dev, "Unsupported bus type %d\n", c->phy_cfg); + return -EINVAL; + } =20 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 5)); @@ -1068,6 +1093,8 @@ static void csiphy_lanes_enable(struct csiphy_device = *csiphy, writel_relaxed(0, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, i)); } + + return 0; } =20 static void csiphy_lanes_disable(struct csiphy_device *csiphy, diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/med= ia/platform/qcom/camss/camss-csiphy.c index 62623393f4144..08dd238e52799 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c @@ -295,9 +295,7 @@ static int csiphy_stream_on(struct csiphy_device *csiph= y) wmb(); } =20 - csiphy->res->hw_ops->lanes_enable(csiphy, cfg, link_freq, lane_mask); - - return 0; + return csiphy->res->hw_ops->lanes_enable(csiphy, cfg, link_freq, lane_mas= k); } =20 /* diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/med= ia/platform/qcom/camss/camss-csiphy.h index d198171700e73..21cf2ce931c1d 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.h +++ b/drivers/media/platform/qcom/camss/camss-csiphy.h @@ -73,9 +73,9 @@ struct csiphy_hw_ops { void (*hw_version_read)(struct csiphy_device *csiphy, struct device *dev); void (*reset)(struct csiphy_device *csiphy); - void (*lanes_enable)(struct csiphy_device *csiphy, - struct csiphy_config *cfg, - s64 link_freq, u8 lane_mask); + int (*lanes_enable)(struct csiphy_device *csiphy, + struct csiphy_config *cfg, + s64 link_freq, u8 lane_mask); void (*lanes_disable)(struct csiphy_device *csiphy, struct csiphy_config *cfg); irqreturn_t (*isr)(int irq, void *dev); --=20 2.51.0 From nobody Sun Feb 8 05:20:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 137EF217704; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260117-qcom-cphy-v3-3-8ce76a06f7db@ixit.cz> References: <20260117-qcom-cphy-v3-0-8ce76a06f7db@ixit.cz> In-Reply-To: <20260117-qcom-cphy-v3-0-8ce76a06f7db@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , Casey Connolly , "Dr. Git" Cc: Konrad Dybcio , Joel Selvaraj , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2138; i=david@ixit.cz; h=from:subject:message-id; bh=VE5OUEM0X//rg3dmLrS4SJXKFfJ1U9PcL8DiivLtXg0=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBpa6xzITwS/qRe5tCt5L/y7dS4eFjQyWEM91iFf Ze39edfJGeJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaWuscwAKCRBgAj/E00kg cgmCD/4+0b1str0cfp4PXBJrESYb8LEnUw1FKC0yicVMLpcrdojfw1/yBTNJ6nY/7uJ1QsU5C/I FgTK+htUhY4Lejj7qrl5PZQe9x49m1N57X2b14SKGTek1khbctUmDgLxAs+0AhQZZgNzcPySgNc znU3cZFNwfBLMzE4mCwAkMoU68maAqOwNnACf9iA0aMn5WeL/hbtxnaHaPT1bB6lL+3Zw2nUpsX W+1QXus9kXgUEDajcszgUG52QcfNsIliYH0aYAa/2BCZPGwNN8pwxEOSDkF7rIbU8A88PuNLwY1 YGNH99dsgnO9XuZjPcbnKuuTadaQSN8Okvmk6q9cmb6C/nKsVWLM8IiB51nQF0np3w9n7Qvnu9M 4wBXuujEN6TnQaBCvcpRcWq0QBbN74hCJ8yYihTXEIYl2+BCv/MMBl4O47vmH92ARjCXsPrWrfq CMrUEuJjrEUECsT3+gJn805C/LvWTZBDZqAIPpNGd/rm3TRsSMjyIz80CJIcwVKdyHb2DT/RI2n er3xig6JevPz4MX3tdcKC9/yG/ioP0CoeyeTS4d059XO59tCHZmlExsbin/zhNWWx1aICgqtswX GLxLDe/XheHIJZZdkFLZoOATcAC7OcjX4HWRjq8hXedp+H2NwbX4e9wdLTVXLKSvJ6peOT9FHr8 IzlNlbo/MJjbIjw== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg Inherit C-PHY information from CSIPHY, so we can configure CSID properly. CSI2_RX_CFG0_PHY_TYPE_SEL must be set to 1, when C-PHY mode is used. Signed-off-by: David Heidelberg Reviewed-by: Bryan O'Donoghue --- drivers/media/platform/qcom/camss/camss-csid-gen2.c | 1 + drivers/media/platform/qcom/camss/camss-csid.c | 1 + drivers/media/platform/qcom/camss/camss-csid.h | 1 + 3 files changed, 3 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen2.c b/drivers/= media/platform/qcom/camss/camss-csid-gen2.c index 2a1746dcc1c5b..033036ae28a4f 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-gen2.c +++ b/drivers/media/platform/qcom/camss/camss-csid-gen2.c @@ -183,6 +183,7 @@ static void __csid_configure_rx(struct csid_device *csi= d, val =3D (lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; val |=3D phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; val |=3D phy->csiphy_id << CSI2_RX_CFG0_PHY_NUM_SEL; + val |=3D csid->phy.cphy << CSI2_RX_CFG0_PHY_TYPE_SEL; writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG0); =20 val =3D 1 << CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN; diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media= /platform/qcom/camss/camss-csid.c index ed1820488c987..b50b0cfe280c1 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.c +++ b/drivers/media/platform/qcom/camss/camss-csid.c @@ -1275,6 +1275,7 @@ static int csid_link_setup(struct media_entity *entit= y, csid->phy.csiphy_id =3D csiphy->id; =20 lane_cfg =3D &csiphy->cfg.csi2->lane_cfg; + csid->phy.cphy =3D (lane_cfg->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY); csid->phy.lane_cnt =3D lane_cfg->num_data; csid->phy.lane_assign =3D csid_get_lane_assign(lane_cfg); } diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media= /platform/qcom/camss/camss-csid.h index aedc96ed84b2f..a82db31bd2335 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.h +++ b/drivers/media/platform/qcom/camss/camss-csid.h @@ -70,6 +70,7 @@ struct csid_phy_config { u32 lane_assign; u32 en_vc; u8 need_vc_update; + bool cphy; }; =20 struct csid_device; --=20 2.51.0 From nobody Sun Feb 8 05:20:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1391A21D3CD; Sat, 17 Jan 2026 15:36:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: Petr Hodina The lanes must not be initialized before the driver has access to the lane configuration, as it depends on whether D-PHY or C-PHY mode is in use. Move the lane initialization to a later stage where the configuration structures are available. Signed-off-by: Petr Hodina Signed-off-by: David Heidelberg Reviewed-by: Bryan O'Donoghue --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 91 ++++++++++++++----= ---- 1 file changed, 57 insertions(+), 34 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index f3a8625511e1e..9e8470358515f 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -1048,6 +1048,62 @@ static int csiphy_lanes_enable(struct csiphy_device = *csiphy, u8 val; int i; =20 + switch (csiphy->camss->res->version) { + case CAMSS_845: + { /* V4L2_MBUS_CSI2_DPHY */ + regs->lane_regs =3D &lane_regs_sdm845[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sdm845); + } + break; + case CAMSS_2290: + case CAMSS_6150: + { /* V4L2_MBUS_CSI2_DPHY */ + regs->lane_regs =3D &lane_regs_qcm2290[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_qcm2290); + } + break; + case CAMSS_7280: + case CAMSS_8250: + { /* V4L2_MBUS_CSI2_DPHY */ + regs->lane_regs =3D &lane_regs_sm8250[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8250); + } + break; + case CAMSS_8280XP: + { /* V4L2_MBUS_CSI2_DPHY */ + regs->lane_regs =3D &lane_regs_sc8280xp[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sc8280xp); + } + break; + case CAMSS_X1E80100: + { /* V4L2_MBUS_CSI2_DPHY */ + regs->lane_regs =3D &lane_regs_x1e80100[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_x1e80100); + } + break; + case CAMSS_8550: + { /* V4L2_MBUS_CSI2_DPHY */ + regs->lane_regs =3D &lane_regs_sm8550[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8550); + } + break; + case CAMSS_8650: + { /* V4L2_MBUS_CSI2_DPHY */ + regs->lane_regs =3D &lane_regs_sm8650[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8650); + } + break; + case CAMSS_8300: + case CAMSS_8775P: + { /* V4L2_MBUS_CSI2_DPHY */ + regs->lane_regs =3D &lane_regs_sa8775p[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sa8775p); + } + break; + default: + break; + } + settle_cnt =3D csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate); =20 val =3D 0; @@ -1119,49 +1175,16 @@ static int csiphy_init(struct csiphy_device *csiphy) return -ENOMEM; =20 csiphy->regs =3D regs; - regs->offset =3D 0x800; regs->common_status_offset =3D 0xb0; =20 switch (csiphy->camss->res->version) { - case CAMSS_845: - regs->lane_regs =3D &lane_regs_sdm845[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sdm845); - break; - case CAMSS_2290: - case CAMSS_6150: - regs->lane_regs =3D &lane_regs_qcm2290[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_qcm2290); - break; - case CAMSS_7280: - case CAMSS_8250: - regs->lane_regs =3D &lane_regs_sm8250[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8250); - break; - case CAMSS_8280XP: - regs->lane_regs =3D &lane_regs_sc8280xp[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sc8280xp); - break; case CAMSS_X1E80100: - regs->lane_regs =3D &lane_regs_x1e80100[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_x1e80100); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260117-qcom-cphy-v3-5-8ce76a06f7db@ixit.cz> References: <20260117-qcom-cphy-v3-0-8ce76a06f7db@ixit.cz> In-Reply-To: <20260117-qcom-cphy-v3-0-8ce76a06f7db@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , Casey Connolly , "Dr. Git" Cc: Konrad Dybcio , Joel Selvaraj , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=4821; i=david@ixit.cz; h=from:subject:message-id; bh=kjpuzxq/baxTX0/t//R00t7SKTfnhMZ+RrKmEOyVIXI=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBpa6xzpPrXzbmQho3g3JkEXedHr28OJ4AspwdzY sBkyIsFTTaJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaWuscwAKCRBgAj/E00kg clhDD/sEkC8zwJJ2UIqIrm0kx3YWvXPL2cB+F3a17EWoYWQtnzBKFwDivafUqk2aKCG22LcUTvX vZAFBgUeO05yCwm1g488SdnMsF7H97NLWeLG6AiblusttRx0xSNmtRVWJtV8I3h78VijRwBdYY+ NudeeMSBA6DqFwUPwumYXMaS3hgA0AvkCb+d7o8paKjm0tR2ws+uQCDlgm79wKqw7SavICrj0W+ o5QYt1cuVIPddWgwihZQ5i/LpWRRTnY2E71odoa6zX23cWrOkDS3ydV54r9l5VAbCBWfl/si80C +Ap5Lr5YU7ynG5sKrcR/u7Pw9nHENpo4CdDOsQrwX2lRzWE7BjVFz/eXHfKDdM2efzkY/Bh79ie 0DoDqCe9uJpmfwoFaiwJ83/dWlGfykNY8vFErCAtnhdSrKwZWVUOdyfsJG0Lgf399OPRJwKeATQ D66Yw5dQjF6DsT3KtKpbbmWG8HKq9/NVq+6z+Pfw74Jp8uWuOa0VxftIddJhOBAtiTE0Z8Dt/SG kj2A5ONESpcRIqLN3xdJ6DMsBPlgY+phPOUXj0HBTYDDaMrxRANr9XYddENEF6zBblLClego5Pu NaiQh4b4fTdZVsH78Z2mkdyFWeyrc9Ag9yyKHlu/IFfr4DdeL8DWyyKgcWXn3OtuGRnUHk/dTlk ObJ4jkbymKqgEPw== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: Casey Connolly Add a PHY configuration sequence for the sdm845 which uses a Qualcomm Gen 2 version 1.1 CSI-2 PHY. The PHY can be configured as two phase or three phase in C-PHY or D-PHY mode. This configuration supports three-phase C-PHY mode. Signed-off-by: Casey Connolly Reviewed-by: Vladimir Zapolskiy Reviewed-by: Bryan O'Donoghue Co-developed-by: David Heidelberg Signed-off-by: David Heidelberg --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 70 ++++++++++++++++++= +++- 1 file changed, 69 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index 9e8470358515f..f819472511823 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -146,6 +146,7 @@ csiphy_lane_regs lane_regs_sa8775p[] =3D { }; =20 /* GEN2 1.0 2PH */ +/* 5 entries: clock + 4 lanes */ static const struct csiphy_lane_regs lane_regs_sdm845[] =3D { {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -220,6 +221,69 @@ csiphy_lane_regs lane_regs_sdm845[] =3D { {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, }; =20 +/* GEN2 1.0 3PH */ +/* 3 entries: 3 lanes (C-PHY) */ +static const struct +csiphy_lane_regs lane_regs_sdm845_3ph[] =3D { + {0x015C, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0168, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x016C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x010C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0114, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0150, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0118, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x011C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0120, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0124, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x012C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0144, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0164, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01DC, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x035C, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0368, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x036C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x030C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0314, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0350, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0318, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x031C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0320, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0324, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x032C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0344, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0364, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03DC, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x055C, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0568, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x056C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x050C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0514, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0550, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0518, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x051C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0520, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0524, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0528, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x052C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0544, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0564, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05DC, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + /* GEN2 1.1 2PH */ static const struct csiphy_lane_regs lane_regs_sc8280xp[] =3D { @@ -1050,7 +1114,11 @@ static int csiphy_lanes_enable(struct csiphy_device = *csiphy, =20 switch (csiphy->camss->res->version) { case CAMSS_845: - { /* V4L2_MBUS_CSI2_DPHY */ + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + regs->lane_regs =3D &lane_regs_sdm845_3ph[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sdm845_3ph); + + } else { /* V4L2_MBUS_CSI2_DPHY */ regs->lane_regs =3D &lane_regs_sdm845[0]; regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sdm845); } --=20 2.51.0 From nobody Sun Feb 8 05:20:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 195F22222D2; Sat, 17 Jan 2026 15:36:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260117-qcom-cphy-v3-6-8ce76a06f7db@ixit.cz> References: <20260117-qcom-cphy-v3-0-8ce76a06f7db@ixit.cz> In-Reply-To: <20260117-qcom-cphy-v3-0-8ce76a06f7db@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , Casey Connolly , "Dr. Git" Cc: Konrad Dybcio , Joel Selvaraj , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=6480; i=david@ixit.cz; h=from:subject:message-id; bh=O6McYvfjF/tfrJTvkeUtSL7j10tbBnhE9haiNL5uDo8=; b=owEBbAKT/ZANAwAIAWACP8TTSSByAcsmYgBpa6xzgc0hoaywx1PneYc0UivRfyaX7OZGoSKUE IYMZ03DY3uJAjIEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaWuscwAKCRBgAj/E00kg coZrD/YhWd8zn5tni06tuP2+G/Tcw0ap6CT8M9mpfKfjE8OgyIGPG/9Wn+vnoxCyFgJNwxe7pWu xvMB0SqRrh/hCQKsUULok93x9IV9IiuXWIj1plpNWCKo1REKaANURVRz0gCEV1uMEjKQyzMesu6 Y8nMzxOo8KZSd3KgJD0idGfsHpQswPhyrpSqsuDvmizBVZoc/Y4WHGBlP2AKkhZLN5Yi4jUbz1x L+lAlytMovdGgO57+mBLPf6q77X1lGaO7TR1z9gCkPCt7XgLoduAAbN8yBIhSBI0vje/6XKsIFD u7ZERnxUZC7MFhrYtX/LwmpHFRwj65X9JHIfp5dFBuvxGBOH/R7dSuJT/Gy0UE/wtnXfj5p4qip o90SEEz6EgjRKYd+UTHVYnFoWPt9iFCrfGzNz1FmlQ9Y2JVibXGFe7QPHFoLOpVK1GWIWPZk4ST QfBMjmvJwmTZZpXnYpv2o61MNIhYRvWWvNZyj2LY4zxQCxYwL3/dwKtgRcf/DAvAeaDlCUI6o9Y J6Mr+dfUJ9sz0ti18RboFao469FZE0oSHbH7M5boxpgGRaQ9BNbdT0q4SyFWdqZ/0+EjOfMQZ6A 2UvLm8VV+7lcJm2AvvoyBaUC0bSt0IoUPa8kpv03RZHT9YYMxArQzhy1329rpAvaLC2FN+MEQhy zeV4WS+ZBke0t X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: Luca Weiss Add a PHY configuration sequence for the sm8250 which uses a Qualcomm Gen 2 version 1.2.1 CSI-2 PHY. The PHY can be configured as two phase or three phase in C-PHY or D-PHY mode. This configuration supports three-phase C-PHY mode. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Signed-off-by: David Heidelberg Reviewed-by: Bryan O'Donoghue --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 110 +++++++++++++++++= +++- 1 file changed, 109 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index f819472511823..d82a88dad74b5 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -548,6 +548,111 @@ csiphy_lane_regs lane_regs_qcm2290[] =3D { {0x0664, 0x3f, 0x00, CSIPHY_DEFAULT_PARAMS}, }; =20 +/* GEN2 1.2.1 3PH */ +/* 3 entries: 3 lanes (C-PHY) */ +static const struct +csiphy_lane_regs lane_regs_sm8250_3ph[] =3D { + {0x0990, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0994, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0998, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0990, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0994, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0998, 0x1a, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x098c, 0xaf, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x015c, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0168, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x010c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0114, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0150, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0188, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x018c, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0190, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0118, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x011c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0120, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0124, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x012c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01dc, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0984, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0988, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0980, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09ac, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09b0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x0e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a90, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a94, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a98, 0x1a, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a8c, 0xaf, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x035c, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0368, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x030c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0314, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0350, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0388, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x038c, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0390, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0318, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x031c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0320, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0324, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x032c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03dc, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a84, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0aac, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0ab0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x0e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b90, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b94, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b98, 0x1a, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b8c, 0xaf, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x055c, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0568, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x050c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0514, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0550, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0588, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x058c, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0590, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0518, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x051c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0520, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0524, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0528, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x052c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05dc, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b84, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0bac, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0bb0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x0e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + /* GEN2 2.1.2 2PH DPHY mode */ static const struct csiphy_lane_regs lane_regs_sm8550[] =3D { @@ -1132,7 +1237,10 @@ static int csiphy_lanes_enable(struct csiphy_device = *csiphy, break; case CAMSS_7280: case CAMSS_8250: - { /* V4L2_MBUS_CSI2_DPHY */ + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + regs->lane_regs =3D &lane_regs_sm8250_3ph[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8250_3ph); + } else { /* V4L2_MBUS_CSI2_DPHY */ regs->lane_regs =3D &lane_regs_sm8250[0]; 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Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , Casey Connolly , "Dr. Git" Cc: Konrad Dybcio , Joel Selvaraj , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1248; i=david@ixit.cz; h=from:subject:message-id; bh=hi1draDMnwPdDs8jfyuKlJLJyRCchlejwfH5kHTkrC0=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBpa6xzZuyGf/U/5S0suMcazfP+fy+n3xT4JQXGi wskuX13a+WJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaWuscwAKCRBgAj/E00kg crGDEACQZprBdLGE9LREwg8hMB/wq0tHg4YCWXxyzX33J01v1AJUB1i4khpdVVL3qAcidGggzU6 +IveUeMakwoJNLE84/o4QYn2f02HgarO/jQj36QzSWr+Gb9cDuDP1MB65fhLqm4e0vqkyVwRwHw tfFFow8Y0HA0q2qJKUpPZfsi5xzbyyPOMhTGMGovppknucM/Jrpdpen6+/DsptVH2bPfcI8yhw4 u47ouLfkeLlO+OY48mXuZv/8BD4X/r6unw2SHpvs1EePASC9BSKRqSkgAmHZ7PorGN60nTdIuvI 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Hopefully this check will disappear as these lane regs gets populated. Signed-off-by: David Heidelberg --- drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c | 16 ++++++++++++= ++++ 1 file changed, 16 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index d82a88dad74b5..89bfe3710fc3a 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -1217,6 +1217,22 @@ static int csiphy_lanes_enable(struct csiphy_device = *csiphy, u8 val; int i; =20 + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + switch (csiphy->camss->res->version) { + case CAMSS_2290: + case CAMSS_8280XP: + case CAMSS_X1E80100: + case CAMSS_8550: + case CAMSS_8650: + case CAMSS_8300: + case CAMSS_8775P: + dev_err(dev, "Missing lane_regs definition for C-PHY\n"); + return -EINVAL; + default: + break; + } + } + switch (csiphy->camss->res->version) { case CAMSS_845: if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { --=20 2.51.0 From nobody Sun Feb 8 05:20:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38FAA238166; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260117-qcom-cphy-v3-8-8ce76a06f7db@ixit.cz> References: <20260117-qcom-cphy-v3-0-8ce76a06f7db@ixit.cz> In-Reply-To: <20260117-qcom-cphy-v3-0-8ce76a06f7db@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , Casey Connolly , "Dr. Git" Cc: Konrad Dybcio , Joel Selvaraj , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=5230; i=david@ixit.cz; h=from:subject:message-id; bh=zf+1tmC7easbpv6t/sgEpQwulzF8Aub919Uos8tEoRE=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBpa6xzgoNRTVAAaJfPCTH6vIbyFRNFO6sSOgG66 pcVCvsCTOKJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaWuscwAKCRBgAj/E00kg coWID/9w6YaD2+O6F//ywNevpVhHnbznEzH2moI7FZhtYr4yOkh9G10xkK17UlPG271pOJbxzuO 1+/0GJ9RAcRq/AMYL3FuCUnHtMiys0LeAPx/VNNzeUYfp6f1tDHYCl9bWV5rmPFhtENSqUTrWiD hAWbMoEOM8RhsmK+8zkUnZbaMXmPZzzSsHSOvbOJSOPT+iQI66akmxI16lFlgQy4xO71xcF0AA5 gvhVoN5iuCg2hLoOFfRcOr+MKl+yhmS6VDPWEVYHbJUDvoh+5xCe9OlaV4JkOesVTz3pQCqSZyk wVtz8N+NoFrSed7RdwL6+ZkvE/plwR7z826T/RIHW6PSYfnm2Zf749/wOHoBIsucIC+Jj3Ljawv ihKPbGbAHjWUQznLnl5a/dcRX6UoKN3xRn7AoeDR5Lc5FIAdT3QQZcm7qaUyYpJEVD9zV6u0p95 5sGMBX/2/rqJdT50s8KvoYyugFnGhGgotqC5PEb7Di00UrjWZxi3P/TezXGlIpVJlDKqqD9uLjx B/cE9NUkubCA5WMm0r0IewbIF1Wq9fvIvYdexa6BH6oLwywCKo6bFVA9GXcZT7K86QSdL+If56w TPEakLbmk1Jmg5YSHUR7fp8DIODhKCEltTyVEguut6Sz7hqmkBk1vY2Xdn4xAit4Q6Ga6IErH+n D54IWlfbHi8Ty0A== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg Ensure that the link frequency divider correctly accounts for C-PHY operation. The divider differs between D-PHY and C-PHY, as described in the MIPI CSI-2 specification. For more details, see: https://docs.kernel.org/driver-api/media/tx-rx.html#pixel-rate Suggested-by: Sakari Ailus Signed-off-by: David Heidelberg --- drivers/media/platform/qcom/camss/camss-csid.c | 2 +- drivers/media/platform/qcom/camss/camss-csiphy.c | 6 ++++-- drivers/media/platform/qcom/camss/camss.c | 16 +++++++++++++--- drivers/media/platform/qcom/camss/camss.h | 2 +- 4 files changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media= /platform/qcom/camss/camss-csid.c index b50b0cfe280c1..24f244d2959c9 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.c +++ b/drivers/media/platform/qcom/camss/camss-csid.c @@ -545,7 +545,7 @@ static int csid_set_clock_rates(struct csid_device *csi= d) fmt =3D csid_get_fmt_entry(csid->res->formats->formats, csid->res->format= s->nformats, csid->fmt[MSM_CSIPHY_PAD_SINK].code); link_freq =3D camss_get_link_freq(&csid->subdev.entity, fmt->bpp, - csid->phy.lane_cnt); + csid->phy.lane_cnt, csid->phy.cphy); if (link_freq < 0) link_freq =3D 0; =20 diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/med= ia/platform/qcom/camss/camss-csiphy.c index 08dd238e52799..1ea0d0ef354ff 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c @@ -144,8 +144,9 @@ static int csiphy_set_clock_rates(struct csiphy_device = *csiphy) u8 bpp =3D csiphy_get_bpp(csiphy->res->formats->formats, csiphy->res->for= mats->nformats, csiphy->fmt[MSM_CSIPHY_PAD_SINK].code); u8 num_lanes =3D csiphy->cfg.csi2->lane_cfg.num_data; + bool cphy =3D csiphy->cfg.csi2->lane_cfg.phy_cfg =3D=3D V4L2_MBUS_CSI2_CP= HY; =20 - link_freq =3D camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes); + link_freq =3D camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes,= cphy); if (link_freq < 0) link_freq =3D 0; =20 @@ -270,9 +271,10 @@ static int csiphy_stream_on(struct csiphy_device *csip= hy) u8 bpp =3D csiphy_get_bpp(csiphy->res->formats->formats, csiphy->res->for= mats->nformats, csiphy->fmt[MSM_CSIPHY_PAD_SINK].code); u8 num_lanes =3D csiphy->cfg.csi2->lane_cfg.num_data; + bool cphy =3D csiphy->cfg.csi2->lane_cfg.phy_cfg =3D=3D V4L2_MBUS_CSI2_CP= HY; u8 val; =20 - link_freq =3D camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes); + link_freq =3D camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes,= cphy); =20 if (link_freq < 0) { dev_err(csiphy->camss->dev, diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index ea0c8cf3cd806..556fedd92e065 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -32,6 +32,14 @@ #define CAMSS_CLOCK_MARGIN_NUMERATOR 105 #define CAMSS_CLOCK_MARGIN_DENOMINATOR 100 =20 +/* + * C-PHY encodes data by 16/7 ~ 2.28 bits/symbol + * D-PHY doesn't encode data, thus 16/16 =3D 1 b/s + */ +#define CAMSS_COMMON_PHY_DIVIDENT 16 +#define CAMSS_CPHY_DIVISOR 7 +#define CAMSS_DPHY_DIVISOR 16 + static const struct parent_dev_ops vfe_parent_dev_ops; =20 static const struct camss_subdev_resources csiphy_res_8x16[] =3D { @@ -4280,20 +4288,22 @@ struct media_pad *camss_find_sensor_pad(struct medi= a_entity *entity) * camss_get_link_freq - Get link frequency from sensor * @entity: Media entity in the current pipeline * @bpp: Number of bits per pixel for the current format - * @lanes: Number of lanes in the link to the sensor + * @nr_of_lanes: Number of lanes in the link to the sensor * * Return link frequency on success or a negative error code otherwise */ s64 camss_get_link_freq(struct media_entity *entity, unsigned int bpp, - unsigned int lanes) + unsigned int nr_of_lanes, bool cphy) { struct media_pad *sensor_pad; + unsigned int div =3D nr_of_lanes * 2 * (cphy ? CAMSS_CPHY_DIVISOR : + CAMSS_DPHY_DIVISOR); =20 sensor_pad =3D camss_find_sensor_pad(entity); if (!sensor_pad) return -ENODEV; =20 - return v4l2_get_link_freq(sensor_pad, bpp, 2 * lanes); + return v4l2_get_link_freq(sensor_pad, CAMSS_COMMON_PHY_DIVIDENT * bpp, di= v); } =20 /* diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/plat= form/qcom/camss/camss.h index 6d048414c919e..6bf7738837b89 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -163,7 +163,7 @@ int camss_enable_clocks(int nclocks, struct camss_clock= *clock, void camss_disable_clocks(int nclocks, struct camss_clock *clock); struct media_pad *camss_find_sensor_pad(struct media_entity *entity); s64 camss_get_link_freq(struct media_entity *entity, unsigned int bpp, - unsigned int lanes); + unsigned int lanes, bool cphy); int camss_get_pixel_clock(struct media_entity *entity, u64 *pixel_clock); int camss_pm_domain_on(struct camss *camss, int id); void camss_pm_domain_off(struct camss *camss, int id); --=20 2.51.0