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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1244af10e21sm4611267c88.16.2026.01.16.15.21.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Jan 2026 15:21:09 -0800 (PST) From: Elson Serrao To: Greg Kroah-Hartman , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Souradeep Chowdhury Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/9] usb: misc: qcom_eud: add per-path High-Speed PHY control Date: Fri, 16 Jan 2026 15:21:00 -0800 Message-Id: <20260116232106.2234978-4-elson.serrao@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260116232106.2234978-1-elson.serrao@oss.qualcomm.com> References: <20260116232106.2234978-1-elson.serrao@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: Gn1gOVvrTx9DjE-SQqhfS5_ICfZUY8qQ X-Authority-Analysis: v=2.4 cv=ZZsQ98VA c=1 sm=1 tr=0 ts=696ac7e7 cx=c_pps a=JYo30EpNSr/tUYqK9jHPoA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=wu0v9trazkx_CZjgA_kA:9 a=Fk4IpSoW4aLDllm1B1p-:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTE2MDE3NSBTYWx0ZWRfX9tfRbJe7Ycja W69yTvhG8aYL2W/5g8KT0CxP6n1ffso5v7Tqp/IL8Px1/5+vZ22VYKiIivEIRLNpE9sD3dnGAOy HmEnBueQVDCSuNa1TIYx4yw4XKRJ6IjPK4volfYo8NwOqG688fU72yVvHNkhd3yhPQiz/Raw6eP /NDfDjYZjxhQMSLtvO7+Rr6+WwUdYdAmLMI+UJD+32hDGViDBxJRMKNsi8OvTQc5Efoj8CJdOaQ JdIOpXNVA1VQQ1H7sCzLCmdy6+A8AYbJt8IyffVq3/X7FD9BQHs9LrfCgGza75B1hRqUcfbmEFK 1NRaKVCvyBOx+q7MzxdUzz8jk0Xjux9uJK6pNpdkSKUoOqeL8A7tRPv6bDZL4e5WpMVT1hNoHRS 4aHW5JtLb0tgo/SPHFjdA6mQmgBmBjHg+OTwu6M1B98rYqpnqts7A+lpPuKlwK0uT8ZWngTKdkC hIHfHUEghGn71GlIBvA== X-Proofpoint-GUID: Gn1gOVvrTx9DjE-SQqhfS5_ICfZUY8qQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-16_08,2026-01-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 bulkscore=0 adultscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601160175 Content-Type: text/plain; charset="utf-8" The Embedded USB Debugger (EUD) is a High-Speed USB on-chip hub that enables debug and trace capabilities on Qualcomm devices. As a HS-USB hub, the EUD requires High-Speed PHY support for proper operation. EUD hardware can support more than one High-Speed USB path, each with its own PHY. The active path is selected via the EUD_PORT_SEL register. To support this multi-path capability, the driver needs to manage PHY resources on a per-path basis, initializing and powering the PHY corresponding to the currently selected port. This patch restructures the driver to support per-path PHY management. PHY resources are powered on/off based on which port is active. This ensures the correct PHY is enabled when EUD is enabled. This change requires path specifications and corresponding PHY references to be added in device tree, breaking backward compatibility. However, this is acceptable since EUD cannot be guaranteed to function without proper PHY control. Signed-off-by: Elson Serrao --- drivers/usb/misc/qcom_eud.c | 130 +++++++++++++++++++++++++++++++++++- 1 file changed, 129 insertions(+), 1 deletion(-) diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index 1a136f8f1ae5..5cebb64f4a67 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -34,26 +35,96 @@ #define EUD_INT_SAFE_MODE BIT(4) #define EUD_INT_ALL (EUD_INT_VBUS | EUD_INT_SAFE_MODE) =20 +struct eud_path { + struct eud_chip *chip; + struct phy *phy; + u8 num; +}; + struct eud_chip { struct device *dev; struct usb_role_switch *role_sw; void __iomem *base; + struct eud_path *paths[EUD_MAX_PORTS]; phys_addr_t mode_mgr; unsigned int int_status; int irq; bool enabled; bool usb_attached; + bool phy_enabled; u8 port_idx; }; =20 +static int eud_phy_enable(struct eud_chip *chip) +{ + struct eud_path *path; + struct phy *phy; + int ret; + + if (chip->phy_enabled) + return 0; + + path =3D chip->paths[chip->port_idx]; + if (!path || !path->phy) { + dev_err(chip->dev, "No PHY configured for port %u\n", chip->port_idx); + return -ENODEV; + } + + phy =3D path->phy; + + ret =3D phy_init(phy); + if (ret) { + dev_err(chip->dev, "Failed to initialize USB2 PHY for port %u: %d\n", + chip->port_idx, ret); + return ret; + } + + ret =3D phy_power_on(phy); + if (ret) { + dev_err(chip->dev, "Failed to power on USB2 PHY for port %u: %d\n", + chip->port_idx, ret); + phy_exit(phy); + return ret; + } + + chip->phy_enabled =3D true; + + return 0; +} + +static void eud_phy_disable(struct eud_chip *chip) +{ + struct eud_path *path; + struct phy *phy; + + if (!chip->phy_enabled) + return; + + path =3D chip->paths[chip->port_idx]; + if (!path || !path->phy) + return; + + phy =3D path->phy; + + phy_power_off(phy); + phy_exit(phy); + chip->phy_enabled =3D false; +} + static int enable_eud(struct eud_chip *priv) { int ret; =20 - ret =3D qcom_scm_io_writel(priv->mode_mgr + EUD_REG_EUD_EN2, 1); + ret =3D eud_phy_enable(priv); if (ret) return ret; =20 + ret =3D qcom_scm_io_writel(priv->mode_mgr + EUD_REG_EUD_EN2, 1); + if (ret) { + eud_phy_disable(priv); + return ret; + } + writel(EUD_ENABLE, priv->base + EUD_REG_CSR_EUD_EN); writel(EUD_INT_VBUS | EUD_INT_SAFE_MODE, priv->base + EUD_REG_INT1_EN_MASK); @@ -70,6 +141,8 @@ static int disable_eud(struct eud_chip *priv) return ret; =20 writel(0, priv->base + EUD_REG_CSR_EUD_EN); + eud_phy_disable(priv); + return 0; } =20 @@ -132,6 +205,12 @@ static ssize_t port_store(struct device *dev, if (port >=3D EUD_MAX_PORTS) return -EINVAL; =20 + /* Check if the corresponding path is available */ + if (!chip->paths[port]) { + dev_err(chip->dev, "EUD not supported on selected port\n"); + return -EOPNOTSUPP; + } + /* Port selection must be done before enabling EUD */ if (chip->enabled) { dev_err(chip->dev, "Cannot change port while EUD is enabled\n"); @@ -231,8 +310,45 @@ static void eud_role_switch_release(void *data) usb_role_switch_put(chip->role_sw); } =20 +static int eud_init_path(struct eud_chip *chip, struct device_node *np) +{ + struct eud_path *path; + u32 path_num; + int ret; + + ret =3D of_property_read_u32(np, "reg", &path_num); + if (ret) { + dev_err(chip->dev, "Missing 'reg' property in path node\n"); + return ret; + } + + if (path_num >=3D EUD_MAX_PORTS) { + dev_err(chip->dev, "Invalid path number: %u (max %d)\n", + path_num, EUD_MAX_PORTS - 1); + return -EINVAL; + } + + path =3D devm_kzalloc(chip->dev, sizeof(*path), GFP_KERNEL); + if (!path) + return -ENOMEM; + + path->chip =3D chip; + path->num =3D path_num; + + path->phy =3D devm_of_phy_get(chip->dev, np, NULL); + if (IS_ERR(path->phy)) + return dev_err_probe(chip->dev, PTR_ERR(path->phy), + "Failed to get PHY for path %d\n", path_num); + + chip->paths[path_num] =3D path; + + return 0; +} + static int eud_probe(struct platform_device *pdev) { + struct device_node *np =3D pdev->dev.of_node; + struct device_node *child; struct eud_chip *chip; struct resource *res; int ret; @@ -252,6 +368,18 @@ static int eud_probe(struct platform_device *pdev) if (ret) return ret; =20 + for_each_child_of_node(np, child) { + ret =3D eud_init_path(chip, child); + if (ret) { + of_node_put(child); + return ret; + } + } + + /* Primary path is mandatory. Secondary is optional */ + if (!chip->paths[0]) + return -ENODEV; + chip->base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(chip->base)) return PTR_ERR(chip->base); --=20 2.34.1