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charset="utf-8" Add support for an optional enable GPIO that allows the multiplexer to be disabled before changing address lines and re-enabled after, preventing glitches during channel transitions. This is useful for devices like the Analog Devices ADG2404 (4:1 mux) that benefit from enable control to ensure clean channel switching. Signed-off-by: Antoniu Miclaus --- Changes in v4: * Add ADG2404 to binding description for discoverability * Add dedicated ADG2404 example showing enable-gpios usage * Update commit message to reference ADG2404 as use case --- .../devicetree/bindings/mux/gpio-mux.yaml | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/Documentation/devicetree/bindings/mux/gpio-mux.yaml b/Document= ation/devicetree/bindings/mux/gpio-mux.yaml index ef7e33ec85d4..2d9f32012127 100644 --- a/Documentation/devicetree/bindings/mux/gpio-mux.yaml +++ b/Documentation/devicetree/bindings/mux/gpio-mux.yaml @@ -17,6 +17,9 @@ description: |+ multiplexer GPIO pins, where the first pin is the least significant bit. An active pin is a binary 1, an inactive pin is a binary 0. =20 + This binding supports GPIO-controlled multiplexers such as the Analog + Devices ADG2404 (4:1 mux with enable control). + properties: compatible: const: gpio-mux @@ -25,6 +28,13 @@ properties: description: List of gpios used to control the multiplexer, least significant bit= first. =20 + enable-gpios: + description: + Optional GPIO to enable the multiplexer. When present, the mux will = be + disabled before changing address lines and re-enabled after to preve= nt + glitches. Required for MUX_IDLE_DISCONNECT idle-state. + maxItems: 1 + mux-supply: description: Regulator to power on the multiplexer. @@ -100,4 +110,19 @@ examples: }; }; }; + + - | + /* Analog Devices ADG2404 4:1 multiplexer with enable control */ + #include + + mux-controller { + compatible =3D "gpio-mux"; + #mux-control-cells =3D <0>; + + mux-gpios =3D <&gpio 1 GPIO_ACTIVE_HIGH>, + <&gpio 2 GPIO_ACTIVE_HIGH>; + enable-gpios =3D <&gpio 3 GPIO_ACTIVE_HIGH>; + + idle-state =3D <0>; + }; ... --=20 2.43.0 From nobody Sun Feb 8 17:04:18 2026 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C81533ADA0; Fri, 16 Jan 2026 15:39:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768577976; 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Fri, 16 Jan 2026 10:38:07 -0500 From: Antoniu Miclaus To: Peter Rosin , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Antoniu Miclaus" , Srinivas Kandagatla , Bartosz Golaszewski , David Lechner , , Subject: [PATCH v4 2/2] mux: gpio-mux: add support for enable GPIO Date: Fri, 16 Jan 2026 17:26:08 +0200 Message-ID: <20260116152621.75205-3-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260116152621.75205-1-antoniu.miclaus@analog.com> References: <20260116152621.75205-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTE2MDExMiBTYWx0ZWRfX+TzSSePEHfBX wJAlx6CJdu9oqUQfixtuU80/WgBlbAsqxqi/fg1s/QJKwOtPiIL0niE6n0Nxfre123C01g+w8il vCppr1OmSJ6BQPAh+a/zaHhkRTyqNqszLhHOaw/2l4CMDv5GE6ECC1q6LMia1I3tgzCCE5c8U7T l/BhXkE40CXdmRwGJi2poitBpukpDb3bAf4ArhIb6OWnSCktN1e/26E8tshNsBGHdSkcgp0NAz3 HcBd5BW4wDg58sIb3EQQzTjgZow/OX51veiQIceMdQ1m2y0RxHzAjkA5rUZJV+DMi/l1KHO92I8 NN2xyOeIgqbx3gTXbtR3nDVsZJQBgVGW3pu94L0HEzm1xrnnvjEQtx+yylo8T699zA7NdWIWbHc AnFuirdVxRpu1uwpxXE4kB9fYW0bO3iD6pdJ29HDf05nzi04hbaISF6tsVRZm0jMWuDoczfdF9F eo6QaI0h4qOtSqZQctg== X-Proofpoint-GUID: bahEAdXezAmowevlVQf0ky8FCmOQ3Z5y X-Authority-Analysis: v=2.4 cv=Y8n1cxeN c=1 sm=1 tr=0 ts=696a5ba5 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=vUbySO9Y5rIA:10 a=VkNPw1HP01LnGYTKEx00:22 a=gAnH3GRIAAAA:8 a=AY8K-kA47ILn5Hm1wlYA:9 X-Proofpoint-ORIG-GUID: bahEAdXezAmowevlVQf0ky8FCmOQ3Z5y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-16_06,2026-01-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 phishscore=0 spamscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601160112 Content-Type: text/plain; charset="utf-8" Add support for an optional enable GPIO to the gpio-mux driver. This allows the mux to be disabled before changing address lines and re-enabled after, preventing glitches that could briefly activate unintended channels during transitions. The enable GPIO is optional and the driver maintains backward compatibility with existing gpio-mux users. Signed-off-by: Antoniu Miclaus --- Changes in v4: * No changes --- drivers/mux/gpio.c | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/drivers/mux/gpio.c b/drivers/mux/gpio.c index 4cc3202c58f3..93487483e81f 100644 --- a/drivers/mux/gpio.c +++ b/drivers/mux/gpio.c @@ -19,6 +19,7 @@ =20 struct mux_gpio { struct gpio_descs *gpios; + struct gpio_desc *enable; }; =20 static int mux_gpio_set(struct mux_control *mux, int state) @@ -27,10 +28,28 @@ static int mux_gpio_set(struct mux_control *mux, int st= ate) DECLARE_BITMAP(values, BITS_PER_TYPE(state)); u32 value =3D state; =20 + if (state =3D=3D MUX_IDLE_DISCONNECT) { + if (mux_gpio->enable) + gpiod_set_value_cansleep(mux_gpio->enable, 0); + return 0; + } + + if (mux_gpio->enable) { + /* + * Disable the mux before changing address lines to prevent + * glitches. Changing address while enabled could briefly + * activate an unintended channel during the transition. + */ + gpiod_set_value_cansleep(mux_gpio->enable, 0); + } + bitmap_from_arr32(values, &value, BITS_PER_TYPE(value)); =20 gpiod_multi_set_value_cansleep(mux_gpio->gpios, values); =20 + if (mux_gpio->enable) + gpiod_set_value_cansleep(mux_gpio->enable, 1); + return 0; } =20 @@ -71,9 +90,20 @@ static int mux_gpio_probe(struct platform_device *pdev) WARN_ON(pins !=3D mux_gpio->gpios->ndescs); mux_chip->mux->states =3D BIT(pins); =20 + mux_gpio->enable =3D devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW= ); + if (IS_ERR(mux_gpio->enable)) + return dev_err_probe(dev, PTR_ERR(mux_gpio->enable), + "failed to get enable gpio\n"); + ret =3D device_property_read_u32(dev, "idle-state", (u32 *)&idle_state); if (ret >=3D 0 && idle_state !=3D MUX_IDLE_AS_IS) { - if (idle_state < 0 || idle_state >=3D mux_chip->mux->states) { + if (idle_state =3D=3D MUX_IDLE_DISCONNECT) { + if (!mux_gpio->enable) { + dev_err(dev, + "invalid idle-state (MUX_IDLE_DISCONNECT requires enable-gpios)\n"); + return -EINVAL; + } + } else if (idle_state < 0 || idle_state >=3D mux_chip->mux->states) { dev_err(dev, "invalid idle-state %u\n", idle_state); return -EINVAL; } --=20 2.43.0