From nobody Sun Feb 8 11:06:59 2026 Received: from mx2.zhaoxin.com (mx2.zhaoxin.com [61.152.208.219]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64B822D47F4 for ; Fri, 16 Jan 2026 07:18:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=61.152.208.219 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768547914; cv=none; b=o4mLN/huaywBgT9fwVlqaPptIZvn+vKUtWGE8lLANSAK7sEik3wFBZZpw9HY0QH72Tq29OEugEjyE0xGVKVNJALtioZuu1rlJfLEBjt23EyN7UWpdA9XVa8T/NbB4JOOpC5Qk1ej1krxbUvTHKGTJ3pfg7MeXSitelHyPmjqu3U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768547914; c=relaxed/simple; bh=H0DoG9fDTAitBB6G9r2+4Ank/okYvVz2A2hDyXcN/PE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gvSpDEnlFva4wIJ2o7oEmeMitXcQK51AzQtCjDa6QC0A68GwJcrEa38FNVF+G1JfUYVJ0iOAi0Nj1rjiXKesbVmMMrQR5lW3wLipmgsnFrnkf0ZfsG65isTZaoic/v+zBR8N1t5t+m5wi1ARYBEFfE+q84TktMjHD54Yt3mwj8o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=zhaoxin.com; spf=pass smtp.mailfrom=zhaoxin.com; arc=none smtp.client-ip=61.152.208.219 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=zhaoxin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zhaoxin.com X-ASG-Debug-ID: 1768547904-1eb14e7c0219540001-xx1T2L Received: from ZXSHMBX3.zhaoxin.com (ZXSHMBX3.zhaoxin.com [10.28.252.165]) by mx2.zhaoxin.com with ESMTP id SGMSHKJlvkcyL6Qx (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO); Fri, 16 Jan 2026 15:18:24 +0800 (CST) X-Barracuda-Envelope-From: AlanSong-oc@zhaoxin.com X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.165 Received: from ZXSHMBX1.zhaoxin.com (10.28.252.163) by ZXSHMBX3.zhaoxin.com (10.28.252.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.59; Fri, 16 Jan 2026 15:18:24 +0800 Received: from ZXSHMBX1.zhaoxin.com ([fe80::936:f2f9:9efa:3c85]) by ZXSHMBX1.zhaoxin.com ([fe80::936:f2f9:9efa:3c85%7]) with mapi id 15.01.2507.059; Fri, 16 Jan 2026 15:18:24 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.165 Received: from DESKTOP-A4I8D8T.zhaoxin.com (10.32.65.156) by ZXBJMBX02.zhaoxin.com (10.29.252.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.59; Fri, 16 Jan 2026 15:16:52 +0800 From: AlanSong-oc To: , , , , , , , CC: , , , , , , AlanSong-oc Subject: [PATCH v3 1/3] crypto: padlock-sha - Disable for Zhaoxin processor Date: Fri, 16 Jan 2026 15:15:11 +0800 X-ASG-Orig-Subj: [PATCH v3 1/3] crypto: padlock-sha - Disable for Zhaoxin processor Message-ID: <20260116071513.12134-2-AlanSong-oc@zhaoxin.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260116071513.12134-1-AlanSong-oc@zhaoxin.com> References: <20260116071513.12134-1-AlanSong-oc@zhaoxin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX02.zhaoxin.com (10.29.252.6) X-Moderation-Data: 1/16/2026 3:18:22 PM X-Barracuda-Connect: ZXSHMBX3.zhaoxin.com[10.28.252.165] X-Barracuda-Start-Time: 1768547904 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.36:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 2164 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.153108 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- Content-Type: text/plain; charset="utf-8" For Zhaoxin processors, the XSHA1 instruction requires the total memory allocated at %rdi register must be 32 bytes, while the XSHA1 and XSHA256 instruction doesn't perform any operation when %ecx is zero. Due to these requirements, the current padlock-sha driver does not work correctly with Zhaoxin processors. It cannot pass the self-tests and therefore does not activate the driver on Zhaoxin processors. This issue has been reported in Debian [1]. The self-tests fail with the following messages [2]: alg: shash: sha1-padlock-nano test failed (wrong result) on test vector 0, = cfg=3D"init+update+final aligned buffer" alg: self-tests for sha1 using sha1-padlock-nano failed (rc=3D-22) ------------[ cut here ]------------ alg: shash: sha256-padlock-nano test failed (wrong result) on test vector 0= , cfg=3D"init+update+final aligned buffer" alg: self-tests for sha256 using sha256-padlock-nano failed (rc=3D-22) ------------[ cut here ]------------ Disable the padlock-sha driver on Zhaoxin processors with CPU family 0x07 and newer. Add PHE Extensions support for SHA-1 and SHA-256 to lib/crypto, following the suggestion in [3]. [1] https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=3D1103397 [2] https://linux-hardware.org/?probe=3D271fabb7a4&log=3Ddmesg [3] https://lore.kernel.org/linux-crypto/aUI4CGp6kK7mxgEr@gondor.apana.org.= au/ Signed-off-by: AlanSong-oc --- drivers/crypto/padlock-sha.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/crypto/padlock-sha.c b/drivers/crypto/padlock-sha.c index 329f60ad4..9214bbfc8 100644 --- a/drivers/crypto/padlock-sha.c +++ b/drivers/crypto/padlock-sha.c @@ -332,6 +332,13 @@ static int __init padlock_init(void) if (!x86_match_cpu(padlock_sha_ids) || !boot_cpu_has(X86_FEATURE_PHE_EN)) return -ENODEV; =20 + /* + * Skip family 0x07 and newer used by Zhaoxin processors, + * as the driver's self-tests fail on these CPUs. + */ + if (c->x86 >=3D 0x07) + return -ENODEV; + /* Register the newly added algorithm module if on * * VIA Nano processor, or else just do as before */ if (c->x86_model < 0x0f) { --=20 2.34.1 From nobody Sun Feb 8 11:06:59 2026 Received: from mx1.zhaoxin.com (MX1.ZHAOXIN.COM [210.0.225.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 658602D47F4 for ; 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Fri, 16 Jan 2026 15:16:57 +0800 From: AlanSong-oc To: , , , , , , , CC: , , , , , , AlanSong-oc Subject: [PATCH v3 2/3] lib/crypto: x86/sha1: PHE Extensions optimized SHA1 transform function Date: Fri, 16 Jan 2026 15:15:12 +0800 X-ASG-Orig-Subj: [PATCH v3 2/3] lib/crypto: x86/sha1: PHE Extensions optimized SHA1 transform function Message-ID: <20260116071513.12134-3-AlanSong-oc@zhaoxin.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260116071513.12134-1-AlanSong-oc@zhaoxin.com> References: <20260116071513.12134-1-AlanSong-oc@zhaoxin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX02.zhaoxin.com (10.29.252.6) X-Moderation-Data: 1/16/2026 3:18:23 PM X-Barracuda-Connect: ZXSHMBX1.zhaoxin.com[10.28.252.163] X-Barracuda-Start-Time: 1768547905 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://mx2.zhaoxin.com:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 2071 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.153109 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- Content-Type: text/plain; charset="utf-8" Zhaoxin CPUs have implemented the SHA(Secure Hash Algorithm) as its CPU instructions by PHE(Padlock Hash Engine) Extensions, including XSHA1, XSHA256, XSHA384 and XSHA512 instructions. With the help of implementation of SHA in hardware instead of software, can develop applications with higher performance, more security and more flexibility. This patch includes the XSHA1 instruction optimized implementation of SHA-1 transform function. Signed-off-by: AlanSong-oc --- lib/crypto/x86/sha1.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/lib/crypto/x86/sha1.h b/lib/crypto/x86/sha1.h index c48a0131f..d4946270a 100644 --- a/lib/crypto/x86/sha1.h +++ b/lib/crypto/x86/sha1.h @@ -48,6 +48,26 @@ static void sha1_blocks_avx2(struct sha1_block_state *st= ate, } } =20 +#if IS_ENABLED(CONFIG_CPU_SUP_ZHAOXIN) +#define PHE_ALIGNMENT 16 +static void sha1_blocks_phe(struct sha1_block_state *state, + const u8 *data, size_t nblocks) +{ + /* + * XSHA1 requires %edi to point to a 32-byte, 16-byte-aligned + * buffer on Zhaoxin processors. + */ + u8 buf[32 + PHE_ALIGNMENT - 1]; + u8 *dst =3D PTR_ALIGN(&buf[0], PHE_ALIGNMENT); + + memcpy(dst, state, SHA1_DIGEST_SIZE); + asm volatile(".byte 0xf3,0x0f,0xa6,0xc8" + : "+S"(data), "+D"(dst) + : "a"((long)-1), "c"(nblocks)); + memcpy(state, dst, SHA1_DIGEST_SIZE); +} +#endif /* CONFIG_CPU_SUP_ZHAOXIN */ + static void sha1_blocks(struct sha1_block_state *state, const u8 *data, size_t nblocks) { @@ -59,6 +79,11 @@ static void sha1_mod_init_arch(void) { if (boot_cpu_has(X86_FEATURE_SHA_NI)) { static_call_update(sha1_blocks_x86, sha1_blocks_ni); +#if IS_ENABLED(CONFIG_CPU_SUP_ZHAOXIN) + } else if (boot_cpu_has(X86_FEATURE_PHE_EN)) { + if (boot_cpu_data.x86 >=3D 0x07) + static_call_update(sha1_blocks_x86, sha1_blocks_phe); +#endif } else if (cpu_has_xfeatures(XFEATURE_MASK_SSE | XFEATURE_MASK_YMM, NULL) && boot_cpu_has(X86_FEATURE_AVX)) { --=20 2.34.1 From nobody Sun Feb 8 11:06:59 2026 Received: from mx1.zhaoxin.com (MX1.ZHAOXIN.COM [210.0.225.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 658DB2DF13F for ; Fri, 16 Jan 2026 07:18:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.0.225.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768547921; cv=none; b=m6mJhqx0QEeZOxyaNzOlnpesDchZkoPkFpuZwKwUnjCUud5J0I84piZmlf5k5y5SwfxGLfBl2EGVoXaIF4WcPfn/qkaXeRn/tCZHlKl2yk8JrxkjLaPXI00zdT/wURiNgoXFPu/5ZIsJ0rla4o3w8S2nW8FPJIyHb5mnb05Secs= ARC-Message-Signature: i=1; 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Fri, 16 Jan 2026 15:18:28 +0800 (CST) X-Barracuda-Envelope-From: AlanSong-oc@zhaoxin.com X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.165 Received: from ZXSHMBX1.zhaoxin.com (10.28.252.163) by ZXSHMBX3.zhaoxin.com (10.28.252.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.59; Fri, 16 Jan 2026 15:18:28 +0800 Received: from ZXSHMBX1.zhaoxin.com ([fe80::936:f2f9:9efa:3c85]) by ZXSHMBX1.zhaoxin.com ([fe80::936:f2f9:9efa:3c85%7]) with mapi id 15.01.2507.059; Fri, 16 Jan 2026 15:18:28 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.165 Received: from DESKTOP-A4I8D8T.zhaoxin.com (10.32.65.156) by ZXBJMBX02.zhaoxin.com (10.29.252.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.59; Fri, 16 Jan 2026 15:17:00 +0800 From: AlanSong-oc To: , , , , , , , CC: , , , , , , AlanSong-oc Subject: [PATCH v3 3/3] lib/crypto: x86/sha256: PHE Extensions optimized SHA256 transform function Date: Fri, 16 Jan 2026 15:15:13 +0800 X-ASG-Orig-Subj: [PATCH v3 3/3] lib/crypto: x86/sha256: PHE Extensions optimized SHA256 transform function Message-ID: <20260116071513.12134-4-AlanSong-oc@zhaoxin.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260116071513.12134-1-AlanSong-oc@zhaoxin.com> References: <20260116071513.12134-1-AlanSong-oc@zhaoxin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX02.zhaoxin.com (10.29.252.6) X-Moderation-Data: 1/16/2026 3:18:27 PM X-Barracuda-Connect: ZXSHMBX3.zhaoxin.com[10.28.252.165] X-Barracuda-Start-Time: 1768547908 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://mx2.zhaoxin.com:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 2262 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.153109 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- Content-Type: text/plain; charset="utf-8" Zhaoxin CPUs have implemented the SHA(Secure Hash Algorithm) as its CPU instructions by PHE(Padlock Hash Engine) Extensions, including XSHA1, XSHA256, XSHA384 and XSHA512 instructions. With the help of implementation of SHA in hardware instead of software, can develop applications with higher performance, more security and more flexibility. This patch includes the XSHA256 instruction optimized implementation of SHA-256 transform function. Signed-off-by: AlanSong-oc --- lib/crypto/x86/sha256.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/lib/crypto/x86/sha256.h b/lib/crypto/x86/sha256.h index 38e33b22a..70b68bad0 100644 --- a/lib/crypto/x86/sha256.h +++ b/lib/crypto/x86/sha256.h @@ -31,6 +31,26 @@ DEFINE_X86_SHA256_FN(sha256_blocks_avx, sha256_transform= _avx); DEFINE_X86_SHA256_FN(sha256_blocks_avx2, sha256_transform_rorx); DEFINE_X86_SHA256_FN(sha256_blocks_ni, sha256_ni_transform); =20 +#if IS_ENABLED(CONFIG_CPU_SUP_ZHAOXIN) +#define PHE_ALIGNMENT 16 +static void sha256_blocks_phe(struct sha256_block_state *state, + const u8 *data, size_t nblocks) +{ + /* + * XSHA256 requires %edi to point to a 32-byte, 16-byte-aligned + * buffer on Zhaoxin processors. + */ + u8 buf[32 + PHE_ALIGNMENT - 1]; + u8 *dst =3D PTR_ALIGN(&buf[0], PHE_ALIGNMENT); + + memcpy(dst, state, SHA256_DIGEST_SIZE); + asm volatile(".byte 0xf3,0x0f,0xa6,0xd0" + : "+S"(data), "+D"(dst) + : "a"((long)-1), "c"(nblocks)); + memcpy(state, dst, SHA256_DIGEST_SIZE); +} +#endif /* CONFIG_CPU_SUP_ZHAOXIN */ + static void sha256_blocks(struct sha256_block_state *state, const u8 *data, size_t nblocks) { @@ -79,6 +99,11 @@ static void sha256_mod_init_arch(void) if (boot_cpu_has(X86_FEATURE_SHA_NI)) { static_call_update(sha256_blocks_x86, sha256_blocks_ni); static_branch_enable(&have_sha_ni); +#if IS_ENABLED(CONFIG_CPU_SUP_ZHAOXIN) + } else if (boot_cpu_has(X86_FEATURE_PHE_EN)) { + if (boot_cpu_data.x86 >=3D 0x07) + static_call_update(sha256_blocks_x86, sha256_blocks_phe); +#endif } else if (cpu_has_xfeatures(XFEATURE_MASK_SSE | XFEATURE_MASK_YMM, NULL) && boot_cpu_has(X86_FEATURE_AVX)) { --=20 2.34.1