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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BN2PEPF0000449E.mail.protection.outlook.com (10.167.243.149) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9542.4 via Frontend Transport; Fri, 16 Jan 2026 03:35:53 +0000 Received: from BLR-L-RBANGORI.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Thu, 15 Jan 2026 21:35:48 -0600 From: Ravi Bangoria To: Peter Zijlstra , Ingo Molnar CC: Ravi Bangoria , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Dapeng Mi , James Clark , , , , "Manali Shukla" , Santosh Shukla , Ananth Narayan , Sandipan Das Subject: [PATCH 07/11] perf/amd/ibs: Support IBS_{FETCH|OP}_CTL2[Dis] to eliminate RMW race Date: Fri, 16 Jan 2026 03:34:46 +0000 Message-ID: <20260116033450.965-8-ravi.bangoria@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260116033450.965-1-ravi.bangoria@amd.com> References: <20260116033450.965-1-ravi.bangoria@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000449E:EE_|LV2PR12MB5822:EE_ X-MS-Office365-Filtering-Correlation-Id: d135a950-6223-4abd-f76f-08de54b059f5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|7416014|376014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jan 2026 03:35:53.3031 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d135a950-6223-4abd-f76f-08de54b059f5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000449E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5822 Content-Type: text/plain; charset="utf-8" The existing IBS_{FETCH|OP}_CTL MSRs combine control and status bits which leads to RMW race between HW and SW: HW SW ------------------------ ------------------------------ config =3D rdmsr(IBS_OP_CTL); config &=3D ~EN; Set IBS_OP_CTL[Val] to 1 trigger NMI wrmsr(IBS_OP_CTL, config); // Val is accidentally cleared Future hardware adds a control-only MSR, IBS_{FETCH|OP}_CTL2, which provides a second-level "disable" bit (Dis). IBS is now: Enabled: IBS_{FETCH|OP}_CTL[En] =3D 1 && IBS_{FETCH|OP}_CTL2[Dis] =3D 0 Disabled: IBS_{FETCH|OP}_CTL[En] =3D 0 || IBS_{FETCH|OP}_CTL2[Dis] =3D 1 The separate "Dis" bit lets software disable IBS without touching any status fields, eliminating the hardware/software race. Signed-off-by: Ravi Bangoria --- arch/x86/events/amd/ibs.c | 45 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 02e7bffe1208..d8216048be84 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -86,9 +86,11 @@ struct cpu_perf_ibs { struct perf_ibs { struct pmu pmu; unsigned int msr; + unsigned int msr2; u64 config_mask; u64 cnt_mask; u64 enable_mask; + u64 disable_mask; u64 valid_mask; u16 min_period; u64 max_period; @@ -292,6 +294,8 @@ static int perf_ibs_init(struct perf_event *event) return -ENOENT; =20 config =3D event->attr.config; + hwc->extra_reg.config =3D 0; + hwc->extra_reg.reg =3D 0; =20 if (event->pmu !=3D &perf_ibs->pmu) return -ENOENT; @@ -316,6 +320,11 @@ static int perf_ibs_init(struct perf_event *event) if (ret) return ret; =20 + if (ibs_caps & IBS_CAPS_DIS) { + hwc->extra_reg.config &=3D ~perf_ibs->disable_mask; + hwc->extra_reg.reg =3D perf_ibs->msr2; + } + if (hwc->sample_period) { if (config & perf_ibs->cnt_mask) /* raw max_cnt may not be set */ @@ -445,6 +454,9 @@ static inline void perf_ibs_enable_event(struct perf_ib= s *perf_ibs, wrmsrq(hwc->config_base, tmp & ~perf_ibs->enable_mask); =20 wrmsrq(hwc->config_base, tmp | perf_ibs->enable_mask); + + if (hwc->extra_reg.reg) + wrmsrq(hwc->extra_reg.reg, hwc->extra_reg.config); } =20 /* @@ -457,6 +469,11 @@ static inline void perf_ibs_enable_event(struct perf_i= bs *perf_ibs, static inline void perf_ibs_disable_event(struct perf_ibs *perf_ibs, struct hw_perf_event *hwc, u64 config) { + if (ibs_caps & IBS_CAPS_DIS) { + wrmsrq(hwc->extra_reg.reg, perf_ibs->disable_mask); + return; + } + config &=3D ~perf_ibs->cnt_mask; if (boot_cpu_data.x86 =3D=3D 0x10) wrmsrq(hwc->config_base, config); @@ -809,6 +826,7 @@ static struct perf_ibs perf_ibs_fetch =3D { .check_period =3D perf_ibs_check_period, }, .msr =3D MSR_AMD64_IBSFETCHCTL, + .msr2 =3D MSR_AMD64_IBSFETCHCTL2, .config_mask =3D IBS_FETCH_MAX_CNT | IBS_FETCH_RAND_EN, .cnt_mask =3D IBS_FETCH_MAX_CNT, .enable_mask =3D IBS_FETCH_ENABLE, @@ -834,6 +852,7 @@ static struct perf_ibs perf_ibs_op =3D { .check_period =3D perf_ibs_check_period, }, .msr =3D MSR_AMD64_IBSOPCTL, + .msr2 =3D MSR_AMD64_IBSOPCTL2, .config_mask =3D IBS_OP_MAX_CNT, .cnt_mask =3D IBS_OP_MAX_CNT | IBS_OP_CUR_CNT | IBS_OP_CUR_CNT_RAND, @@ -1389,6 +1408,9 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_= ibs, struct pt_regs *iregs) =20 out: if (!throttle) { + if (ibs_caps & IBS_CAPS_DIS) + wrmsrq(hwc->extra_reg.reg, perf_ibs->disable_mask); + if (perf_ibs =3D=3D &perf_ibs_op) { if (ibs_caps & IBS_CAPS_OPCNTEXT) { new_config =3D period & IBS_OP_MAX_CNT_EXT_MASK; @@ -1460,6 +1482,9 @@ static __init int perf_ibs_fetch_init(void) if (ibs_caps & IBS_CAPS_ZEN4) perf_ibs_fetch.config_mask |=3D IBS_FETCH_L3MISSONLY; =20 + if (ibs_caps & IBS_CAPS_DIS) + perf_ibs_fetch.disable_mask =3D IBS_FETCH_2_DIS; + perf_ibs_fetch.pmu.attr_groups =3D fetch_attr_groups; perf_ibs_fetch.pmu.attr_update =3D fetch_attr_update; =20 @@ -1481,6 +1506,9 @@ static __init int perf_ibs_op_init(void) if (ibs_caps & IBS_CAPS_ZEN4) perf_ibs_op.config_mask |=3D IBS_OP_L3MISSONLY; =20 + if (ibs_caps & IBS_CAPS_DIS) + perf_ibs_op.disable_mask =3D IBS_OP_2_DIS; + perf_ibs_op.pmu.attr_groups =3D op_attr_groups; perf_ibs_op.pmu.attr_update =3D op_attr_update; =20 @@ -1727,6 +1755,23 @@ static void clear_APIC_ibs(void) static int x86_pmu_amd_ibs_starting_cpu(unsigned int cpu) { setup_APIC_ibs(); + + if (ibs_caps & IBS_CAPS_DIS) { + /* + * IBS enable sequence: + * CTL[En] =3D 1; + * CTL2[Dis] =3D 0; + * + * IBS disable sequence: + * CTL2[Dis] =3D 1; + * + * Set CTL2[Dis] when CPU comes up. This is needed to make + * enable sequence effective. + */ + wrmsrq(MSR_AMD64_IBSFETCHCTL2, 1); + wrmsrq(MSR_AMD64_IBSOPCTL2, 1); + } + return 0; } =20 --=20 2.43.0